WO2017045185A1 - A method for three dimensional sculpturing of nanowire arrays - Google Patents
A method for three dimensional sculpturing of nanowire arrays Download PDFInfo
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- WO2017045185A1 WO2017045185A1 PCT/CN2015/089884 CN2015089884W WO2017045185A1 WO 2017045185 A1 WO2017045185 A1 WO 2017045185A1 CN 2015089884 W CN2015089884 W CN 2015089884W WO 2017045185 A1 WO2017045185 A1 WO 2017045185A1
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- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
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Abstract
A method of fabricating nanowire arrays is provided, which comprises: preparing nanowires by means of vapor transport process; sculpturing of the nanowires, which comprises: the nanowires being coated with a plurality of photoresist layers to form an NAs@PR matrix, the NAs@PR matrix being exposed to a UV light, and the NAs@PR matrix being dipped into an etching solution.
Description
Description
Title of Invention: A Method for Three Dimensional Sculpturing of
Nanowire Arrays
Technical Field
[0001] The present application relates to the field of nanotechnology, in particular, it relates to a method for 3 dimensional sculpturing vertical nanowire arrays and the product made thereof.
Background Art
[0002] Ultraviolet semiconductor lasers are widely used for applications in photonics, information storage, biology and medical therapeutics. Among others, zinc oxide is an important basic material due to its low cost, large band gap (3.37 eV), large exciton binding energy (60 MeV), and luminescent properties. It is widely employed in many applications such as gas sensor, filtering materials for ultraviolet light, and antimicrobial materials. Nowadays, many ZnO nanostructures (e.g. nanorods, nanobridges and nanonails) have been manufactured. These products are expected to have potential applications in building functional nanoelectronic devices.
[0003] Exercising rational control over nanostructures is necessary to tailor the functionalities and properties of various nanomaterials. Ordered nanoarchitectures on substrate assembled by ZnO nanowire arrays (NAs) are extremely desirable, in which anisotropic parameters, periodic structure and size may be tuned which could result in novel and promising properties for applications in optical, thermal, and electric/ electronic related nanodevices.
[0004] Various methods have been developed to fabricate patterned ZnO vertical NAs in a large area on substrate; these methods are classified into three main categories: pre- patterned template methods, post assembly methods and in-situ growth methods. These existing approaches are limited to two-dimensional patterning of NAs with a poor rough control of the NW length and/or a low patterning resolution owing to the unavoidable lateral growth or impurities induced growth. It is, therefore, desirable to realize large-scale sculpturing of vertical ZnO NWs on substrate though it remains one of the great challenges for nanotechnologists, preventing effective use of their promising properties and fabrication of practical devices.
Technical Problem
[0005] The present application provides a method for fabricating high-quality nanowire arrays with a controlled morphology and nanowire density. The method comprises: preparing nanowires by means of vapor transport process; sculpturing of the nanowires, which comprises the following steps: the nanowires being coated with a
plurality of layers of photoresist to form a NAs @ PR matrix, the NAs @ PR matrix being exposed to a UV light, and the NAs @ PR matrix being dipped into an etching solution.
Solution to Problem
Technical Solution
[0006] According to another embodiment of the present application, nanowire arrays made by the method according to the present application are provided.
Advantageous Effects of Invention
Advantageous Effects
[0007] The present application provides a simple and effective method for 3 dimensional sculpturing of vertical nanowire arrays. According to the present application, the step of coating thick PR layers onto NAs enables the precise cutting and patterning of NAs as well as the controlled tailoring of NAs. Combined with laser direct write
lithography, it is possible to extend the method for the sculpture of more complicated NAs-based nanoarchitectures. With simplicity and excellent compatibility to complement metal oxide semiconductor processing, the present method facilitates the fabrication of nanoarchitectures using nanowire arrays/nanoparticles as nano bricks in functional nanodevice applications such as resonators, nanophotonics, sensors, super- capacitors, solar cells, nanogenerators, 3D FETs and more.
Brief Description of Drawings
Description of Drawings
[0008] Figure 1 is a flow figure of two basic operations of 3D sculpturing.
[0009] Figure 2a shows SEM images of the results of ZnO NAs with exposure times of 0s, 4.3s and 8.6s.
[0010] Figure 2b shows SEM images of ZnO NAs with a square grid design.
[0011] Figure 3a to 3d show SEM images of sculpturing of ZnO NAs with various patterns.
[0012] Figure 4 is a sketch map for the formation of the inclined planes at the pattern edge of the sculptured NAs.
Mode for the Invention
Mode for Invention
[0013] Objects, advantages and embodiments of the present application will be explained below in detail with reference to the accompanying drawings. However, it is to be appreciated that the following description of the embodiments is merely exemplary in nature and is not intended to limit the application, its application, or uses.
[0014] According to an embodiment of the present application, a method for sculpturing nanowire arrays is provided, wherein the method comprises:
[0015] (1) preparing nanowires grown on a silicon substrate, the nanowires are synthesized
using a vapor transport process;
[0016] (2) sculpturing the nanowires, which comprises the following steps:
[0017] (a) the nanowires being coated with a plurality of layers of photoresist to obtain an
NAs @ PR matrix,
[0018] (b) the NAs @ PR matrix being exposed to a UV light, and the NAs @ PR matrix being dipped into an etching solution.
[0019] The nanowire arrays to be sculptured by the present method can be made of ZnO, Si, or GaN.
[0020] The etching solution in the above step (b) can be a diluted HN03 solution (5 % V/ V), or a mixture of HN03 (70% wt) and HF (49% wt) in the molar ratio of lto 2.5, or an NaOH solution (4.5 mol/L).
[0021] According to an embodiment of the present application, the NWs ( nanowires) have a length of 9-12 μιη.
[0022] Considering the ZnO is an important basic material in this field as mentioned above, the present application will at first take ZnO nanowires as a preferable embodiment to be sculptured.
[0023] Figure 1 schematically shows the process of two basic operations of 3D sculpturing: cutting/shortening and patterning. Firstly, the ZnO NAs are wholly immersed in photoresist (PR) by spin coating to form a ZnO NAs@PR matrix (Fig. la). This matrix is exposed to UV light and developed following a photolithography process (Fig. lb).
[0024] According to a preferable embodiment, the ZnO nanowires grown on a silicon
substrate can be made as follows: an alumina boat containing ZnO powder is placed in the center of a tube furnace, and Si substrates with PR (photoresist) patterns are placed downstream for the nucleation and growth of ZnO NWs. The furnace is heated to 1200-1400 °C and the temperature maintained for 0.5 to 1 hour under vacuum conditions (-10-2 Torr) to evaporate the ZnO. ZnO NWs with a length of 9-12 μιη grew on the substrates located at 700 ~ 900 °C.
[0025] According to an embodiment of the present application, the ZnO NAs grown on Si substrates can be sculptured as follows: the ZnO NAs grown on Si substrates is coated with several layers of PR, and then treated by hard-baking. The formed ZnO NAs @ PR matrix is positioned under photomasks using a mask aligner and then exposed to 400 nm UV light. The matrix is dipped into diluted HN03 solution to etch out the naked part of NAs, then the obtained product is washed with acetone and deionized water. The concentration of the diluted HN03 solution may be 4-6 % V/V.
[0026] According to a preferable embodiment, the ZnO NAs grown on Si substrates is
coated by spin coating at a speed of 3500-4500 rpm for 25 s -35 s, and the number of PR layers to be coated on the ZnO NAs varies with the length of NWs. Preferably, ZnO NAs with a length of about 12 μιη are taken, and the standard coating process is
repeated for three times to form an NAs@PR matrix with NAs wholly immersed in PR, accordingly, the total thickness of the coated PR layers is up to 13 μιη. Preferably, the total thickness of the coated PR layers is from 12 to 13μιη.Τ1ιε final thickness of the layers is relatively large compared with the existing photolithography process.
[0027] It is reported that vertically aligned NAs can effectively trap light and the gap
between NWs helps the transmission of light. In a normal photolithography process, a typical PR layer with a thickness of less than 2 μιη is coated on the surface of the targeted substrate and the diffraction of light at the edge of a metal layer (usually Cr) on the mask is the main factor that degrades the photolithography resolution. To reduce this impact, a contact mode, in which the mask and substrate are closely attached, is the most common photolithography mode. Different from the above mode, in the present application, the PR is immersed in the NAs and forms a relatively thick layer of up to 12 μιη. Though the selected PR is transparent to 400 nm UV light for exposure, the relatively long light transmission path will definitely reduce the resolution of the sculpturing owing to an enhanced diffraction of light.
[0028] According to an embodiment of the present application, the hard-baking is carried out at 110-130°C for 50-70 s.
[0029] For the cutting of NAs, the exposure time is controlled in such a way that only a certain thickness of PR is removed with the top part of NAs revealed after this step of development. Figure 2a) shows the SEM images of height shortening results of ZnO NAs by the cutting process. It can be seen that, the height of NAs decreased from 12 μιη to 9.9 μιη, about 2.1 μιη after being exposed for 4.3s. The shortening of NAs increased two fold, by about 4.2 μιη, when the exposure time is increased by a factor of two to 8.6s. The height shortening of NAs increases linearly with exposure time.
Therefore, the cutting process enables a precise control on the height of ZnO NAs, which is something hardly achieved by other self-assembly techniques on NAs. Figure 2b) shows SEM images of ZnO NAs with a square grid design achieved by the patterning process. It is found that the conventional photolithography technique can be well applied on NAs for 2D patterning and the resultant sample is similar to that achieved by patterned metal-catalysts/seeds guiding NAs growth. Compared to other assembly techniques for patterned micro-nanostructures, the 3D sculpturing method according to the present application shows remarkable advantages since cutting and patterning can be easily achieved simultaneously by conventional photolithography, and sculpturing of NAs can be expected. Figure 3 panels a-d illustrate several ZnO NAs tailored by our strategy, such as line arrays (Figures 3a), networks (Figure 3b), and disk arrays (Figure 3c). The size, height, and shape of the ZnO NAs and their densities in one unit can be modified by photolithography conditions, such as masks and exposure time. Figure 3d) shows round, hexagonal and trigonal shaped ZnO NAs,
revealing excellent shape sculpturing. Normally, the resolution for photolithography is about 2 μιη. In order to obtain the smallest 2D feature size, a mask with a pattern of a series of round disks can be employed, wherein the round disks have sizes ranging from 1 μιη to 20 μιη. Our experimental results show that ZnO NAs with a disk diameter larger than 5 μιη can still hold a round shape, however, those smaller than 5 μιη are fabricated into irregular shapes (figure not show).
[0030] According to an embodiment of patterning of NAs, a mask with the desired pattern can be used and a relatively long exposure time of 30 s is required owing to the rather thick PR layer (12 μιη).
[0031] The inventors further discover that the aspect ratio and the diameter of NWs greatly affect the sculpturing results. When the light enters the NAs @ PR matrix, the reflection and refraction across the interface of PR and NWs results in a diffused light dose distribution. NWs with a large aspect ratio tend to aggregate into bundles owing to capillary effect after being coated with PR and this significantly blocks the light transmission and enhances light scattering. NWs with a large diameter are rigid and hardly aggregate but they still contribute to light scattering. As a consequence, the pattern edge of the sculptured NAs is usually expected to possess inclined planes, which is confirmed by the observed results as shown in Figures 2 and 3. Figure 4 demonstrates the sketch map for the formation of inclined planes at the pattern edge of the sculptured NAs. The edge of the patterned PR layer shows an inclined plane profile. This result indicates strong light scattering during the exposure process in the NAs @ PR matrix, which is the main reason for the reduction of resolution of the sculpturing technique according to the present application. In order to achieve an acceptable performance, it is necessary to consider all related factors such as NW diameter, NW aspect ratio and the PR selection.
[0032] According to a preferable embodiment, NWs with a diameter smaller than 200 nm and aspect ratio of less than 20 are employed, and experimental results show that these NWs are less affected by the light scattering when undergoing a sculpturing process. A resolution of about 2.5 μιη, close to that of conventional photolithography (2.0 μιη), can be obtained. More preferable, the NWs have a diameter ranging from 50 nm to 200 nm.
[0033] Preferably, the aspect ratio of the NWs is from 1 to 20.
[0034] The above sculpturing process and its parameters are also applicable to Si nanowire arrays and GaN nanowire arrays.
[0035] The present application will be further described in the following Examples.
[0036] Example 1
[0037] Growth of ZnO NAs: ZnO NWs were synthesized using a vapor transport method:
An alumina boat containing 3 g of ZnO powder was placed in the center of a tube
furnace. Si substrates with PR patterns were placed downstream for the nucleation and growth of ZnO NWs. The furnace was heated to 1300 °C and the temperature maintained for half an hour under vacuum conditions (-10-2 Torr), then the temperature was dropped to about 800 °C. ZnO NWs with a length of about 12 μιη grew on the substrates were obtained at the temperature of 800 °C.
[0038] Example 2
[0039] Sculpturing of ZnO NAs: As-grown ZnO NAs on Si substrates were coated with three layers of PR (AZ1518 photoresist) by spin coating at a speed of 4000 rpm for 30 s, and then treated by hard-baking at 120°C for 60 s. In this example, the ZnO NAs had a length of about 12 μιη, and the standard coating process was repeated for three times to form a NAs @ PR matrix with NAs wholly immersed in PR. The as-formed ZnO NAs@PR matrix was positioned under photomasks using a mask aligner (ABM Inc.) and then exposed to 400 nm UV light. For the cutting of NAs, the exposure time was 4.3s, and the height of NAs decreased about 2.1 μιη. For the patterning of NAs, a mask with the desired pattern was used and the exposure time was 30 s because of the rather thick PR layer (12 μιη). Then, the matrix was dipped in diluted HN03 solution (5 % V/V) for 5 s to etch out the naked part of NAs (Fig. lc). The cutting and patterning of NAs were realized, respectively, after removing the PR by washing the sample with acetone and deionized water (Fig. Id).
[0040] Example 3
[0041] Sculpturing of Si NAs: Si NAs prepared in advance on Si substrates were coated with three layers of PR (AZ1518 photoresist) by spin coating at a speed of 4000 rpm for 30 s, and then treated by hard-baking at 120°C for 60 s. In this example, the obtained Si NAs had a length of about 12 μιη, and the standard coating process was repeated for three times to form a NAs @ PR matrix with NAs wholly immersed in PR. The
NAs@PR matrix was positioned under photomasks using a mask aligner (ABM Inc.) and then exposed to 400 nm UV light. For the cutting of NAs, the exposure time was 4.3s, as a result the height of NAs decreased about 2.1 μιη. For the patterning of NAs, a mask with the desired pattern was used and the exposure time was 30 s because of the rather thick PR layer (12 μιη). Then, the matrix was dipped in etching solution, HN03 (70% wt): HF (49% wt) = 1:2.5 (molar ratio) for 5 s to etch out the naked part of NAs. The cutting and patterning of NAs were realized, respectively, after removing the PR by washing the sample with acetone and deionized water.
[0042] Example 4
[0043] Sculpturing of GaN NAs: GaN NAs prepared in advance on Si substrates were
coated with three layers of PR (AZ1518 photoresist) by spin coating at a speed of 4000 rpm for 30 s, and then treated by hard-baking at 120°C for 60 s. In this example, the GaN NAs had a length of about 12 μιη, and the standard coating process was repeated
for three times to form a NAs @ PR matrix with NAs wholly immersed in PR. The NAs@PR matrix was positioned under photomasks using a mask aligner (ABM Inc.) and then exposed to 400 nm UV light. For the cutting of NAs, the exposure time was 4.3s, and the height of NAs decreased about 2.1 μιη. For the patterning of NAs, a mask with the desired pattern was used and the exposure time was 30 s because of the rather thick PR layer (12 μιη). Then, the matrix was dipped in etching solution, NaOH (4.5 mol/L) for 5 s to etch out the naked part of NAs. The cutting and patterning of NAs were realized, respectively, after removing the PR by washing the sample with acetone and deionized water.
[0044] Sample Characterizations: All the above samples were examined by a Philips
scanning electron microscope (SEM, XL-30) and a JEOL high resolution transmission electron microscope (HRTEM, 2010F) equipped with an energy-dispersive X-ray spectrometer (EDX).
[0045] Therefore, 3D sculpturing of vertical NAs can be easily achieved by a combination of the above cutting and patterning process.
[0046] The present application may be embodied in other forms without departing from the spirit or novel characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limitative.
Claims
Claims
A method of fabricating nanowire arrays comprising:
preparing nanowires;
sculpturing of the nanowires, wherein the process of sculpturing of the nanowires comprises: the nanowires being coated with a plurality of photoresist layers to form an NAs@PR matrix, the NAs@PR matrix being exposed to a UV light, and the NAs@PR matrix being dipped into an etching solution.
The method of claim 1, wherein the nanowires have a length of 9-12 μιη.
The method of claim 1, wherein the nanowires are made of ZnO, Si, or GaN.
The method of claim 1, wherein the nanowires are made of ZnO, and the nanowires are grown on a silicon substrate.
The method of claim 1, wherein the total thickness of the photoresist layers is 12 to 13μιη.
The method of claim 1, wherein the NAs@PR matrix being exposed to a UV light in such a way that only a certain thickness of photoresist is removed.
The method of claim 1, wherein a mask with a series of round disks having sizes ranging from 1 μιη to 20 μιη is used in the process of the NAs@PR matrix being exposed to a UV light.
The method of claim 1, wherein the nanowires have a diameter ranging from 1 nm to 500 nm.
Nanowire arrays made by the method of claim 1.
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| CN201580069459.XA CN107112234A (en) | 2015-09-17 | 2015-09-17 | The engraving process of nano-wire array and nano-wire array |
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| CN102556949A (en) * | 2012-01-13 | 2012-07-11 | 合肥工业大学 | Preparation method of silicon micro/nanometer line array with controllable dimension |
| CN103257178A (en) * | 2013-04-25 | 2013-08-21 | 南通大学 | One-dimensional nanometer electrode material, and preparation method and application thereof |
| US20140030873A1 (en) * | 2012-07-27 | 2014-01-30 | National Taiwan University Of Science And Technology | Method for fabricating patterned silicon nanowire array and silicon microstructure |
| CN103984055A (en) * | 2014-05-09 | 2014-08-13 | 京东方科技集团股份有限公司 | Polarization structure, manufacturing method thereof and display panel |
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| CN102556949A (en) * | 2012-01-13 | 2012-07-11 | 合肥工业大学 | Preparation method of silicon micro/nanometer line array with controllable dimension |
| US20140030873A1 (en) * | 2012-07-27 | 2014-01-30 | National Taiwan University Of Science And Technology | Method for fabricating patterned silicon nanowire array and silicon microstructure |
| CN103257178A (en) * | 2013-04-25 | 2013-08-21 | 南通大学 | One-dimensional nanometer electrode material, and preparation method and application thereof |
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