CN103000769A

CN103000769A - Method for preparing nanoscale high-aspect-ratio orderly-patterned substrate of high-voltage array LED

Info

Publication number: CN103000769A
Application number: CN 201110273927
Authority: CN
Inventors: 张庆
Original assignee: Individual
Current assignee: Individual
Priority date: 2011-09-15
Filing date: 2011-09-15
Publication date: 2013-03-27

Abstract

The invention provides a method for preparing a nanoscale high-aspect-ratio orderly-patterned substrate of a high-voltage array LED. The method includes: forming high-aspect-ratio nanocrystalline metal cone-column masks in ordered arrangement on the surface of a GaN substrate by the aid of the nanoimprint lithography compatible metal layer stripping process, and reproducing mask patterns on the surface of the GaN substrate by the aid of the ICP (inductively coupled plasma) etching technology so as to control geometrical shapes, arrangement modes, arrangement density and high aspect ratio of three-dimensional nanostructures in sapphire substrate patterns. The substrate is applied to high-voltage array LED preparation by limiting distribution of the three-dimensional nanostructures on the bottom surfaces of device micro units.

Description

The method of the orderly graph substrate of nano-scale high-aspect-ratio of preparation array high-voltage LED

Technical field

The present invention relates to a kind of effective ways that prepare nano-scale, the orderly graph substrate of high-aspect-ratio, be applied to prepare the array high-voltage LED.

Background technology

The substrate of present most popular extension gallium nitride (GaN) material is lower-cost Sapphire Substrate, yet, Sapphire Substrate and GaN material exist huge lattice mismatch (16%) and coefficient of thermal expansion mismatch (34%), so the GaN material internal of heteroepitaxy has very high dislocation density (10 ⁹-10 ¹¹Cm ^-2), this can cause the harmful effects such as Carrier Leakage and non-radiative recombination center increase, and reduces the internal quantum efficiency of device; On the other hand, because GaN Refractive Index of Material (n=2.4) is higher than Sapphire Substrate (n=1.7) and outer enclosure resin (n=1.5), so that the photon that active area produces seriously reduces the light extraction efficiency of device at GaN upper and lower interface generation multiple total reflection.The graph substrate technology is by making the figure with micro-structure on Sapphire Substrate surface, and then carries out material epitaxy at this patterned substrate surface.Patterned interface has changed the growth course of GaN material, can suppress defective to the extension of epitaxial surface, improves the device internal quantum efficiency; Simultaneously, the scattering of the GaN sapphire interface of roughening energy is from the photon of active area emission, so that the photon of script total reflection has an opportunity to shine the device outside, and can Effective Raise light extraction efficiency [1].

The surface topography of graph substrate is to the growth pattern of the GaN on the substrate, the body quality of materials, and final device efficiency all will have far-reaching influence.Theoretical and experimental study shows, when the construction unit size of graph substrate is reduced to sub-micron even nanometer, the epitaxial growth of GaN material can be by horizontal hyperplasia method reduce injection defect density to greatest extent, improve as much as possible the internal quantum efficiency [2] of LED; Simultaneously, the 3-D nano, structure that forms at the GaN sapphire interface by the graph substrate technology is because size and ultraviolet are approximate to the optical wavelength of blue wave band, and most effectively scattering significantly improves the light extraction efficiency [2] of LED from the photon of active area emission; And these nanostructures also can be arranged by orderly two and three dimensions, make photon crystal structure, further control the light-emitting mode of active area by the Pusell effect, improve the luminous efficiency of LED and improve its lighting angle distribute [3]; In addition, make the nitride device that contains nanostructure, can overcome the lattice dislocation problem in the material, increase productive rate, reduce cost.

Yet; the application of graph substrate technology in large-scale production also rests on the physical dimension more than the micron up to now; its basic reason is to have the above in order graph substrate of cellular construction of micron can make on a large scale by photoetching technique very ripe on the technique; cost is lower; and the graph substrate of micro-nanometer ordered structure need be utilized special technique; such as electron beam exposure; laser direct-writing; the coherent light diffraction; the costlinesses such as self assembly, poor efficiency and time-consuming mode are made, and have hindered the possibility of its large-scale production.Nanoimprint Lithography is as a kind of technology of efficient, low-cost preparation nanostructure, although in the research of graph substrate preparation, attempted, but because the used mask glue thickness limits (≤200 nanometer) of Nanoimprint Lithography, the ordered arrangement [4] of nanoscale shallow bore hole can only be formed at sapphire surface at present, the ordered arrangement of the nanocone chondritic of high-aspect-ratio can't be realized at the GaN sapphire interface; Because gallium nitride growth pattern and horizontal extension are very similar on the sapphire pattern substrate of conisphere shape structure; can discharge to greatest extent because the adaptive compressive strain that causes of lattice; and possess optimized light extraction efficiency, above-mentioned restriction has hindered the graph substrate of micro-nanometer ordered structure and has used in efficient, scale that LED makes the field.

List of references

1.Oh?TS，Kim?SH，Kim?TK，et?al.GaN-Based?Light-Emitting?Diodes?on?Micro-Lens.Patterned?Sapphire?Substrate.Jpn.J.Appl.Phys.2008；47：5333-5336.

2.Huang?HW，Lin?CH，Huang?JK，et?al.Investigation?of?GaN-based?light?emittingdiodes?with?nano-hole?patterned?sapphire?substrate(NHPSS)?by?nano-imprintlithography.Mater.Sci.Eng.B.2009；164：76-79.

3.Ji?R，Hornung?M，Verschuuren?MA，et?al.UV?enhanced?substrate?conformalimprint?lithography(UV-SCIL)technique?for?photonic?crystals?patterning?in?LEDmanufacturing.Microelectron.Eng.2010；87：963-967.

4.Sreenivasan?SV，Willson?CG，Schumaker?NE，Resnick?DJ.Low-CostNanostructure?Patterning?Using?Step?and?Flash?Imprint?Lithography.NIST-SPIEConference?on?Nanotechnology.2002.

Summary of the invention

The invention provides a kind of effective ways that prepare nano-scale, the orderly graph substrate of high-aspect-ratio LED, by inventing a kind of novel technical process, can improve productive rate and scale in conjunction with existing nano print technology (NanoimprintLithography), and can have the cone of nano-scale, the oldered array of chondritic in the sapphire surface manufacturing at low cost, thereby realize that the nano graph substrate is in the practical application in LED field.

Technological core of the present invention by a kind of innovation, with the metal level stripping technology of nanoimprint lithography compatibility, form a kind of nano metal cone-post mask with high-aspect-ratio and ordered arrangement at the GaN substrate surface, by inductively coupled plasma (ICP) lithographic technique mask pattern is copied to the GaN substrate surface again, specifically comprise following process steps: (1) forms the positive photoresist layer of 100-1000 nano thickness by spin-coating method on the Sapphire Substrate surface of twin polishing; (2) form 10-500 nanometer titanium dioxide silicon thin film on positive photoresist layer surface by plasma enhanced chemical vapor deposition (PECVD); (3) utilize nanoimprint lithography technology at the impression polymer column array of structures of silica membrane surface formation 10-500 nanometer height, as shown in Figure 1; (use therein nano impression polymer is the Silmat of Molecular Imprint Inc company, and work is a kind of molecule marking material that comprises the silicon composition, is nanoimprint lithography technology-specific); (4) take impression polymer column array of structures as mask, by reactive ion etching process positive photoresist layer and the silica membrane of sapphire surface carried out etching, the degree of depth is carried out lateral etches to the positivity photoresist layer simultaneously to substrate, the formation side is cut, as shown in Figure 2; (5) by electron beam evaporation plating at the sample surfaces depositing metal membrane layer; (6) utilize the side of positive photoresist layer to cut, selective detachment is at the metal level on evaporation positive photoresist layer and silica membrane surface, thereby forms a kind of nano metal cone-post mask with high-aspect-ratio and ordered arrangement at substrate surface; (7) the nano metal cone-post mask that utilizes order to arrange uses inductance coupling high (ICP) the plasma etching equipment in upper/lower electrode Double RF source, and the etching Sapphire Substrate is to set depth, as shown in Figure 3; (8) utilize wet chemical etch to remove metal mask, form the nanocone chondritic of the high-aspect-ratio of ordered arrangement at sapphire surface, the sapphire pattern substrate of the nanocone chondritic of the final high-aspect-ratio that realizes possessing ordered arrangement, as shown in Figure 4.All the flow chart of processing step as shown in Figure 5.

In this processing step, nanoimprint lithography technology can be used to control spacing, density and the array pattern of nanocone-post in the metal mask structure; The formed side of etching positive photoresist layer cut the floor space that size can be controlled nanocone-post in the metal mask structure; In addition, the gradient of the formed side wall of etching silicon dioxide can comprise reactive gas species, gas flow rate, air pressure and voltage by changing the parameter of reactive ion etching, and controlled; And the gradient of side wall of silicon dioxide can change the inclination angle of nanocone-post in the metal mask structure; And then pattern of rows and columns, density, high-aspect-ratio and the cone sphere three-dimensional geometry parameter of nanocone chondritic in the control Sapphire Substrate figure.

When the present invention is applied to prepare high brightness array high-voltage LED, will be by pattern of rows and columns and the spacing of nanocone chondritic in the control Sapphire Substrate figure: with the substrate figure be limited in each device micro unit in the array high-voltage LED below, and there is not the three-dimensional substrate figure in the insulated trenches zone between the micro unit, to guarantee that the bridging metallic film is not subjected to the impact of substrate figure when passing through the insulated trenches zone, keep the continuity of plain conductor and good conductive capability, see Fig. 6.

Description of drawings

The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:

Fig. 1: utilize nanoimprint lithography technology to form the Silmat column structure array of 100-200 nanometer height on the silica membrane surface;

Fig. 2: take Silmat column structure array as mask, by reactive ion etching process PMGI-SF6 photoresist layer and the silica membrane of sapphire surface carried out etching, the degree of depth is carried out lateral etches to the PMGI-SF6 photoresist layer simultaneously to substrate, forms side and cuts;

Fig. 3: the nano metal cone-post mask that utilizes order to arrange, use inductance coupling high (ICP) the plasma etching equipment in upper/lower electrode Double RF source, the formed pattern of etching Sapphire Substrate;

Fig. 4: after utilizing wet chemical etch to remove metal mask, the nanocone chondritic of the high-aspect-ratio of the ordered arrangement that forms at sapphire surface.

Fig. 5: the flow chart of the whole processing steps of the art of this patent.

Fig. 6: the cross sectional representation that possesses the array high-voltage LED chip of nano-structural ordered graph substrate.

Embodiment

Implementation example: in this example, will be by above-mentioned patented technology, utilize nanoimprint lithography and metal level stripping technology, form the nano graph with high-aspect-ratio and ordered arrangement at the GaN substrate surface, as an example, step is as follows: at first, form PMGI-SF6 (Microlithography Chemical Inc company) the positive photoresist layer of 200 nano thickness by spin-coating method on the Sapphire Substrate surface of a twin polishing, wherein the diameter of Sapphire Substrate can be any number in the 1-8 inch; Then, form 150 nanometer titanium dioxide silicon thin films on PMGI-SF6 photoresist layer surface by plasma enhanced chemical vapor deposition (PECVD); Then, utilize nanoimprint lithography technology to form the Silmat column structure array of 200 nanometer height on the silica membrane surface, then, take Silmat column structure array as mask, by reactive ion etching process PMGI-SF6 photoresist layer and the silica membrane of sapphire surface carried out etching, the degree of depth is carried out lateral etches to the PMGI-SF6 photoresist layer simultaneously to substrate, forms side and cuts; Then, at sample surfaces deposition Ni metallic diaphragm, thickness is 100 nanometers by electron beam evaporation plating; Then, utilize the side of PMGI-SF6 photoresist layer to cut, selective detachment is at the metal level on PMGI-SF6 photoresist layer and silica membrane surface, thereby forms a kind of nano metal cone-post mask with high-aspect-ratio and ordered arrangement at substrate surface; Then, the nano metal cone-post mask that utilizes order to arrange uses inductance coupling high (ICP) the plasma etching equipment in upper/lower electrode Double RF source, adopts based on Cl ₂/ Ar/BCl ₃The inductively coupled plasma of gas (ICP) etching Sapphire Substrate is to 600nm; At last, utilize wet chemical etch to remove metal mask, form the nanocone chondritic of the high-aspect-ratio of ordered arrangement at sapphire surface, the sapphire pattern substrate of the nanocone chondritic of the final high-aspect-ratio that realizes possessing ordered arrangement.

Claims

1. method for preparing the orderly graph substrate of nano-scale high-aspect-ratio of array high-voltage LED, it is characterized in that: by a kind of innovation, with the metal level stripping technology of nanoimprint lithography compatibility, form a kind of nano metal cone-post mask with high-aspect-ratio and ordered arrangement at the GaN substrate surface, by inductively coupled plasma (ICP) lithographic technique mask pattern is copied to the GaN substrate surface again.The method comprises following process steps: (1) forms the positive photoresist layer of 100-1000 nano thickness by spin-coating method on the Sapphire Substrate surface of twin polishing; (2) form 10-500 nanometer titanium dioxide silicon thin film on positive photoresist layer surface by plasma enhanced chemical vapor deposition (PECVD); (3) utilize the nanoimprintlithography technology to form the impression polymer column array of structures of 10-500 nanometer height on the silica membrane surface; (4) take impression polymer column array of structures as mask, by reactive ion etching process positive photoresist layer and the silica membrane of sapphire surface carried out etching, the degree of depth is carried out lateral etches to the positivity photoresist layer simultaneously to substrate, forms side and cuts; (5) by electron beam evaporation plating at the sample surfaces depositing metal membrane layer; (6) utilize the side of positive photoresist layer to cut, selective detachment is at the metal level on evaporation positive photoresist layer and silica membrane surface, thereby forms a kind of nano metal cone-post mask with high-aspect-ratio and ordered arrangement at substrate surface; (7) the nano metal cone-post mask that utilizes order to arrange uses inductance coupling high (ICP) the plasma etching equipment in upper/lower electrode Double RF source, and the etching Sapphire Substrate is to set depth; (8) utilize wet chemical etch to remove metal mask, form the nanocone chondritic of the high-aspect-ratio of ordered arrangement at sapphire surface, the sapphire pattern substrate of the nanocone chondritic of the final high-aspect-ratio that realizes possessing ordered arrangement.

2. a kind of method for preparing the orderly graph substrate of nano-scale high-aspect-ratio of array high-voltage LED according to claim 1, it is characterized in that: the formed side of etching positive photoresist layer cut the floor space that size can be controlled nanocone-post in the metal mask structure.

3. a kind of method for preparing the orderly graph substrate of nano-scale high-aspect-ratio of array high-voltage LED according to claim 1, it is characterized in that: the gradient of the formed side wall of etching silicon dioxide can be by changing the parameter of reactive ion etching, comprise reactive gas species, gas flow rate, air pressure and voltage, and controlled; And the gradient of side wall of silicon dioxide can change the inclination angle of nanocone-post in the metal mask structure; And then pattern of rows and columns, density, high-aspect-ratio and the cone sphere three-dimensional geometry parameter of nanocone chondritic in the control Sapphire Substrate figure.

4. a kind of method for preparing the orderly graph substrate of nano-scale high-aspect-ratio of array high-voltage LED according to claim 1, it is characterized in that: by pattern of rows and columns and the spacing of nanocone chondritic in the control Sapphire Substrate figure, with the substrate figure be limited in each device micro unit in the array high-voltage LED below, and there is not the three-dimensional substrate figure in the insulated trenches zone between the micro unit, to guarantee that the bridging metallic film is not subjected to the impact of substrate figure when passing through the insulated trenches zone, keep the continuity of plain conductor and good conductive capability.