WO2017030591A1 - Circuits de fixation de niveau d'alimentation à memristances - Google Patents

Circuits de fixation de niveau d'alimentation à memristances Download PDF

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Publication number
WO2017030591A1
WO2017030591A1 PCT/US2015/046112 US2015046112W WO2017030591A1 WO 2017030591 A1 WO2017030591 A1 WO 2017030591A1 US 2015046112 W US2015046112 W US 2015046112W WO 2017030591 A1 WO2017030591 A1 WO 2017030591A1
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WO
WIPO (PCT)
Prior art keywords
memristor
electrostatic discharge
supply rail
supply
circuit
Prior art date
Application number
PCT/US2015/046112
Other languages
English (en)
Inventor
Brent Buchanan
Ning GE
Richard James AULETTA
Original Assignee
Hewlett Packard Enterprise Development Lp
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Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/046112 priority Critical patent/WO2017030591A1/fr
Publication of WO2017030591A1 publication Critical patent/WO2017030591A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • Electrostatic discharge can damage or destroy components of an integrated circuit (IC). Electrostatic discharge occurs when an accumulated electric charge is shorted to a lower potential. There are many situations in which an electrostatic discharge event can arise for an integrated circuit, for example, when a charged body touches the integrated circuit and when a charged integrated circuit touches a grounded element. When the electric charge moves between surfaces, the electric charge becomes a current that can damage the integrated circuit.
  • FIG. 1 illustrates a block diagram of an example device including a supply clamp circuit with a memristor to record occurrences of electrostatic discharge currents;
  • FIG. 2 illustrates an additional example device including a supply clamp circuit with a memristor to record occurrences of electrostatic discharge currents
  • FIG. 3 illustrates an example supply clamp circuit that includes a memristor to record occurrences of electrostatic discharge currents
  • FIG. 4 illustrates an additional example supply clamp circuit that includes a memristor to record occurrences of electrostatic discharge currents and a read/reset unit;
  • FIG. 5 illustrates an additional example supply clamp circuits that includes memristors to record occurrences of electrostatic discharge currents
  • FIG. 6 illustrates an example device including multiple supply clamp circuits, where at least one of the supply clamp circuits includes a memristor to record occurrences of electrostatic discharge currents;
  • FIG. 7 illustrates an additional example device including multiple supply clamp circuits, where at least one of the supply clamp circuits includes a memristor to record occurrences of electrostatic discharge currents.
  • the present disclosure describes a device that may include a core circuit coupled to a positive supply rail and coupled to a negative supply rail, and a supply clamp circuit to divert an electrostatic discharge current away from the core circuit.
  • the supply clamp circuit is coupled to the positive supply rail and coupled to the negative supply rail, and may include a memristor to record an occurrence of the electrostatic discharge current.
  • the present disclosure describes a supply clamp circuit that may include a first resistor coupled to a first supply rail, a capacitor coupled to a second supply rail, and a memristor in parallel with the resistor and in series with the capacitor, to record an occurrence of the electrostatic discharge current.
  • the present disclosure describes a device that may include a core circuit and a plurality of supply clamp circuits to divert an electrostatic discharge current away from the core circuit.
  • a first supply clamp circuit of the plurality of supply clamp circuits comprises a first memristor to record an occurrence of the electrostatic discharge current.
  • a resistive memory e.g., a passive two-terminal circuit element that maintains a functional relationship between the time integral of current, and the time integral of voltage.
  • a resistive memory can include a two-terminal non-volatile memory device based on resistance switching.
  • additional resistive memory types may comprise: a transistor-less cross point memory, a phase-change memory, and the like.
  • the resistive memory of the present disclosure is not limited by these illustrative examples. In other words, any other types of resistive memories can be used in the present disclosure.
  • Electrostatic discharge may occur without warning and may arise in manufacturing and operating environments. Electrostatic discharge protection circuits have been developed to shunt electrostatic discharge currents away from components in an integrated circuit that would otherwise be damaged by the discharge. However, electrostatic discharge protection circuits may not be totally reliable because electrostatic discharge protection circuits may turn on too late, trigger at a voltage that is too high to protect the integrated circuit, or fail during the occurrence of an electrostatic discharge current. Further, a single electrostatic discharge pulse may be insufficiently strong to damage the integrated circuit, as determined through functional testing of the integrated circuit. But if the integrated circuit is subjected to multiple weak electrostatic discharge pulses, the integrated circuit may be degraded more with each pulse, ultimately resulting in failure. Therefore, it may be beneficial to know when an integrated circuit has experienced an electrostatic discharge event, independent of whether the electrostatic discharge event was strong enough to cause immediately measurable damage.
  • a supply clamp circuit may be used for electrostatic discharge protection as an alternative to, or in addition to other electrostatic discharge protection structures, such as input and output pad electrostatic discharge protection structures.
  • an electrostatic discharge current in an integrated circuit may be detected at a memristor incorporated into a supply clamp circuit.
  • a supply clamp circuit may provide a near- constant voltage across supply rails and may provide a low impedance path for electrostatic discharge currents to flow from the positive supply rail (VDD) to the negative supply rail (V ss ), thereby protecting other components of the integrated circuit. Therefore, an electrostatic discharge current passing through the supply clamp circuit may be detected and recorded via a state change of the memristor.
  • a memristor may switch between two states, such as, a low resistance state (LRS) and a high resistance state (HRS).
  • LRS low resistance state
  • HRS high resistance state
  • a bipolar memristor when a voltage is applied to the memristor in one direction, the memristor is set to the low resistance state, and when voltage is applied to the element in the opposite direction, the memristor is set to the high resistance state.
  • a unipolar memristor when a voltage of a first magnitude is applied to the memristor, the memristor is set to the low resistance state, and when a voltage of a second, different magnitude is applied to the memristor in the same direction, the memristor is set to the high resistance state.
  • an electrostatic discharge current may result in a voltage across the memristor that causes the memristor to change from the low resistance state to the high resistance state.
  • the components such as metal-oxide-semiconductor field effect transistors (MOSFETs), diodes, and the like, may be designed with a relatively large areas to withstand the large power dissipation associated with electrostatic discharge currents. For example, this may be the case with respect to input/output pad electrostatic discharge protection structures.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • the large component sizes may lead to large parasitic capacitances and thus to a degradation in the circuit performance of the core circuit being protected, especially for radio frequency (RF) circuits.
  • RF radio frequency
  • a supply clamp circuit may enable a reduction in size of other electrostatic discharge protection structures within the same device, such as input/output pad electrostatic discharge protection structures.
  • diodes of diode-based input/output pad electrostatic discharge protection structures may be operating in the breakdown region. Therefore, larger size diodes may be used as compared to when the device includes a supply clamp circuit. In other words, a supply clamp circuit may allow the use of smaller diodes and other components in additional portions of the integrated circuit.
  • a memristor for recording electrostatic discharge currents within the supply clamp circuit, this may also reduce the number of structures near the input/output pads, leading to an easier and/or a more space-efficient integrated circuit layout. For instance, placing a memristor- based electrostatic discharge recording circuit in an input/output pad electrostatic discharge protection structure may occupy valuable space in the integrated circuit and lead to an overall increase in size of the device.
  • the purpose of an input/output pad electrostatic discharge protection structure may be to shunt away as quickly as possible an electrostatic discharge current.
  • a memristor may be placed within each input/output pad electrostatic discharge protection structure to detect an electrostatic discharge current for each of the input/output pads.
  • a supply clamp circuit based memristor may detect and record electrostatic discharge currents arising from multiple input/output pads, or from other integrated circuit components from which electrostatic discharge currents are originated.
  • FIG. 1 illustrates a block diagram of example device 100 that includes a memristor to record occurrences of electrostatic discharge currents.
  • the device 100 may comprise an integrated circuit that includes a core circuit 1 10 and a supply clamp circuit 140.
  • the term core circuit is not intended to refer solely to a central processing unit core, but may refer more broadly to any integrated circuit components that are to be protected from electrostatic discharge.
  • the core circuit 1 10 and the supply clamp circuit 140 may be coupled to a positive supply rail 150 and a negative supply rail 160, respectively.
  • the supply clamp circuit 140 may include a memristor 145 to record an occurrence of an electrostatic discharge current.
  • an electrostatic discharge current may be directed to the positive supply rail 150, and through the supply clamp circuit 140 to the negative supply rail 160.
  • the memristor 145 may initially be in a first state having a lower resistance, and may switch to a second state having a higher resistance when a voltage across the memristor 145 is sufficiently large in response to the electrostatic discharge current.
  • the terms "lower” resistance and “higher” resistance are in relation to each other, and may, but do not necessarily indicate any specific resistance values or ranges of resistance values.
  • the memristor 145 may remain in the second state after the electrostatic discharge event occurs.
  • the resistance of the memristor 145 may be read to determine whether the device 100 experienced the electrostatic discharge event. For example, if the resistance of memristor 145 is determined to be the lower resistance, it may be concluded that no electrostatic discharge event occurred. However, if the resistance of the memristor 145 is determined to be the higher resistance, this may be used as an indication that the memristor has experienced an electrostatic discharge event, and thus, that the components of the integrated circuit may have been exposed to the electrostatic discharge current.
  • a read circuit (not shown) may be used to determine the resistance of the memristor 145.
  • the supply clamp circuit 140 may include additional components to shunt an electrostatic discharge current from an additional, subsequent electrostatic discharge event, after an earlier electrostatic discharge event.
  • a resistor may be included in parallel with the memristor 145, where the resistor has a resistance that is lower than the resistance of the second state of the memristor 145, but greater than the resistance of the first state of the memristor 145.
  • the memristor 145 may be reset to the first state with the lower resistance by applying a reset signal. For instance, the device 100 may be placed back into use if it is determined to be functional or is deemed likely to still be functional. However, it may also be determined to discard the device 100. For example, it may be determined that the device 100 is no longer reliable based on the number of electrostatic discharge events recorded for the device 100.
  • FIG. 2 depicts an example device 200 that includes a memristor 245 to record occurrences of electrostatic discharge currents.
  • device 200 may comprise at least a portion of the device 100 of FIG. 1 .
  • device 200 may represent a more detailed depiction of device 100 of FIG. 1 .
  • device 200 includes a core circuit 210, and a supply clamp circuit 240 having the memristor 245 to record at least one occurrence of electrostatic discharge currents.
  • device 200 also includes a positive supply rail 250 coupled to a positive supply voltage pin 251 .
  • the positive supply voltage may be indicated by V D D.
  • Device 200 may further include a negative supply rail 260 coupled to a negative supply voltage pin 261 .
  • the negative supply voltage may be indicated by Vss.
  • V ss may be a ground voltage, such as at or near zero volts.
  • the device 200 may further comprise input/output pads 220 and 221 .
  • input/output pad 220 may comprise an input pad
  • input/output pad 221 may comprise an output pad.
  • either or both of input/output pads 220 and 221 may be used for both input signals and output signals.
  • Diodes 230-233 may form input/output pad electrostatic discharge protection structures for the input/output pads 220 and 221 , respectively.
  • an electrostatic discharge current 290 may appear at input/output pad 220 and may be directed along the path through diode 231 , along positive supply rail 250, through supply clamp circuit 240, and on to the negative supply rail 260.
  • Electrostatic discharge current 290 may comprise a positive current.
  • memristor 245 When the current is passing through supply clamp circuit 240, initially memristor 245 may be in a first state, e.g., a lower resistance state. However, a voltage across the memristor 245 may increase to a sufficient voltage in response to the electrostatic discharge current 290 such that the memristor 245 may be transitioned to a second state having a higher resistance.
  • the second state may be used as an indication that an electrostatic discharge event has been detected. In other words, an electrostatic discharge current of the electrostatic discharge event has been detected and recorded by the memristor 245. In the second state having the higher resistance, memristor 245 may allow less current to pass through. However, other components within the supply clamp 240 continue to shunt energy from the electrostatic discharge current to the negative supply rail 260.
  • the diodes 230 and 231 may form a first electrostatic discharge protection structure for input/output pad 220, and the diodes 232 and 233 may form a second electrostatic discharge protection structure for input/output pad 221 .
  • the diodes 230-233 have positive bias such that signals that are considered to be non-damaging will pass between input/output pads 220 and 221 and core circuit 210, while high current and/or high voltage signals that are considered to be potentially damaging will be directed through diode 231 or diode 233 to the positive supply rail 250. No current will flow directly from the input/output pads 220 and 221 to the negative supply rail 260 due to the positive bias of diodes 230 and 232.
  • the device 200 may also include negative bias input/output pad protection structures for one or both of the input/output pads 220 and 221 .
  • additional diodes with a similar configuration to diodes 230-233 may be provided, albeit with a reverse bias.
  • diodes 230 and 231 , and diodes 232 and 233 represent just one example of input/output pad electrostatic discharge protection structure.
  • device 200 may alternatively or additionally include other input/output pad electrostatic discharge protection structures, such as, silicon controlled rectifier (SCR)-based structures, grounded gate n-type metal-oxide-semiconductor (ggNMOS)-based structures, and so forth.
  • electrostatic discharge protection structures associated with input/output pads 220 and 221 may also include memristor-based recorders for detecting and recording electrostatic discharge currents at the respective input/output pad.
  • memristor 245 in the supply clamp circuit 240 is able to detect and record the occurrences of electrostatic discharge currents arising from both of input/output pads 220 and 221 , as well from other components, such as transients from supply pin 251 , due to the configuration of device 200 and the circuit-wide routing of high current and/or high voltage signals, such as electrostatic discharge current 290, through supply clamp circuit 240.
  • input/output pads 220 and 221 are shown in FIG. 2 for illustrative purposes.
  • device 200 may include more or less input/output pads and associated electrostatic discharge protection structures.
  • FIG. 3 illustrates an example circuit 300, e.g., a supply clamp circuit having a memristor 345 to record at least one occurrence of electrostatic discharge current.
  • the circuit 300 may comprise at least a portion of the device 100 of FIG. 1 or the device 200 of FIG. 2.
  • circuit 300 may represent a more detailed depiction of supply clamp circuit 140 of FIG. 1 or supply clamp circuit 240 of FIG. 2.
  • circuit 300 includes a first supply rail 350, a second supply rail 360, a resistor 341 , a capacitor 342 in series with the resistor 341 between the first supply rail 350 and the second supply rail 360, and a selective discharge unit 346 coupled to the first supply rail 350 and the second supply rail 360.
  • the first supply rail 350 may comprise a positive supply rail and the second supply rail 360 may comprise a negative supply rail.
  • the first supply rail 350 may comprise a negative supply rail and the second supply rail 360 may comprise a positive supply rail.
  • the selective discharge unit 346 may present a high impedance state, when little to no current is flowing between the first supply rail 350 and the second supply rail 360, and a low impedance state, where current is allowed to flow between the first supply rail 350 and the second supply rail 360.
  • the selection of the high impedance state or the low impedance state may be controlled by a voltage at the control node 344, where the control node 344 is coupled to the selective discharge unit 346.
  • Circuit 300 may further include the memristor 345 in parallel with the resistor 341 and in series with the capacitor 342.
  • the functioning of circuit 300 is now described in connection with an example of an electrostatic discharge current on the first supply rail 350.
  • the first supply rail 350 may be considered to be a positive supply rail.
  • a voltage potential difference between the first supply rail 350 and the second supply rail 360 causes the capacitor 342 to be charged and results in a first voltage at the control node 344.
  • Memristor 345 may initially be in a first state having a lower resistance. However, in one example, this resistance of the first state of the memristor 345 may be greater than the resistance of resistor 341 .
  • the electrostatic discharge current When the electrostatic discharge current is presented on the first supply rail 350, the effective current through resistor 341 and memristor 345 increases.
  • the voltage at control node 344 may also increase.
  • the memristor 345 When the voltage at control node 344 is sufficiently high, the memristor 345 may switch to a second state having a higher resistance as compared to the lower resistance of the first state.
  • the increased voltage at control node 344 may turn on the selective discharge unit 346.
  • the selective discharge unit may take the form of an n-type transistor or other configuration, such as illustrated in the examples of FIG. 5.
  • the selective discharge unit 346 when the selective discharge unit 346 is turned on, it provides a low impedance path from the first supply rail 350, which may comprise a positive supply rail, to the second supply rail 360, which may comprise a negative supply rail, or ground. Thus, the electrostatic discharge current is shunted through the selective discharge unit 346.
  • the second state of memristor 345 may be used an indication that electrostatic discharge current has been detected, and that an electrostatic discharge event has therefore occurred.
  • FIG. 4 illustrates an example circuit 400, e.g., a supply clamp circuit having a memristor 445 to record at least one occurrence of electrostatic discharge currents.
  • the circuit 400 may comprise at least a portion of the device 100 of FIG. 1 or the device 200 of FIG. 2.
  • circuit 400 may represent a more detailed depiction of supply clamp circuit 140 of FIG. 1 or supply clamp circuit 240 of FIG. 2.
  • circuit 400 may represent a more detailed depiction of the circuit 300 of FIG. 3. As illustrated in FIG.
  • circuit 400 includes a first supply rail 450, a second supply rail 460, a resistor 441 , a capacitor 442 in series with the resistor 441 between the first supply rail 450 and the second supply rail 460, and a selective discharge unit 446.
  • the first supply rail 450 may comprise a positive supply rail and the second supply rail 460 may comprise a negative supply rail.
  • the first supply rail 450 may comprise a negative supply rail and the second supply rail 460 may comprise a positive supply rail.
  • the selective discharge unit 446 may present a high impedance state, when little to no current is flowing between the first supply rail 450 and the second supply rail 460, and a low impedance state, where current is allowed to flow between the first supply rail 450 and the second supply rail 460.
  • the selection of the high impedance state or the low impedance state may be controlled by a voltage at the control node 444.
  • circuit 400 further includes a memristor 445 coupled to a read/reset unit 470.
  • the read/reset unit 470 may include circuitry to effectively couple the memristor 445 to control node 444 and to the second supply rail 460 with low impedances and to present high impedances between the memristor 445 and the positive supply rail 450, and between the memristor 445 and a first set/reset line 471 , a second set/reset line 472, a read line 478, and a read output line 479.
  • this arrangement may be implemented when circuit 400 is to be used for electrostatic discharge current detection and recording.
  • a read signal may be provided on read line 478.
  • the read/reset unit 470 may compare a voltage across the memristor 445, or in some cases across the memristor 445 and one or more other components, to a reference voltage, where the voltage is indicative of whether the memristor 445 has the higher resistance, and thus is in the second state, or whether the memristor 445 has the lower resistance, and is therefore in the first state.
  • the memristor 445 may also be set or reset by a signal, or signals, via one or both of the first set/reset line 471 and the second set/reset line 472.
  • a first signal or pair of signals may cause a relatively higher voltage to be applied across memristor 445 to place the memristor 445 in the second state having the higher resistance
  • a second signal or pair of signals may cause a relatively lower voltage to be applied across memristor 445 to place the memristor 445 in the first state having the lower resistance.
  • the relatively lower voltage may comprise a negative voltage and/or a reverse bias across memristor 445.
  • the state of memristor 445 may be read to indicate whether an electrostatic discharge current was detected, and the memristor 445 may then be placed back into any state.
  • memristor 445 may be set or reset back to the first state for continued operation of circuit 400 to detect and record subsequent electrostatic discharge currents.
  • FIG. 5 illustrates example circuits 51 0, 520, 530, and 540, e.g., supply clamp circuits including memristors to record electrostatic discharge events.
  • the circuits 51 0, 520, 530, and 540 may respectively comprise at least a portion of the device 1 00 of FIG. 1 or device 200 of FIG. 2.
  • circuits 51 0, 520, 530, and 540 may respectively represent examples of more detailed depictions of supply clamp circuit 1 40 of FIG. 1 or supply clamp circuit 240 of FIG. 2.
  • circuits 51 0, 520, 530, and 540 may represent examples of more detailed depictions of the circuit 300 of FIG. 3 and/or the circuit 400 of FIG. 4.
  • the example circuit 51 0 includes a positive supply rail 51 2, a negative supply rail 51 1 , a resistor 51 3, and a capacitor 514 in series with the resistor 51 3 between the positive supply rail 512 and the negative supply rail 51 1 as shown.
  • Circuit 51 0 may also include an n-type transistor 51 6 with a source coupled to the negative supply rail 51 1 and with a drain coupled to the positive supply rail 512.
  • n-type transistor 51 6 may comprise the selective discharge unit 346 of FIG. 3 and/or the selective discharge unit 446 of FIG. 4.
  • a voltage at the control node 51 7 may control the gate of the n-type transistor 51 6.
  • Circuit 51 0 may also include a memristor 51 5 in parallel with the resistor 51 3 and in series within the capacitor 514, where the memristor 51 5 is coupled to the negative supply rail 51 1 and to the control node 51 7.
  • the memristor 51 5 may initially be in a first state, such as a lower resistance state.
  • circuit 51 0 The functioning of circuit 51 0 is now described in connection with an example of an electrostatic discharge current on the positive supply rail 512.
  • the electrostatic discharge current is presented on the positive supply rail 512
  • the effective current through resistor 513 and memristor 515 increases.
  • the voltage at control node 517 may also increase.
  • the memristor 515 may switch to a second state having a higher resistance as compared to the lower resistance of the first state. Although less current will flow through the memristor 515 in the second state, a current may still flow through the resistor 513.
  • the increased voltage at control node 517 may turn on the n-type transistor 516.
  • the n-type transistor 516 When turned on, the n-type transistor 516 may provide a low impedance path between the positive supply rail 512 and the negative supply rail 51 1 . As such, a majority of the electrostatic discharge current will be shunted through the n-type transistor 516.
  • the second state of memristor 515 may be used as an indication that an electrostatic discharge current has been detected, and that an electrostatic discharge event has therefore occurred.
  • circuit 520 may comprise a complimentary metal-oxide-semiconductor (CMOS) inverter-based supply clamp circuit with a memristor 525 to detect and to record an electrostatic discharge current.
  • circuit 520 may include similar components to circuit 510, such as a positive supply rail 522, a negative supply rail 521 , a resistor 523, and a capacitor 524 in series with the resistor 523 between the positive supply rail 522 and the negative supply rail 521 as shown.
  • CMOS complimentary metal-oxide-semiconductor
  • Circuit 520 may also include the memristor 525 in series with the capacitor 524 and in parallel with the resistor 523, where the memristor 525 is coupled to the negative supply rail 521 and to the control node 527.
  • the orientation of the capacitor 524, the resistor 523, and the memristor 525 are reversed with respect to the positive supply rail 522 and negative supply rail 521 as compared to the circuit 510.
  • the functioning of memristor 525 is similar to the example memristor 515 of circuit 510. For instance, memristor 525 may be switched from a first state having a lower resistance to a second state having a higher resistance relative to the first state when an electrostatic discharge current is processed via the circuit 520.
  • control node 527 of circuit 520 is similar to the control node 517 of circuit 510. However, control node 527 controls the gates of a p-type transistor 527 and an n-type transistor 528. In one example, p-type transistor
  • n-type transistor 528 may collectively comprise an inverter.
  • the respective drains of p-type transistor 529 and n-type transistor 528 are tied together and control a gate of n-type transistor 526.
  • N-type transistor 526 is coupled to the positive supply rail 522 and the negative supply rail 521 via its drain and its source respectively.
  • p-type transistor 529, n-type transistor 528, and n-type transistor 526 may comprise the selective discharge unit 346 of FIG. 3 and/or the selective discharge unit 446 of FIG. 4, and may provide a path to shunt an electrostatic discharge current from the positive supply rail 522 to the negative supply rail 521 when turned on in response to an electrostatic discharge current.
  • FIG. 5 illustrates a further example circuit 530.
  • circuit 530 circuit
  • circuit 530 may comprise a bipolar junction transistor (BJT)-based supply clamp circuit with a memristor 535 to detect and to record an electrostatic discharge current.
  • Circuit 530 may include similar components to circuits 510 and 520.
  • circuit 530 includes a positive supply rail 532, a negative supply rail 531 , a resistor 533, and a capacitor 534 in series with the resistor 533 between the positive supply rail 532 and the negative supply rail
  • Circuit 530 may also include the memristor 535 in series with the capacitor 534 and in parallel with the resistor 533, where the memristor 535 is coupled to the negative supply rail 531 and to the control node 537.
  • the functioning of memristor 535 is similar to the example memristors 515 and 525 of circuits 510 and 520, respectively. For instance, memristor 535 may be switched from a first state having a lower resistance to a second state having a higher resistance relative to the first state when an electrostatic discharge current is processed via the circuit 530.
  • the control node 537 of circuit 530 is similar to the control nodes 517 and 527 of circuits 510 and 520, respectively. However, control node 537 controls the bulk of a bipolar junction transistor 539.
  • the bipolar junction transistor 539 is an NPN-type device with collector coupled to the positive supply rail 532 and emitter coupled to a resistor 538 and to a bulk of another bipolar junction transistor 536. As shown in FIG. 5, the resistor 538 is further coupled to the negative supply rail 531 , the collector of bipolar junction transistor 536 is coupled to the positive supply rail 532, and the emitter of bipolar junction transistor 536 is coupled to the negative supply rail 531 .
  • the bipolar junction transistor 539, the resistor 538, and the bipolar junction transistor 536 may comprise the selective discharge unit 346 of FIG. 3 and/or the selective discharge unit 446 of FIG. 4, and may provide a path to shunt an electrostatic discharge current from the positive supply rail 532 to the negative supply rail 531 when turned on in response to an electrostatic discharge current.
  • FIG. 5 illustrates a further example circuit 540.
  • circuit 540 may comprise a silicon controlled rectifier-based supply clamp circuit with a memristor 545 to detect and to record an electrostatic discharge current.
  • Circuit 540 may comprise a silicon controlled rectifier-based supply clamp circuit with a memristor 545 to detect and to record an electrostatic discharge current.
  • circuit 540 may include similar components to circuits 510, 520, and 530.
  • circuit 540 includes a positive supply rail 542, a negative supply rail 541 , a resistor 543, and a capacitor 544 in series with the resistor 543 between the positive supply rail 542 and the negative supply rail
  • capacitor 544 may comprise a drain- source shorted field effect transistor (FET). However, in other examples, the capacitor 544 may have a different form.
  • Circuit 540 may also include a memristor 545 in series with the capacitor 544 and in parallel with the resistor 543, where the memristor 545 is coupled to the negative supply rail 541 and to the control node 547.
  • the functioning of memristor 545 is similar to the example memristors 515, 525, and 535 of circuits 510, 520, and 530, respectively. For instance, memristor 545 may be switched from a first state having a lower resistance to a second state having a higher resistance relative to the first state when an electrostatic discharge current is processed via the circuit 540.
  • circuit 540 further includes a silicon controlled rectifier 546 coupled to the positive supply rail 542 and the negative supply rail 541 .
  • the silicon controlled rectifier 546 may comprise an NPNP-type device.
  • the silicon controlled rectifier 546 may comprise a low voltage threshold silicon controlled rectifier (LVTSCR). Starting from a cathode end toward an anode end, the silicon controlled rectifier 546 includes a p-region 571 , an n-region 572, a p-region 573, and an n-region 574.
  • LVTSCR low voltage threshold silicon controlled rectifier
  • the control node 547 of circuit 540 is similar to the control nodes 517, 527, and 537 of circuits 510, 520, and 530, respectively. However, the control node 547 controls the gate of the silicon controlled rectifier 546. Silicon controlled rectifier 546 may comprise the selective discharge unit 346 of FIG. 3 and/or the selective discharge unit 446 of FIG. 4, and may provide a path to shunt an electrostatic discharge current from the positive supply rail 542 to the negative supply rail 541 when turned on in response to an electrostatic discharge current.
  • FIG. 6 illustrates an example device 600 of the present disclosure.
  • the device 600 may comprise an integrated circuit that includes a positive supply rail 650, a negative supply rail 660, a core circuit 610, and supply clamp circuits 640, 670, and 680.
  • Supply clamp circuits 640, 670, and 680 may have a similar structure, or may have different structures.
  • supply clamp circuits, 640, 670, and 680 may all have a structure similar to circuit 530 of FIG. 5.
  • the supply clamp circuit 640 may have a structure similar to circuit 520 of FIG. 5, while supply clamp circuit 680 may have a structure similar to circuit 540 of FIG. 5, and so forth. As shown in FIG.
  • the supply clamp circuit 640 and the supply clamp circuit 680 include memristors 645 and 685, respectively, to detect and to record electrostatic discharge currents.
  • supply clamp circuit 670 does not include a memristor.
  • three supply clamp circuits are shown in the device 600, it should be appreciated that the device 600 may be modified or expanded to include more or less supply clamp circuits, some of which may include memristors to detect and to record electrostatic discharge events, and some of which may not include memristors.
  • device 600 may include at least one supply clamp circuit having a memristor to detect and to record at least one electrostatic discharge event, and at least one supply clamp circuit without a similar memristor.
  • FIG. 7 illustrates an example device 700 of the present disclosure.
  • device 700 may comprise at least a portion of the device 600 of FIG. 6.
  • device 700 may represent a more detailed depiction of device 600 of FIG. 6.
  • the device 700 may comprise an integrated circuit that includes a core circuit 710, a positive supply rail 750, a negative supply rail 760, and a plurality of supply clamp circuits 740. All or a portion of the supply clamp circuits 740 may include a respective memristor 745 to detect and to record electrostatic discharge currents.
  • device 700 may also include a positive supply pad 751 , a negative supply pad 752, and a plurality of input/output pads 720.
  • each of the input/output pads 720 is associated with a respective electrostatic discharge protection structure comprising a pair of diodes 730.
  • the diodes 730 in device 700 are illustrated as having a forward, or positive bias.
  • device 700 may also include reverse, or negative bias diode pairs to provide additional protection to the input/output pads 720.
  • positive supply pad 751 is also protected by a pair of diodes 731 with a forward bias.
  • negative supply pad 752 may be protected by a pair of diodes 732 with reverse, or negative bias.
  • circuit 700 is now described in connection with an example of an electrostatic discharge current on one of the input/output pads 720.
  • the pair of diodes 730 associated with the one of the input/output pad 720 will shunt the electrostatic discharge current away from the core circuit 710 and direct the electrostatic discharge current to the positive supply rail 750.
  • the current may flow along the positive supply rail 750 to the respective supply clamp circuit 740.
  • Selective discharge units within each supply clamp circuit 740 may be turned on to provide a low impedance path for the electrostatic discharge current to flow from the positive supply rail 750 to the negative supply rail 760.
  • 5 may further include read-reset circuitry, such as illustrated in FIG. 4, for reading and resetting memristors embedded therein.
  • device 200 of FIG. 2 or device 700 of FIG. 7 may omit diode pairs associated with each input/output pad, or may use another electrostatic discharge protection structure, such as grounded gate n- type metal-oxide-semiconductor-based structures, silicon controlled rectifier- based structures, and so forth.
  • Other modifications of a similar nature may be made in accordance with the present disclosure.
  • variants of the above- disclosed and other features and functions, or alternatives thereof, may be omitted, or may be combined or altered into many other different systems or applications.

Abstract

Dans un exemple, l'invention concerne un dispositif qui comprend un circuit central, couplé à un pôle d'alimentation positif et couplé à un pôle d'alimentation négatif, et un circuit de fixation de niveau d'alimentation pour détourner un courant de décharge électrostatique au loin du circuit central. Dans un exemple, le circuit de fixation de niveau d'alimentation est couplé au pôle d'alimentation positif et au pôle d'alimentation négatif, et comprend une memristance pour enregistrer une occurrence du courant de décharge électrostatique. Dans un autre exemple, le circuit de fixation de niveau d'alimentation comprend une première résistance couplée à un premier pôle d'alimentation, un condensateur couplé à un second pôle d'alimentation et une memristance en parallèle avec la résistance et en série avec le condensateur, pour enregistrer une occurrence du courant de décharge électrostatique.
PCT/US2015/046112 2015-08-20 2015-08-20 Circuits de fixation de niveau d'alimentation à memristances WO2017030591A1 (fr)

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CN109193601A (zh) * 2018-09-25 2019-01-11 华为技术有限公司 一种esd保护电路
CN109727798A (zh) * 2017-10-27 2019-05-07 西华大学 一种地铁绝缘结灭弧装置
WO2023147817A1 (fr) * 2022-02-02 2023-08-10 Schaeffler Technologies AG & Co. KG Circuit de décharge, circuit onduleur, dispositif d'entraînement électrique et procédé de détermination d'un état de vieillissement d'un circuit de décharge

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CN109727798A (zh) * 2017-10-27 2019-05-07 西华大学 一种地铁绝缘结灭弧装置
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