WO2017028343A1 - 一种源极驱动电路 - Google Patents

一种源极驱动电路 Download PDF

Info

Publication number
WO2017028343A1
WO2017028343A1 PCT/CN2015/088963 CN2015088963W WO2017028343A1 WO 2017028343 A1 WO2017028343 A1 WO 2017028343A1 CN 2015088963 W CN2015088963 W CN 2015088963W WO 2017028343 A1 WO2017028343 A1 WO 2017028343A1
Authority
WO
WIPO (PCT)
Prior art keywords
driving circuit
pixel
source driving
output
grayscale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/088963
Other languages
English (en)
French (fr)
Inventor
郭星灵
安泰生
李曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/893,095 priority Critical patent/US10008146B2/en
Publication of WO2017028343A1 publication Critical patent/WO2017028343A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a source driving circuit.
  • the source driving circuit 10 includes a shift register 11, a first latch (Latch) 12, a second latch 13, and a level shifter 14 (Level) corresponding to each data channel. Shifter), Digital Analog Converter (DAC) 15, Output Buffer 16 (Output Buffer).
  • the shift register 11 is electrically connected to the first latches 12 of the plurality of data channels, respectively, the shift register 11 sequentially gates the first latch 11 of one data channel, and transmits the data signals to the corresponding data. on-line.
  • the first latches 12 of the first data channel D1 are respectively connected to the second latch 13 of the first data channel D1, and the second lock of the second data channel D2.
  • the memory 13 is connected, and the first latch 12 of the second data signal D2 is connected to the second latch 13 of the first data signal D1 and to the second latch 13 of the second data signal D2, respectively.
  • the second latch 13 of each data channel is electrically connected in turn by a level shifter 14, a digital to analog converter 15, and an output buffer 16.
  • the output buffer 16 of the first data channel D1 is electrically connected to the output end of the second data channel D2 and the output end of the first data channel D1, respectively, and the output buffer 16 of the second data channel D2 and the second data channel D2 are respectively The output is electrically connected to the output of the first data channel D1.
  • white gray scale data 21 and red gray scale are outputted on the left data channel.
  • Data 22, blue grayscale data 23, green grayscale data 24 (that is, a 1:4 structure), white grayscale data 26, red grayscale data 27, and blue grayscale data 28 are output on the right data channel.
  • the blue pixel 32, the red pixel 33, and the white pixel 34; the green grayscale data 29, the blue grayscale data 28, the red grayscale data 27, and the white grayscale data 26 are respectively input to the right data line on the display panel 30.
  • Green pixel 35, blue a pixel 36, a red pixel 37, and a white pixel 38 can reduce the number of data channels, since a plurality of grayscale values are input on one data line, when the grayscale difference between two adjacent pixels is large, Lead to higher power consumption.
  • a source driving circuit which includes:
  • a digital-to-analog conversion module configured to convert raw image data into grayscale image data, where the grayscale image data includes input grayscale values of all of the pixels; wherein the source driving circuit inputs the original image data;
  • An optimization module configured to obtain an optimal output order of grayscale values of pixels in each row of pixel units on the display panel; and sort the grayscale values of the pixels in the pixel unit corresponding to the data line according to the optimal output
  • the order is output to form first image data, which includes:
  • a gray-scale obtaining unit configured to acquire a grayscale value of each pixel in each of the pixel units corresponding to the data line
  • a display order setting unit configured to set a display order of the pixel units corresponding to each of the data lines according to an order of grayscale values acquired by the grayscale acquiring unit from large to small or from small to large to obtain a plurality of displays Order;
  • An energy consumption value obtaining unit configured to sequentially calculate an energy consumption value of the entire display panel by using each of the display sequences of the display order setting unit to obtain a plurality of energy consumption values; and to minimize the energy consumption value
  • the display order is set to the optimal output ordering; wherein the display panel includes a plurality of the data lines and a plurality of the pixel units, the pixel units including pixels of at least three colors;
  • the buffer module configured to increase load driving capability of the first image data output by the optimization module, and input the same to the pixel
  • the buffer module includes a plurality of output buffers corresponding to the data lines; An output of an output buffer of any one of the data lines is connected to an output of an output buffer of the remaining one of the data lines.
  • the energy consumption value is an average value of a difference between grayscale values of adjacent two pixels of the entire display panel.
  • the energy consumption value acquiring unit is specifically configured to:
  • the source driving circuit further includes a latching module, the latching module including a plurality of latches corresponding to the data lines, the latches being used for the original The image data is stored; the output of the latch of any one of the two of the data lines is connected to the output of the latch of the remaining one of the data lines.
  • the source driving circuit further includes a level converting module, the level converting module including a plurality of level shifters corresponding to the data lines, the level shifters being used The voltage of the original image data stored by the latch is boosted.
  • the digital-to-analog conversion module is further configured to convert raw image data after voltage boosting by the level shifter into grayscale image data.
  • pixels of the same color in the pixel unit of each row simultaneously receive corresponding grayscale values.
  • the pixel unit includes a red pixel, a green pixel, a blue pixel, and a white pixel.
  • a source driving circuit which includes:
  • a digital-to-analog conversion module configured to convert raw image data into grayscale image data, where the grayscale image data includes input grayscale values of all of the pixels; wherein the source driving circuit inputs the original image data;
  • An optimization module configured to obtain an optimal output order of grayscale values of pixels in each row of pixel units on the display panel; and sort the grayscale values of the pixels in the pixel unit corresponding to the data line according to the optimal output And outputting to form first image data; wherein the display panel includes a plurality of the data lines and a plurality of the pixel units, the pixel units including pixels of at least three colors;
  • a buffer module configured to increase load driving capability of the first image data output by the optimization module, and input the same to the pixel.
  • the optimization module includes:
  • a gray-scale obtaining unit configured to acquire a grayscale value of each pixel in each of the pixel units corresponding to the data line
  • a display order setting unit configured to set a display order of the pixel units corresponding to each of the data lines according to an order of grayscale values acquired by the grayscale acquiring unit from large to small or from small to large to obtain a plurality of displays order;
  • An energy consumption value obtaining unit configured to sequentially calculate an energy consumption value of the entire display panel by using each of the display sequences of the display order setting unit to obtain a plurality of energy consumption values; and to minimize the energy consumption value
  • the display order is set to the optimal output ordering.
  • the energy consumption value is an average value of a difference between grayscale values of adjacent two pixels of the entire display panel.
  • the energy consumption value acquiring unit is specifically configured to:
  • the buffer module includes a plurality of output buffers corresponding to the data lines; an output of an output buffer of any one of the two data lines Connected to the output of the output buffer on the remaining one of the data lines.
  • the source driving circuit further includes a latching module, the latching module including a plurality of latches corresponding to the data lines, the latches being used for the original The image data is stored; the output of the latch of any one of the two of the data lines is connected to the output of the latch of the remaining one of the data lines.
  • the source driving circuit further includes a level converting module, the level converting module including a plurality of level shifters corresponding to the data lines, the level shifters being used The voltage of the original image data stored by the latch is boosted.
  • the digital-to-analog conversion module is configured to convert raw image data after voltage boosting by the level shifter into grayscale image data.
  • pixels of the same color in the pixel unit of each row simultaneously receive corresponding grayscale values.
  • the pixel unit includes a red pixel, a green pixel, a blue pixel, and a white pixel.
  • the source driving circuit of the present invention optimizes the output order of the gray scale data of the existing source driving circuit, thereby reducing the power consumption of the display panel and saving the production cost.
  • FIG. 1 is a schematic structural view of a source driving circuit of the prior art
  • FIG. 2 is a schematic diagram of driving of a source driving circuit of the prior art
  • FIG. 3 is a schematic structural diagram of a source driving circuit according to a first embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an optimization module in a driving circuit of the present invention.
  • FIG. 5 is a schematic diagram of driving of a source driving circuit of the present invention.
  • FIG. 6 is a schematic structural diagram of a source driving circuit according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a source driving circuit according to a first embodiment of the present invention.
  • the source driving circuit application and display panel of the present invention wherein the display panel comprises a plurality of data lines for inputting data signals; a plurality of scanning lines for inputting scanning signals; and a plurality of pixel units, the data A line and the scan line are defined to form, and the pixel unit includes pixels of at least three colors.
  • the pixel unit includes a red pixel, a green pixel, and a blue pixel, and may further include a white pixel.
  • the source driving circuit includes: a digital-to-analog conversion module 51, an optimization module 52, and a buffer module 53;
  • the source driving circuit is configured to input the original image data;
  • the digital-to-analog conversion module 51 is configured to convert raw image data into grayscale image data, where the grayscale image data includes input grayscales of all the pixels. Value (grayscale voltage); converting raw digital image data into analog grayscale voltage;
  • the optimization module 52 acquires an optimal output order of the grayscale values of the pixels in each row of pixel units on the display panel; and the grayscale values of the pixels in the pixel unit corresponding to the data lines are in accordance with the optimal Outputting the order of sorting to output to form first image data;
  • the buffer module 53 increases the load driving capability of the first image data output by the optimization module 52 and inputs it into the pixel.
  • the optimal output order is obtained for each of the three or four gray scale values outputted by the source driving circuit, and the optimal incremental or descending order is obtained, so that the voltage difference of the source driving chip is minimized. , thereby reducing the power consumption of the display panel.
  • the optimization module 52 includes a grayscale acquisition unit 61, a display order setting unit 62, and an energy consumption value acquisition unit 63;
  • the grayscale obtaining unit 61 is configured to acquire a grayscale value of each pixel in each row of the pixel unit corresponding to the data line;
  • the display order setting unit 62 is configured to set the display order of the pixel units corresponding to each of the data lines in order of the gray scale values acquired by the gray scale acquiring unit from large to small or from small to large. Display order;
  • the energy consumption value obtaining unit 63 is configured to sequentially calculate an energy consumption value of the entire display panel by using each of the display sequences of the display order setting unit to obtain a plurality of energy consumption values; The display order with the smallest value is set to the optimal output ordering.
  • the energy consumption value is an average value of a difference between grayscale values of adjacent two pixels of the entire display panel.
  • the energy consumption value obtaining unit 63 is specifically configured to: sequentially use the display order to calculate an average value of differences between grayscale values of adjacent two pixels in each row of the pixel unit to obtain An average of the difference between the grayscale values of the adjacent two pixels of the entire display panel.
  • the pixels of the same color in the same row of pixel units on the display panel 30 are controlled by the same signal, so that pixels of the same color in the pixel unit of each row simultaneously receive corresponding grayscale values.
  • the switch of the first row 41 is turned on, and the green pixel 31 or 35 of the pixel unit of the first row receives the gray scale data of the G on the data line 45 or the data line 46;
  • the switch of the second row 42 When the red gray scale data arrives, the switch of the second row 42 is turned on, and the red pixel 32 or 36 of the pixel unit of the first row receives the gray scale data of R on the data line 45 or the data line 46, and the switches of the remaining rows are similar. .
  • the four RGBW data cooperation switches sequentially output gray scale data of G, gray scale data of B, gray scale data of R, W Gray scale data;
  • the gray scale acquiring unit 61 respectively obtains the grayscale value of the pixel 31-32 corresponding to the data line 45 and the grayscale value of the pixel 35-38 corresponding to the data line 46; for example, the output of the data line 45
  • the R gray scale is 255
  • the gray scale of G is 0,
  • the gray scale of B is 255
  • the R gray scale of the data line 46 is 125
  • the gray scale of G is 75
  • the gray scale of B is 200, and then the display is performed.
  • the sequence setting unit 62 sorts according to the gray scale value from small to large or from small to small, the data line 45 first outputs 0 gray scale G, then outputs 225 gray scale B, and then outputs 255 gray scale R; The display order of the pixel units corresponding to the data lines 45 is output in the order of GBR.
  • the data line 46 first outputs 75 gray scale G, then outputs 125 gray scale R, and then outputs 200 gray scale B; the display order of the pixel units corresponding to the data line 46 is output in the order of GRB, thereby obtaining two Display order GBR, GRB;
  • the energy consumption value obtaining unit 63 calculates the energy consumption values of the display order GBR and the GRB, respectively:
  • the grayscale value of the adjacent two pixels of each row of pixel units in the display order GRB is calculated, and then the grayscale values of the adjacent two pixels in all the row of pixel units are calculated, that is, the adjacent two pixels of the entire panel display panel
  • the average of the differences between the grayscale values which is called the energy consumption value.
  • the display order corresponding to the smallest one of the energy consumption values is taken as the order of outputting all the data lines.
  • the buffer module 53 includes a plurality of output buffers corresponding to the data lines; as shown in FIG. 5, the data lines 45 are connected with a first output buffer 47, and the data line 46 is connected with a second An output buffer 48; the first output buffer 47 is, for example, a positive polarity buffer, and the second output buffer 48 is, for example, a negative polarity buffer, and is described in any one of every two of the data lines
  • the output of the output buffer on the data line is coupled to the output of the output buffer on the remaining one of the data lines.
  • the first output buffer 47 is connected to the output ends of the data line 45 and the data line 46; the second output buffer 48 is connected to the output ends of the data line 46 and the data line 45, which can save the source driving circuit. Drive line.
  • the difference between the three or four grayscale values outputted by the source driver circuit is compared, and the optimal incremental or descending order is obtained, so that the voltage difference of the source driver chip is minimized. This reduces the power consumption of the display panel.
  • FIG. 6 is a schematic structural diagram of a source driving circuit according to a second embodiment of the present invention.
  • the source driving circuit further includes a latch module 54 and a level converting module 55;
  • the latch module 54 includes a plurality of latches corresponding to the data lines, the latches for storing the original image data; any one of the two data lines on the data line The output of the latch is coupled to the output of the latch of the remaining one of the data lines.
  • the level conversion module 55 includes a plurality of level shifters corresponding to the data lines, and the level shifters are used to boost the voltage of the original image data stored by the latches;
  • the digital-to-analog conversion module 51 is further configured to convert the original image data after the voltage boosting by the level converter into grayscale image data.
  • the source driving circuit of the present invention optimizes the output order of the gray scale data of the existing source driving circuit, thereby reducing the power consumption of the display panel and saving the production cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种源极驱动电路，包括：数模转换模块(51)，用于将原始图像数据转换为灰阶图像数据；优化模块(52)，用于获取显示面板上的每行像素单元中像素的灰阶值的最优输出排序，并将数据线对应的像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据；缓冲模块(53)，用于提高所述优化模块(52)输出的第一图像数据的负载驱动能力。采用上述源极驱动电路的显示面板能够降低功耗。

Description

一种源极驱动电路 技术领域
本发明涉及显示器技术领域，特别是涉及一种源极驱动电路。
 背景技术
图1给出了现有技术中液晶显示面板的源极驱动电路的示意图，图中仅示出多个数据通道D1-DN的源极驱动电路。如图1所示，该源极驱动电路10包括移位寄存器11、对应于每个数据通道上的第一锁存器(Latch)12、第二锁存器13、电平转换器14(Level Shifter)、数模转换器(Digital Analog Converter，DAC)15、输出缓冲器16(Output Buffer)。具体地，移位寄存器11分别与多个数据通道的第一锁存器12电连接，移位寄存器11依次选通一个数据通道的第一锁存器11，并将数据信号传输到相应的数据线上。以第一和第二数据通道为例，第一数据通道D1的第一锁存器12分别与第一数据通道D1的第二锁存器13连接，以及与第二数据通道D2的第二锁存器13连接，第二数据信号D2的第一锁存器12分别与第一数据信号D1的第二锁存器13连接，以及与第二数据信号D2的第二锁存器13连接。
每路数据通道的第二锁存器13依次通过电平转换器14、数模转换器15和输出缓冲器16电连接。第一数据通道D1的输出缓冲器16分别与第二数据通道D2的输出端和第一数据通道D1的输出端电连接，第二数据通道D2的输出缓冲器16分别与第二数据通道D2的输出端和第一数据通道D1的输出端电连接。
随着技术的发展，为了提升数据转换速率，在同一根数据通道上，先后输出三个或四个数据，如图2所示，左侧的数据通道上输出白色灰阶数据21、红色灰阶数据22、蓝色灰阶数据23、绿色灰阶数据24（也就是1：4的结构），右侧的数据通道上输出白色灰阶数据26、红色灰阶数据27、蓝色灰阶数据28、绿色灰阶数据29，随着显示面板30上的通道41、42、43、44的开关的先后开启和关闭，四个RGBW数据配合开关依次输出G、B、R、W数据；就可以将相应的数据送到了对应的像素上，即将绿色灰阶数据24、蓝色灰阶数据23、红色灰阶数据22、白色灰阶数据21分别输入显示面板30上左侧数据线对应的绿色像素31、蓝色像素32、红色像素33、白色像素34；将绿色灰阶数据29、蓝色灰阶数据28、红色灰阶数据27、白色灰阶数据26分别输入显示面板30上右侧数据线对应的绿色像素35、蓝色像素36、红色像素37、白色像素38；这种电路虽然能够减少数据通道的数量，但由于一条数据线上输入多个灰阶值，当相邻两个像素的灰阶差值较大时，导致功耗较大。
因此，有必要提供一种源极驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种源极驱动电路，以解决现有技术的源极驱动电路在一个数据通道上输出多个灰阶数据时，功耗较大的技术问题。
 技术解决方案
为解决上述技术问题，本发明构造了一种源极驱动电路，其包括：
数模转换模块，用于将原始图像数据转换为灰阶图像数据，所述灰阶图像数据包括全部所述像素的输入灰阶值；其中所述源极驱动电路输入有所述原始图像数据；
优化模块，用于获取显示面板上的每行像素单元中像素的灰阶值的最优输出排序；并将数据线对应的所述像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据，其包括：
灰阶获取单元，用于获取所述数据线对应的每行所述像素单元中各像素的灰阶值；
显示顺序设置单元，用于按所述灰阶获取单元获取的灰阶值从大到小或者从小到大的顺序，设置每条所述数据线对应的像素单元的显示顺序，以获得多个显示顺序；以及
能量消耗值获取单元，用于依次使用所述显示顺序设置单元的每个所述显示顺序，计算整个所述显示面板的能量消耗值，以获取多个能量消耗值；将所述能量消耗值最小的所述显示顺序设置为所述最优输出排序；其中所述显示面板包括多条所述数据线以及多个所述像素单元，所述像素单元包括至少三种颜色的像素；以及
缓冲模块，用于提高所述优化模块输出的第一图像数据的负载驱动能力，并将其输入到所述像素，所述缓冲模块包括多个与所述数据线对应的输出缓冲器；每两条所述数据线中任意一条所述数据线上的输出缓冲器的输出端与其余一条所述数据线上的输出缓冲器的输出端连接。
在本发明的源极驱动电路中，所述能量消耗值为整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
在本发明的源极驱动电路中，所述能量消耗值获取单元具体用于：
依次使用所述显示顺序，计算每行所述像素单元中相邻两个像素的灰阶值之间的差值的平均值，以获取整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
在本发明的源极驱动电路中，所述源驱动电路还包括锁存模块，所述锁存模块包括多个与所述数据线对应的锁存器，所述锁存器用于对所述原始图像数据进行存储；每两条所述数据线中任意一条所述数据线上的锁存器的输出端与其余一条所述数据线上的锁存器的输出端连接。
在本发明的源极驱动电路中，所述源驱动电路还包括电平转换模块，所述电平转换模块包括多个与所述数据线对应的电平转换器，所述电平转换器用于提升所述锁存器存储的原始图像数据的电压。
在本发明的源极驱动电路中，所述数模转换模块，还用于将经过所述电平转换器进行电压提升后的原始图像数据转换为灰阶图像数据。
在本发明的源极驱动电路中，每行所述像素单元中相同颜色的像素同时接收相应的灰阶值。
在本发明的源极驱动电路中，所述像素单元包括红色像素、绿色像素、蓝色像素、白色像素。
为解决上述技术问题，本发明构造了一种源极驱动电路，其包括：
数模转换模块，用于将原始图像数据转换为灰阶图像数据，所述灰阶图像数据包括全部所述像素的输入灰阶值；其中所述源极驱动电路输入有所述原始图像数据；
优化模块，用于获取显示面板上的每行像素单元中像素的灰阶值的最优输出排序；并将数据线对应的所述像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据；其中所述显示面板包括多条所述数据线以及多个所述像素单元，所述像素单元包括至少三种颜色的像素；以及
缓冲模块，用于提高所述优化模块输出的第一图像数据的负载驱动能力，并将其输入到所述像素。
在本发明的源极驱动电路中，所述优化模块包括：
灰阶获取单元，用于获取所述数据线对应的每行所述像素单元中各像素的灰阶值；
显示顺序设置单元，用于按所述灰阶获取单元获取的灰阶值从大到小或者从小到大的顺序，设置每条所述数据线对应的像素单元的显示顺序，以获得多个显示顺序；
能量消耗值获取单元，用于依次使用所述显示顺序设置单元的每个所述显示顺序，计算整个所述显示面板的能量消耗值，以获取多个能量消耗值；将所述能量消耗值最小的所述显示顺序设置为所述最优输出排序。
在本发明的源极驱动电路中，所述能量消耗值为整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
在本发明的源极驱动电路中，所述能量消耗值获取单元具体用于：
依次使用所述显示顺序，计算每行所述像素单元中相邻两个像素的灰阶值之间的差值的平均值，以获取整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
在本发明的源极驱动电路中，所述缓冲模块包括多个与所述数据线对应的输出缓冲器；每两条所述数据线中任意一条所述数据线上的输出缓冲器的输出端与其余一条所述数据线上的输出缓冲器的输出端连接。
在本发明的源极驱动电路中，所述源驱动电路还包括锁存模块，所述锁存模块包括多个与所述数据线对应的锁存器，所述锁存器用于对所述原始图像数据进行存储；每两条所述数据线中任意一条所述数据线上的锁存器的输出端与其余一条所述数据线上的锁存器的输出端连接。
在本发明的源极驱动电路中，所述源驱动电路还包括电平转换模块，所述电平转换模块包括多个与所述数据线对应的电平转换器，所述电平转换器用于提升所述锁存器存储的原始图像数据的电压。
在本发明的源极驱动电路中，所述数模转换模块，用于将经过所述电平转换器进行电压提升后的原始图像数据转换为灰阶图像数据。
在本发明的源极驱动电路中，每行所述像素单元中相同颜色的像素同时接收相应的灰阶值。
在本发明的源极驱动电路中，所述像素单元包括红色像素、绿色像素、蓝色像素、白色像素。
 有益效果
本发明的源极驱动电路，通过对现有的源极驱动电路的灰阶数据的输出顺序进行优化，从而降低显示面板的功耗，节省生产成本。
 附图说明
图1为现有技术的源极驱动电路的结构示意图；
图2为现有技术的源极驱动电路的驱动示意图；
图3为本发明第一实施例的源极驱动电路的结构示意图；
图4为本发明的驱动电路中优化模块的结构示意图；
图5为本发明的源极驱动电路的驱动示意图；
图6为本发明第二实施例的源极驱动电路的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图3，图3为本发明第一实施例的源极驱动电路的结构示意图；
本发明的源极驱动电路应用与显示面板中，其中所述显示面板包括多条数据线，用于输入数据信号；多条扫描线，用于输入扫描信号；多个像素单元，由所述数据线和所述扫描线限定形成，所述像素单元包括至少三种颜色的像素。所述像素单元包括红色像素、绿色像素、蓝色像素，还可包括白色像素。
所述源极驱动电路，如图3所示，包括：数模转换模块51、优化模块52、缓冲模块53；
其中所述源极驱动电路输入有所述原始图像数据；所述数模转换模块51用来将原始图像数据转换为灰阶图像数据，所述灰阶图像数据包括全部所述像素的输入灰阶值（灰阶电压）；即将数字的原始图像数据转换为模拟的灰阶电压；
所述优化模块52获取所述显示面板上的每行像素单元中像素的灰阶值的最优输出排序；并将数据线对应的所述像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据；
所述缓冲模块53提高所述优化模块52输出的第一图像数据的负载驱动能力后，将其输入到所述像素中。
本实施例通过增加优化模块，对源极驱动电路每次输出的三个或者四个灰阶值获取最优输出排序，得到最优的递增或者递减排序，使得源驱动芯片的电压压差最小化，从而降低了显示面板的功耗。
优选地，如图4所示，所述优化模块52包括灰阶获取单元61、显示顺序设置单元62、能量消耗值获取单元63；
所述灰阶获取单元61用于获取所述数据线对应的每行所述像素单元中各像素的灰阶值；
所述显示顺序设置单元62用于按所述灰阶获取单元获取的灰阶值从大到小或者从小到大的顺序，设置每条所述数据线对应的像素单元的显示顺序，以获得多个显示顺序；
所述能量消耗值获取单元63用于依次使用所述显示顺序设置单元的每个所述显示顺序，计算整个所述显示面板的能量消耗值，以获取多个能量消耗值；将所述能量消耗值最小的所述显示顺序设置为所述最优输出排序。
优选地，所述能量消耗值为整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
优选地，所述能量消耗值获取单元63具体用于：依次使用所述显示顺序，计算每行所述像素单元中相邻两个像素的灰阶值之间的差值的平均值，以获取整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
结合图5，从图5看出显示面板30上的同一行像素单元中同种颜色的像素由同一信号控制，使得每行所述像素单元中相同颜色的像素同时接收相应的灰阶值。譬如当绿色灰阶数据到来时，第一行41的开关打开，第一行像素单元的绿色像素31或者35接收数据线45或者数据线46上的G的灰阶数据；
当红色灰阶数据到来时，第二行42的开关打开，第一行像素单元的红色像素32或者36接收数据线45或者数据线46上的R的灰阶数据，其余行的开关与此类似。
随着显示面板30上的通道41、42、43、44的开关的先后开启和关闭，四个RGBW数据配合开关依次输出G的灰阶数据、B的灰阶数据、R的灰阶数据、W的灰阶数据；
以两条数据线为例，所述灰阶获取单元61分别获取数据线45对应的像素31-32的灰阶值和数据线46对应的像素35-38的灰阶值；譬如数据线45输出的R灰阶为255，G的灰阶为0，B的灰阶为255，数据线46输出的R灰阶为125，G的灰阶为75，B的灰阶为200，接着所述显示顺序设置单元62按照所述灰阶值从小到大或者从打到小的顺序进行排序，数据线45先输出0灰阶的G，接着输出225灰阶的B，再输出255灰阶的R；将所述数据线45对应的像素单元的显示顺序按照GBR的顺序进行输出。数据线46先输出75灰阶的G，接着输出125灰阶的R，再输出200灰阶的B；将所述数据线46对应的像素单元的显示顺序按照GRB的顺序进行输出，从而得到两种显示顺序GBR、GRB；
所述能量消耗值获取单元63分别计算显示顺序GBR、GRB的能量消耗值，具体为：
先将每行像素单元在显示顺序GBR下的相邻两个像素的灰阶值，再计算所有行像素单元中相邻两个像素的灰阶值，即整个面板显示面板的相邻两个像素的灰阶值之间的差值的平均值，将其称为能量消耗值。
再将每行像素单元在显示顺序GRB下的相邻两个像素的灰阶值，再计算所有行像素单元中相邻两个像素的灰阶值，即整个面板显示面板的相邻两个像素的灰阶值之间的差值的平均值，将其称为能量消耗值。
对比上述两个能量消耗值，将其中最小的一个能量消耗值对应的显示顺序作为所有数据线输出的顺序。
譬如计算后发现GRB的能量消耗值最小，因此将所有数据线上的灰阶的输出顺序都按照GRB的顺序输出。
优选地，所述缓冲模块53包括多个与所述数据线对应的输出缓冲器；譬如图5中，所述数据线45连接有第一输出缓冲器47，所述数据线46连接有第二输出缓冲器48；所述第一输出缓冲器47譬如为正极性的缓冲器，所述第二输出缓冲器48譬如为负极性的缓冲器，且每两条所述数据线中任意一条所述数据线上的输出缓冲器的输出端与其余一条所述数据线上的输出缓冲器的输出端连接。所述第一输出缓冲器47连接所述数据线45和数据线46的输出端；所述第二输出缓冲器48连接所述数据线46和数据线45的输出端，能够节省源极驱动电路的驱动线。
通过增加优化模块，对源极驱动电路每次输出的三个或者四个灰阶值之间的差值进行比对后，得到最优的递增或者递减排序，使得源驱动芯片的电压压差最小化，从而降低了显示面板的功耗。
请参照图6，图6为本发明第二实施例的源极驱动电路的结构示意图；
本实施例与上一实施例的区别在于：所述源驱动电路还包括锁存模块54、电平转换模块55；
所述锁存模块54包括多个与所述数据线对应的锁存器，所述锁存器用于对所述原始图像数据进行存储；每两条所述数据线中任意一条所述数据线上的锁存器的输出端与其余一条所述数据线上的锁存器的输出端连接。
所述电平转换模块55包括多个与所述数据线对应的电平转换器，所述电平转换器用于提升所述锁存器存储的原始图像数据的电压；
更进一步地，所述数模转换模块51还用于将经过所述电平转换器进行电压提升后的原始图像数据转换为灰阶图像数据。
本发明的源极驱动电路，通过对现有的源极驱动电路的灰阶数据的输出顺序进行优化，从而降低显示面板的功耗，节省生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种源极驱动电路，其包括：
    数模转换模块，用于将原始图像数据转换为灰阶图像数据，所述灰阶图像数据包括全部所述像素的输入灰阶值；其中所述源极驱动电路输入有所述原始图像数据；
    优化模块，用于获取显示面板上的每行像素单元中像素的灰阶值的最优输出排序；并将数据线对应的所述像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据，其包括：
    灰阶获取单元，用于获取所述数据线对应的每行所述像素单元中各像素的灰阶值；
    显示顺序设置单元，用于按所述灰阶获取单元获取的灰阶值从大到小或者从小到大的顺序，设置每条所述数据线对应的像素单元的显示顺序，以获得多个显示顺序；以及
    能量消耗值获取单元，用于依次使用所述显示顺序设置单元的每个所述显示顺序，计算整个所述显示面板的能量消耗值，以获取多个能量消耗值；将所述能量消耗值最小的所述显示顺序设置为所述最优输出排序；其中所述显示面板包括多条所述数据线以及多个所述像素单元，所述像素单元包括至少三种颜色的像素；以及
    缓冲模块，用于提高所述优化模块输出的第一图像数据的负载驱动能力，并将其输入到所述像素；所述缓冲模块包括多个与所述数据线对应的输出缓冲器；每两条所述数据线中任意一条所述数据线上的输出缓冲器的输出端与其余一条所述数据线上的输出缓冲器的输出端连接。
  2. 根据权利要求1所述的源极驱动电路，其中
    所述能量消耗值为整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
  3. 根据权利要求2所述的源极驱动电路，其中所述能量消耗值获取单元具体用于：
    依次使用所述显示顺序，计算每行所述像素单元中相邻两个像素的灰阶值之间的差值的平均值，以获取整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
  4. 根据权利要求1所述的源极驱动电路，其中
    所述源驱动电路还包括锁存模块，所述锁存模块包括多个与所述数据线对应的锁存器，所述锁存器用于对所述原始图像数据进行存储；每两条所述数据线中任意一条所述数据线上的锁存器的输出端与其余一条所述数据线上的锁存器的输出端连接。
  5. 根据权利要求4所述的源极驱动电路，其中
    所述源驱动电路还包括电平转换模块，所述电平转换模块包括多个与所述数据线对应的电平转换器，所述电平转换器用于提升所述锁存器存储的原始图像数据的电压。
  6. 根据权利要求5所述的源极驱动电路，其中
    所述数模转换模块，还用于将经过所述电平转换器进行电压提升后的原始图像数据转换为灰阶图像数据。
  7. 根据权利要求1所述的源极驱动电路，其中
    每行所述像素单元中相同颜色的像素同时接收相应的灰阶值。
  8. 根据权利要求1所述的源极驱动电路，其中
    所述像素单元包括红色像素、绿色像素、蓝色像素、白色像素。
  9. 一种源极驱动电路，其包括：
    数模转换模块，用于将原始图像数据转换为灰阶图像数据，所述灰阶图像数据包括全部所述像素的输入灰阶值；其中所述源极驱动电路输入有所述原始图像数据；
    优化模块，用于获取显示面板上的每行像素单元中像素的灰阶值的最优输出排序；并将数据线对应的所述像素单元中各像素的灰阶值按照所述最优输出排序的顺序进行输出，以形成第一图像数据；其中所述显示面板包括多条所述数据线以及多个所述像素单元，所述像素单元包括至少三种颜色的像素；以及
    缓冲模块，用于提高所述优化模块输出的第一图像数据的负载驱动能力，并将其输入到所述像素。
  10. 根据权利要求9所述的源极驱动电路，其中所述优化模块包括：
    灰阶获取单元，用于获取所述数据线对应的每行所述像素单元中各像素的灰阶值；
    显示顺序设置单元，用于按所述灰阶获取单元获取的灰阶值从大到小或者从小到大的顺序，设置每条所述数据线对应的像素单元的显示顺序，以获得多个显示顺序；
    能量消耗值获取单元，用于依次使用所述显示顺序设置单元的每个所述显示顺序，计算整个所述显示面板的能量消耗值，以获取多个能量消耗值；将所述能量消耗值最小的所述显示顺序设置为所述最优输出排序。
  11. 根据权利要求10所述的源极驱动电路，其中
    所述能量消耗值为整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
  12. 根据权利要求11所述的源极驱动电路，其中所述能量消耗值获取单元具体用于：
    依次使用所述显示顺序，计算每行所述像素单元中相邻两个像素的灰阶值之间的差值的平均值，以获取整个所述显示面板的相邻两个像素的灰阶值之间的差值的平均值。
  13. 根据权利要求9所述的源极驱动电路，其中
    所述缓冲模块包括多个与所述数据线对应的输出缓冲器；每两条所述数据线中任意一条所述数据线上的输出缓冲器的输出端与其余一条所述数据线上的输出缓冲器的输出端连接。
  14. 根据权利要求9所述的源极驱动电路，其中
    所述源驱动电路还包括锁存模块，所述锁存模块包括多个与所述数据线对应的锁存器，所述锁存器用于对所述原始图像数据进行存储；每两条所述数据线中任意一条所述数据线上的锁存器的输出端与其余一条所述数据线上的锁存器的输出端连接。
  15. 根据权利要求14所述的源极驱动电路，其中
    所述源驱动电路还包括电平转换模块，所述电平转换模块包括多个与所述数据线对应的电平转换器，所述电平转换器用于提升所述锁存器存储的原始图像数据的电压。
  16. 根据权利要求15所述的源极驱动电路，其中
    所述数模转换模块，还用于将经过所述电平转换器进行电压提升后的原始图像数据转换为灰阶图像数据。
  17. 根据权利要求9所述的源极驱动电路，其中
    每行所述像素单元中相同颜色的像素同时接收相应的灰阶值。
  18. 根据权利要求9所述的源极驱动电路，其中
    所述像素单元包括红色像素、绿色像素、蓝色像素、白色像素。
PCT/CN2015/088963 2015-08-19 2015-09-06 一种源极驱动电路 Ceased WO2017028343A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/893,095 US10008146B2 (en) 2015-08-19 2015-09-06 Source driving circuit for optimizing an order of driving gray scale voltages

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510510802.1 2015-08-19
CN201510510802.1A CN105047157B (zh) 2015-08-19 2015-08-19 一种源极驱动电路

Publications (1)

Publication Number Publication Date
WO2017028343A1 true WO2017028343A1 (zh) 2017-02-23

Family

ID=54453647

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/088963 Ceased WO2017028343A1 (zh) 2015-08-19 2015-09-06 一种源极驱动电路

Country Status (3)

Country Link
US (1) US10008146B2 (zh)
CN (1) CN105047157B (zh)
WO (1) WO2017028343A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105590600A (zh) * 2015-12-15 2016-05-18 武汉华星光电技术有限公司 显示器和其驱动方法
CN105847479B (zh) * 2016-05-26 2018-12-21 武汉华星光电技术有限公司 显示屏驱动器、显示屏及移动终端
CN105957484B (zh) * 2016-07-01 2019-01-04 武汉华星光电技术有限公司 一种基于液晶面板的驱动电路及液晶面板
CN106652963B (zh) * 2017-03-09 2020-01-17 南京迈智芯微光电科技有限公司 一种数模融合驱动的硅基显示器
CN106847219B (zh) * 2017-03-10 2018-03-23 惠科股份有限公司 一种显示方法及显示装置
CN107610633B (zh) * 2017-09-28 2020-12-04 惠科股份有限公司 一种显示面板的驱动装置及驱动方法
CN108172166A (zh) * 2018-01-10 2018-06-15 深圳市华星光电技术有限公司 源极驱动器及显示面板的驱动方法
CN110675833B (zh) * 2019-09-24 2021-07-23 Tcl华星光电技术有限公司 控制电路及其应用的显示面板
CN113168803B (zh) * 2019-11-05 2022-12-16 京东方科技集团股份有限公司 显示面板的驱动方法、驱动装置和显示设备
KR102684198B1 (ko) * 2020-06-25 2024-07-11 매그나칩믹스드시그널 유한회사 패널 제어 회로 및 이를 포함하는 표시 장치
CN113160746A (zh) * 2021-04-21 2021-07-23 晟合微电子(肇庆)有限公司 Oled面板的节能型驱动电路及驱动方法
CN113205760B (zh) * 2021-04-29 2023-12-01 无锡唐古半导体有限公司 硅基微显示器及其驱动电路
CN114519967B (zh) * 2022-02-21 2024-04-16 北京京东方显示技术有限公司 源驱动装置及其控制方法、显示系统
CN114627835A (zh) * 2022-03-17 2022-06-14 惠科股份有限公司 时序控制方法、时序控制器及显示装置
CN114822348B (zh) * 2022-04-01 2025-01-28 北京京东方显示技术有限公司 源极驱动电路、显示装置和显示驱动方法
JP2025060088A (ja) * 2023-09-29 2025-04-10 ローム株式会社 映像信号送信装置、映像信号受信装置、及び、映像信号送受信システム

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011979A1 (en) * 2000-07-27 2002-01-31 Hiroyuki Nitta Liquid crystal driving device for controlling a liquid crystal panel and liquid crystal display apparatus
US20020163490A1 (en) * 2001-05-07 2002-11-07 Takashi Nose Liquid crystal display and method for driving the same
CN1417769A (zh) * 2001-11-03 2003-05-14 Lg.菲利浦Lcd株式会社 液晶显示器的数据驱动装置及驱动方法
CN1417771A (zh) * 2001-11-10 2003-05-14 Lg.菲利浦Lcd株式会社 对液晶显示器进行数据驱动的装置和方法
CN1434431A (zh) * 2002-01-21 2003-08-06 夏普公司 显示驱动装置及使用它的显示装置
CN1551065A (zh) * 2003-05-15 2004-12-01 ƽ 显示控制电路及显示驱动电路
US20060181494A1 (en) * 2005-02-17 2006-08-17 Seiko Epson Corporation Reference voltage generation circuit, display driver, electro-optical device, and electronic instrument
US20070013638A1 (en) * 2005-07-12 2007-01-18 Che-Li Lin Source driver and data switching circuit thereof
CN101144922A (zh) * 2006-09-11 2008-03-19 Nec液晶技术株式会社 液晶显示器件及其使用的控制方法
CN102081896A (zh) * 2009-11-26 2011-06-01 奇景光电股份有限公司 源极驱动器、显示装置及显示面板的驱动方法
CN102243833A (zh) * 2010-05-14 2011-11-16 天钰科技股份有限公司 源极驱动器及驱动方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3403635B2 (ja) * 1998-03-26 2003-05-06 富士通株式会社 表示装置および該表示装置の駆動方法
CN100550094C (zh) * 2005-08-17 2009-10-14 点晶科技股份有限公司 可降低功率消耗的显示器驱动方法
TWI343556B (en) * 2006-08-15 2011-06-11 Novatek Microelectronics Corp Voltage buffer and source driver thereof
KR100846966B1 (ko) * 2007-07-27 2008-07-17 삼성에스디아이 주식회사 레벨 쉬프터 및 이를 이용한 평판 표시장치
US8717274B2 (en) * 2010-10-07 2014-05-06 Au Optronics Corporation Driving circuit and method for driving a display
TWI416497B (zh) * 2010-12-28 2013-11-21 Au Optronics Corp 液晶顯示裝置之驅動方法及其相關裝置
CN102693701B (zh) * 2011-03-22 2015-05-20 上海中航光电子有限公司 液晶显示装置及其驱动方法
TWI530926B (zh) 2011-05-03 2016-04-21 天鈺科技股份有限公司 源極驅動器及顯示裝置
CN104577440B (zh) 2013-10-09 2017-02-08 德尔福中央电气（上海）有限公司 一种用于屏蔽多股线系统的装置
KR102231279B1 (ko) * 2013-10-30 2021-03-25 삼성디스플레이 주식회사 영상 데이터 인코딩 장치 및 방법
CN104715729B (zh) * 2015-02-04 2017-02-22 深圳市华星光电技术有限公司 源极驱动电路
CN104575440A (zh) * 2015-02-15 2015-04-29 京东方科技集团股份有限公司 一种显示驱动电路及其驱动方法、显示装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011979A1 (en) * 2000-07-27 2002-01-31 Hiroyuki Nitta Liquid crystal driving device for controlling a liquid crystal panel and liquid crystal display apparatus
US20020163490A1 (en) * 2001-05-07 2002-11-07 Takashi Nose Liquid crystal display and method for driving the same
CN1417769A (zh) * 2001-11-03 2003-05-14 Lg.菲利浦Lcd株式会社 液晶显示器的数据驱动装置及驱动方法
CN1417771A (zh) * 2001-11-10 2003-05-14 Lg.菲利浦Lcd株式会社 对液晶显示器进行数据驱动的装置和方法
CN1434431A (zh) * 2002-01-21 2003-08-06 夏普公司 显示驱动装置及使用它的显示装置
CN1551065A (zh) * 2003-05-15 2004-12-01 ƽ 显示控制电路及显示驱动电路
US20060181494A1 (en) * 2005-02-17 2006-08-17 Seiko Epson Corporation Reference voltage generation circuit, display driver, electro-optical device, and electronic instrument
US20070013638A1 (en) * 2005-07-12 2007-01-18 Che-Li Lin Source driver and data switching circuit thereof
CN101144922A (zh) * 2006-09-11 2008-03-19 Nec液晶技术株式会社 液晶显示器件及其使用的控制方法
CN102081896A (zh) * 2009-11-26 2011-06-01 奇景光电股份有限公司 源极驱动器、显示装置及显示面板的驱动方法
CN102243833A (zh) * 2010-05-14 2011-11-16 天钰科技股份有限公司 源极驱动器及驱动方法

Also Published As

Publication number Publication date
CN105047157B (zh) 2017-10-24
US20170140695A1 (en) 2017-05-18
CN105047157A (zh) 2015-11-11
US10008146B2 (en) 2018-06-26

Similar Documents

Publication Publication Date Title
WO2017028343A1 (zh) 一种源极驱动电路
WO2019010801A1 (zh) 适用rgbw显示的分区背光显示方法及装置
WO2020052008A1 (zh) 显示面板的驱动方法、装置以及显示设备
WO2016101299A1 (zh) 一种液晶显示面板的源极驱动电路及液晶显示器
WO2017015982A1 (zh) 一种液晶显示面板及装置
WO2018176561A1 (zh) 一种液晶面板驱动电路及液晶显示装置
WO2013100686A1 (ko) 유기발광다이오드 표시장치의 문턱전압 센싱 회로
KR19980083732A (ko) 디지탈방식의 액정표시판넬 구동회로
WO2018205333A1 (zh) 一种液晶显示面板及装置
US20060017680A1 (en) Data driving system and method for eliminating offset
WO2013075364A1 (zh) 彩色平面显示面板及相应的彩色平面显示装置
WO2020051994A1 (zh) 显示面板的驱动方法、装置以及显示设备
WO2017219400A1 (zh) Hsd液晶显示面板及液晶显示装置
WO2013033928A1 (zh) Lcd过激驱动方法、装置及液晶显示器
WO2017193438A1 (zh) 一种图像显示方法及显示装置
WO2020155254A1 (zh) 显示面板的驱动方法及显示设备
WO2017045215A1 (zh) 一种液晶显示装置及其栅极驱动电路
WO2016106818A1 (zh) 图像数据处理方法及装置
WO2017049687A1 (zh) 一种goa电路、显示装置和goa电路的驱动方法
WO2020062556A1 (zh) 伽马电压调节电路及显示装置
WO2018045625A1 (zh) 平面显示装置及其扫描驱动电路
WO2019090843A1 (zh) 像素驱动架构及显示装置
WO2018000451A1 (zh) 液晶显示面板及液晶显示装置
WO2018014412A1 (zh) Goa电路及液晶显示面板
WO2020155257A1 (zh) 显示面板的驱动方法、装置及设备

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14893095

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15901547

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15901547

Country of ref document: EP

Kind code of ref document: A1