WO2017027704A1 - Semiconductor structure with a spacer layer - Google Patents
Semiconductor structure with a spacer layer Download PDFInfo
- Publication number
- WO2017027704A1 WO2017027704A1 PCT/US2016/046546 US2016046546W WO2017027704A1 WO 2017027704 A1 WO2017027704 A1 WO 2017027704A1 US 2016046546 W US2016046546 W US 2016046546W WO 2017027704 A1 WO2017027704 A1 WO 2017027704A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- gate
- semiconductor structure
- sublayer
- iii
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 162
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 164
- 239000000463 material Substances 0.000 claims abstract description 138
- 230000008569 process Effects 0.000 claims description 95
- 238000001039 wet etching Methods 0.000 claims description 33
- 229910002704 AlGaN Inorganic materials 0.000 claims description 17
- 239000000969 carrier Substances 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 238000013461 design Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 467
- 230000004888 barrier function Effects 0.000 description 114
- 238000005530 etching Methods 0.000 description 89
- 229910002601 GaN Inorganic materials 0.000 description 46
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 44
- 239000000758 substrate Substances 0.000 description 42
- 238000001312 dry etching Methods 0.000 description 33
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 24
- 239000000203 mixture Substances 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 17
- 239000002019 doping agent Substances 0.000 description 16
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 16
- 150000004767 nitrides Chemical class 0.000 description 14
- 238000000407 epitaxy Methods 0.000 description 13
- 238000001020 plasma etching Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000002355 dual-layer Substances 0.000 description 11
- 230000010354 integration Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000010287 polarization Effects 0.000 description 8
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- 230000005669 field effect Effects 0.000 description 7
- 229910052731 fluorine Inorganic materials 0.000 description 7
- 239000011737 fluorine Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- NJXPYZHXZZCTNI-UHFFFAOYSA-N 3-aminobenzonitrile Chemical compound NC1=CC=CC(C#N)=C1 NJXPYZHXZZCTNI-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- IRPGOXJVTQTAAN-UHFFFAOYSA-N 2,2,3,3,3-pentafluoropropanal Chemical compound FC(F)(F)C(F)(F)C=O IRPGOXJVTQTAAN-UHFFFAOYSA-N 0.000 description 2
- KLZUFWVZNOTSEM-UHFFFAOYSA-K Aluminum fluoride Inorganic materials F[Al](F)F KLZUFWVZNOTSEM-UHFFFAOYSA-K 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 239000002585 base Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003637 basic solution Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000013213 extrapolation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Definitions
- Described herein are semiconductor structures, and processes for forming semiconductor structures. Etching techniques are described for forming recesses in a semiconductor structure, such as gate recesses and/or ohmic recesses, for monolithic integration of Ill-Nitride transistors on a common substrate. Such structures and techniques can be used to produce high performance transistors for various uses such as in power electronics, power amplification and digital electronics.
- III-N Group Ill-Nitride
- Such systems rely on efficient converters to step-up or step-down electric voltages, and use power transistors capable of blocking large voltages and/or carrying large currents.
- power transistors with blocking voltages of more than 500V are used in hybrid vehicles to convert DC power from the batteries to AC power.
- Some other exemplary applications of power transistors include power supplies, automotive electronics, automated factory equipment, motor controls, traction motor drives, high voltage direct current (HVDC) electronics, lamp ballasts, telecommunication circuits and display drives.
- HVDC high voltage direct current
- III-N semiconductor devices for producing high- efficiency power electronics such as power amplifiers and converters
- silicon-based control circuits are still necessary for integrated circuit design for power electronic devices.
- E-mode enhancement-mode
- D-mode depletion mode
- an integrated E/D mode GaN logic circuit may replace a separate, conventional, silicon logic chip.
- Such monolithic integration of III-N transistors with different threshold voltages may allow the addition of digital or control functions to analog and mix-signal components on a common substrate, thus improving the performance of the resulting integrated circuits, while also providing design flexibility to reduce production cost and circuit foot-print.
- Accurate and flexible control of threshold voltages for different III-N transistors on a common substrate is also highly desirable. To achieve these implementation and integration objectives, careful technological developments are needed to determine optimal semiconductor material compositions, device structures, and fabrication processes.
- an important technology for use in fabricating normally -off E-mode field effect transistors for power switching applications is gate recess.
- Chlorine-based dry plasma etching is typically used to form gate recesses in AlGaN/GaN devices, as both GaN and AlGaN are very inert to wet chemical etchants.
- dry plasma etching is prone to plasma-induced damage and etch- based process variations. Plasma damage creates a high density of defect states and degrades channel mobility in the recessed region. Variations in the plasma etch rate make it difficult to control recess depth precisely by timed etching, which causes a variation in transistor parameters such as the transconductance and threshold voltage. Etching rates can further vary for different transistor gate lengths and/or aspect ratios.
- dry plasma etching-based gate recess techniques are insufficient for the integration of different types of transistors with different target threshold voltages on the same substrate.
- the present invention provides semiconductor structures and methods for fabricating Ill-nitride transistors with different threshold voltages on a common substrate.
- one embodiment of the present invention is a multi-layer semiconductor structure for use in a Ill-Nitride (III-N) semiconductor device, comprising a channel layer, a band-offset layer, a spacer layer, and a cap layer.
- the channel layer comprises a first III-N material for providing electrical conduction.
- the band-offset layer is disposed on the channel layer, comprises a second III-N material, and has a wider bandgap than the channel layer.
- the spacer layer is disposed on the band-offset layer, comprises a third III-N material, and has a narrower bandgap than the band-offset layer.
- the cap layer is disposed on the spacer layer, and comprises at least two sublayers, wherein each sublayer is selectively etchable with respect to sublayers immediately below and above, wherein each sublayer comprises a III-N material Al x In j ,Ga z N in which 0 ⁇ ⁇ ⁇ 1, 0 ⁇ > ⁇ 1, and 0 ⁇ z ⁇ 1, wherein at least one of the sublayers has a non-zero Ga content with 0 ⁇ z ⁇ 1, and wherein a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer.
- multi-layer semiconductor structure further comprises a Ga-polar surface.
- a thickness of the spacer layer is less than or equal to 20 nanometers (nm), and greater than or equal to 0.2 nm.
- the spacer layer is n-type doped.
- the sublayer immediately above the spacer layer may be selectively etchable over the spacer layer using a wet etching process. The sublayer immediately above the spacer layer may be etched at a rate greater than three times as high as the spacer layer. Adjacent sublayers of the cap layer may have Al contents alternating between less than 50% (0 ⁇ x ⁇ 0.5) and greater than 50% (0.5 ⁇ x ⁇ 1).
- the spacer layer comprising the third III-N material has zero Al content.
- the band-offset layer comprising the second III-N material has a non-zero Al content.
- the first III-N material is GaN
- the third III-N material is GaN.
- the first, the second, and the third III-N materials are selected from the group consisting of GaN, A1N, AlGaN, InAIN, and AlInGaN.
- the multi-layer semiconductor structure further comprises a carrier-donor layer disposed above at least a portion of the channel layer to provide carriers to the channel layer.
- the carrier-donor layer may have a thickness of at least 0.2 nm, and a doping concentration of at least 10 16 cm "3 .
- the semiconductor structure further comprises a gate region comprising a gate dielectric material disposed above at least a portion of the channel layer, and a pair of ohmic contacts disposed outside the gate region.
- the semiconductor structure may further comprise a gate recess in the gate region, wherein the gate dielectric material is disposed over the gate recess, and wherein a bottom of the gate recess is within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and a sublayer of the cap layer.
- the semiconductor structure further comprises a gate contact disposed above and covering the gate recess, and a gate field plate extension disposed over the gate dielectric material, outside the gate recess.
- each bottom of the pair of ohmic contacts are within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and a sublayer of the cap layer.
- FIGS. 1A, IB, 1C, and ID show a semiconductor structure with a dual layer barrier structure and an etching process for forming a recess in the semiconductor structure, according to one embodiment of the present invention.
- FIGS. 2A, 2B, 2C, and 2D show a semiconductor structure with a carrier-donor layer and an etching process for forming a recess in the semiconductor structure, according to one embodiment of the present invention.
- FIGS. 3A, 3B, 3C, and 3D show a semiconductor structure with a band-offset layer and an etching process for forming a recess in the semiconductor structure, according to one embodiment of the present invention.
- FIG. 5 shows the structure of an exemplary transistor, according to one embodiment of the present invention.
- FIG. 6B shows a semiconductor structure with a spacer layer, according to one embodiment of the present invention.
- FIG. 7 shows an exemplary structure with a recessed-gate transistor and a planar-gate transistor, according to one embodiment of the present invention.
- FIG. 8 shows an exemplary structure with two recessed-gate transistors, according to one embodiment of the present invention.
- FIG. 9 shows an exemplary structure containing two recessed-gate transistors, with doped sublayers, according to one embodiment of the present invention.
- FIG. 10 shows an exemplary structure containing two recessed-gate transistors with recessed ohmic contacts, according to one embodiment of the present invention.
- FIG. 11 shows a process for forming a recess on a semiconductors structure, according to one embodiment of the present invention.
- FIG. 12 shows a process for forming a structure containing two types of recessed-gate transistors, according to one embodiment of the present invention.
- FIG. 13 shows an illustrative fabricated device with both D-mode and E-mode transistors, and corresponding I D -VGS characteristics, according to one embodiment of the present invention.
- FIG. 14 shows a plot of I D -VGS characteristics for integrated D-mode and E-mode transistors, according to one embodiment of the present invention.
- FIG. 15 shows plots of I D -V D s characteristics for integrated D-mode and E-mode transistors, according to one embodiment of the present invention.
- FIG. 17 shows an exemplary recessed-gate transistor with a gate field plate, using the semiconductor structure with a spacer layer shown in FIG. 6B, according to one embodiment of the present invention.
- FIG. 18 is a band diagram illustrating the conduction and valence bands of an exemplary semiconductor structure with a spacer layer, according to one embodiment of the present invention.
- FIG. 19 shows an exemplary structure containing a planar-gate transistor and a recessed-gate transistor, using the semiconductor structure with a spacer layer shown in FIG. 6B, according to one embodiment of the present invention.
- FIG. 20 shows an exemplary diode using the semiconductor structure with a spacer layer shown in FIG. 6B, according to one embodiment of the present invention.
- embodiments of the present invention relate to multi-layer semiconductor structures and methods for fabricating such structures, with one or more gate recesses.
- Such multi-layer structure may facilitate the monolithic integration of Group Ill-Nitride (III-N) transistors having different threshold voltages.
- the threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa.
- Such multi-layer semiconductor structures utilize selectively etchable layers or sublayers disposed over a common substrate, where selective etchability enables gate recesses and/or ohmic recesses to be formed with controllable depths, leading to desired or targeted threshold voltages.
- Monolithic integration of different types of transistors, especially E- mode and D-mode transistors, may greatly enhance the utility of such devices, by allowing the further addition of digital or control functions to analog and mix-signal components on a common substrate, thus improving the performance of the resulting integrated circuits, while also providing design flexibility to reduce production cost and circuit foot-print.
- Gate recess is an important technology for certain types of transistors, including nitride semiconductor-based transistors such as AlGaN/GaN high-electron-mobility transistors (HEMTs).
- HEMTs high-electron-mobility transistors
- gate recess has been used to reduce short channel effects and to improve the current gain cut-off frequency.
- gate recess has been used to fabricate normally-off field effect transistors, such as AlGaN/GaN HEMTs. Since both GaN and AlGaN are very inert to wet chemical etchants, chlorine-based dry plasma etching is typically used to form gate recesses in AlGaN/GaN devices.
- the semiconductor structures described herein may be formed of compound semiconductor material(s), such as III-V semiconductor material(s), particularly Group Ill-Nitride (III-N) semiconductor material(s). Using such techniques, high performance transistors can be fabricated, such as RF III-N and/or normally-off III-N power transistors, for example.
- multi-layer semiconductor structures that enable the integration of multiple transistors with different threshold voltages on a common substrate, and processes for forming such semiconductor structures. While providing precise control over individual etching depths and producing extremely low defect densities on recessed surfaces, the multi-layer semiconductor structure and recess etching fabrication technology as described herein further enable flexible, side-by-side integration of multiple transistor devices with different gate recess depths and/or ohmic recess depths, leading to different threshold voltages.
- GaN can be selectively etched over materials such as A1N, AlGaN, InAIN and AllnGaN with high Al content using a dry etching technique.
- a selective dry etching step followed by a wet etching step can be used to achieve precise control of recess depth and to produce a surface with a low density of defect states.
- the wet etching step, if performed, may be selective or non-selective.
- wet etching step is selective, A1N, AlGaN, InAIN and AllnGaN with high Al content can be selectively etched over materials such as GaN, AlGaN, InGaN, and AllnGaN with low Al content using a wet etching technique.
- a wet etching technique the techniques described herein are not limited as to a wet etching step.
- FIG. 1A shows a semiconductor structure 1 on which an etching technique as described herein may be performed.
- Semiconductor structure 1 may include a substrate 2, a buffer layer 4, a channel layer 6, and a barrier layer 8. Each layer may have a thickness of at least 0.2 nanometers (nm), and channel layer 6 may have a thickness between 1 nm and 10,000 nm or ⁇ .
- Barrier layer 8 includes an upper barrier layer 10 and a lower barrier layer 12.
- upper barrier layer 10 is formed of a material that is etchable by a first etching technique, such as dry etching
- lower barrier layer 12 is formed of a material that is etchable by a second etching technique, such as wet etching.
- first etching technique such as dry etching
- second etching technique such as wet etching
- lower barrier layer 12 is substantially not etched by the first etching technique used to etch upper barrier layer 10, thus forming an etch-stop. Examples of materials that may form the semiconductor structure 1 will now be described.
- a semiconductor material with a lattice constant different from that of substrate 2 may be formed over substrate 2.
- a buffer layer 4 may be included between substrate 2 and the overlying semiconductor material to accommodate a difference in lattice constant.
- Substrate 2 may include a group IV, III-V, or II-VI semiconductor material such as silicon, germanium, or ZnO for example. Other typical substrates include SiC, Sapphire, Si, and bulk GaN.
- the semiconductor material formed over substrate 2 may include a compound semiconductor material, such as a III-V semiconductor material (e.g., a III-N material).
- a substrate 2 having a suitable lattice constant for the formation of overlying compound semiconductor material(s) may be used, and buffer layer 4 may be omitted.
- substrate 2 may be a GaN substrate, a ZnO substrate or another substrate of a material with a lattice constant similar to that of a compound semiconductor material to be formed thereon.
- the techniques described herein are not limited as to substrate 2 or buffer layer 4.
- a nucleation layer is disposed between substrate 2 and buffer layer 4; in some other embodiments, buffer layer 4 includes the nucleation layer or a nucleation region at the interface with substrate 2.
- Substrate 2 and the layers of semiconductor materials formed thereon may be monocrystalline, and may have any suitable crystallographic orientation.
- Compound semiconductor materials, if included in substrate 2 or an overlying layer, may have any suitable composition at the face of the semiconductor material.
- a III-N material is included, it may have an N-face composition or a group III face composition.
- GaN may be grown either N-face/N-polar, Ga-face/Ga-polar or in non-polar orientations.
- Channel layer 6 may be formed of a semiconductor material suitable for formation of a channel therein.
- channel layer 6 may include a III-V semiconductor material, such as a III-N semiconductor material.
- channel layer 6 may include gallium nitride (GaN).
- GaN gallium nitride
- a semiconductor heterostructure may be formed in the semiconductor structure 1.
- a barrier layer 8 comprising and a channel layer 6 comprising B ⁇ AL ⁇ In ⁇ Ga ⁇ N may be formed, where a semiconductor material of barrier layer 8 has a larger bandgap and/or polarization than that of channel layer 6.
- the techniques described herein are not limited as to the formation of heterostructures.
- each layer formed over substrate 2, including buffer layer 4, channel layer 6, and barrier layer 8 may comprise more than one materials, including III-N materials.
- buffer layer 4 may comprise an AIN/GaN superlattice.
- a portion or one or more regions of buffer layer 4 or channel 6 may be GaN. Such regions may be located at layer interfaces, or at positions particularly defined with respect to desired gate or ohmic contact regions.
- the nucleation layer as described before may be included as part of buffer layer 4 at the interface with substrate 2.
- one or more layers formed over substrate 2 may be doped with a suitable dopant.
- barrier layer 8 may be formed having two or more layers or sublayers.
- barrier layer 8 may include a "dual-layer" barrier structure having an upper barrier layer 10 of a first semiconductor material that is etchable using a first etching technique and a lower barrier layer 12 of a second semiconductor material that is etchable using a second etching technique.
- upper barrier layer 10 may include a semiconductor material such as B w Al x In j ,Ga z N in which x is less than 0.25.
- Upper barrier layer 10 may be doped or undoped. Doping of upper barrier layer 10 may supply carriers to channel layer 6 underneath. After gate recessing, one or more doped regions may be formed between the gate and the source and/or between the gate and the drain, outside of the gate-recess.
- a doped region may be polarization doped or may include dopants such as n-type dopants or p-type dopants.
- a doped region may have any suitable doping concentration and distribution. For example, dopants may be provided at the lower surface of upper barrier layer 10, the upper surface of upper barrier layer 10, and/or in another location.
- the doping profile can be uniform or non-uniform.
- the doping concentration may be at least 10 16 cm "3 .
- a delta-doping profile may be used.
- any suitable doping technique may be used, such as implantation or diffusion.
- upper barrier layer 10 may be doped during its formation (e.g., growth).
- the doping type of upper barrier layer 10 may be of the same type as that of carriers in the channel region.
- the doping type in upper barrier layer 10 may be n-type for an n-channel transistor and p-type for a p-channel transistor.
- the doped region may be highly doped.
- lower barrier layer 12 may include a semiconductor material such as B w Al x In j ,Ga z N in which x is greater than 0.5.
- lower barrier layer 12 may be doped using any suitable doping technique such as those discussed above with respect to the optional doping of upper barrier layer 10.
- B w Al x In j ,Ga z N or a "B w Al x In y Ga z N material” refers to a semiconductor material having nitride and one or more of boron, aluminum, indium and gallium.
- B w Al x In j ,Ga z N materials include binary, ternary, and quaternary compounds such as GaN, A1N, AlGaN, AlInGaN, InGaN, and BAlInGaN, by way of illustration.
- a material may include other materials besides nitride, boron, aluminum, indium and/or gallium as well.
- a B ⁇ AlJn ⁇ Ga z N material may be doped with a suitable dopant such as silicon and germanium.
- the terms material" and "III-N material” are used interchangeably to represent nitride-based compound semiconductor materials, unless otherwise specified or limited.
- the first etching technique may include a dry etching technique (e.g., dry plasma etching, also referred-to as reactive ion etching (RIE)).
- RIE reactive ion etching
- the upper barrier layer includes GaN
- a fluorine-based etching process may be used, for example.
- FIG. IB shows semiconductor structure 1 following the removal of a region of upper barrier layer 10 using a dry etching process.
- Lower barrier layer 12 may serve as an etch stop to stop the dry etching process at its upper surface.
- the dry etching process may damage the upper surface of lower barrier layer 12, creating a damaged region 14.
- the dry etching process may not produce any significant damage.
- a damaged region 14 of barrier layer 12 may be oxidized prior to removal of damaged region 14 in a second etching step.
- a second etching step may be performed using a second etching technique to remove a portion of lower barrier layer 12.
- the second etching step is optional, and is not required be performed.
- the etch process used in the second etching step may selectively etch lower barrier layer 12 with respect to a layer overlying lower barrier layer 12 and which may be in contact with lower barrier layer 12, such as upper barrier layer 10, for example.
- the etch process used in the second etching step may selectively etch lower barrier layer 12 with respect to a layer below lower barrier layer 12 which may be in contact with lower barrier layer 12, such as channel layer 6 and/or a band-offset layer.
- the etching technique used in the second etching step may be a wet etching technique.
- FIG. 1C shows the semiconductor structure 1 following the removal of a region of lower barrier layer 12 using a wet etching process.
- the wet etching process may remove damaged region 14, and may enable forming a gate recess 16 without a damaged region at its lower surface.
- the wet etching process may remove the entire thickness of lower barrier layer 12, as shown in FIG. 1C, or a portion of the thickness of lower barrier layer 12.
- the use of a wet etching process to etch lower barrier layer 12 may provide fine control over the depth of gate recess 16 and reduce or eliminate process-induced variations in transistor characteristics such as threshold voltages.
- a gate dielectric 18 and a gate 20 may be formed in gate recess 16. Any suitable material may be used for gate dielectric 18 and gate 20.
- Gate dielectric 18 may be formed of any suitable insulator, such as silicon oxide, silicon nitride, A1 2 0 3 , A1N, or high- ⁇ dielectric, or a combination of such.
- Gate 20 may be formed of any suitable conductor or semiconductor, such as a metal or polysilicon.
- Source and drain regions S and D can also be formed, as understood by those of ordinary skill in the art.
- the source and/or drain regions S and D may be formed of a suitable conductor or semiconductor, such as a metal and/or a doped semiconductor region.
- the source and/or drain regions S and D may have ohmic contacts.
- upper barrier layer 10 may be selectively etched over lower barrier layer 12 in the source and/or drain region(s).
- Lower barrier layer 12 may be wet etched in the source and/or drain regions(s) so that an ohmic metallization can be formed on the remaining barrier layer in the source and/or drain regions(s).
- the dry and/or wet etching of upper barrier layer 10 and/or lower barrier layer 12, respectively, to form the source and/or drain region(s) may be performed in the same etching process(es) used to form the gate recess, in some embodiments, or in a different process.
- the portion of barrier layer 8 remaining after the formation of gate recess is the portion of barrier layer 8 remaining after the formation of gate recess
- normally-off transistor 16 may have a thickness smaller than a critical thickness to prevent the formation of a two dimensional electron gas (2DEG) under the gate (see FIG. 5, for example), thereby forming a normally-off transistor.
- 2DEG two dimensional electron gas
- the techniques described herein are not limited to the formation of normally-off transistors, and may be used to form other devices, such as normally-on transistors.
- normally-on and normally-off transistors are summarized as follows.
- E-mode Enhancement mode
- the transistor When a normally-off, or Enhancement mode (E-mode) transistor has no voltage applied to the gate, the transistor is in the off-state and is substantially non-conducting.
- a normally-off transistor When a suitable voltage is applied to the gate, a normally-off transistor is in the on-state and carriers can flow between its main conduction terminals (e.g., source and drain).
- the threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa.
- the threshold voltage V T of a normally- off (E-mode) transistor is generally positive.
- FIGS. 2A-2D illustrate an embodiment in which a dedicated carrier-donor layer 22 is included in the semiconductor structure. In the embodiment shown in FIGS.
- carrier-donor layer 22 is formed over upper barrier layer 10.
- carrier-donor layer 22 may be formed below upper barrier layer 10 or in another location.
- carrier-donor layer 22 may be formed of the same material as that of upper barrier layer 10.
- Carrier-donor layer 22 may supply carriers to channel layer 6. After gate recessing, which removes a portion of carrier-donor layer 22 as well, the remaining portion of carrier-donor layer 22 may supply carriers to channel layer 6 approximately outside of the region under the gate.
- Carrier-donor layer 22, if included in the semiconductor stack, may be doped using any suitable doping technique such as those discussed above with respect to the optional doping of upper barrier layer 10. After gate recessing, one or more doped regions may be formed in carrier-donor layer 22 between the gate and the source and/or between the gate and the drain, outside of the gate-recess. A doped region may be polarization doped or may include dopants such as n-type dopants or p-type dopants.
- a doped region may have any suitable doping concentration and distribution.
- dopants may be provided at the lower surface of carrier-donor layer 22, the upper surface of carrier-donor layer 22, and/or in another location.
- the doping profile may be uniform or non-uniform.
- carrier- donor layer 22 may have a thickness of at least 0.2 nm, and a doping concentration of at least 10 16 cm "
- carrier-donor layer 22 may comprise sublayers with different doping concentrations.
- a delta-doping profile may be used. Any suitable doping technique may be used, such as implantation or diffusion, for example.
- carrier- donor layer 22 may be doped during its formation or growth.
- the doping type of carrier-donor layer 22 may be of the same type as that of carriers in the channel region.
- the doping type in carrier-donor layer 22 may be n-type for an n-channel transistor and p-type for a p- channel transistor.
- a doped region may be highly doped. If a carrier-donor layer 22 is included, in some embodiments, upper barrier layer 10 and/or lower barrier layer 12 may not be doped.
- carrier-donor layer 22 may be formed of a semiconductor material that is etchable by a dry etching process.
- a barrier layer 28 may include a carrier-donor layer 22, an upper barrier layer 10 and a lower barrier layer 12.
- carrier-donor layer 22 may shape the electric field in the semiconductor structure (e.g., in the channel region). The doping density may be tuned as needed to shape the electric field. In some embodiments, carrier-donor layer 22 may be used as a passivation layer. Carrier-donor layer 22 may have any suitable thickness. In some embodiments, the thickness of carrier-donor layer 22 may be greater than 5 nm.
- a first etching process such as a dry etching process, may be used to etch away regions of carrier-donor layer 22 and upper barrier layer 10.
- a region of the lower barrier layer 12 may be removed using a wet etching process, as illustrated in FIG. 2C.
- a gate dielectric 18 and gate 20 may be formed in the gate recess, as illustrated in FIG. 2D. Source and drain regions S and D of the transistor may be formed as well.
- a semiconductor structure may include a band-offset layer 32 between channel layer 6 and lower barrier layer 12.
- Band-offset layer 32 may increase the band-offset between a barrier layer 38 and channel layer 6.
- barrier layer 38 may include an upper barrier layer 10, a lower barrier layer 12 and a band-offset layer 32.
- a first etching process such as a dry etching process, may be used to etch away a region of upper barrier layer 10.
- a region of lower barrier layer 12 may then be removed using a wet etching process, as illustrated in FIG. 3C.
- band-offset layer 32 may be very thin, with a thickness below a critical thickness so as to produce a normally-off transistor when a gate is formed over band-offset layer 32.
- band-offset layer 32 may be thicker than the critical thickness.
- band-offset layer 32 When band-offset layer 32 is thicker than the critical thickness, a normally- off transistor may be produced by removing at least a portion of band-offset layer 32 using the wet etching process such that the remaining portion has a thickness below the critical thickness.
- a gate dielectric 18 and gate 20 may be formed in the gate recess, as illustrated in FIG. 3D. Source and drain regions S and D of the transistor may be formed.
- an embodiment as illustrated in FIGS. 3A-3D may include a carrier-donor layer 22 (not shown in FIGS. 3A-3D).
- a semiconductor structure may include a plurality of "dual-layer” barrier structures. Any suitable number of “dual-layer” barrier structures may be included.
- a semiconductor structure 40 may include a first dual-layer barrier structure 8a and a second dual-layer barrier structure 8b, each having an upper barrier layer 10 and a lower barrier layer 12.
- the upper and lower barrier layers are indicated in FIG. 4 as 10a and 12a, respectively, for dual- layer barrier structure 8a, and indicated as 10b and 12b, respectively, for dual-layer barrier structure 8b.
- Dual-layer barrier structures 8a and 8b may have the same structure and/or composition, or a different structure and/or composition.
- a first etching process e.g., a dry etching process
- a second etching process e.g., a wet etching process
- the first etching process e.g., a dry etching process
- the second etching process e.g., a wet etching process
- a gate dielectric 18 and gate 20 may be formed in the gate recess, as discussed above.
- FIG. 5 illustrates a non-limiting example of transistors with gate recesses produced according to at least some of the techniques described herein.
- upper barrier layer 10 may be formed of GaN
- lower barrier layer 12 may be formed of A1N
- band-offset layer 32 may be formed of Alo.15Gao.85 .
- the GaN upper barrier layer can be selectively etched over the A1N lower barrier layer by fluorine-based dry etching.
- the A1N lower barrier layer can be selectively etched over the GaN upper barrier layer and the Alo.15Gao.85N band-offset layer by a wet etching process with a base such as potassium hydroxide (KOH) and/or tetramethylammonium hydroxide (TMAH), or by a digital etching process.
- KOH potassium hydroxide
- TMAH tetramethylammonium hydroxide
- Digital etching processes are understood by those of ordinary skill in the art and will not be detailed herein. However, these are only examples, and any suitable etchants may be used.
- FIG. 5 shows a structure 500 of the exemplary transistor, according to some embodiments of the present invention.
- Exemplary devices have been fabricated having the structure shown in FIG. 5.
- the structure was grown on a 4-inch silicon substrate by metal-organic chemical vapor deposition.
- the structure includes a 22-nm GaN:Si cap layer with 3-6 ⁇ 10 18 cm "3 Si doping, a 1.5-nm barrier A1N layer, a 3-nm Alo.15Gao.85N band-offset layer, a 1.2-um i-GaN channel layer, and a 2.8- ⁇ buffer layer on p- type Si(l l l) substrate.
- Hall measurement shows a sheet resistance of 579 ⁇ 11 ⁇ /sq and two- dimensional-electron-gas (2DEG) mobility of 1529 ⁇ 18 cm 2 V _1 s 1 with a sheet charge density of 7.1 ⁇ 0.1x l0 12 cm “2 .
- the device fabrication started with mesa isolation and Ti/Al/Ni/Au ohmic contact formation which was annealed at 870°C for 30 s.
- the n-GaN cap in the recessed-gate region was selectively etched over the A1N layer by fluorine-based electron- cyclotron-resonance reactive ion etching (ECR-RIE).
- A1F 3 Due to the non-volatility of aluminum fluoride (A1F 3 ), very high etch selectivity of GaN over A1N is achieved for the gas flow rates of 5 seem BCl 3 /35 seem SF 6 at 35 mtorr, 100 W ECR power and 100 V DC bias.
- a 350 second etch with 70 second over- etching was used to achieve uniform and complete removal of the n-GaN layer.
- the surface of the A1N layer was then oxidized by low-energy oxygen plasma and wet etched by a 1-min dip in tetramethylammonium hydroxide (TMAH) at room temperature to remove the dry etching damage.
- TMAH tetramethylammonium hydroxide
- a 10-nm A1 2 0 3 gate dielectric was then deposited by atomic layer deposition at 250°C and annealed at 500°C for 1 min in forming gas.
- a Ni/Au gate electrode was deposited covering the recessed-gate region with a 2.5-um overhang length, as shown in FIG. 5B.
- the sample was then annealed in forming gas at 400°C for 5 min to reduce the positive fixed charge in A1 2 0 3 .
- the resulting recessed-gate transistors have recessed-gate lengths L rec _ g varying from 3 to 20 ⁇ .
- V T V gsi - 0.5 ds , where V gsi is the interception voltage from a linear extrapolation of an I d -V gs curve, not shown here.
- V ds 0. 1 V
- the recessed-gate GaN MISFETs have a uniform V T of 0.30 ⁇ 0.04 V.
- the average subthreshold slope is 62 ⁇ 1 mV/decade.
- a bidirectional gate voltage sweep in the transfer characteristics shows less than 10 mV hysteresis in the threshold voltage.
- the relatively low maximum drain current of both recessed-gate and planar gate transistors is due to the large gate length and gate-to-source distance, relatively low 2DEG density (7.1 ⁇ 10 12 cm-2), and high contact resistance (1.2 ⁇ ⁇ mm) of the non-optimized ohmic contact.
- FIG. 6A shows another multi-layer epitaxy structure 600 further extending the "dual layer” barrier structure 40 shown in FIG. 4.
- FIG. 6B shows yet another multi-layer epitaxy structure 650, with an additional optional spacer layer 632 disposed on band-offset layer 630.
- both semiconductor structure 600 and semiconductor structure 650 may be used for fabricating multiple types of transistors with different threshold voltages (Vj).
- the threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa.
- Semiconductor structure 600 may include a substrate layer 602, a buffer layer 604, a channel layer 606, a band-offset layer 630 and a cap layer 608.
- Each of substrate layer 602, buffer layer 604, channel layer 606, and band-offset layer 630 may be formed using materials and processes similar for substrate layer 2, buffer layer 4, channel layer 6, and band-offset layer 32 respectively, according to descriptions of embodiments shown in FIGS. 1A- 1D, 2A-3D, 3A-3D, and 4.
- Cap layer 608 may be formed using materials and processes similar for barrier layers 8, 8a, 8b, or barrier layer 28, according to descriptions of embodiments shown in FIGS. 1A- 1D, 2A-3D, and 4.
- each layer or sublayer shown in FIG. 6A may comprise a III-N material B w Al x In j ,Ga z N.
- epitaxy structure 600 includes a cap layer 608 comprising a plurality of n selectively etchable sublayers, such as sublayer 61 1 with thickness t sublayer 612 with thickness t 2 , sublayer 618 with thickness f n -i, and sublayer 619 with thickness f n , where n may be any even or odd integer greater than or equal to two, according to various embodiments of the present invention.
- t n may be between 2 angstroms and 500 nanometers, and may or may not be the same in various embodiments of the present invention.
- t n may be greater than or equal to the total thickness of all other sublayers.
- all odd-numbered or odd sublayers may be grown to a first thickness, while all even-numbered or even sublayers may be grown to a second thickness.
- each z ' -th sublayer ( 1 ⁇ / ' ⁇ «) is selectively etchable with respect to the (/ ' +l)-th sublayer below using some etching technique, thus the (/ ' +l)-th sublayer below may serve as an etch stop for the z ' -th sublayer under the given etching technique.
- the n-th sublayer may further be selectively etchable with respect to band-offset layer 630, spacer layer 632, or any layer disposed directly below and/or in contact with the n-th sublayer. Spacer layer 632 may or may not be selectively etchable over band-offset layer 630.
- each sublayer is selectively etchable with respect to both the sublayer above and the sublayer below using some etching technique, such as dry etching, wet etching, or a combination of dry etching and wet etching.
- some etching technique such as dry etching, wet etching, or a combination of dry etching and wet etching.
- selectively etchable sublayers may be classified into two types. All odd sublayers counting from the first sublayer 611 may be formed of a material that is selectively etchable with respect to even sublayers by a first etching technique, such as dry etching, while all even sublayers counting from the second sublayer 612 may be formed of a material that is selectively etchable with respect to odd sublayers by a second etching technique, such as wet etching, or vice versa.
- the n-th sublayer may further be selectively etchable with respect to band-offset layer 630, spacer layer 632, or any layer disposed directly below and/or in contact with the n-th sublayer, using a dry etch process, a wet etch process or a combination thereof.
- the n-th sublayer may be etched at a faster rate the layer below, and the selectivity of the etch process may be greater than 3: 1, such that the n-th sublayer is etched at a rate greater than three times as high as the rate at which layer below is etched.
- Spacer layer 632 may or may not be selectively etchable over sublayer 619 and/or band-offset layer 630.
- Band-offset layer 630 may or may not be selectively etchable over sublayer 619 and/or spacer layer 632.
- Each of the odd sublayers may have the same structure, composition, and/or thickness.
- each of the odd sublayers may have a different structure, composition, and/or thickness.
- each of the even sublayers may have the same structure, composition, and/or thickness, or a different structure, composition, and/or thickness.
- each sublayer may be selectively etchable with respect to a selected subset of all other sublayers, using one or more etching techniques.
- selectively etchable sublayers may be classified into three types, where each type is repeated every three sublayers, and where each type is selectively etchable over the other two types using one or more etching techniques.
- all odd sublayers counting from the first sublayer 611 may include or comprise a semiconductor material that is selectively etchable in a dry etching process, such as GaN, or another nitride semiconductor material B w Al x In,,Ga z N, in which w, x, y and z each has a suitable value between zero and one inclusive (0 ⁇ w, x, y, z ⁇ 1), and the composition is such that the nitride semiconductor material is selectively etchable using a dry etching process.
- a semiconductor material that is selectively etchable in a dry etching process such as GaN, or another nitride semiconductor material B w Al x In,,Ga z N, in which w, x, y and z each has a suitable value between zero and one inclusive (0 ⁇ w, x, y, z ⁇ 1), and the composition is such that the nitride semiconductor material is selectively etchable using a dry
- all even sublayers counting from the second sublayer 612 may include or comprise a semiconductor material that is selectively etchable in a wet etching process, such as A1N, or another nitride semiconductor material B w Al x In j ,Ga z N, in which w, x, y and z each has a suitable value between zero and one inclusive (0 ⁇ w, x, y, z ⁇ 1), and the composition is such that the nitride semiconductor material is selectively etchable using a wet etching process.
- the values of w, x, y, and z may or may not add to 1.
- even sublayers may be formed of a semiconductor material B w Al x In j ,Ga z N where x is greater than 0.5.
- even sublayers may be formed of a semiconductor material Al x In j ,Ga z N in which x, y, and z each has a suitable value between zero and one inclusive (0 ⁇ x, y, z ⁇ 1), and where the values of x, y, and z may or may not add to 1.
- at least one of the selectively etchable sublayers may have a non-zero Ga content (0 ⁇ z ⁇ 1) that makes the epitaxy growth process easier.
- cap layer 608 When consecutive, adjacent or continuous sublayers of cap layer 608 have their material compositions alternate between GaN and A1N, fluorine-based chemicals may be used to dry etch GaN without etching A1N, while tetramethylammonium hydroxide (TMAH) may be used to wet etch A1N without etching GaN.
- TMAH tetramethylammonium hydroxide
- odd layers may include or comprise a semiconductor material that is selectively etchable in a wet etching process, such as A1N
- even layers may include or comprise a semiconductor material that is selectively etchable in a dry etching process, such as GaN.
- B w Al x In,,Ga z N, "B ⁇ AlJn ⁇ Ga z N material,” or “III-N material” refers to a semiconductor material having nitride and one or more of boron, aluminum, indium and gallium.
- B ⁇ AlJn ⁇ Ga z N materials include, but are not limited to, GaN, A1N, AlGaN, AlInGaN, InGaN, and BAlInGaN, Alo.15Gao.85N, and Alo.65Gao.35N, by way of illustration.
- a B ⁇ AlJn ⁇ Ga z N material may include other materials besides nitride, boron, aluminum, indium and/or gallium.
- a B ⁇ AlJn ⁇ Ga z N material may be doped with a suitable dopant such as silicon or germanium.
- selective etchability of sublayers within cap layer 608 is achieved by alternating aluminum content or composition of adjacent or consecutive sublayers between a relatively high value or percentage and a relatively low value or percentage.
- selective etchability may be achieved by alternating between Al-light and Al-rich sublayers, or adjusting the value of x for material B w Al x In,,Ga z N or Al x In j ,Ga z N as described above.
- consecutive or adjacent sublayers of cap layer 608 may have Al contents alternating between less than 0.5 inclusive and greater than 0.5 exclusive, less than 0.5 exclusive and greater than 0.5 inclusive, or less than 0.5 exclusive and greater than 0.5 exclusive.
- consecutive or adjacent sublayers of cap layer 608 may have Al content alternate between less than 0.25 and greater than 0.5, less than 0.35 and greater than 0.5, or less than 0.35 and greater than 0.65, inclusive or exclusive.
- at lest one of the plurality of selectively etchable sublayers has an Al content great than 0.5.
- at least one of the selectively etchable sublayers may have a non-zero Ga content (0 ⁇ z ⁇ 1).
- each layer or sublayer of multi-layer semiconductor structure 650, including optional spacer layer 632 may comprise a III-N material B w Al x In j ,Ga z N.
- spacer layer 632 may comprise a III-N material with a zero Al content in the form of B w In j ,Ga z N, including materials such as GaN and InGaN.
- Spacer layer 632 may also be n-type doped.
- band- offset layer 630 may have a wider bandgap or a higher conduction band edge than channel layer 606 below and spacer layer 632 above.
- spacer layer 632 may have a narrower bandgap or a lower conduction band edge than sublayer 619 immediately above.
- a spacer layer with a narrower bandgap makes the net polarization charge at the interface between the spacer layer and the band-offset layer negative as the polarization of the spacer layer is smaller than that of the band-offset layer, thus helping to improve the threshold voltages when the multi-layer structure 650 with spacer layer 632 is used in a field-effect transistor.
- one or more layers or sublayers shown in FIG. 6B may comprise III-N materials such as GaN, A1N, AlGaN, InAIN, and AlInGaN.
- channel layer 606 may comprise GaN
- band-offset layer 630 may comprise AlGaN
- spacer layer 632 may comprise GaN
- cap layer 606 may comprise alternating layers of GaN and A1N.
- band-offset layer 630 may comprise a III-N material with a non-zero Al content.
- optional spacer layer 632 shown in FIG. 6B may have a thickness less than or equal to 20nm, and/or greater than or equal to 0.2 nm.
- thickness of a layer or sublayer may refer to an average, maximum, or medium vertical distance measured between points on an upper interface and a lower interface of the layer or sublayer.
- FIG. 7 illustrates a non-limiting exemplary structure 700 containing two types of transistors produced on a common substrate, using epitaxy structure 600 shown in FIG. 6A, or epitaxy structure 650 shown in FIG. 6B, with a gate recess produced according to some of the techniques described herein. More specifically, semiconductor structure 700 includes two transistors 710 and 720.
- Transistor 710 is gate-recessed and includes a gate 712 with gate recess depth 713, through the entire cap layer 608.
- Transistor 720 has a planer gate.
- gate 712 may be recessed through a proper subset of the selectively etchable sublayers, so cap layer 608 is not removed entirely for forming gate 712, as shown in FIG. 7.
- a normally-off E-mode transistor is formed with a positive threshold voltage V T1 .
- planar transistor 720 is a normally-on D-mode transistor with a negative threshold voltage V T2 .
- transistor threshold voltage depends monotonically on gate-recess depth, or the number of layers and/or sublayers etched under the gate, where the dependence may be linear or nonlinear. The threshold voltage also depends on the type of materials and compositions of the layers and/or sublayers etched.
- a higher average Al content for cap layer 608 generally moves the threshold voltage of a transistor fabricated thereon negatively.
- etching selectivity between different semiconductor materials for individual sublayers may be taken into account when determining the corresponding gate recess depth.
- etching depths can be accurately controlled in discrete steps to achieve or approximate a desired threshold voltage.
- the E/D-mode integration shown in FIG. 7 may offer a large difference in threshold voltages between the two types of transistors.
- the difference in threshold voltages between the two types of transistors may be as large as 35V.
- both transistors may be E-mode transistors, with different positive threshold voltages, or both transistors may be D- mode transistors, with different negative threshold voltages.
- V T1 and V T2 may be within the range between - 10V and +3V, respectively.
- a portion of optional spacer layer 632, all of spacer layer 632, a portion of band-offset layer 630, and/or all of band-offset layer 630 may be removed to further increase gate recess depth 713, to achieve a higher threshold voltage V T1 .
- the bottom of the gate recess for transistor 710 may be within or on band- offset layer 630, spacer layer 632, or any sublayer of cap layer 608.
- a suitable masking process may be used to define a region to be etched.
- a first etching process may be performed to selectively etch the material of first selectively etchable layer 611 with respect to the material of second selectively etchable layer 612.
- the selectivity of the etch process used in the first etching step may be greater than one, such that first selectively etchable layer 611 is etched at a faster rate than second selectively etchable layer 612.
- the selectivity of the etch process used in the first etching step may be greater than 3: 1, such that first selectively etchable layer 611 is etched at a rate greater than three times as high as the rate at which second selectively etchable layer 612 is etched.
- the first etching technique may include a dry etching technique (e.g., dry plasma etching, or reactive ion etching (RIE)). If first selectively etchable layer 611 includes GaN, a fluorine-based etching process may be used.
- Second selectively etchable sublayer 612 may serve as an etch stop to stop the dry etching process at its upper surface. The dry etching process may damage the upper surface of second selectively etchable sublayer 612, creating a damaged region. However, in some embodiments the dry etching process may not produce any significant damage.
- a second etching step may be performed using a second etching technique to remove a portion of second selectively etchable sublayer 612, through a window formed by the removal of a region of first selectively etchable sublayer 611 in the first etching step.
- the etch process used in the second etching step may selectively etch second selectively etchable sublayer 612 with respect to a layer overlying second selectively etchable sublayer 612 and which may be in contact with second selectively etchable sublayer 612, such as first selectively etchable sublayer 611, for example.
- the etch process used in the second etching step may selectively etch second selectively etchable sublayer 612 with respect to a layer below second selectively etchable sublayer 612 which may be in contact with second selectively etchable sublayer 612, such a third selectively etchable sublayer below, and/or spacer layer 632, or band-offset layer 630.
- the selectivity of the etching of second selectively etchable sublayer 612 with respect to first selectively etchable sublayer 611 and/or the third selectively etchable sublayer, spacer layer 632, or band-offset layer 630 may be greater than one, such that the rate of etching of second selectively etchable sublayer 612 is greater than that of first or third selectively etchable sublayers, for example.
- the selectivity may be greater than 3: 1, such that second selectively etchable sublayer 612 is etched at a rate greater than three times as high as the first or the third selectively etchable sublayers.
- the etching technique used in the second etching step may be a wet etching technique.
- gate recess is formed through first selectively etchable sublayer 611 and second selectively etchable sublayer 612
- the first and second etching techniques may be performed iteratively to remove consecutive or adjacent selectively etchable sublayers, until gate recess depth 713 is achieved.
- the last etching step to remove a portion of sublayer 619 may be either dry etching or wet etching.
- gate recess depth 713 is approximately the summation of layer thicknesses ti, t 2 , ... , and t n .
- Gate dielectric 714 and gate 712 may be formed in the resulting gate recess for transistor 710, using processes similar to those for depositing gate dielectric 18 and gate 20 shown in FIG. ID.
- gate dielectric 724 and gate 722 may be formed concurrently with, or separately from, gate dielectric 714 and gate 712 of transistor 710.
- Source contacts 716 and 726, and drain contacts 718 and 728 may be formed before or thereafter.
- FIG. 8 illustrates another exemplary structure 800 containing two types of transistors 810 and 820 produced on the same substrate, using epitaxy structure 600 shown in FIG. 6A or epitaxy structure 650 shown in FIG. 6B.
- Transistors 810 and 820 are gate-recessed to different depths and fabricated according to techniques described herein.
- transistor 810 with a deeper gate recess has a more positive threshold voltage V T than transistor 820 with a shallower gate recess.
- V T is monotonically dependent on gate recess depths, varying the number of layer and/or sublayers etched or recessed below the gate allows direct and accurate control of achievable threshold voltages.
- each selectively etchable sublayer may contain a mono layer of III-N atoms, recess depths may be discretely controlled at intervals as small as 0.2 nm to 0.5 nm.
- Gate recesses may stop in or on at any selectively etchable sublayer, spacer layer 632, band-offset layer 630, or one or more optional carrier-donor layers not shown here.
- gate recesses of transistors 810 and 820 stop on two different sublayers, and these two sublayers may or may not have the same material compositions.
- Gate dielectrics 814 and 824, and gate contacts 812 and 822 are deposited over the etched regions.
- ohmic contacts may be made with or without recesses, and either before or after the formation of the gate regions to accommodate for other process considerations such as thermal budget, ohmic contact performance and process complexity.
- ohmic contacts 816 and 818 of transistor 810 are made with ohmic recesses into cap layer 608. Both source 816 and drain 818 are recessed through the entire cap layer, with the same ohmic recess depth to simplify fabrication.
- ohmic recesses for a single transistor may or may not have the same recess depth.
- an ohmic contact may have a thickness between 1 nm and 10,000 nm .
- ohmic contacts are rectangular shaped in FIG. 8, they may also be alloyed, in which the contacts have no regular shapes.
- the bare epi surface of multi-layer structure 650 may be first covered with a dielectric layer, such as Si0 2 or SiN.
- a gate opening for transistor 810 may be defined by using photolithography, and etched in the deposited dielectric. After removal of photoresist, fluorine-based dry-etch may be performed to remove Al-light sublayers and stop on Al- rich sublayers, while TMAH or other basic solutions may be used to remove Al-rich sublayers and stop on Al-light sublayers. Selective etching may be repeated until a desired recess depth is reached for gate 812.
- the whole structure may be covered with another dielectric layer, generally the same as the first dielectric used before, and photolithography can be performed, followed by photoresist removal and iterative selective etching of sublayers until a desired recess depth for gate 822 is reached.
- gate dielectrics and gate contact materials such as gate metals may be deposited to cover the whole structure.
- Gate electrodes are then defined by photolithography, where gate metals outside gate electrode regions are etched off.
- gate electrodes are formed by depositing gate electrode materials followed by lifting-off, using at least one material selected from Ti, Mo, W, Ta, Pt, Ni, Al, Cu, poly-Si, TiN, WN, TaN, TiW, and silicide.
- gate electrodes for different transistors are made of different materials. Another way of recessing for gate 812 and gate 822 is to define both gate openings concurrently, to selectively etch in both gate openings until a first, smaller, gate depth is reached, and to further selectively etch in one of the gate openings until a second, larger, gate depth is reached.
- ohmic recesses for contacts 816 and 818 may be formed before gate electric and gate metal deposition.
- ohmic recesses may be formed together or concurrently with one of the gate recesses, if the recess depths are the same.
- ohmic metal deposition, patterning and optional thermal annealing steps may be performed either before or after gate dielectric and gate metal deposition, or gate electrodes formation, to allow optimization of thermal budgets and process complexities.
- the recessed structure is subjected to a thermal annealing at a temperature below 1500°C, before gate electrode and ohmic contact deposition or formation.
- metal layers are deposited over ohmic contacts and formed transistors, for interconnecting the ohmic contacts, or as field plates for managing electric field in the transistors.
- FIG. 9 shows an exemplary structure 900 containing two recessed-gate transistors 910 and 920, with doped selectively etchable sublayers, according to some embodiments of the present invention.
- a block or set of consecutive, adjacent, or continuous sublayers between sublayers 611 and 617 (exclusive) are doped. Doping may be performed during epitaxy growth. After recess etching, doped regions are formed between the gate and the source, and between the gate and the drain, outside of the gate and ohmic recesses.
- any subset of the selectively etchable sublayers, continuous or discontinuous may be doped to supply carriers to the channel layer.
- un-etched sublayers below one or both recessed gates may be doped as well.
- Each doped region may be polarization doped or may include dopants such as n-type dopants or p-type dopants.
- Each doped selectively etchable sublayer or each doped region may have any suitable doping concentration and distribution.
- dopants may be provided at the lower surface of a sublayer, the upper surface of a sublayer, or throughout a sublayer.
- the doping profile can be uniform or non-uniform. In some embodiments, a doping concentration of at least 10 16 cm "3 may be used.
- a delta-doping profile may be used, through an individual sublayer, or a block of consecutive sublayers.
- any suitable doping technique may be used, such as implantation or diffusion.
- a selected set of selectively etchable sublayer may be doped during the formation or growth of cap layer 608.
- the doping type may be of the same type as that of the carriers in the channel region.
- the doping type in doped regions shown in FIG. 9 may be n-type for an n-channel transistor, and p-type for a p-channel transistor.
- a doped region may be highly doped.
- additional carrier-donor layers such as layer 22 as shown in FIG. 2A may be further deposited on top of or below cap layer 608.
- a passivation layer may be deposited on top of cap layer 608, wherein the passivation material may be silicon nitride, silicon oxide, aluminum oxide, aluminum nitride, polyimide, benzocyclobutene, silicon oxynitride, aluminum oxynitride, Teflon, and phosphosilicate glass.
- FIG. 10 shows yet another exemplary structure 1000 containing two recessed-gate transistors both with ohmic recesses, according to some embodiments of the present invention.
- ohmic contacts 1016 and 1018 of transistor 1010 are disposed over and cover a first pair of ohmic recesses of one depth
- ohmic contacts 1026 and 1028 of transistor 1020 are disposed over and cover a second pair of ohmic recesses of the same depth.
- Recessed gates 1012 and 1022 are disposed over gate dielectrics 1014 and 1024, which are in turn disposed over and cover gate recesses with different depths.
- each ohmic region may be recessed to reach channel layer 606, band-offset layer 630, spacer layer 632, or a selectively etchable sublayer.
- Ohmic recesses for contacts 1016, 1018, 1026, and 1028 may be formed concurrently, since they are of the same depth.
- Transistors 1010 and 1020 may both be E-mode, or one may be E-mode while the other may be D- mode.
- One advantage of using structures such as 900 in FIG. 9 and 1000 in FIG. 10, with gate recesses and ohmic recesses, over a design such as structure 700 in FIG. 7, which includes a planar transistor without gate recess or ohmic recesses, is to maximize sheet electron density in access regions between gate and S/D, and to minimize sheet resistance in these regions, by retaining the maximum epi layer thickness in these access regions. In addition, trapping effect in these access regions can be mitigated, by keeping the top surfaces of these regions far away from the channel.
- multi-layer structure 600 or 650 may be configured to include more than two types of transistors, each with a different threshold voltage. At least three selectively etchable sublayers may be necessary to achieve different threshold voltages, accordingly.
- FIGS. 7, 8, 9, 10 provide illustrative examples of semiconductor structures for integrating two types of transistors with different threshold voltages on a common substrate, in some embodiments, other devices may be further integrated on the same substrate. Exemplary devices include diodes, capacitors, memories, memristors, optical modulators, waveguides, light emitting diodes, optocouplers, detectors, transformers, resistors, and inductors. In some embodiments, the semiconductor structures as described herein as used for applications including analog circuits, mixed- signal circuits, gate drive circuits, and digital control circuits.
- FIG. 11 shows an exemplary process flow for forming a recess on a semiconductors structure, according to fabrication techniques as described herein.
- a key feature of the recess etching process as discussed is progressive removal of selectively etchable sublayers until a desired recess depth is reached.
- photolithography may be first performed to define a recess opening.
- two or more etching techniques may be iteratively applied to remove odd-numbered and even-numbered sublayers, until a desired recess depth is reached. Any block of consecutive, adjacent, or continuous sublayers may be removed in this manner.
- FIG. 11 shows a process flow for forming a recess on a semiconductor structure such as 600, and where odd-numbered sublayers are Al-light while even-numbered sublayers are Al-rich.
- odd-numbered or odd sublayers may be formed of a first semiconductor material Al x iIn j ,iGa z iN in which x y and ⁇ ⁇ each has a suitable value between zero and one inclusive (0 ⁇ i, yi, and ⁇ ⁇ ⁇ 1), and where X ⁇ ⁇ 0.35;
- even-numbered or even sublayers may be formed of a second semiconductor material A in ⁇ Ga ⁇ in which x 2 , y 2 , and z 2 each has a suitable value between zero and one inclusive (0 ⁇ x 2 , y 2 , and z 2 ⁇ 1), and where x 2 > 0.5.
- the desired recess depths cover an even total number of selectively etchable sublayers in this example.
- photolithography is first performed at step 1120.
- the epitaxy surface of structure 600 is first covered with a dielectric layer, and a recess opening is defined.
- the recess opening is etched in the dielectric and the photoresist is subsequently removed.
- two etching techniques such as dry etching and wet etching may be iteratively applied through steps 1140 and 1150 to remove odd and even sublayers, until a desired recess depth is reached at step 1160.
- step 1140 dry etching is applied to remove an Al-light sublayer and to stop on an Al-rich sublayer; at step 1150, wet etching is applied to remove an Al-rich sublayer and to stop on an Al-light sublayer.
- step 1190 the overall process stops at step 1190. If the desired recess depths cover an odd total number of selectively etchable sublayers, process flow 1100 may be modified accordingly so the total number of selectively etching steps is also odd.
- FIG. 12 shows an exemplary process flow for forming a structure containing two types of recessed-gate transistors according to fabrication techniques as described herein.
- two gate recesses are formed individually at steps 1220 and 1230, through the recess formation process shown in FIG. 11.
- Gate dielectrics and gate contacts may then be deposited at step 1240, and 1250.
- a protective layer may be deposited for the gate stacks at step 1260, before a pair of ohmic recesses is formed at step 1270.
- a second pair of ohmic recesses may be further formed, concurrently with the first pair if both pairs have the same recess depths, or after the first pair, if the two pairs have different recess depths.
- Ohmic contacts are then deposited at step 1280. The overall process ends at step 1290.
- Gate and ohmic recesses are approximately 30nm in depth, and may be formed together, concurrently or in parallel, using appropriate photolithography and progressive etching steps as described with respect to FIGS. 1 1 and 12.
- a threshold voltage Vj as gate-to-source voltage V GS with drain current ⁇ ⁇ of le-3 mA/mm
- a threshold voltage V T of -4.2 V is obtained for the D-mode transistors
- a threshold voltage V T of 0.5 V is obtained for the E-mode transistors.
- threshold voltages are gate voltages past which transistors are turned from an on-state to an off-state, or vice versa.
- FIGS. 14 and 15 Illustrative DC (direct current) characteristics of integrated E/D-mode transistors, with or without gate or ohmic recesses as illustrated by FIGS. 7- 10 are shown in FIGS. 14 and 15.
- FIG. 14 displays a plot 1400 of approximate ID-VGS characteristics for E/D transistors integrated on the same substrate. Drain current I D is expressed in arbitrary units, while drain-to-source voltages are fixed at 5V and 0. IV for each type of transistors. Threshold voltages for the two different types of transistors are within expected ranges of positive or negative values.
- FIG. 15 shows plots 1500 and 1550 representing ID-V D S characteristics for E/D transistors integrated on the same substrate. Drain current I D is expressed in arbitrary units, while VGS varies from - IV to - 10V in - IV steps for D-mode transistors, and from 9V to 0V in - IV steps for E-mode transistors.
- FIG. 16 illustrates a planar-gate, normally-on, D-mode transistor 1600 according to one embodiment of the present invention, using multi-layer structure 650 shown in FIG. 6B, with spacer layer 632.
- Transistor 1600 has a planar gate 1612, disposed above gate dielectric layer 1614 and positioned between recessed ohmic contacts 1616 and 1618.
- a dedicated carrier-donor layer 610 is included in the multi-layer structure, and formed over the top sublayer 61 1 of cap layer 608.
- carrier- donor layer 610 may be optional and omitted.
- structures and techniques as described herein are not limited in this respect, and one or more carrier-donor layers such as carrier-donor layer 610 may be formed within cap layer 608, inserted between selectively etchable sublayers, or in another location.
- carrier-donor layer 610 may be formed of the same material as that of top sublayer 61 1.
- the reaming portions of carrier-donor layer 610 may supply carriers to channel 606 approximately outside the region under the gate.
- spacer layer 632 has an identical bandgap as channel layer 606.
- ohmic recesses are formed through carrier-donor layer 610 and the one or more selectively etchable sublayers, so bottoms of ohmic contacts 1616 and 1618 are placed on spacer layer 632.
- the bottom of each of ohmic contacts 1616 and 1618 may be positioned within or on any selectively etchable sublayer of cap layer 608, spacer layer 632, band- offset layer 630, or channel layer 606.
- transistor 1600 To fabricate transistor 1600, exemplary processes described with respect to transistors 710 and
- Schottky gate contact and ohmic contacts such as 1616 and 1618 may be made gold-free and thus reproducible on large scale wafers with high yield.
- Most low -resistance ohmic contacts in III-N devices use Gold (Au) as a top layer to reduce sheet resistance underneath the ohmic contact region, and to reduce oxidation during high temperature annealing processes.
- Au-based Schottky contacts are also commonly used in III-N semiconductor devices for their low contact resistances.
- carrier-donor layer 610 and sublayers of cap layer 608 may be selectively wet and/or dry etched to stop in a facile and accurate manner with strongly reduced or without any etching damages at spacer layer 632.
- the defect-free surface of space layer 632 may then be alloyed with an ohmic metal to obtain an ohmic contact with low contact resistance.
- Exemplars ohmic metals include, but are not limited to, Ti, TiN, Al, Ta, TaN, Mo, W, VVN, Pt, Ni, and Cu.
- an ohmic contact may have a thickness between 1 nm and 10,000 mm.
- FIG. 17 illustrates an exemplary recessed-gate, normally-off, E-mode transistor 1700 according to one embodiment of the present invention, using epitaxy structure 650 shown in FIG. 6B, with spacer layer 632.
- Transistor 1700 has a recessed gate 1712, disposed above gate dielectric layer 1714 and positioned between recessed ohmic contacts 1716 and 1718.
- bottom of the gate recess for gate 1712 is positioned on spacer layer 632, while bottoms of ohmic recesses for ohmic contacts 1716 and 1718 are positioned within spacer layer 632.
- gate and ohmic recesses may each have a different depth, and bottoms of gate and ohmic recesses may be positioned within or on any selectively etchable sublayer of cap layer 608, spacer layer 632, band-offset layer 630, or channel layer 606.
- gate 1712 is further extended beyond the gate recess region to form a gate field plate 1713 which may help reduce maximum electric field, achieve a desirable electrical field profile across the channel, and increase the breakdown voltage of the III-N transistor.
- any non-zero number of selectively etchable sublayers may be present, where each sublayer is selectively etchable with respect to a sublayer immediately below or above, or both sublayers immediately below and above.
- Spacer layer 632 may serve as an etch stop as well and may or may not be selectively etchable over sublayer 619 immediately above.
- spacer layer 632 may have a narrower bandgap or a lower conduction band edge than band-offset layer 630 below, and a narrower bandgap or a lower conduction band edge than sublayer 619 above.
- FIG. 18 is a band diagram showing the conduction and valence bands of an exemplary semiconductor structure with a spacer layer, according to one embodiment of the present invention.
- the channel layer, band-offset layer, and spacer layers comprise GaN, AlGaN, and GaN respectively, while the cap layer comprises a sublayer of A1N and a sublayer of n-GaN.
- the band-offset layer may have a wider bandgap or a higher conduction band edge than the channel layer below and the spacer layer above.
- the spacer layer may have a narrower bandgap or a lower conduction band edge than not only the band-offset layer, but also the sublayer immediately above.
- a spacer layer with a narrower bandgap makes the net polarization charge at the interface between the spacer layer and the band-offset layer negative as as the polarization of the spacer layer is smaller than that of the band-offset layer, thus helping to improve the threshold voltages when such a multi-layer semiconductor structure with a spacer layer is used in a field-effect transistor.
- FIG. 19 shows an exemplary integrated structure 1900 containing two types of transistors produced on a common substrate, using epitaxy structure 650 shown in FIG. 6B, with a spacer layer 632, and a gate recess produced according to some of the techniques described herein.
- Semiconductor structure 1900 includes two transistors 1910 and 1920.
- Transistor 1910 has a planer gate 1912.
- Transistor 1920 is gate-recessed and includes a gate 1922 with a gate recess through carrier-donor layer 610, cap layer 608, spacer layer 632, and band-offset layer 630.
- Transistors 1910 and 1920 include pairs of ohmic contacts 1916, 1918, and 1926, 1928 respectively. Ohmic recesses are formed in this example to place such ohmic contacts within spacer layer 632.
- bottoms of gate and ohmic recesses may be placed within or on any selectively etchable sublayer of cap layer 608, spacer layer 632, band-offset layer 630, or channel layer 606.
- transistors may be electrically isolated from one another through mesa etching, ion implementation, or a combination of both.
- transistor 1910 is normally -on, with a negative threshold voltage
- transistor 1920 is normally-off, with a positive threshold voltage.
- FIG. 20 shows a cross-sectional view of an exemplary Schottky diode 2000, according to one embodiment of the present invention, using epitaxy structure 650 shown in FIG. 6B.
- cathode 2016 etched to spacer layer 632 is a Schottkey contact
- anode 2012 etched through dielectric 2014 is an ohmic contact. Both are metal structures for biasing the Schottky diode device.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201680048524.5A CN107924939A (zh) | 2015-08-11 | 2016-08-11 | 具有间隔层的半导体结构 |
EP16835909.9A EP3335242A4 (de) | 2015-08-11 | 2016-08-11 | Halbleiterstruktur mit einer abstandsschicht |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562203438P | 2015-08-11 | 2015-08-11 | |
US62/203,438 | 2015-08-11 | ||
US15/094,985 | 2016-04-08 | ||
US15/094,985 US9502535B2 (en) | 2015-04-10 | 2016-04-08 | Semiconductor structure and etch technique for monolithic integration of III-N transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017027704A1 true WO2017027704A1 (en) | 2017-02-16 |
Family
ID=57984111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2016/046546 WO2017027704A1 (en) | 2015-08-11 | 2016-08-11 | Semiconductor structure with a spacer layer |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP3335242A4 (de) |
CN (1) | CN107924939A (de) |
WO (1) | WO2017027704A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220199802A1 (en) * | 2020-12-22 | 2022-06-23 | Applied Materials, Inc. | Implantation Enabled Precisely Controlled Source And Drain Etch Depth |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200052782A (ko) * | 2018-11-07 | 2020-05-15 | 엘지디스플레이 주식회사 | 표시 장치 |
CN110047979B (zh) * | 2019-02-20 | 2020-10-09 | 华灿光电(苏州)有限公司 | 紫外发光二极管外延片及其制造方法 |
CN110444600A (zh) * | 2019-08-05 | 2019-11-12 | 中国电子科技集团公司第十三研究所 | GaN基异质结场效应晶体管及制造方法 |
CN110444599A (zh) * | 2019-08-05 | 2019-11-12 | 中国电子科技集团公司第十三研究所 | GaN基异质结场效应晶体管及其制造方法 |
CN110335898A (zh) * | 2019-08-05 | 2019-10-15 | 中国电子科技集团公司第十三研究所 | GaN基异质结场效应晶体管及制造方法 |
CN112928022B (zh) * | 2021-01-29 | 2023-07-25 | 中国科学院微电子研究所 | 高电子场效应晶体管及其制作方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050072986A1 (en) * | 2001-09-03 | 2005-04-07 | Nec Corporation | Group-III nitride semiconductor device |
US20070164315A1 (en) * | 2004-11-23 | 2007-07-19 | Cree, Inc. | Cap Layers Including Aluminum Nitride for Nitride-Based Transistors and Methods of Fabricating Same |
US20070235775A1 (en) * | 2006-03-29 | 2007-10-11 | Cree, Inc. | High efficiency and/or high power density wide bandgap transistors |
US20080237605A1 (en) | 2007-03-29 | 2008-10-02 | Tomohiro Murata | Semiconductor device and manufacturing method of the same |
US20080258135A1 (en) * | 2007-04-19 | 2008-10-23 | Hoke William E | Semiconductor structure having plural back-barrier layers for improved carrier confinement |
US20120217506A1 (en) * | 2011-02-28 | 2012-08-30 | International Rectifier Corporation (El Segundo, Ca) | III-Nitride Heterojunction Devices Having a Multilayer Spacer |
US20130099245A1 (en) * | 2010-03-26 | 2013-04-25 | Nec Corporation | Field effect transistor, method for producing the same, and electronic device |
US20130256829A1 (en) | 2012-03-29 | 2013-10-03 | Fujitsu Limited | Compound semiconductor device and method of manufacturing the same |
US8592868B2 (en) * | 2008-07-31 | 2013-11-26 | Cree, Inc. | Normally-off semiconductor devices |
US20140306235A1 (en) * | 2013-04-16 | 2014-10-16 | Imec | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7470967B2 (en) * | 2004-03-12 | 2008-12-30 | Semisouth Laboratories, Inc. | Self-aligned silicon carbide semiconductor devices and methods of making the same |
KR100620393B1 (ko) * | 2005-11-03 | 2006-09-06 | 한국전자통신연구원 | 전계효과 트랜지스터 및 그의 제조 방법 |
JP2009060042A (ja) * | 2007-09-03 | 2009-03-19 | Asahi Kasei Electronics Co Ltd | 半導体デバイス |
-
2016
- 2016-08-11 CN CN201680048524.5A patent/CN107924939A/zh active Pending
- 2016-08-11 WO PCT/US2016/046546 patent/WO2017027704A1/en active Application Filing
- 2016-08-11 EP EP16835909.9A patent/EP3335242A4/de not_active Withdrawn
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050072986A1 (en) * | 2001-09-03 | 2005-04-07 | Nec Corporation | Group-III nitride semiconductor device |
US20070164315A1 (en) * | 2004-11-23 | 2007-07-19 | Cree, Inc. | Cap Layers Including Aluminum Nitride for Nitride-Based Transistors and Methods of Fabricating Same |
US20070235775A1 (en) * | 2006-03-29 | 2007-10-11 | Cree, Inc. | High efficiency and/or high power density wide bandgap transistors |
US20080237605A1 (en) | 2007-03-29 | 2008-10-02 | Tomohiro Murata | Semiconductor device and manufacturing method of the same |
US20080258135A1 (en) * | 2007-04-19 | 2008-10-23 | Hoke William E | Semiconductor structure having plural back-barrier layers for improved carrier confinement |
US8592868B2 (en) * | 2008-07-31 | 2013-11-26 | Cree, Inc. | Normally-off semiconductor devices |
US20130099245A1 (en) * | 2010-03-26 | 2013-04-25 | Nec Corporation | Field effect transistor, method for producing the same, and electronic device |
US20120217506A1 (en) * | 2011-02-28 | 2012-08-30 | International Rectifier Corporation (El Segundo, Ca) | III-Nitride Heterojunction Devices Having a Multilayer Spacer |
US20130256829A1 (en) | 2012-03-29 | 2013-10-03 | Fujitsu Limited | Compound semiconductor device and method of manufacturing the same |
US20140306235A1 (en) * | 2013-04-16 | 2014-10-16 | Imec | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor |
Non-Patent Citations (1)
Title |
---|
See also references of EP3335242A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220199802A1 (en) * | 2020-12-22 | 2022-06-23 | Applied Materials, Inc. | Implantation Enabled Precisely Controlled Source And Drain Etch Depth |
US11721743B2 (en) * | 2020-12-22 | 2023-08-08 | Applied Materials, Inc. | Implantation enabled precisely controlled source and drain etch depth |
Also Published As
Publication number | Publication date |
---|---|
EP3335242A1 (de) | 2018-06-20 |
EP3335242A4 (de) | 2019-04-10 |
CN107924939A (zh) | 2018-04-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9536984B2 (en) | Semiconductor structure with a spacer layer | |
US9502535B2 (en) | Semiconductor structure and etch technique for monolithic integration of III-N transistors | |
US9614069B1 (en) | III-Nitride semiconductors with recess regions and methods of manufacture | |
CN113169228B (zh) | 包括垂直栅极模块的横向iii族氮化物器件 | |
US9935190B2 (en) | Forming enhancement mode III-nitride devices | |
US9570600B2 (en) | Semiconductor structure and recess formation etch technique | |
US11322599B2 (en) | Enhancement mode III-nitride devices having an Al1-xSixO gate insulator | |
CN108735810B (zh) | 半导体器件和半导体器件的制造方法 | |
EP3335242A1 (de) | Halbleiterstruktur mit einer abstandsschicht | |
JP5126733B2 (ja) | 電界効果トランジスタ及びその製造方法 | |
US9111956B2 (en) | Rectifier structures with low leakage | |
US20180033631A1 (en) | Self-aligning source, drain and gate process for iii-v nitride mishemts | |
Morgan et al. | Enhancement-mode insulating-gate AlInN/AlN/GaN heterostructure field-effect transistors with threshold voltage in excess of+ 1.5 V | |
US9543425B2 (en) | Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate | |
US20150034958A1 (en) | Hemt-compatible lateral rectifier structure | |
US20240047451A1 (en) | Nitride-based semiconductor ic chip and method for manufacturing the same | |
EP2851944A1 (de) | Halbleitervorrichtung und Verfahren zu ihrer Herstellung | |
EP3440704A1 (de) | Halbleiterstruktur und ätztechnik zur monolithischen integration von iii-n-transistoren |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16835909 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2016835909 Country of ref document: EP |