WO2017024819A1 - Système et procédé de mise en œuvre de lecture/écriture d'informations de carte - Google Patents

Système et procédé de mise en œuvre de lecture/écriture d'informations de carte Download PDF

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Publication number
WO2017024819A1
WO2017024819A1 PCT/CN2016/080555 CN2016080555W WO2017024819A1 WO 2017024819 A1 WO2017024819 A1 WO 2017024819A1 CN 2016080555 W CN2016080555 W CN 2016080555W WO 2017024819 A1 WO2017024819 A1 WO 2017024819A1
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WIPO (PCT)
Prior art keywords
board
serial bus
service
bus interface
memory
Prior art date
Application number
PCT/CN2016/080555
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English (en)
Chinese (zh)
Inventor
董超
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中兴通讯股份有限公司
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Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2017024819A1 publication Critical patent/WO2017024819A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • This document relates to, but is not limited to, the field of electronic communication, and in particular, to a system and method for reading and writing single board information.
  • the board information mainly includes the electronic label of the board, the manufacturing information, and the working status record.
  • the data is stored in a non-volatile memory on the board.
  • the electronic label and manufacturing information are used to record and identify the name of the board.
  • Model, barcode, BOM (Bill of Material) code and description, production date, manufacturer, manufacturing location and other key content can also include software / logic / hardware / structure information on the board, business configuration data, single Board processing / maintenance records, etc.
  • the working status record is mainly for some abnormal states of the board during the working process, such as reset/dead, and corresponding records are made to facilitate fault location.
  • the board information is one of the important data of the board. Its function is equivalent to the “ID card” and “archive information” of the board. It is the only traceable mark in the whole life cycle of the board. Installability, maintainability, manageability, etc., reduce maintenance costs and management costs of the product production cycle.
  • the storage medium is generally EEPROM (Electrically-Erasable Programmable Read). -Only Memory, electrically erasable programming read-only memory) or non-volatile memory such as FLASH (Flash Memory).
  • the reading and writing technology of the board information depends on the CPU (Central Processing Unit) on the service board.
  • the system structure is shown in Figure 1.
  • the inter-board communication interface of the main control board CPU passes through an interface.
  • Switching module the function of the module is mainly to function as a switch. According to the currently accessed service board slot, the inter-board communication interface of the CPU is switched to the inter-board communication interface of the corresponding slot.
  • the inter-board communication interface exits the interface switching module through the backplane interconnection line and reaches the service board CPU.
  • the local bus of the service board CPU is also converted into a serial interface that the memory can recognize after passing through an interface conversion module. Read and write operations to the memory.
  • any of the above three intermediate links has a problem, which will cause the board information on the board to fail to read and write.
  • the CPU may be on the board. The work is abnormal. Therefore, the reliability of reading and writing the board information in this way is poor, which is not conducive to the positioning and maintenance of the board fault.
  • the solution needs to occupy the communication interface resources between the system boards, which reduces the efficiency of the system, and at the same time realizes more links and higher costs. .
  • the embodiment of the invention provides a system and a method for reading and writing information of a board, which can solve the problem of low reliability of reading and writing information of the existing board.
  • a system for reading and writing information on a board including:
  • Main control board back board and one or more business boards
  • the main control board includes: a central processing unit CPU and a serial bus interface driving module, and each of the service boards includes: a memory;
  • the serial bus interface driving module on the main control board is connected to the CPU on the main control board through a serial interface, and drives the serial bus interface signal of the CPU on the main control board to be multi-channel, wherein At least one serial bus interface signal is used as a dedicated serial bus interface signal of the service board;
  • the CPU on the main control board is configured to perform read and write operations on the board information in the memory on each of the service boards by using the dedicated serial bus interface signal of the service board;
  • the backplane is configured to connect a serial bus interface of the CPU on the main control board to a serial bus interface of each of the service boards, and to each of the service boards Provide the service board slot number signal.
  • the memory on the service board is configured to obtain address information according to the service board slot number signal provided by the backboard, and according to the acquired address information, and the service board dedicated serial bus interface.
  • the signal communicates with the CPU on the main control board.
  • the address pin of the memory on each of the service boards is configured to receive the service board slot number signal from the backplane.
  • serial bus interface of the memory on each of the service boards is a two-wire serial bus I2C interface or a serial peripheral interface SPI.
  • the interconnection line on the backplane adopts a star topology
  • the serial bus interface of the CPU on the main control board is respectively connected to the serial bus interface of the memory on each of the service boards.
  • a method for reading and writing information on a board should be implemented in the system for reading and writing information on a board.
  • the method includes:
  • the system for reading and writing the board information drives the serial bus interface signal of the central processing unit CPU on the main control board into multiple channels, wherein at least one serial bus interface signal is used as a service board dedicated serial bus interface signal. ;
  • the CPU on the main control board performs read and write operations on the board information in the memory on each service board through the dedicated serial bus interface signal of the service board.
  • the serial bus interface of the CPU on the main control board is respectively connected to the serial bus interface of the memory on each of the service boards through the backplane, and the backplane is respectively directed to each of the service boards.
  • the upper memory provides a service board slot number signal.
  • the memory on the service board acquires address information according to the service board slot number signal provided by the backboard, and according to the acquired address information, and the service board dedicated serial bus interface signal, The CPU on the main control board communicates.
  • the obtaining, by the memory on the service board, the address information according to the service board slot number signal provided by the backplane includes:
  • the address pin of the memory on each of the service boards receives the slot number signal of the service board on the backplane, and obtains the address information by using the slot number signal of the service board.
  • serial bus interface of the memory on each of the service boards is a two-wire serial bus I2C interface or a serial peripheral interface SPI.
  • the interconnect line on the backplane adopts a star topology, and the serial bus interface of the CPU on the main control board is respectively connected to the serial bus interface of the memory on each of the service boards.
  • the technical solution of the embodiment of the present application is relatively simple to implement.
  • the intermediate link between the interface of the main control board and the memory of the service board is small. Even if the CPU of the service board is abnormal, as long as the service board has power, the service board can be used.
  • the board information in the memory is read and written, which has high reliability and low cost, and improves the efficiency of board fault location and maintenance.
  • FIG. 1 is a schematic structural diagram of a board information reading and writing system in the related art
  • FIG. 2 is a schematic structural diagram of a board information reading and writing system according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a board reading and writing method according to an embodiment of the present invention.
  • This embodiment provides a system for reading information of a single board, including:
  • main control board includes at least: a CPU and a serial bus driving module, and each of the service boards includes at least a memory;
  • a serial interface is connected between the CPU and the serial bus driver module on the main control board, and the serial bus driver module is configured to drive the serial bus interface signal of the CPU into multiple channels, wherein between the main control board and the service board
  • the serial bus interface signal that is exchanged through the backplane is driven as a separate signal.
  • At least one of the serial bus interface signals driven as multiple channels is used as a service board dedicated serial bus interface signal;
  • the CPU on the main control board is configured to perform read and write operations on the board information in the memory on each of the service boards by using the dedicated serial bus interface signal of the service board;
  • the backplane is configured to connect a serial bus interface of a CPU of the main control board to a serial bus interface of each of the service boards, and to provide memory to each of the service boards Service board slot number signal to distinguish the memory of the service board in different slots.
  • the memory on the service board is configured to obtain address information according to the service board slot number signal provided by the backboard, and according to the acquired address information, and the service board dedicated serial bus interface.
  • the signal communicates with the CPU on the main control board.
  • the interconnect line on the backplane may adopt a star topology to implement a connection between the main control board and the service board (ie, the serial bus interface on the main control board and each of the service boards are respectively The serial bus interface of the memory is connected).
  • the serial bus interface of the memory on the service board is connected to the main control board through the backplane interconnection line, wherein the address pin of the memory is connected to the slot number signal on the backplane (ie, the service board slot is received from the backplane). Number signal) to distinguish the address of the memory corresponding to different slots, that is, the address of the memory of different service boards.
  • the serial bus interface used for memory access may generally be an I2C interface or a serial programming interface SPI.
  • the main control board of the system reads and writes the board information in the memory of each service board through the serial bus interface.
  • the memory on all service boards is equivalent to different devices on the serial bus interface of the CPU, and the address passes through the service board.
  • the slot number is distinguished.
  • FIG. 2 is a schematic diagram of the structure of the board reading and writing system in this example.
  • 101 is the main control board, which is set to be responsible for the board information collection of the entire system
  • 102 is the back board, which is set to be responsible for the relationship between the main control board and the service board.
  • the signal connection, 103, 104 is the service board A and the service board B, respectively, and is configured to implement a specific service, and the service board has a memory for storing the board information.
  • the main control board contains the CPU and serial bus driver module, and the serial bus interface used by the CPU is generally For the I2C or the SPI, you can read and write the board information according to the software-configured process. You can also use the external control platform to manually interpret the board information of each board. Since the number of serial bus interfaces provided by the CPU is limited, some devices on the main control board use the interface. If the memory on each service board of each slot is connected together, the CPU interface driving capability may be Can not meet the load requirements, and also cause signal integrity problems, so add a serial bus driver module after the serial bus interface of the CPU, the serial bus of each memory interface on the service board as a separate branch driver, directly Connected to the backplane to ensure the drive capability of the interface.
  • the function of the backplane in the system is to provide a signal connection between the main control board and the serial bus interface of the service board.
  • the optional connection mode uses a star topology, and the backplane also provides a slot number to the service board. signal.
  • FIG. 3 is a complete process for reading and writing information of a board in the above system, including steps 301-305.
  • the CPU of the main control board checks whether the command to read or write the information of the memory board is received. If not, the related process is in the waiting state. When the command is received, 302 is executed.
  • the CPU parses out the physical address of the memory according to the slot number of the service board that needs to read and write the board information.
  • the CPU reads and writes the memory on the service board through the serial bus interface according to the physical address.
  • the number of possible service boards in many application scenarios is greater than the implementation of the present invention.
  • the schematic diagram of the embodiment is much more.
  • the schematic diagram of the embodiment of the present invention is only a case of two service boards, and the manner in which the board information reading and writing system of the embodiment of the present invention is implemented is described.
  • the memory on the service board may be processed in the manner described in the embodiment of the present invention. If the number of service boards is too large, for example, there are 12 or 16 blocks, they can be divided into two groups and driven by serial bus drivers to ensure the drive capability of the interface.
  • This embodiment provides a method for reading and writing information of a board.
  • the method may be implemented by using the foregoing system or applied to the foregoing system.
  • the method mainly includes the following operations:
  • the CPU on the main control board reads and writes the board information in the memory of each service board through the dedicated serial bus interface signal of the service board.
  • serial bus interface of the CPU on the main control board is respectively connected to the serial bus interface of the memory on each of the service boards through the backplane, and the backplane respectively provides a service board to the memory on each of the service boards.
  • Slot number signal to distinguish the memory of the service board in different slots.
  • the method may further include:
  • the memory on the service board acquires address information according to the service board slot number signal provided by the backboard, and then communicates with the CPU on the main control board according to the obtained address information and the service board dedicated serial bus interface signal.
  • the obtaining, by the memory on the service board, the address information according to the service board slot number signal provided by the backplane includes:
  • the address pin of the memory on each of the service boards receives the slot number signal of the service board from the backplane, and obtains the address information of the service board through the slot number signal of the service board.
  • connecting the serial bus interface of the CPU on the main control board in the embodiment to the serial bus interface of the memory on each of the service boards through the backplane may be:
  • the interconnect line on the backplane uses a star topology to connect the serial bus interface of the CPU on the main control board to the serial bus interface of the memory on each of the service boards.
  • the memory serial bus interface on the service board can adopt an I2C interface or an SPI interface.
  • the technical solution of the embodiment of the present application directly uses the serial bus interface of the CPU to read and write the memory, so that the information of the board of the service board can be read and written in the case that the service board CPU is abnormal. Operation reduces unnecessary intermediate links, high reliability, low cost, and reduces the occupation of system resources, and the operation process is also very simple.
  • the remote positioning method can expand the scope of fault location and reduce the cost of equipment maintenance and fault location.
  • the technical solution of the embodiment of the present invention is relatively simple to implement.
  • the intermediate link between the main control board interface and the service board memory is small. Even if the service board CPU is abnormal, as long as the service board has power, the board information in the memory on the service board can be The read and write operations are performed with high reliability and low cost, which improves the efficiency of board fault location and maintenance.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention concerne un système et un procédé pour la mise en œuvre de lecture/écriture d'informations de carte. Le système comprend une carte de commande, une carte arrière et une ou plusieurs cartes de service. La carte de commande comprend une UC et un module de commande d'interface de bus série et chaque carte de service comprend une mémoire. Le module de commande d'interface de bus série sur la carte de commande est configuré pour commander de multiples signaux d'interface de bus série de l'UC sur la carte de commande, au moins un signal parmi les signaux d'interface de bus série servant de signal d'interface de bus série spécifique pour la carte de service. L'UC sur la carte de commande est configurée pour réaliser une opération de lecture/écriture relative aux informations de carte dans la mémoire sur chaque carte de service au moyen du signal d'interface de bus série spécifique pour la carte de service. La carte arrière est configurée pour connecter l'interface de bus série de l'UC sur la carte de commande à l'interface de bus série de la mémoire sur chaque carte de service et pour fournir un signal de numéro de fente à la mémoire sur chaque carte de service.
PCT/CN2016/080555 2015-08-11 2016-04-28 Système et procédé de mise en œuvre de lecture/écriture d'informations de carte WO2017024819A1 (fr)

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CN201510489913.9 2015-08-11
CN201510489913.9A CN106445846A (zh) 2015-08-11 2015-08-11 一种实现单板信息读写的系统和方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362522A (zh) * 2019-05-31 2019-10-22 中兴通讯股份有限公司 一种模块标识的获取方法、装置及系统
CN112838668A (zh) * 2019-11-22 2021-05-25 华为技术有限公司 一种断路器识别方法、装置和设备

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CN107766273B (zh) * 2017-11-09 2020-07-31 安徽皖通邮电股份有限公司 两线编解码与localbus互转以实现板间数据交互的方法
CN107943733A (zh) * 2017-12-05 2018-04-20 安徽皖通邮电股份有限公司 一种单板间并行总线的互联方法
CN109144942B (zh) * 2018-08-28 2021-05-14 深圳市新格林耐特通信技术有限公司 主控板管理业务板的装置及主控板管理业务板的方法
CN111414327B (zh) * 2020-03-17 2021-09-14 深圳市信锐网科技术有限公司 网络设备
CN113032306B (zh) * 2021-03-19 2024-05-28 北京华力智飞科技有限公司 一种仿真机及仿真测试方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1862512A (zh) * 2005-10-25 2006-11-15 华为技术有限公司 单板信息的读写系统与方法
CN101055622A (zh) * 2006-05-17 2007-10-17 华为技术有限公司 一种单板电子标签读写控制系统及方法
US20100106987A1 (en) * 2008-10-29 2010-04-29 Lambert Timothy M Method for pre-chassis power multi-slot blade identification and inventory
CN104615545A (zh) * 2013-11-05 2015-05-13 中兴通讯股份有限公司 单板信息的存储方法及单板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1862512A (zh) * 2005-10-25 2006-11-15 华为技术有限公司 单板信息的读写系统与方法
CN101055622A (zh) * 2006-05-17 2007-10-17 华为技术有限公司 一种单板电子标签读写控制系统及方法
US20100106987A1 (en) * 2008-10-29 2010-04-29 Lambert Timothy M Method for pre-chassis power multi-slot blade identification and inventory
CN104615545A (zh) * 2013-11-05 2015-05-13 中兴通讯股份有限公司 单板信息的存储方法及单板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110362522A (zh) * 2019-05-31 2019-10-22 中兴通讯股份有限公司 一种模块标识的获取方法、装置及系统
CN110362522B (zh) * 2019-05-31 2023-05-12 中兴通讯股份有限公司 一种模块标识的获取方法、装置及系统
CN112838668A (zh) * 2019-11-22 2021-05-25 华为技术有限公司 一种断路器识别方法、装置和设备
CN112838668B (zh) * 2019-11-22 2024-05-17 华为数字能源技术有限公司 一种断路器识别方法、装置和设备

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