WO2017023291A1 - Logique nmos statique pour têtes d'impression - Google Patents

Logique nmos statique pour têtes d'impression Download PDF

Info

Publication number
WO2017023291A1
WO2017023291A1 PCT/US2015/043337 US2015043337W WO2017023291A1 WO 2017023291 A1 WO2017023291 A1 WO 2017023291A1 US 2015043337 W US2015043337 W US 2015043337W WO 2017023291 A1 WO2017023291 A1 WO 2017023291A1
Authority
WO
WIPO (PCT)
Prior art keywords
nmos
high impedance
pull
supply voltage
static
Prior art date
Application number
PCT/US2015/043337
Other languages
English (en)
Inventor
Ning GE
Boon Bing NG
Leong Yap CHIA
Reynaldo V Villavelez
Mun Hooi YAOW
Xiao Song LIU
Ser Chia KOH
Chaw Sing Ho
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2015/043337 priority Critical patent/WO2017023291A1/fr
Publication of WO2017023291A1 publication Critical patent/WO2017023291A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01—Ink jet
    • B41J2/17—Ink jet characterised by ink handling
    • B41J2/175—Ink supply systems ; Circuit parts therefor
    • B41J2/17503—Ink cartridges
    • B41J2/17543—Cartridge presence detection or type identification
    • B41J2/17546—Cartridge presence detection or type identification electronically
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
    • B41J29/393—Devices for controlling or analysing the entire machine ; Controlling or analysing mechanical parameters involving printing of test patterns

Definitions

  • NMOS metal-oxide-semiconductor field effect transistor
  • dynamic NMOS based logic may include a pull-down network including a number of NMOS transistors to couple the output to a first supply voltage that may be associated with one logic value.
  • the dynamic NMOS based logic may also include another load that connects the output to the second supply voltage that may be associated with a second logic value.
  • FIG. 1 depicts an example block diagram of a printer system in accordance with one example of the present specification
  • FIG. 2 depicts an example block diagram of an IPH in accordance with one example of the present specification
  • FIG. 3 depicts an example block diagram of static NMOS based logic with a high impedance load in accordance with one example of the present specification
  • Figs. 4A - 4C illustrates example inverters that are memristor load based static NMOS logic used in an IPH, such as those shown in Figs. 1 and 2, in accordance with one example of the present specification.
  • CMOS circuits implement both p-channel metal-oxide-semiconductor field effect transistor (PMOS) and NMOS circuits to generate a logic value output.
  • PMOS metal-oxide-semiconductor field effect transistor
  • NMOS circuit may be coupled to a first supply voltage and an output.
  • PMOS circuit may be coupled to a second supply voltage and the output.
  • each PMOS circuit is in series with an NMOS circuit such that when one is in an open state the other is in a closed state, preventing current flow. It is when the PMOS and NMOS circuits are changing states that significant amount of current may flow through the CMOS circuit.
  • CMOS architecture Because of the reduced power consumption of CMOS circuits and the attendant reduction in heating, CMOS architecture has seen widespread use in electronics. However, while CMOS circuits may be beneficial, some characteristics may prevent their expanded use. Such dynamic NMOS based logic may be beneficial in providing a reduced foot print, and consequently higher density, compared to complementary metal oxide semiconductor (CMOS) and pseudo-NMOS logic based circuits.
  • CMOS complementary metal oxide semiconductor
  • CMOS circuits by incorporating both NMOS circuits and
  • PMOS circuits may have a greater quantity of transistors, and more complicated, operations to fabricate and accordingly may be more expensive. Accordingly, a pulldown network including a number of NMOS transistors may be used instead of CMOS circuit to couple to the output to the first supply voltage that may be associated with one logic value.
  • the pull-down network also includes another load that connects the output to the second supply voltage that may be associated with a second logic value.
  • Such pulldown networks may offer manufacturing advantages over CMOS due to the reduced number of manufacturing operations during wafer fabrication. Moreover, such pull-down networks may also utilize smaller logic elements. While such pull-down networks may be beneficial, they may have some restraints on expanded use.
  • the other load on the pull-down network may take up significant space on the circuit due in part to the large resistance used for a pseudo-pull-up network.
  • such pull-down network i.e., dynamic NMOS based logic
  • ASIC dedicated specification specific integrated circuit
  • the speed and power dissipation of such NMOS based logic may need to be simulated and optimized.
  • existing IPHs use CMOS logic with other analog functions and have fewer circuit designs and bond pads. However, they may result in using more complicated and expensive processes, since both PMOS and NMOS logic may need to be integrated during the fabrication process.
  • present specification discloses techniques to alleviate these and other complications that may arise in the control logic used in IPHs. More specifically, the present specification describes a pull-down network that includes a high impedance load that is much smaller in size than other high impedance loads. Resistor dimensions are defined by length and width and for example, for a given width, the length of the resistor may have to be increased to increase the resistance and vice versa.
  • the term "high impedance load” refers to an electrical load having high impedance.
  • Example electrical load is an electrical component or a portion of a circuit that consumes electrical power.
  • the high impedance load may be a memristor.
  • the memristor is a two connection electronic component whose resistance is dependent upon its current history.
  • a memristor may also be used as a memory element of the IPH to store a logic value based on a resistance of the memristor.
  • a memristor is non-volatile, meaning that data in the resistance state are retained even when power is not applied to the memristor.
  • memristors may have a metal-insulator-metal structure that occupies a relatively small amount of surface area on a chip, making them attractive for use in an inverter and memory for IPHs in printing systems.
  • memristor can be 4F 2 size.
  • memristors can be manufactured and implemented relatively cheaply, thereby reducing the cost associated with production. Memristors may be added to wafer with few or no additional manufacturing operations.
  • memristors in the control logic may reduce the number of bond pads needed in the control logic and thereby increasing circuit features/bond pads ratio.
  • memristors, being compact in layout and having tunable resistance property, can be easily integrated into static logic.
  • Memristors can be made in a number of geometries and using a variety of materials.
  • One form is a metal-insulator-metal memristor.
  • the term "metal” is meant to refer broadly to indicate a conductor, for instance doped silicon.
  • a memristor may include a bottom electrode (metal), a switching oxide (insulator), and a top electrode (metal).
  • the bottom electrode which may be part of another electronic component, can be coated with an insulator to form a switching oxide. This switching oxide insulator is then coated with a layer of another conductive material to form a top electrode.
  • the switching oxide of the memristor may be doped with p type impurities and thus having holes. When an electrical field is applied to the memristor in one direction, the holes spread throughout the switching oxide, rendering it conductive. When an electrical field is applied to the memristor in the opposite direction, the holes are collected on one side, rendering the switching oxide non-conductive.
  • the specification of an electrical field can shift a memristor from high resistance to low resistance (or vice versa). Absent an applied field, the holes are stable, and thus the resistance state of the memristor can be used to store data without a continuous supply of power.
  • the memristor can be used to provide high impedance values in the high resistant state.
  • the thickness, composition, and structure of the insulating switching oxide can be controlled during deposition to generate a desired resistance.
  • the present specification describes control logic in an IPH having inverters with a high impedance load.
  • the control logic in the IPHs includes an output and a pull-down network serially-coupled between a first voltage and the output.
  • the control logic in the IPHs also include high impedance load serially coupled between a second supply voltage and the output.
  • the high impedance load being a memristor that is smaller in size than a transistor based load, such as PMOS based electrical component in the pull-down network.
  • the present specification describes a printing system having such pulldown network with a high impedance load.
  • the printing system includes a first supply voltage, a second supply voltage, and an output.
  • the printing system also includes at least one n-channel metal-oxide semiconductor field effect transistor (NMOSs) serially- coupled between the first supply voltage and the output and a high impedance load serially-coupled between the second supply voltage and the output.
  • NMOSs metal-oxide semiconductor field effect transistor
  • the high impedance load is disposed on a drain of an NMOS.
  • Such memristor based NMOS logic for IPHs enable more on-chip functionality like serial to parallel convention, registers operation and so on.
  • ADC analog-to-digital converter
  • Fig. 1 depicts an example printer system 100 and a host system 102, according to one example of the principles described herein.
  • the printer system 100 comprises various hardware components.
  • the printer system 100 may include a controller 104, an ink supply device 106, a power supply 108, and an IPH 110.
  • the ink supply device 106 may include memory 107.
  • the memory 107 may store information associated with ink to be supplied for printing. In this case, the information may include the quantity of ink in the ink supply device 106, ink manufacturer, expiration date of the ink, color of the ink, conductivity of the ink, and the like. Further as shown in Fig.
  • the IPH 110 may include memory 114 and nozzle control logic 112.
  • the memory 114 may store data associated with the printing operation.
  • data include a document and or a file to be printed.
  • the term "memories 107 and 114" include any type of integrated circuit or other storage device for storing digital data including, without limitation, ROM, PROM, EEPROM, DRAM, Mobile DRAM, SDRAM, DDR 2 SDRAM, EDO/FPMS. RLDRAM, SRAM, "flash” memory (e.g., NAND/NOR), memristor memory, and PSRAM.
  • the nozzle control logic 112 may include a data processor
  • the data processor 116 may be in electrical communication with the driver head 118. In operation, the data processor 116 may instruct the driver head 118 to drive printer nozzles to fire the ink.
  • the term "data processor” means generally to include all types of digital processing devices including, without limitation, digital signal processors (DSPs), reduced instruction set computers (RISC), general-purpose (CISC) processors, microprocessors, gate arrays (e.g., field programmable gate arrays (FPGAs)), PLDs, reconfigurable computer fabrics (RCFs), array processors, secure microprocessors, and application-specific integrated circuits (ASICs).
  • DSPs digital signal processors
  • RISC reduced instruction set computers
  • CISC general-purpose
  • microprocessors e.g., gate arrays (e.g., field programmable gate arrays (FPGAs)), PLDs, reconfigurable computer fabrics (RCFs), array processors, secure microprocessors, and application-specific integrated circuits (ASICs).
  • Fig. 2 depicts the example IPH 110, according to one example of the principles described herein.
  • the IPH 110 may include a nozzle control logic 112 that is communicatively coupled to each of primitive logics 1-N 210 to send associated data addresses.
  • the IPH 110 may include a memory array 114 and memory control logic 220.
  • each logic i.e., nozzle control logic 112, primitive logics 1-N 210, memory control logic 220, and the like
  • each logic includes a static NMOS logic 230 with a high impedance load 312 (shown in Fig. 3).
  • Fig 3 depicts the example block diagram of the static NMOS logic also referred to as ratioed logic 230 including a high impedance load 312.
  • the static NMOS logic 230 may refer to circuitry that connects an output 317 to either first supply voltage 314, which may be ground, negative, or less than a second supply voltage 315, which second supply voltage 315 may be positive. More specifically, the static NMOS logic 230 implements pull up devices and pull down devices of different strengths to pass either a high or low output 317.
  • the static NMOS logic 230 is included in circuitry, such as nozzle control logic, primitive logic, memory control logic and the like in the IPH 110 to carry out operations.
  • the static NMOS logic 230 may be included in any type of element that is used in performing logic functions in the IPH 110 and among other integrated circuits in the printer system 100.
  • the static NMOS logic 230 generates an output 317.
  • the output 317 may reflect one of two voltages (314 and 315) - either the first supply voltage
  • the pull-down network 313 may be a collection of logic elements.
  • the pull-down network 313 receives input from control signals 316, which determines the state of pull-down network 313.
  • the pull-down network 313 is in either an open state or a closed state.
  • the pull-down network 313 is in open state, there is no electrical connection between the output 317 and the first supply voltage 314, so the voltage on the output 317 may reflect the second supply voltage 315.
  • the pull-down network 313 When the pull-down network 313 is in closed state, an electrical connection is established between the first supply voltage 314 and the output 317. Because the high impedance load 312 may limit the flow of current from the second supply voltage 315, while no similar limit exists between the first supply voltage 314 and the output 317, the output 317 may reflect the first supply voltage 314. Accordingly, depending on the state of the pull-down network 313, the output value may reflect either the first supply voltage 314 or the second supply voltage 315.
  • the pulldown network 313 may be in an open or closed state when the high impedance load 312 is in a closed state.
  • the first supply voltage 314 is a ground, negative, or positive but of a lower voltage value than the second supply voltage 315.
  • the pull-down network 313 can take a variety of forms. In one example, it is a number of NMOSs formed as a multi-enclosed transistor. In another example, the NMOSs include a number of double enclosed NMOSs, in which a drain for a first NMOS functions as a source for a second NMOS. The NMOSs may be connected so as to perform a variety of logic operations on the control signals 316.
  • the pull-down network 313 may contain other electronic components besides NMOSs to facilitate the printer system 100 operations.
  • the static NMOS logic includes a high impedance load 312.
  • the high impedance load 312 allows the output 317 to be generated based on the second supply voltage 315 which may be a positive supply voltage greater than the first supply voltage 314.
  • the high impedance load 312 may reduces the total current consumed by reducing flow between the first supply voltage 314 and the second supply voltage 3 5.
  • the high impedance load 312 also allows the output 317 to reflect either voltage (314, 315) using a single switch. Without the high impedance load 312, the load from the pull-down network 313 may prevent the output 317 from reading the first supply voltage 314.
  • the static N OS logic as described herein may provide reduced amounts of current from the second supply voltage 315 to the output 317 due to the high impedance load 312 being connected in series with the pull-down network 313.
  • the output 317 can be used to control a transistor directly connected to the second supply voltage 315.
  • the resistance of the high impedance loads 312 can be varied to control the fan-out and to optimize the response time of the controlled logic.
  • the high impedance load 312 is a memristor in a high resistance state.
  • the high impedance load 312 is a plurality of memristors, where some are in a high resistance state.
  • the memristor may be non- rewritable. This allows the memristor to be included independent of switching controls for the memristor, which further simplifies the device. This is advantageous in that the memristor cannot be set to the wrong value and cannot be accidentally changed to the wrong value.
  • the memristor state may be set during manufacturing or may be set later.
  • Figs. 4A through 4C depict example circuit diagrams of static NMOS logics 400A to 400Cwith respective memristors 416-1 to 416-3 according to examples of the principles described herein.
  • the NMOS logics 400A to 400C may refer to circuits that connect outputs 317-1 to 317-3 to either first supply voltages 314-1 to 314-3 or second supply voltages 315-1 to 315-3, respectively.
  • Fig. 4A depicts the static NMOS logic 400A to perform an "AND" function that relies on inputs 419-1 and 419-2.
  • the memristor 416-1 is a memory element that indicates a logic value based on a resistance level of the memristor 416-1.
  • FIG. 4B depicts the static NMOS logic 416-2 implementing an AND as well as an OR function that relies on inputs 419-3 to 419-5.
  • Fig. 4C depicts the static NMOS logic 416-3 implementing a NOT function. Implementing a NOT function relies on a single input 419-6 which may be indicated as a sixth input 419-6 to distinguish between the inputs 419-1 to 419-5 shown in Figs. 4A and 4B.
  • memristors may add benefits to IPH (Fig. 2, 110), including potentially high memory densities, simple formation, non-volatile memory, and low costs
  • using a high impedance load (Fig. 3. 312) comprising memristor (Figs. 4A-C, 416-1 to 416-3) components may be incorporated into some designs without additional process operations or production costs.
  • the compact design of memristor (Figs. 4A-C, 416-1 to 416-3) being built into the size of the transistor offers the advantage of a high impedance load (Fig. 3, 312) without occupying additional space.
  • the memristor (Fig. 4, 416-1 to 416-3) functioning as a high impedance load (Fig. 3, 312).
  • some control elements that would otherwise be desired to set or clear the memristor (fig. 4, 416-1 to 416-3) memory may not be included. Because the memristor (Fig. 4, 416-1 to 416-3) does not serve as a low resistance element, the electrical contacts can be relatively poor conductors and still perform their function.
  • the IPH (Fig. 2, 110) with multi enclosed transistors and circuits (112, 114 and 210) to allow functioning of a static N OS pull-down logic (Fig. 2, 230) may have a number of advantages, including: reduced manufacturing costs, fewer process operations, ability to vary the high impedance load (Fig. 3, 312) from area to area of the circuit, smaller geometries for the logic, significant reduction in bond pads, shorter connection distances between elements, and slimmer die. Further, such multi enclosed transistors and circuits (112, 114 and 210) to allow functioning of a static NMOS pulldown logic (Fig.
  • the present specification discloses techniques to use memristors in static NMOS logic used in print heads such as IPHs including print heads with cartridge and print heads without cartridges. Even though the present specification discloses techniques to use memristors in IPH and printer system, it can be envisioned that the disclosed techniques may be used in any other electronic devices.

Abstract

Dans un exemple, l'invention concerne une tête d'impression comprenant un circuit à transistor à effet de champ à structure métal-oxyde-semiconducteur à canal n (nMOS) avec une charge de haute impédance. Le circuit nMOS statique comprend un réseau de rappel vers le niveau bas (pull-down network) couplé entre une première tension d'alimentation et une sortie. La tête d'impression comprend également une charge de haute impédance couplée entre une seconde tension d'alimentation et la sortie. La charge de haute impédance est plus petite que celle d'un transistor du réseau de rappel vers le niveau bas.
PCT/US2015/043337 2015-07-31 2015-07-31 Logique nmos statique pour têtes d'impression WO2017023291A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/043337 WO2017023291A1 (fr) 2015-07-31 2015-07-31 Logique nmos statique pour têtes d'impression

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/043337 WO2017023291A1 (fr) 2015-07-31 2015-07-31 Logique nmos statique pour têtes d'impression

Publications (1)

Publication Number Publication Date
WO2017023291A1 true WO2017023291A1 (fr) 2017-02-09

Family

ID=57943369

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/043337 WO2017023291A1 (fr) 2015-07-31 2015-07-31 Logique nmos statique pour têtes d'impression

Country Status (1)

Country Link
WO (1) WO2017023291A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019148784A1 (fr) * 2018-02-05 2019-08-08 杭州旗捷科技有限公司 Circuit de rétroaction de seuil variable, puce de consommable et consommable
CN110325371A (zh) * 2017-04-05 2019-10-11 惠普发展公司，有限责任合伙企业 管芯上时移的致动器评估
CN110719845A (zh) * 2017-07-11 2020-01-21 惠普发展公司，有限责任合伙企业 基于致动器激活数据的流体致动器评估

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6471324B1 (en) * 1998-11-11 2002-10-29 Canon Kabushiki Kaisha Printhead with malfunction prevention function and printing apparatus using it
US20020191044A1 (en) * 2001-06-15 2002-12-19 Ichiro Saito Ink-jet printhead board, ink-jet printhead, and ink-jet printing apparatus
US20040017414A1 (en) * 2002-07-23 2004-01-29 Canon Kabushiki Kaisha Printhead and image printing apparatus
US20140078223A1 (en) * 2012-09-18 2014-03-20 Canon Kabushiki Kaisha Printhead substrate and printing apparatus
US20150114927A1 (en) * 2013-10-31 2015-04-30 Hewlett-Packard Development Company, L.P. Forming memristors on imaging devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6471324B1 (en) * 1998-11-11 2002-10-29 Canon Kabushiki Kaisha Printhead with malfunction prevention function and printing apparatus using it
US20020191044A1 (en) * 2001-06-15 2002-12-19 Ichiro Saito Ink-jet printhead board, ink-jet printhead, and ink-jet printing apparatus
US20040017414A1 (en) * 2002-07-23 2004-01-29 Canon Kabushiki Kaisha Printhead and image printing apparatus
US20140078223A1 (en) * 2012-09-18 2014-03-20 Canon Kabushiki Kaisha Printhead substrate and printing apparatus
US20150114927A1 (en) * 2013-10-31 2015-04-30 Hewlett-Packard Development Company, L.P. Forming memristors on imaging devices

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110325371A (zh) * 2017-04-05 2019-10-11 惠普发展公司，有限责任合伙企业 管芯上时移的致动器评估
US10786987B2 (en) 2017-04-05 2020-09-29 Hewlett-Packard Development Company, L.P. On-die time-shifted actuator evaluation
CN110325371B (zh) * 2017-04-05 2020-11-17 惠普发展公司，有限责任合伙企业 管芯上时移的致动器评估
CN110719845A (zh) * 2017-07-11 2020-01-21 惠普发展公司，有限责任合伙企业 基于致动器激活数据的流体致动器评估
EP3606762A4 (fr) * 2017-07-11 2020-11-18 Hewlett-Packard Development Company, L.P. Évaluation d'actionneur de fluide sur la base de données d'activation d'actionneur
CN110719845B (zh) * 2017-07-11 2021-08-31 惠普发展公司，有限责任合伙企业 射流模具和用于评估其中的流体致动器的方法
US11975534B2 (en) 2017-07-11 2024-05-07 Hewlett-Packard Development Company, L.P. Fluid actuator evaluation based on actuator activation data
WO2019148784A1 (fr) * 2018-02-05 2019-08-08 杭州旗捷科技有限公司 Circuit de rétroaction de seuil variable, puce de consommable et consommable
US11351790B2 (en) 2018-02-05 2022-06-07 Hangzhou Chip Jet Technology Co., Ltd. Threshold variable feedback circuit,consumable chip, and consumable

Similar Documents

Publication Publication Date Title
US9425192B2 (en) Integrated circuit decoupling capacitors
JP3802239B2 (ja) 半導体集積回路
JP7422205B2 (ja) 抵抗変化素子アレイにおける抵抗変化素子にアクセスするためのデバイスおよび方法
US11004479B2 (en) Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array
US8929119B2 (en) Memory module and on-die termination setting method thereof
US8619488B2 (en) Multi-level electrical fuse using one programming device
CN102122528A (zh) 将相变存储器并入cmos工艺的非易失性sram单元
US9899079B2 (en) Memory devices
US10741246B2 (en) Method, system and device for integration of volatile and non-volatile memory bitcells
EP2159800A1 (fr) Décodeur de rangée pour une dispositif de mémoire non volatile de matériaux changement de phase
US8289800B2 (en) Nonvolatile semiconductor memory device
WO2017023291A1 (fr) Logique nmos statique pour têtes d'impression
TW586229B (en) Semiconductor integrated circuit
US7170116B2 (en) Integrated circuit well bias circuitry
US20120106243A1 (en) Current control apparatus and phase change memory having the same
US7831845B2 (en) Power-up circuit and semiconductor memory apparatus with the same
US8823415B2 (en) Logic gate
WO2020158531A1 (fr) Dispositif de stockage et procédé de programmation
JPH0917964A (ja) 半導体装置
JP2007504592A5 (fr)
KR101062758B1 (ko) 서로 상이한 기능을 갖는 상변화 메모리 장치로 구성되는 퓨젼 메모리 장치 및 이를 이용한 데이터 처리 시스템
CN111564427B (zh) 整合式多功能芯片
CN114189242A (zh) 一种基于三端阻变器件的三态门电路
CN115223630A (zh) 驱动电路和电子装置
CN111279417A (zh) 可重配置电路体系架构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900559

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15900559

Country of ref document: EP

Kind code of ref document: A1