WO2017018991A1 - Modification de canal de bus - Google Patents

Modification de canal de bus Download PDF

Info

Publication number
WO2017018991A1
WO2017018991A1 PCT/US2015/042004 US2015042004W WO2017018991A1 WO 2017018991 A1 WO2017018991 A1 WO 2017018991A1 US 2015042004 W US2015042004 W US 2015042004W WO 2017018991 A1 WO2017018991 A1 WO 2017018991A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
bus
switch
signals
slot
Prior art date
Application number
PCT/US2015/042004
Other languages
English (en)
Inventor
Melvin K. Benedict
Edward G. BENSON
Karl J. Bois
Original Assignee
Hewlett Packard Enterprise Development Lp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Enterprise Development Lp filed Critical Hewlett Packard Enterprise Development Lp
Priority to PCT/US2015/042004 priority Critical patent/WO2017018991A1/fr
Publication of WO2017018991A1 publication Critical patent/WO2017018991A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

L'invention concerne un système et des procédés se rapportant à la modification d'un canal de bus. Le système peut comprendre un processeur et un contrôleur mémoire connecté électriquement au processeur. Le système peut comprendre un bus mémoire et des bancs de mémoire connectés électriquement à au contrôleur mémoire par l'intermédiaire du bus mémoire. Chaque banc de mémoire peut comprendre un connecteur pour recevoir un module de mémoire et pour coupler le module de mémoire au bus mémoire. Le système peut comprendre au moins un commutateur connecté électriquement au contrôleur mémoire par l'intermédiaire du bus mémoire, le commutateur servant à isoler au moins un banc de mémoire du bus de mémoire.
PCT/US2015/042004 2015-07-24 2015-07-24 Modification de canal de bus WO2017018991A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/042004 WO2017018991A1 (fr) 2015-07-24 2015-07-24 Modification de canal de bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/042004 WO2017018991A1 (fr) 2015-07-24 2015-07-24 Modification de canal de bus

Publications (1)

Publication Number Publication Date
WO2017018991A1 true WO2017018991A1 (fr) 2017-02-02

Family

ID=57885151

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/042004 WO2017018991A1 (fr) 2015-07-24 2015-07-24 Modification de canal de bus

Country Status (1)

Country Link
WO (1) WO2017018991A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090204736A1 (en) * 2005-05-27 2009-08-13 Ati Technologies Ulc Computing device with flexibly configurable expansion slots, and method of operation
US20090248969A1 (en) * 2008-03-31 2009-10-01 Larry Wu Registered dimm memory system
WO2010144624A1 (fr) * 2009-06-09 2010-12-16 Google Inc. Programmation de valeurs de résistance de terminaison dimm
US20120110229A1 (en) * 2008-05-28 2012-05-03 Rambus Inc. Selective switching of a memory bus
US20130341790A1 (en) * 2004-03-02 2013-12-26 Michael W. Leddige Interchangeable connection arrays for double-sided dimm placement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130341790A1 (en) * 2004-03-02 2013-12-26 Michael W. Leddige Interchangeable connection arrays for double-sided dimm placement
US20090204736A1 (en) * 2005-05-27 2009-08-13 Ati Technologies Ulc Computing device with flexibly configurable expansion slots, and method of operation
US20090248969A1 (en) * 2008-03-31 2009-10-01 Larry Wu Registered dimm memory system
US20120110229A1 (en) * 2008-05-28 2012-05-03 Rambus Inc. Selective switching of a memory bus
WO2010144624A1 (fr) * 2009-06-09 2010-12-16 Google Inc. Programmation de valeurs de résistance de terminaison dimm

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