WO2017004850A1 - 源极驱动模块以及液晶面板 - Google Patents

源极驱动模块以及液晶面板 Download PDF

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WO2017004850A1
WO2017004850A1 PCT/CN2015/084377 CN2015084377W WO2017004850A1 WO 2017004850 A1 WO2017004850 A1 WO 2017004850A1 CN 2015084377 W CN2015084377 W CN 2015084377W WO 2017004850 A1 WO2017004850 A1 WO 2017004850A1
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Prior art keywords
data
timing controller
liquid crystal
pixels
switches
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French (fr)
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吴晶晶
熊志
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/770,140 priority Critical patent/US10147380B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a source driving module and a liquid crystal panel including the same.
  • Liquid Crystal Display is a flat ultra-thin display device consisting of a certain number of color or black-and-white pixels placed in front of a light source or a reflective surface. LCD monitors have low power consumption and are characterized by high image quality, small size, and light weight. Therefore, they are favored by everyone and become the mainstream of displays.
  • the liquid crystal display is mainly a Thin Film Transistor (TFT) liquid crystal display, and the liquid crystal panel is a main component of the liquid crystal display.
  • the liquid crystal panel generally includes a color film substrate and a TFT array substrate disposed opposite to each other and sandwiched between the two substrates. Liquid crystal layer.
  • the driving of the liquid crystal panel is performed by the gate driving module and the source driving module respectively supplying scan signals and data signals to the respective pixels, and the voltage difference between the different data signal voltages and the common electrode voltage causes the liquid crystals to have different rotation angles to form brightness.
  • the difference that is, the display of the liquid crystal panel forms different gray levels.
  • the source driving module sequentially includes a bi-directional shift register (S/R) and a data register according to the direction of the data signal.
  • Latch, L potential shifter
  • L/S digital to analog converter
  • D/A Converter digital to analog converter
  • Buffer B
  • the digital signal output from the Timing Control is input to the data register L in the bidirectional shift register S/R control, and the voltage of the digital signal is boosted by the potential shifter L/S.
  • the converter DAC is converted into an analog signal input to the analog buffer amplifier B, and a signal output from the analog buffer amplifier B is supplied to each pixel.
  • the source driving module needs to output N signals respectively to provide the N pixels, and at this time, the source driving module correspondingly includes N pixels.
  • Bidirectional shift register S/R 1 to S/R N N data registers L 1 to L N , N potential shifters L/S 1 to L/S N , N digital-to-analog converters DAC 1 to DAC N and N analog buffer amplifiers B 1 to B N .
  • Each signal output channel includes a bidirectional shift register S/R, a data register L, a potential shifter L/S, a digital to analog converter DAC, and an analog buffer amplifier B.
  • each row of pixels of the liquid crystal panel includes a large number of pixels, that is, the value of N is usually large. Therefore, in the source driver module of the above structure, each sub-function module requires a large number of devices and a high cost.
  • the present invention provides a source driver module in which the number of devices required for each sub-function module is small and the cost is reduced.
  • a source driving module is configured to receive a data signal from a timing controller and provide each sub-pixel in a liquid crystal panel, wherein each row of sub-pixels in the liquid crystal panel includes N sub-pixels, wherein the source driving module includes : n data input channels, receiving n sets of data signals from the timing controller; n potential shifters respectively connected to the n data input channels; n digital-to-analog converters respectively connected to the n Potential shifter; N switches, divided into a group, each set of switches is respectively connected to the n digital-to-analog converters; N analog buffer amplifiers are sequentially divided into a group, one to one connected to the a group switch; a frequency divider converts a clock signal output from the timing controller into a switch control signal for sequentially turning on the One of the group switches; in the mth data transmission period, the n data input channels receive a data signal of n pixels from the timing controller, and the switch control signal controls the mth group switch to be turned on, a data signal of
  • n 6
  • the data transmission period includes a plurality of clock signal periods, and each data input channel receives a data signal of one pixel from the timing controller respectively during a data transmission period; wherein a period of the switch control signal is The data transmission periods are equal.
  • the data signal received by each data input channel is an 8-bit digital signal.
  • the data transmission period includes four clock signal periods.
  • the present invention also provides a liquid crystal panel including a liquid crystal display unit, a timing controller, a source driving module, and a gate driving module;
  • the liquid crystal display unit includes a plurality of sub-pixels, each row of sub-pixels including N sub-pixels,
  • the timing controller controls the source driving module to provide a data signal to the sub-pixel, and the timing controller controls the gate driving module to provide a scan signal to the sub-pixel, wherein the source driving module is The source drive module as described above.
  • the source driving module provided by the embodiment of the present invention, the number of devices required for each sub-function module is small, and the cost is reduced.
  • FIG. 1 is a schematic structural view of a conventional source driving module.
  • FIG. 2 is a schematic structural view of a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a source driving module according to an embodiment of the present invention.
  • FIG. 4 is a timing diagram showing a relationship between a switch control signal and a clock signal in an embodiment of the present invention.
  • the liquid crystal panel 100 includes a liquid crystal display unit 10 , a timing controller 20 , a source driving module 30 , and a gate driving module 40 .
  • the liquid crystal display unit includes a plurality of sub-pixels P, each row of sub-pixels includes N sub-pixels P 1 , P 2 , . . . , P N , and the timing controller 20 controls the source driving module 30 to the sub-pixels.
  • the pixel P provides a data signal
  • the timing controller 20 controls the gate driving module 40 to supply a scan signal to the sub-pixel P.
  • the present embodiment provides a novel structure source driving module 30.
  • the source driving module 30 includes n data input channels, n potential shifters, n digital-to-analog converters, and N switches. Group), N analog buffer amplifiers Group) and a divider.
  • N is an integer greater than 1
  • n is an even number
  • N>>n Is an integer greater than 1.
  • the value of N depends on the number of sub-pixels included in each row of the liquid crystal display unit 10, for example, the value is 960 or 1024, etc., and the value of N is much larger than n, and the value of n is preferably in the range of 2 ⁇ n ⁇ 10.
  • the source driving module 30 includes six data input channels C 1 - C 6 , six potential shifters L / S 1 - L / S 6 , and six digital-to-analog converters DAC 1 - DAC 6.
  • N switches SW 1 to SW N , N analog buffer amplifiers B 1 to B N and one frequency divider 31.
  • the six data input channels C 1 -C 6 receive six sets of data signals Data from the timing controller 20, and the data signals Data are digital signals.
  • six potential shifters L/S 1 to L/S 6 are respectively connected to the six data input channels C 1 - C 6 for boosting the voltage of the boosted digital signal.
  • Six digital-to-analog converters DAC 1 to DAC 6 are respectively connected to the six potential shifters L/S 1 to L/S 6 for converting digital signals into analog signals.
  • N switches SW 1 to SW N are sequentially divided into Groups, each group including six switches are respectively connected to the six digital-to-analog converters DAC 1 to DAC 6 .
  • the first set of switches comprises six switches SW 1 ⁇ SW 6, the six switches SW 1 ⁇ SW 6-one correspondence to the 6 digital to analog converter connected to DAC 1 ⁇ DAC 6;
  • 6 second set of switches comprises switches SW 7 ⁇ SW 12, the six switches SW 7 ⁇ SW 12 is connected to the six one-analog converter DAC 1 ⁇ DAC 6; and so on, of Switch group comprising six switches SW N-5 ⁇ SW N, the six switches SW N-5 ⁇ SW N are connected to the six one-analog converter DAC 1 ⁇ DAC 6.
  • the N analog buffer amplifiers B 1 to B N are connected to the N switches SW 1 to SW N in a one-to-one correspondence. It can also be considered that the N analog buffer amplifiers B 1 to B N are sequentially divided into The first group of analog buffer amplifiers B 1 -B 6 are connected one-to-one to the first group of switches SW 1 -SW 6 , and the second group of analog buffer amplifiers B 7 -B 12 are connected to the second group of switches one by one. SW 7 ⁇ SW 12 ; and so on, The group analog buffer amplifiers B N-5 to B N are connected one by one to the first Group switch SW N-5 to SW N .
  • the frequency divider 31 converts the clock signal CLK output from the timing controller 10 into a switch control signal SC for sequentially turning on the One of the group switches.
  • One cycle of the switch control signal SC includes a period of a plurality of clock signals CLK, and the period of the switch control signal SC should be equal to the data transfer period.
  • the data transmission period refers to a period in which the data input channels C 1 to C 6 receive the data signals of one pixel from the timing controller 20 .
  • a pixel data signal output from the timing controller 20 is a 8bit digital signal
  • the six data input channels C 1 ⁇ C 6 receives a 8bit digital signal requires 4 cycles
  • the clock signal CLK at this time, the data transmission period is 4 clock signals CLK.
  • the period of the switching control signal SC is equal to the data transmission period. Therefore, as shown in FIG. 4, the period of the switching control signal SC includes four periods of the clock signal CLK.
  • the process of transmitting the data signal by the source driving module 30 as provided above is specifically: the six data input channels C 1 - C 6 receive the data signals of six pixels from the timing controller 20 during the mth data transmission period.
  • the switch control signal SC controls the mth group switch to be turned on (at this time, the other group switches are turned off), and the data signals of the 6 pixels are input to the mth group of analog buffer amplifiers;
  • N analog buffer amplifiers B 1 -B N receive data signals (that is, receive data signals of a whole row of sub-pixels P 1 -P N )
  • the timing controller 20 sends N analog buffer amplifiers B 1 to B N inputs a TP (Latch Pulse Signal) signal, and controls the N analog buffer amplifiers B 1 to B N to supply data signals to the N sub-pixels P 1 to P N , respectively .
  • TP Lock Pulse Signal
  • the switch control signal SC corresponding to the first cycle, a first set of switches SW 1 ⁇ SW 6 is turned on, the remaining group of switches are closed, then six channel data input C 1 ⁇ C 6 6 signal timing data received from the controller 20 through the first set of input switches SW 1 ⁇ SW 6 to a first set of analog buffer amplifier B 1 ⁇ B 6; in the second data transmission cycle, corresponding to In the second cycle of the switch control signal SC, the second group of switches SW 7 to SW 12 are turned on, and the switches of the other groups are turned off, and the six data input channels C 1 - C 6 are received from the timing controller 20 at this time.
  • the timing controller 20 controls the N analog buffer amplifiers B 1 to B N to N correspondingly.
  • the sub-pixels P 1 -P N provide data signals.
  • the number of devices required for each sub-function module is small, which reduces the cost.
  • the existing source driver module referring to FIG. 1, should include 960 bidirectional shift registers S/R 1 ⁇ S/R N , 960 data registers L 1 to L N , 960 potential shifters L/S 1 to L/S N , 960 digital-to-analog converters DAC 1 to DAC N and 960 analog buffer amplifiers B 1 to B N .
  • the source driving module provided in the above embodiment referring to FIG.
  • the source driving module provided in the above embodiment eliminates the bidirectional shift register and the data register, and the number of the potential shifter and the digital-to-analog converter is greatly reduced, although more switches are added.
  • the frequency divider on the whole, the number of components required for each sub-function module has been greatly reduced, which not only reduces the cost, but also makes the structure of the source driver module simpler and reduces the design difficulty.

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Abstract

提供了一种源极驱动模块（30），用于从时序控制器（20）中接收数据信号并提供给液晶面板（10）中的各个子像素，该源极驱动模块（30）包括：n个数据输入通道，从所述时序控制器（20）中接收n组数据信号；n个电位转移器，分别连接于所述n个数据输入通道；n个数模转换器，分别连接于所述n个电位转移器；分为N/n组的N个开关，每一组开关分别连接于所述n个数模转换器；以及分为N/n组的N个模拟缓冲放大器，一一对应地连接于所述N/n组开关；还包括一分频器（31），将从时序控制器（20）输出的时钟信号转换为一开关控制信号，用于依次开启所述N/n组开关的其中一组。还提供了一种包括该源极驱动模块（30）的液晶面板（10）。

Description

源极驱动模块以及液晶面板 技术领域
本发明涉及液晶显示器技术领域,尤其涉及一种源极驱动模块以及包含该驱动模块的液晶面板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)，为平面超薄的显示设备，它由一定数量的彩色或黑白像素组成，放置于光源或者反射面前方。液晶显示器功耗很低，并且具有高画质、体积小、重量轻的特点，因此倍受大家青睐，成为显示器的主流。目前液晶显示器是以薄膜晶体管(Thin Film Transistor，TFT)液晶显示器为主，液晶面板是液晶显示器的主要组件，液晶面板一般包括相对设置的彩膜基板和TFT阵列基板以及夹在两基板之间的液晶层。
液晶面板的驱动是由栅极驱动模块和源极驱动模块分别向各个像素提供扫描信号和数据信号的，不同的数据信号电压与共电极电压之间的压差造成液晶体旋转角度不同从而形成亮度的差异，即液晶面板的显示形成不同的灰阶。如图1所示的现有的一种源极驱动模块，按照数据信号的走向，该源极驱动模块依次包括双向移位寄存器(Bi-directional shift register，S/R)、数据暂存器(Latch，L)、电位转移器(Level shifter，L/S)、数模转换器(D/A Converter，DAC)以及模拟缓冲放大器(Buffer，B)。从时序控制器(Timing Control，TCOM)输出的数字信号，在双向移位寄存器S/R控制输入到数据暂存器L中，由电位转移器L/S提升数字信号的电压，再由数模转换器DAC转换为模拟信号输入到模拟缓冲放大器B，由模拟缓冲放大器B输出的信号提供给各个像素。如图1所示的，若液晶面板的每一行像素包括N个像素，则需要源极驱动模块输出N个信号分别提供给该N个像素，此时，源极驱动模块中对应包含有N个双向移位寄存器S/R1～S/RN、N个数据暂存器L1～LN、N个电位转移器L/S1～L/SN、N个数模转换器DAC1～DACN以及N个模拟缓冲放大器B1～BN。每一个信号输出通道包括一个双向移位寄存器S/R、一个数据暂存器L、一个电位转移器L/S、一个数模转换器DAC以及一个模拟缓冲放大器B。通过来说，液晶面板的每一行像素都包括很多个像素，即，N 的数值通常都很大，因此，如上结构的源极驱动模块中，各个子功能模块需要的器件数量很多，成本高。
发明内容
鉴于现有技术存在的不足，本发明提供了一种源极驱动模块，该源极驱动模块中，各个子功能模块所需要的器件数量较少，降低了成本。
为了实现上述目的，本发明采用了如下的技术方案：
一种源极驱动模块，用于从时序控制器中接收数据信号并提供给液晶面板中的各个子像素，所述液晶面板中每一行子像素包括N个子像素，其中，该源极驱动模块包括：n个数据输入通道，从所述时序控制器中接收n组数据信号；n个电位转移器，分别连接于所述n个数据输入通道；n个数模转换器，分别连接于所述n个电位转移器；N个开关，依次分为
Figure PCTCN2015084377-appb-000001
组，每一组开关分别连接于所述n个数模转换器；N个模拟缓冲放大器，依次分为
Figure PCTCN2015084377-appb-000002
组，一一对应地连接于所述
Figure PCTCN2015084377-appb-000003
组开关；一分频器，将从时序控制器输出的时钟信号转换为一开关控制信号，用于依次开启所述
Figure PCTCN2015084377-appb-000004
组开关的其中一组；在第m个数据传输周期内，所述n个数据输入通道从时序控制器中接收n个像素的数据信号，所述开关控制信号控制第m组开关开启，将该n个像素的数据信号输入到第m组模拟缓冲放大器中；其中，
Figure PCTCN2015084377-appb-000005
当N个模拟缓冲放大器均接收有数据信号后，由时序控制器控制所述N个模拟缓冲放大器向所述N个子像素提供数据信号；其中，N为大于1的整数，n为偶数，且N＞＞n，
Figure PCTCN2015084377-appb-000006
为大于1的整数。
其中，2≤n≤10。
其中，n的取值为6。
其中，所述数据传输周期包括多个时钟信号周期，在一个数据传输周期内，每一个数据输入通道分别从时序控制器中接收完成一个像素的数据信号；其中，所述开关控制信号的周期与所述数据传输周期相等。
其中，在一个数据传输周期内，每一个数据输入通道接收的的数据信号为一个8bit的数字信号。
其中，所述数据传输周期包括4个时钟信号周期。
本发明还提供了一种液晶面板，其包括液晶显示单元、时序控制器、源极驱动模块以及栅极驱动模块；所述液晶显示单元包括多个子像素，每一行子像素包括N个子像素，所述时序控制器控制所述源极驱动模块向所述子像素提供数据信号，所述时序控制器控制所述栅极驱动模块向所述子像素提供扫描信号，其中，所述源极驱动模块为如上所述的源极驱动模块。
相比于现有技术，本发明实施例提供的源极驱动模块中，各个子功能模块所需要的器件数量较少，降低了成本。
附图说明
图1是现有的一种源极驱动模块的结构示意图。
图2是本发明实施例提供的液晶面板的结构示意图。
图3是本发明实施例提供的源极驱动模块的结构示意图。
图4是本发明实施例中开关控制信号与时钟信号的时序关系图。
具体实施方式
下面将结合附图以及具体实施例，对本发明实施例中的技术方案进行详细地描述，显然，所描述的实施例仅仅是本发明一部分实例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护范围。
如图2所示，本实施例提供的液晶面板100包括液晶显示单元10、时序控制器20、源极驱动模块30以及栅极驱动模块40。其中，所述液晶显示单元包括多个子像素P，每一行子像素包括N个子像素P1、P2、…、PN，所述时序控制器20控制所述源极驱动模块30向所述子像素P提供数据信号，所述时序控制器20控制所述栅极驱动模块40向所述子像素P提供扫描信号。
其中，本实施例提供了一种新型结构源极驱动模块30。参阅图3，该源极驱动模块30包括n个数据输入通道、n个电位转移器、n个数模转换器、N个开关(依次分为
Figure PCTCN2015084377-appb-000007
组)、N个模拟缓冲放大器(依次分为
Figure PCTCN2015084377-appb-000008
组)以及一个分频器。其中，N为大于1的整数，n为偶数，且N＞＞n，
Figure PCTCN2015084377-appb-000009
为大于1的整数。N的取值 取决于液晶显示单元10中每一行包括的子像素的数量，例如该数值为960或1024等，N的数值远大于n，n的取值优选的范围是2≤n≤10。
本实施例中以n＝6为例对本发明的技术方案做详细的说明。
如图3所示的，该源极驱动模块30包括6个数据输入通道C1～C6、6个电位转移器L/S1～L/S6、6个数模转换器DAC1～DAC6、N个开关SW1～SWN、N个模拟缓冲放大器B1～BN以及一个分频器31。
其中，6个数据输入通道C1～C6从时序控制器20中接收6组数据信号Data，该数据信号Data为数字信号。
其中，6个电位转移器L/S1～L/S6分别连接于所述6个数据输入通道C1～C6，用于提升提升数字信号的电压。
其中6个数模转换器DAC1～DAC6分别连接于所述6个电位转移器L/S1～L/S6，用于将数字信号转换为模拟信号。
其中，N个开关SW1～SWN，依次分为
Figure PCTCN2015084377-appb-000010
组，每一组包括6个开关分别连接于所述6个数模转换器DAC1～DAC6。具体地，第一组开关包括6个开关SW1～SW6，该6个开关SW1～SW6一一对应地连接于6个数模转换器DAC1～DAC6；第二组开关包括6个开关SW7～SW12，该6个开关SW7～SW12也是一一对应地连接于6个数模转换器DAC1～DAC6；依次类推，第
Figure PCTCN2015084377-appb-000011
组开关包括6个开关SWN-5～SWN，该6个开关SWN-5～SWN也是一一对应地连接于6个数模转换器DAC1～DAC6。
其中，N个模拟缓冲放大器B1～BN一一对应地连接于N个开关SW1～SWN。也可以这样认为，将N个模拟缓冲放大器B1～BN依次分为
Figure PCTCN2015084377-appb-000012
组，第一组模拟缓冲放大器B1～B6一一对应地连接于第一组开关SW1～SW6，第二组模拟缓冲放大器B7～B12一一对应地连接于第二组开关SW7～SW12；依次类推，第
Figure PCTCN2015084377-appb-000013
组模拟缓冲放大器BN-5～BN一一对应地连接于第
Figure PCTCN2015084377-appb-000014
组开关SWN-5～SWN。
其中，所述分频器31将从时序控制器10输出的时钟信号CLK转换为一开关控制信号SC，用于依次开启所述
Figure PCTCN2015084377-appb-000015
组开关的其中一组。开关控制信号SC的 一个周期包含多个时钟信号CLK的周期，开关控制信号SC的周期应当与数据传输周期相等。其中，数据传输周期是指6个数据输入通道C1～C6从时序控制器20中接收到一个像素的数据信号的周期。例如，本实施例中，从时序控制器20中输出的一个像素的数据信号为一个8bit的数字信号，而6个数据输入通道C1～C6分别接收一个8bit的数字信号需要4个周期的时钟信号CLK，此时数据传输周期就为4个周期的时钟信号CLK。而开关控制信号SC的周期与数据传输周期相等，因此，如图4所示的，开关控制信号SC的周期包括时钟信号CLK的4个周期。
如上提供的源极驱动模块30传输数据信号的过程具体为：在第m个数据传输周期内，所述6个数据输入通道C1～C6从时序控制器20中接收6个像素的数据信号，所述开关控制信号SC控制第m组开关开启(此时其他组开关关闭)，将该6个像素的数据信号输入到第m组模拟缓冲放大器中；其中，
Figure PCTCN2015084377-appb-000016
Figure PCTCN2015084377-appb-000017
当N个模拟缓冲放大器B1～BN均接收有数据信号后(即接收完成一整行子像素P1～PN的数据信号)，由时序控制器20向N个模拟缓冲放大器B1～BN输入TP(锁存脉冲信号)信号，控制所述N个模拟缓冲放大器B1～BN对应地向N个子像素P1～PN提供数据信号。
具体地，在第1个数据传输周期内，对应于开关控制信号SC的第1个周期，第一组开关SW1～SW6开启，其余组的开关均关闭，此时6个数据输入通道C1～C6从时序控制器20中接收的6个数据信号通过第一组开关SW1～SW6输入到第一组模拟缓冲放大器B1～B6；在第2个数据传输周期内，对应于开关控制信号SC的第2个周期，第二组开关SW7～SW12开启，其余组的开关均关闭，此时6个数据输入通道C1～C6从时序控制器20中接收的6个数据信号通过第二组开关SW7～SW12输入到第二组模拟缓冲放大器B7～B12；依次类推，在第
Figure PCTCN2015084377-appb-000018
个数据传输周期内，对应于开关控制信号SC的第
Figure PCTCN2015084377-appb-000019
个周期，第
Figure PCTCN2015084377-appb-000020
组开关SWN-5～SWN开启，其余组的开关均关闭，此时6个数据输入通道C1～C6从时序控制器20中接收的6个数据信号通过第
Figure PCTCN2015084377-appb-000021
组开关SWN-5～SWN输入到第
Figure PCTCN2015084377-appb-000022
组模拟缓冲放大器BN-5～BN。在N个模拟缓冲放大器B1～BN接收完成一整行子像素P1～PN的数据信号后，由时序控制器20控制所述N个模拟缓冲放大器B1～BN对应地向N个子像素P1～PN提供数据信号。
如上实施例提供的源极驱动模块中，各个子功能模块所需要的器件数量较少，降低了成本。例如，若每一行子像素包括960个子像素(即N的取值为960)，则现有的源极驱动模块中，参阅附图1，其应当包括960个双向移位寄存器S/R1～S/RN、960个数据暂存器L1～LN、960个电位转移器L/S1～L/SN、960个数模转换器DAC1～DACN以及960个模拟缓冲放大器B1～BN。而如上实施例提供的源极驱动模块中，参阅图2，其包含6个电位转移器L/S1～L/S6、6个数模转换器DAC1～DAC6、960个开关SW1～SWN、960个模拟缓冲放大器B1～BN以及一个分频器31。相比较而言，如上实施例提供的源极驱动模块中省去了双向移位寄存器、数据暂存器，而电位转移器和数模转换器数量也大大减少，虽然有增加了较多的开关以及一个分频器，但是从整体上来说，已经极大地减少了各个子功能模块所需要的器件数量，不仅降低了成本，还使得源极驱动模块的结构更为简单，降低了设计难度。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (12)

  1. 一种源极驱动模块，用于从时序控制器中接收数据信号并提供给液晶面板中的各个子像素，所述液晶面板中每一行子像素包括N个子像素，其中，该源极驱动模块包括：
    n个数据输入通道，从所述时序控制器中接收n组数据信号；
    n个电位转移器，分别连接于所述n个数据输入通道；
    n个数模转换器，分别连接于所述n个电位转移器；
    N个开关，依次分为
    Figure PCTCN2015084377-appb-100001
    组，每一组开关分别连接于所述n个数模转换器；
    N个模拟缓冲放大器，依次分为
    Figure PCTCN2015084377-appb-100002
    组，一一对应地连接于所述
    Figure PCTCN2015084377-appb-100003
    组开关；
    一分频器，将从时序控制器输出的时钟信号转换为一开关控制信号，用于依次开启所述
    Figure PCTCN2015084377-appb-100004
    组开关的其中一组；
    在第m个数据传输周期内，所述n个数据输入通道从时序控制器中接收n个像素的数据信号，所述开关控制信号控制第m组开关开启，将该n个像素的数据信号输入到第m组模拟缓冲放大器中；其中，
    Figure PCTCN2015084377-appb-100005
    当N个模拟缓冲放大器均接收有数据信号后，由时序控制器控制所述N个模拟缓冲放大器向所述N个子像素提供数据信号；
    其中，N为大于1的整数，n为偶数，且N＞＞n，
    Figure PCTCN2015084377-appb-100006
    为大于1的整数。
  2. 根据权利要求1所述的源极驱动模块，其中，2≤n≤10。
  3. 根据权利要求1所述的源极驱动模块，其中，n的取值为6。
  4. 根据权利要求1所述的源极驱动模块，其中，所述数据传输周期包括多个时钟信号周期，在一个数据传输周期内，每一个数据输入通道分别从时序控制器中接收完成一个像素的数据信号；其中，所述开关控制信号的周期与所述数据传输周期相等。
  5. 根据权利要求4所述的源极驱动模块，其中，在一个数据传输周期内，每一个数据输入通道接收的的数据信号为一个8bit的数字信号。
  6. 根据权利要求5所述的源极驱动模块，其中，所述数据传输周期包括4个时钟信号周期。
  7. 一种液晶面板，包括液晶显示单元、时序控制器、源极驱动模块以及栅极驱动模块；所述液晶显示单元包括多个子像素，每一行子像素包括N个子像素，所述时序控制器控制所述源极驱动模块向所述子像素提供数据信号，所述时序控制器控制所述栅极驱动模块向所述子像素提供扫描信号，其中，所述源极驱动模块包括：
    n个数据输入通道，从所述时序控制器中接收n组数据信号；
    n个电位转移器，分别连接于所述n个数据输入通道；
    n个数模转换器，分别连接于所述n个电位转移器；
    N个开关，依次分为
    Figure PCTCN2015084377-appb-100007
    组，每一组开关分别连接于所述n个数模转换器；
    N个模拟缓冲放大器，依次分为
    Figure PCTCN2015084377-appb-100008
    组，一一对应地连接于所述
    Figure PCTCN2015084377-appb-100009
    组开关；
    一分频器，将从时序控制器输出的时钟信号转换为一开关控制信号，用于依次开启所述
    Figure PCTCN2015084377-appb-100010
    组开关的其中一组；
    在第m个数据传输周期内，所述n个数据输入通道从时序控制器中接收n个像素的数据信号，所述开关控制信号控制第m组开关开启，将该n个像素的数据信号输入到第m组模拟缓冲放大器中；其中，
    Figure PCTCN2015084377-appb-100011
    当N个模拟缓冲放大器均接收有数据信号后，由时序控制器控制所述N个模拟缓冲放大器向所述N个子像素提供数据信号；
    其中，N为大于1的整数，n为偶数，且N＞＞n，
    Figure PCTCN2015084377-appb-100012
    为大于1的整数。
  8. 根据权利要求7所述的液晶面板，其中，2≤n≤10。
  9. 根据权利要求7所述的液晶面板，其中，n的取值为6。
  10. 根据权利要求7所述的液晶面板，其中，所述数据传输周期包括多个时钟信号周期，在一个数据传输周期内，每一个数据输入通道分别从时序控制器中接收完成一个像素的数据信号；其中，所述开关控制信号的周期与所述数据传输周期相等。
  11. 根据权利要求10所述的液晶面板，其中，在一个数据传输周期内，每一个数据输入通道接收的的数据信号为一个8bit的数字信号。
  12. 根据权利要求11所述的液晶面板，其中，所述数据传输周期包括4个时钟信号周期。
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