WO2017002677A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2017002677A1
WO2017002677A1 PCT/JP2016/068493 JP2016068493W WO2017002677A1 WO 2017002677 A1 WO2017002677 A1 WO 2017002677A1 JP 2016068493 W JP2016068493 W JP 2016068493W WO 2017002677 A1 WO2017002677 A1 WO 2017002677A1
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WO
WIPO (PCT)
Prior art keywords
storage unit
memory
display
correction data
unevenness correction
Prior art date
Application number
PCT/JP2016/068493
Other languages
French (fr)
Japanese (ja)
Inventor
佐々木　崇
Original Assignee
シャープ株式会社
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Publication date
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Publication of WO2017002677A1 publication Critical patent/WO2017002677A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to a display device such as a liquid crystal display device.
  • a liquid crystal panel of a general liquid crystal display device includes an array substrate on which TFTs, pixel electrodes, and the like are formed and a counter substrate on which color filters are formed.
  • the interval may vary. That is, in one liquid crystal panel, the interval between the array substrate and the counter substrate may be different between a certain position and another position. In such a case, although a so-called “solid image” (an image in which the entire screen has the same color) is being displayed, an image having a different color or luminance depending on the position is displayed (that is, display unevenness occurs). .
  • the display unevenness caused by manufacturing as described above differs in the location and degree of occurrence for each device. Therefore, even if the input video signal is corrected in common to all apparatuses, the display unevenness is not eliminated. Therefore, the occurrence of display unevenness is suppressed by correcting the input video signal using the correction data so as to hold the correction data unique to each device.
  • the correction data used to eliminate the display unevenness as described above is referred to as “display unevenness correction data” for convenience.
  • display unevenness correction data is generally stored in a memory provided on a control board on which a timing controller called TCON is mounted.
  • TCON timing controller
  • the timing controller reads the display unevenness correction data from the memory, and corrects the input video signal using the display unevenness correction data.
  • display signal By driving the liquid crystal panel based on the corrected signal (hereinafter referred to as “display signal”), an image without display unevenness is displayed.
  • the control board may be replaced when a failure occurs in the liquid crystal display device. Since the replacement control board has a common specification for each model, display unevenness correction data, which is correction data unique to each apparatus, is not stored in the memory on the replacement control board. For this reason, when replacing the control board, the display unevenness correction data stored in the memory on the control board before replacement is transferred to the memory on the control board after replacement or on the control board before replacement. It is necessary to attach the memory to the control board after replacement. Therefore, the burden on the operator who replaces the control board is increased.
  • a memory 210 storing display unevenness correction data is used as a source substrate (a substrate on which a source driver IC that is an integrated circuit for driving a video signal line is mounted, strictly speaking, A structure provided on a substrate 20 directly connected to a source driver IC which is an integrated circuit for driving video signal lines is disclosed (see FIG. 13).
  • the memory 210 storing the display unevenness correction data is not removed from the apparatus. This eliminates the need to store display unevenness correction data in the memory of the control board 10 after replacement, thereby reducing the burden on the replacement operator.
  • the memory on the source substrate 20 in FIG. 13 is assigned the same reference numeral as the second memory in each embodiment of the present invention.
  • Japanese Unexamined Patent Publication No. 2011-209513 discloses a technique for suppressing the occurrence of display unevenness in a liquid crystal display device.
  • Japanese Unexamined Patent Application Publication No. 2010-134169 discloses a technique for suppressing the occurrence of luminance unevenness in an organic EL display device.
  • the memory 210 storing display unevenness correction data is provided on the source substrate 20 as in the liquid crystal display device 9 (see FIG. 13) disclosed in the pamphlet of International Publication No. 2010/146929
  • the display by the timing controller 140 is performed.
  • a read error may occur.
  • the reason why the read error occurs is that an error occurs in data transmission due to the influence of wiring delay and noise caused by the length of the wiring distance between the memory 210 on the source board 20 and the timing controller 140 on the control board 10. It is.
  • Such a data transmission error is likely to occur particularly when high-speed communication is performed. Therefore, it is conceivable to perform communication at a low speed.
  • an object of the present invention is to realize a display device that can promptly display an image in which correction by display unevenness correction data is reflected after startup (after power-on) without causing display unevenness correction data transmission error or the like.
  • a first aspect of the present invention is a display device comprising a display panel, a drive circuit that drives the display panel, and a timing controller that supplies a display control signal including a display signal to the drive circuit,
  • a first storage unit and a second storage unit which are two storage units for holding unique data set for each individual display panel;
  • the first storage unit is provided on a control board on which the timing controller is mounted,
  • the second storage unit is provided on a substrate other than the control substrate,
  • the timing controller is Generating the display signal by correcting the input video signal based on the unique data read from the first storage unit; If the unique data held in the first storage unit does not match the unique data held in the second storage unit, the unique data held in the second storage unit
  • the first storage unit is updated.
  • the second storage unit is provided on a substrate on which the driving circuit is mounted.
  • the display panel includes a plurality of video signal lines for transmitting a video signal corresponding to the display signal
  • the second storage unit is provided on a substrate on which a video signal line driving circuit for driving the plurality of video signal lines is mounted.
  • the transmission of unique data between the timing controller and the first storage unit and the transmission of unique data between the timing controller and the second storage unit are performed using the same bus line. It is characterized by.
  • the control board includes a first bus line used for transmission of unique data between the timing controller and the first storage unit, and between the timing controller and the second storage unit. And a second bus line used for transmission of the unique data.
  • a sixth aspect of the present invention is the fifth aspect of the present invention,
  • the first bus line transmits the unique data at a higher speed than the second bus line.
  • a seventh aspect of the present invention is the sixth aspect of the present invention.
  • An SPI is adopted as an interface related to transmission of specific data using the first bus line
  • I2C is adopted as an interface related to transmission of specific data using the second bus line.
  • an error detection code of unique data is held in the first storage unit and the second storage unit.
  • the timing controller is held in the first storage unit by comparing the error detection code held in the first storage unit with the error detection code held in the second storage unit. It is determined whether or not the unique data stored in the second storage unit matches the unique data.
  • identification information for identifying individual display panels is held
  • the timing controller is held in the first storage unit by comparing the identification information held in the first storage unit with the identification information held in the second storage unit. It is characterized in that it is determined whether or not the unique data matches the unique data held in the second storage unit.
  • the timing controller compares the specific data held in each of the first storage unit and the second storage unit with a part of the unique data held in the first storage unit. It is determined whether or not the unique data held in the second storage unit matches.
  • the timing controller updates the first storage unit if the unique data held in the first storage unit and the unique data held in the second storage unit do not match.
  • a display signal is supplied to the driving circuit so that a specific image is displayed on the display panel during a period of time.
  • the unique data is data for suppressing the occurrence of display unevenness on the display panel.
  • two storage units are display devices as components for holding unique data set for each display panel.
  • the first storage unit is provided on a control board on which a timing controller having a function of correcting an input video signal based on unique data is mounted
  • the second storage unit is provided on a board other than the control board. It is done.
  • the unique data held in the first storage unit does not match the unique data held in the second storage unit
  • the unique data held in the second storage unit The first storage unit is updated using the data. For this reason, when exchanging the control board, it is not necessary for the exchange operator to store the unique data in the first storage unit of the control board after the exchange.
  • the timing controller performs a process of correcting the input video signal using the unique data read from the first storage unit, so that the unique data can be read from the second storage unit at a high speed. There is no need to employ communication. For this reason, it is possible to reliably read the unique data from the second storage unit without causing a transmission error. Further, since the unique data is read from the first storage unit in a short time, the correction process using the unique data is promptly performed after the display device is activated. As described above, a display device capable of displaying an image in which correction by the unique data is reflected promptly after activation without causing a transmission error of the unique data or the like is realized.
  • the second storage unit is provided on the substrate on which the drive circuit is mounted (strictly, the substrate directly connected to the drive circuit).
  • a substrate on which a drive circuit is mounted is often crimped to a display panel via a source driver IC (an integrated circuit for driving video signal lines).
  • source driver IC an integrated circuit for driving video signal lines.
  • the reading of the unique data from the first storage unit and the reading of the unique data from the second storage unit can be performed in parallel. For this reason, the period from the start of the apparatus to the completion of reading of the unique data from the second storage unit is shortened. Therefore, when the control board is replaced, the period from the start of the apparatus to the completion of rewriting (updating) of data in the first storage unit is shortened. As a result, when the control board is replaced, an image reflecting the correction based on the unique data is promptly displayed.
  • the sixth aspect of the present invention by performing data transmission (transmission of unique data between the timing controller and the second storage unit) using the second bus line at a low speed, It is possible to more reliably suppress the occurrence of transmission errors.
  • I2C is adopted as an interface related to transmission of specific data between the timing controller and the second storage unit. Since the number of signal lines required for data transmission is small in I2C, the cost of the control board and the overall cost are reduced. In addition, the difficulty in designing the substrate is reduced due to a decrease in the number of signal lines.
  • the process for determining whether or not the unique data held in the first storage unit matches the unique data held in the second storage unit Since this is a simple process, the time required for data comparison is reduced. Further, since the amount of data to be compared is reduced, the data processing load at the time of starting the display device is reduced, and an effect of reducing power consumption and EMI is expected.
  • the eleventh aspect of the present invention when the control board is replaced, a specific image is displayed on the display panel after the apparatus is started. For this reason, the operator who replaces the control board can easily visually confirm that the data update process in the first storage unit is normally performed and that the process has been completed.
  • a display device capable of displaying an image without display unevenness immediately after startup without causing a transmission error of unique data or the like is realized.
  • 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a block diagram which shows the function structure of the liquid crystal display device which concerns on the said 1st Embodiment.
  • 6 is a flowchart for explaining a flow of processing after activation of the liquid crystal display device in the first embodiment. It is a figure for demonstrating the processing time of various processes in the said 1st Embodiment.
  • 10 is a flowchart for explaining a flow of processing after activation of the liquid crystal display device in a modification of the first embodiment. In the modification of the said 1st Embodiment, it is a figure for demonstrating the display of the image of a special pattern.
  • FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device 1 according to the first embodiment of the present invention.
  • the liquid crystal display device 1 includes a control substrate 10 on which a timing controller 140 is mounted, a source substrate 20 on which a source driver IC 230 is mounted (strictly speaking, a source substrate 20 directly connected to the source driver IC 230), a liquid crystal panel (Display panel) 40.
  • a source driver IC 230 mounted on the source substrate 20 is connected to the liquid crystal panel 40.
  • the control board 10 and the source board 20 are connected via the connector 120 of the control board 10 and the connector 220 of the source board 20.
  • the connector 120 of the control board 10 and the connector 220 of the source board 20 are connected by an FFC (flexible flat cable) 30.
  • the connector 130 of the control board 10 is connected to a signal line for transmitting various signals (input video signal DIN and timing signal group TG, which will be described later) supplied from the outside.
  • the liquid crystal display device 1 includes two memories (a first memory 110 and a first memory 110) as components for holding display unevenness correction data that is unique data set for each liquid crystal panel 40.
  • Two memories 210) are provided.
  • the first memory 110 is provided on the control board 10
  • the second memory 210 is provided on one of the source boards 20.
  • the first memory 110 and the second memory 210 are nonvolatile rewritable memories (for example, flash memory, EEPROM, etc.).
  • the first memory 110 also stores common data that is data commonly used for each model.
  • Common data includes gamma correction data, a QS drive table, a lookup table for various processes, a timing setting register value for liquid crystal drive, and the like.
  • a first storage unit is realized by the first memory 110
  • a second storage unit is realized by the second memory 210.
  • reference numeral 150 denotes a bus line used for transmission of display unevenness correction data in the control board 10
  • reference numeral 190 denotes a bus line used for transmission of a display signal in the control board 10.
  • reference numeral 250 is assigned to a bus line used for transmission of display unevenness correction data
  • reference numeral 290 is assigned to a bus line used for transmission of display signals on the source substrate 20.
  • a bus line used for transmission of display unevenness correction data is referred to as a “display unevenness correction data bus line”
  • a bus line used for display signal transmission is referred to as a “display signal bus line”.
  • the display unevenness correction data bus line 150 is connected to the first memory 110, the connector 120, and the timing controller 140, and the display signal bus line 190 is connected to the connector 120 and the timing controller 140.
  • the display unevenness correction data bus line 250 is connected to the second memory 210 and the connector 220, and the display signal bus line 290 is connected to the connector 220 and the source driver IC 230. And connected to.
  • the transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and the transmission of display unevenness correction data between the timing controller 140 and the second memory 210 are the same.
  • the display unevenness correction data bus line is used.
  • the timing controller 140 reads the common data from the first memory 110, and both the first memory 110 and the second memory 210 are read.
  • the display unevenness correction data is read out from.
  • the data read from the first memory 110 immediately after the replacement of the control board 10 is not display unevenness correction data set for each liquid crystal panel 40.
  • the timing controller 140 compares the display unevenness correction data read from the first memory 110 with the display unevenness correction data read from the second memory 210, and if they do not match, the timing controller 140 reads from the second memory 210.
  • the first memory 110 is updated using the display unevenness correction data.
  • the timing controller 140 is provided with a function (hereinafter referred to as “display unevenness correction function”) for correcting the input video signal DIN using display unevenness correction data so that occurrence of display unevenness is suppressed.
  • the timing controller 140 corrects the input video signal DIN using the display unevenness correction data read out through the display unevenness correction data bus line 150, and the display signal obtained by the correction is displayed on the display signal bus lines 190 and 290.
  • the description will be made on the assumption that the display unevenness correction function is built in the timing controller 140, but an integrated circuit for realizing the display unevenness correction function is provided separately from the timing controller 140 on the control board 10. Also good.
  • FIG. 2 is a block diagram showing a functional configuration of the liquid crystal display device 1.
  • the liquid crystal display device 1 is functionally configured by a timing controller 140, a video signal line driving circuit 23, a scanning signal line driving circuit 402, and a display unit 400.
  • the video signal line drive circuit 23 includes a plurality of source driver ICs 230.
  • the scanning signal line driver circuit 402 is formed in the liquid crystal panel 40 including the display portion 400 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (for example, indium gallium zinc oxide), or the like.
  • the scanning signal line drive circuit 402 and the display unit 400 are formed on the same substrate (one of the two substrates constituting the liquid crystal panel 40).
  • the scanning signal line driver circuit 402 may be provided on a substrate different from the substrate constituting the liquid crystal panel 40.
  • the display unit 400 is provided with a plurality (m) of video signal lines SL1 to SLm and a plurality (n) of scanning signal lines GL1 to GLn.
  • a pixel forming portion 401 for forming pixels is provided corresponding to each intersection of the video signal lines SL1 to SLm and the scanning signal lines GL1 to GLn. That is, the display unit 400 includes a plurality (n ⁇ m) of pixel forming units 401.
  • the plurality of pixel forming portions 401 are arranged in a matrix to form a pixel matrix of n rows ⁇ m columns.
  • Each pixel formation portion 401 has a thin film transistor (TFT) which is a switching element having a gate terminal connected to the scanning signal line GL passing through the corresponding intersection and a source terminal connected to the video signal line SL passing through the intersection.
  • TFT thin film transistor
  • the liquid crystal capacitor 43 and the auxiliary capacitor 44 constitute a pixel capacitor 47. Note that only components corresponding to one pixel formation portion 401 are shown in the display portion 400 in FIG. In addition, the configuration of the pixel formation portion 401 is not limited to the configuration illustrated in FIG. 2, and for example, a configuration in which the auxiliary capacitor 44 and the auxiliary capacitor electrode 46 are not provided may be employed.
  • the timing controller 140 receives an input video signal DIN and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal, and controls a digital video signal DV as a display signal and an operation of the video signal line driving circuit 23.
  • a start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS, and a gate start pulse signal GSP and a gate clock signal GCK for controlling the operation of the scanning signal line driver circuit 402 are output.
  • the digital video signal DV (display signal) is generated by correcting the input video signal DIN using the display unevenness correction data.
  • the video signal line drive circuit 23 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the timing controller 140, and drives the video signal lines SL1 to SLm to drive video signals. Is applied. At this time, the video signal line driving circuit 23 sequentially holds the digital video signal DV indicating the voltage to be applied to the video signal lines SL1 to SLm at the timing when the pulse of the source clock signal SCK is generated. The held digital video signal DV is converted into an analog voltage at the timing when the pulse of the latch strobe signal LS is generated. The converted analog voltage is applied simultaneously to all the video signal lines SL1 to SLm as drive video signals.
  • the scanning signal line driving circuit 402 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the timing controller 140, the scanning signal line driving circuit 402 applies an active scanning signal to the scanning signal lines GL1 to GLn for one vertical scanning period. Repeat as.
  • the scanning signals are applied to the scanning signal lines GL1 to GLn, and the driving video signals are applied to the video signal lines SL1 to SLm.
  • An image is displayed on the display unit 400.
  • a drive circuit for driving the liquid crystal panel 40 is realized by the video signal line drive circuit 23 and the scanning signal line drive circuit 402.
  • the display control signal is realized by the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, the gate start pulse signal GSP, and the gate clock signal GCK.
  • the timing controller 140 After activation of the liquid crystal display device 1 (after power-on), first, the timing controller 140 reads data (common data and display unevenness correction data) from the first memory 110 (step S100). At that time, for example, the common data is read first, and then the display unevenness correction data is read. After the reading of data from the first memory 110 is completed, image display is performed while correction using the display unevenness correction data is performed (step S110). In parallel with this image display, the display unevenness correction data is read from the second memory 210 by the timing controller 140.
  • data common data and display unevenness correction data
  • the timing controller 140 compares the display unevenness correction data read from the first memory 110 with the display unevenness correction data read from the second memory 210. (Step S120). Here, it is assumed that all data is compared with respect to display unevenness correction data. Then, a determination is made as to whether or not they match (step S130). As a result, if the two match, the image display is continued as it is. In this case, when the image is displayed in step S110, an image in which the correction using the display unevenness correction data is reflected is displayed. On the other hand, if the two do not match, the process proceeds to step S140.
  • step S140 the timing controller 140 rewrites the data held in the first memory 110 using the display unevenness correction data read from the second memory 210. Thereafter, in order to execute the display unevenness correction function, the timing controller 140 reads the display unevenness correction data from the first memory 110 again (step S150). Then, image display is performed while correction using display unevenness correction data is performed (step S160). Thereby, even when the control board 10 is replaced, an image reflecting the correction using the display unevenness correction data is displayed. Note that an image reflecting correction using display unevenness correction data may be displayed after the power is turned on again.
  • the first method uses an error detection code. Specifically, the checksum of the display unevenness correction data held in the first memory 110 is written to a specific address of the first memory 110 and the display unevenness held in the second memory 210 is written. The checksum of the correction data is written in a specific address of the second memory 210.
  • step S120 the timing controller 140 compares the checksum held in the first memory 110 with the checksum held in the second memory 210. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
  • the second method is a method using identification information. Specifically, identification information unique to each liquid crystal panel (for example, panel ID, serial number, date of data creation, etc.) is written in advance in specific addresses of the first memory 110 and the second memory 210, respectively.
  • step S120 the timing controller 140 compares the identification information held in the first memory 110 with the identification information held in the second memory 210. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
  • the third method is a method of comparing a part of display unevenness correction data. For example, comparison is made only for data in a specific range, and comparison is made only for data at every other address. As described above, in step S120 (see FIG. 3), the timing controller 140 compares only some data with respect to the display unevenness correction data. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
  • the display unevenness correction data held in the first memory 110 and the display unevenness correction data held in the second memory 210 match. Since the process for determining whether or not is a simple process, the time required for data comparison is shortened. In addition, since the amount of data to be compared is reduced, the data processing load when the liquid crystal display device 1 is started up is reduced, and an effect of reducing power consumption and EMI is expected.
  • the timing controller 140 accesses the first memory 110 and the second memory 210 for data comparison for a certain period after the liquid crystal display device 1 is activated. For this reason, when a configuration is adopted in which data is read from the first memory 110 for data processing other than execution of the display unevenness correction function after the apparatus is activated, the data processing to the first memory 110 is performed. There may be a restriction that access for the mobile phone cannot be performed during the predetermined period. In this regard, according to the first to third methods, the amount of data to be compared is reduced, so that the possibility of the above-described restrictions being reduced.
  • access for reading parameters for QS driving when the surface temperature of the liquid crystal panel 40 changes.
  • an access for reading out a parameter for gamma correction and a parameter for QS driving when a display mode is changed for example, a change between 2D mode and 3D mode.
  • FIG. 4 is a diagram for explaining processing times of various processes.
  • symbol L1 represents the length of time required to read common data from the memory on the control board 10
  • symbol L2 represents the length of time required to read display unevenness correction data from the memory on the source board 20
  • symbol L3 represents the length of time required to read display unevenness correction data from the memory on the control board 10 (the same applies to FIGS. 8 and 10).
  • the conventional technique here is a technique disclosed in the pamphlet of International Publication No. 2010/146929 (configuration shown in FIG. 13). In the conventional technique, it is assumed that common data is read from a memory (not shown in FIG. 13) on the control board 10.
  • the wiring distance between the timing controller 140 and the memory on the source substrate 20 is relatively long, it is necessary to perform data transmission at a relatively low frequency in order not to cause a data transmission error in communication between the timing controller 140 and the memory on the source substrate 20. is there.
  • the wiring distance between the first memory 110 and the timing controller 140 is short, data transmission can be performed at a relatively high frequency between the two. Accordingly, the length of time L3 required for reading the display unevenness correction data from the memory on the control board 10 is shorter than the length L2 of the time required for reading the display unevenness correction data from the memory on the source board 20.
  • display unevenness correction data is read from the memory on the control board 10 (first memory 110), and then read from the memory on the source board 20 (second memory 210).
  • the display unevenness correction data is read out. That is, in the present embodiment, display unevenness correction data is read from the memory (first memory 110) on the control board 10 during a period from time t1 to time t2, and image display is started at time t2. .
  • display unevenness correction data is read from the memory (second memory 210) on the source substrate 20 during a period from time t2 to time t4.
  • the display unevenness correction data read from the memory on the control board 10 (first memory 110) and the display unevenness correction data read from the memory on the source board 20 (second memory 210) are compared after time t4. To be done.
  • the time required for reading the display unevenness correction data necessary for image display is shorter than that of the prior art.
  • the liquid crystal display device 1 includes two memories (a first memory 110 and a second memory) as components for holding display unevenness correction data that is unique data set for each liquid crystal panel 40.
  • Memory 210 the first memory 110 is provided on the control board 10 on which the timing controller 140 having a display unevenness correction function is mounted, and the second memory 210 is the source board 20 on which the source driver IC 230 is mounted (strictly speaking, It is provided on the source substrate 20) directly connected to the source driver IC 230.
  • the display unevenness correction data held in the first memory 110 and the display unevenness correction data held in the second memory 210 must match.
  • the first memory 110 is updated using the display unevenness correction data held in the second memory 210. For this reason, when the control board 10 is replaced, the replacement operator does not need to store the display unevenness correction data in the memory (first memory 110) of the control board 10 after the replacement.
  • the timing controller 140 performs a process of correcting the input video signal DIN using the display unevenness correction data read from the first memory 110, and thus the second memory 210. It is not necessary to employ high-speed communication for reading the display unevenness correction data from. For this reason, it is possible to reliably read the display unevenness correction data from the second memory 210 without causing a transmission error.
  • the display unevenness correction data is read from the first memory 110 in a short time, the display unevenness correction function is immediately executed after the liquid crystal display device 1 is started.
  • a liquid crystal display device capable of displaying an image (an image having no display unevenness) in which the correction based on the display unevenness correction data is reflected promptly after startup without causing a display unevenness correction data transmission error or the like. 1 is realized.
  • the source substrate 20 is often connected to the liquid crystal panel 40 via the source driver IC 230 by pressure bonding. For this reason, when the source substrate 20 is to be replaced, it is impossible to repair by a simple operation, and it is necessary to perform repair work using a dedicated crimping facility. The work of storing the display unevenness correction data in the second memory 210 is not a heavy burden for the replacement operator.
  • FIG. 5 is a flowchart for explaining the flow of processing after activation of the liquid crystal display device according to this modification.
  • the flow of processing up to step S230 is the same as the flow of processing up to step S130 in the first embodiment.
  • the image display is continued as in the first embodiment. If it is determined in step S230 that the two do not match, the process proceeds to step S240.
  • step S240 the display of the special pattern image described above is started.
  • the timing controller 140 rewrites the data held in the first memory 110 using the display unevenness correction data read from the second memory 210 (step S250).
  • the timing controller 140 reads the display unevenness correction data from the first memory 110 again in order to execute the display unevenness correction function (step S260).
  • the display of the special pattern image ends (step S270).
  • image display display of a normal image
  • step S280 an image reflecting correction using display unevenness correction data may be displayed after the power is turned on again.
  • a normal image reflecting the correction based on the display unevenness correction data is displayed immediately after the apparatus is started.
  • the special pattern image 62 is displayed immediately after the apparatus is started, and after the rewriting of the data in the first memory 110 is completed, the correction by the display unevenness correction data is performed.
  • the reflected normal image 61 is displayed.
  • Second Embodiment> A second embodiment of the present invention will be described. In the following, differences from the first embodiment will be mainly described, and description of the same points as the first embodiment will be omitted.
  • FIG. 7 is a block diagram showing the overall configuration of the liquid crystal display device 2 according to the second embodiment of the present invention.
  • transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and transmission of display unevenness correction data between the timing controller 140 and the second memory 210. is performed using the same display unevenness correction data bus line.
  • transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and display unevenness correction data between the timing controller 140 and the second memory 210 This transmission is performed using a display irregularity correction data bus line different from the transmission of. Specifically, as shown in FIG.
  • the control board 10 displays information between the timing controller 140 and the first memory 110 as a bus line for transmitting display unevenness correction data.
  • the display unevenness correction data bus line 151 and the display unevenness correction data bus line 152 perform data transmission using the same interface. It should be noted that here, regarding both the transmission of the display unevenness correction data using the display unevenness correction data bus line 151 and the transmission of the display unevenness correction data using the display unevenness correction data bus line 152, the interface includes an SPI (Serial). It is assumed that Peripheral Interface) is adopted.
  • SPI Serial
  • the timing controller 140 reads the display unevenness correction data from the first memory 110 and the display unevenness correction data from the second memory 210 in parallel. It is possible.
  • the first bus line is realized by the display unevenness correction data bus line 151
  • the second bus line is realized by the display unevenness correction data bus line 152.
  • FIG. 8 is a diagram for explaining processing times of various processes. Also in this embodiment, common data is read during a period from time t0 (starting time) to time t1. At time t1, reading of display unevenness correction data from the memory on the control board 10 (first memory 110) and reading of display unevenness correction data from the memory on the source board 20 (second memory 210) are performed. Done in parallel. Reading of display unevenness correction data from the memory (first memory 110) on the control board 10 ends at time t2. Then, image display is started at time t2. Note that the reading of display unevenness correction data from the memory (second memory 210) on the source substrate 20 ends at time t3.
  • reading of display unevenness correction data from the memory on the source substrate 20 is completed earlier in the present embodiment than in the first embodiment.
  • the display unevenness correction data read from the memory on the control board 10 (first memory 110) and the display unevenness correction data read from the memory on the source board 20 (second memory 210) are compared after time t3. To be done.
  • the period from the start of the apparatus to the completion of the reading of display unevenness correction data from the memory (second memory 210) on the source substrate 20 is shortened. For this reason, when the control board 10 is replaced, it is possible to shorten the period from the start of the apparatus to the completion of the rewriting of data in the first memory 110. Thereby, when the control board 10 is exchanged, an image without display unevenness is promptly displayed.
  • FIG. 9 is a block diagram showing an overall configuration of a liquid crystal display device 3 according to a modification of the second embodiment.
  • the control board 10 has a display unevenness correction data bus line 151 used for transmission of display unevenness correction data between the timing controller 140 and the first memory 110 as a bus line for transmitting display unevenness correction data.
  • a display unevenness correction data bus line 153 used for transmission of display unevenness correction data between the timing controller 140 and the second memory 210.
  • the first bus line is realized by the display unevenness correction data bus line 151
  • the second bus line is realized by the display unevenness correction data bus line 153.
  • the display unevenness correction data bus line 151 and the display unevenness correction data bus line 152 perform data transmission using the same interface.
  • data transmission is performed using different interfaces between the display unevenness correction data bus line 151 and the display unevenness correction data bus line 153.
  • an SPI is adopted as an interface related to transmission of display unevenness correction data using the display unevenness correction data bus line 151
  • an interface related to transmission of display unevenness correction data using the display unevenness correction data bus line 153 is adopted for the.
  • I2C Inter-Integrated Circuit
  • the combination of interfaces employed in the display unevenness correction data bus line 151 and the display unevenness correction data bus line 153 is not limited to this.
  • SPI is an interface used for communication at a relatively high speed
  • I2C is an interface used for communication at a relatively low speed.
  • data communication at 32 MHz is performed in SPI
  • data communication at 400 KHz is performed in I2C.
  • the display unevenness correction data bus line 151 transmit the display unevenness correction data at a higher speed than the display unevenness correction data bus line 153.
  • FIG. 10 is a diagram for explaining processing times of various processes.
  • the symbol L4 represents the length of time required to read display unevenness correction data from the memory (second memory 210) on the source substrate 20 in the configuration according to this modification.
  • common data is read during a period from time t0 (starting time) to time t1.
  • time t1 reading of display unevenness correction data from the memory on the control board 10 (first memory 110) and reading of display unevenness correction data from the memory on the source board 20 (second memory 210) are performed. Done in parallel. Reading of display unevenness correction data from the memory (first memory 110) on the control board 10 ends at time t2. Then, image display is started at time t2.
  • the display unevenness correction data is read from the memory (second memory 210) on the source substrate 20 after time t4.
  • the display unevenness correction data is read from the first memory 110 in a short time as in the first embodiment and the second embodiment.
  • a liquid crystal display device 3 that can display an image (an image with no display unevenness) reflecting the correction by the correction data is realized.
  • the cost of the control board 10 is reduced.
  • the number of signal lines required for connecting the control board 10 and the source board 20 is reduced, the overall cost can be reduced.
  • the difficulty in designing the substrate is reduced due to the decrease in the number of signal lines.
  • the display unevenness correction data is read from the second memory 210 at a low speed, the occurrence of a transmission error is more reliably suppressed.
  • the second memory 210 is provided on the source substrate 20.
  • the present invention is not limited to this.
  • the gate substrate 50 on which the gate driver IC 520 which is an integrated circuit for driving the scanning signal line GL is mounted (strictly speaking, the gate driver IC 520 which is an integrated circuit for driving the scanning signal line GL is directly connected to the gate substrate 50
  • the second memory 510 may be provided on the gate substrate 50 as shown in FIG.
  • the second memory 410 may be provided on a substrate constituting the liquid crystal panel 40.
  • the second memory may be provided on a power supply substrate, a backlight substrate, or the like.
  • the first memory 110 may be provided on the control board 10 and the second memory may be provided on a board other than the control board 10.
  • the case where the data held in the first memory 110 and the second memory 210 is display unevenness correction data has been described as an example. It is not limited to this. As long as the unique data is set for each individual device (each panel), the data held in the first memory 110 and the second memory 210 may be data other than display unevenness correction data.
  • liquid crystal display device has been described as an example.
  • the present invention is not limited to this, and the present invention can also be applied to display devices other than liquid crystal display devices (for example, organic EL display devices).

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Abstract

Provided is a display device capable of displaying an image corrected based on display unevenness correction data immediately after startup without generating propagation errors and the like in the display unevenness correction data. A first memory (110) is provided on a control substrate (10) on which a timing controller (140) is mounted and a second memory (210) is provide on a source substrate (20), the first memory and the second memory being components for maintaining the display unevenness correction data set for each liquid crystal panel (40). The timing controller (140) corrects an input video signal on the basis of the display unevenness correction data read out from the first memory (110). Further, the timing controller (140) updates the first memory (110) with the display unevenness correction data maintained in the second memory (210) if the display unevenness correction data maintained in the first memory (110) does not match with the display unevenness correction data maintained in the second memory (210).

Description

表示装置Display device
　本発明は、液晶表示装置などの表示装置に関する。 The present invention relates to a display device such as a liquid crystal display device.
　従来より、液晶表示装置などの表示装置においては、表示むらが生じることがある。表示むらは、例えば個々の装置の製造に起因して生じる。例えば、一般的な液晶表示装置の液晶パネルはＴＦＴや画素電極などが形成されたアレイ基板とカラーフィルタなどが形成された対向基板とによって構成されているところ、アレイ基板と対向基板との間の間隔にばらつきが生じることがある。すなわち、１つの液晶パネルにおいてアレイ基板と対向基板との間の間隔が或る位置と別の位置とで異なることがある。このような場合、いわゆる「べた画像」（画面全体が同じ色となる画像）を表示しようとしているにもかかわらず、位置によって色や輝度が異なる画像が表示される（すなわち、表示むらが生じる）。 Conventionally, display unevenness may occur in a display device such as a liquid crystal display device. Display irregularities occur, for example, due to the manufacture of individual devices. For example, a liquid crystal panel of a general liquid crystal display device includes an array substrate on which TFTs, pixel electrodes, and the like are formed and a counter substrate on which color filters are formed. The interval may vary. That is, in one liquid crystal panel, the interval between the array substrate and the counter substrate may be different between a certain position and another position. In such a case, although a so-called “solid image” (an image in which the entire screen has the same color) is being displayed, an image having a different color or luminance depending on the position is displayed (that is, display unevenness occurs). .
　上述のような製造に起因する表示むらについては、個々の装置毎に発生場所や程度が異なる。従って、入力映像信号に対して全ての装置に共通的な補正を施しても、表示むらは解消されない。そこで、装置毎に固有の補正データを保持するようにして当該補正データを用いて入力映像信号に補正を施すことによって、表示むらの発生が抑止されている。なお、以下においては、上述のような表示むらを解消するために用いられる補正データのことを便宜上「表示むら補正データ」という。 The display unevenness caused by manufacturing as described above differs in the location and degree of occurrence for each device. Therefore, even if the input video signal is corrected in common to all apparatuses, the display unevenness is not eliminated. Therefore, the occurrence of display unevenness is suppressed by correcting the input video signal using the correction data so as to hold the correction data unique to each device. In the following, the correction data used to eliminate the display unevenness as described above is referred to as “display unevenness correction data” for convenience.
　液晶表示装置においては、一般的に、表示むら補正データは、ＴＣＯＮと呼ばれるタイミングコントローラを搭載するコントロール基板に設けられたメモリに格納されている。そして、電源が投入されると、タイミングコントローラは、メモリから表示むら補正データを読み出し、当該表示むら補正データを用いて入力映像信号に補正を施す。その補正後の信号（以下、「表示信号」という。）に基づいて液晶パネルが駆動されることにより、表示むらのない画像が表示される。 In a liquid crystal display device, display unevenness correction data is generally stored in a memory provided on a control board on which a timing controller called TCON is mounted. When the power is turned on, the timing controller reads the display unevenness correction data from the memory, and corrects the input video signal using the display unevenness correction data. By driving the liquid crystal panel based on the corrected signal (hereinafter referred to as “display signal”), an image without display unevenness is displayed.
　ところで、液晶表示装置に故障が生じたときにコントロール基板の交換が行われることがある。交換用のコントロール基板は機種毎の共通仕様となっているため、交換用のコントロール基板上のメモリには、装置毎の固有の補正データである表示むら補正データは格納されていない。そのため、コントロール基板の交換の際には、交換前のコントロール基板上のメモリに格納されている表示むら補正データを交換後のコントロール基板上のメモリ内に移し替える作業もしくは交換前のコントロール基板上のメモリを交換後のコントロール基板に取り付ける作業が必要となる。それ故、コントロール基板の交換を行う作業者の負担が大きくなっている。 By the way, the control board may be replaced when a failure occurs in the liquid crystal display device. Since the replacement control board has a common specification for each model, display unevenness correction data, which is correction data unique to each apparatus, is not stored in the memory on the replacement control board. For this reason, when replacing the control board, the display unevenness correction data stored in the memory on the control board before replacement is transferred to the memory on the control board after replacement or on the control board before replacement. It is necessary to attach the memory to the control board after replacement. Therefore, the burden on the operator who replaces the control board is increased.
　そこで、国際公開２０１０／１４６９２９号パンフレットには、表示むら補正データを格納したメモリ２１０をソース基板（映像信号線を駆動するための集積回路であるソースドライバＩＣが搭載された基板、厳密には、映像信号線を駆動するための集積回路であるソースドライバＩＣに直接的に接続された基板）２０上に設けた構成が開示されている（図１３参照）。この構成によれば、コントロール基板１０の交換の際に、表示むら補正データを格納したメモリ２１０が装置から取り外されることはない。従って、交換後のコントロール基板１０のメモリに表示むら補正データを格納するという作業が不要となり、交換作業者の負担が軽減される。なお、図１３におけるソース基板２０上のメモリには、便宜上、本発明の各実施形態における第２のメモリと同じ符号を付している。 Accordingly, in the pamphlet of International Publication No. 2010/146929, a memory 210 storing display unevenness correction data is used as a source substrate (a substrate on which a source driver IC that is an integrated circuit for driving a video signal line is mounted, strictly speaking, A structure provided on a substrate 20 directly connected to a source driver IC which is an integrated circuit for driving video signal lines is disclosed (see FIG. 13). According to this configuration, when the control board 10 is replaced, the memory 210 storing the display unevenness correction data is not removed from the apparatus. This eliminates the need to store display unevenness correction data in the memory of the control board 10 after replacement, thereby reducing the burden on the replacement operator. For convenience, the memory on the source substrate 20 in FIG. 13 is assigned the same reference numeral as the second memory in each embodiment of the present invention.
　また、本件発明に関連して、以下の先行技術文献が知られている。日本の特開２０１１－２０９５１３号公報には、液晶表示装置における表示むらの発生を抑制する技術が開示されている。日本の特開２０１０－１３４１６９号公報には、有機ＥＬ表示装置における輝度むらの発生を抑制する技術が開示されている。 Also, the following prior art documents are known in relation to the present invention. Japanese Unexamined Patent Publication No. 2011-209513 discloses a technique for suppressing the occurrence of display unevenness in a liquid crystal display device. Japanese Unexamined Patent Application Publication No. 2010-134169 discloses a technique for suppressing the occurrence of luminance unevenness in an organic EL display device.
国際公開２０１０／１４６９２９号パンフレットInternational Publication 2010/146929 Pamphlet 日本の特開２０１１－２０９５１３号公報Japanese Unexamined Patent Publication No. 2011-209513 日本の特開２０１０－１３４１６９号公報Japanese Unexamined Patent Publication No. 2010-134169
　ところが、国際公開２０１０／１４６９２９号パンフレットに開示された液晶表示装置９（図１３参照）のように、表示むら補正データを格納したメモリ２１０をソース基板２０上に設けた場合、タイミングコントローラ１４０による表示むら補正データの読み出しが行われる際に、読み出しエラーが発生することがある。読み出しエラーが発生する理由は、ソース基板２０上のメモリ２１０とコントロール基板１０上のタイミングコントローラ１４０との間の配線距離の長さに起因する配線遅延やノイズの影響によってデータ伝送にエラーが生じるからである。なお、このようなデータ伝送エラーは、特に高速での通信が行われるときに生じやすい。そこで、低速での通信を行うことが考えられる。しかしながら、通信速度を低くすると、表示むら補正データの読み出しに要する時間が長くなるので、装置の起動時点（電源オン時点）から表示むら補正データによる補正が反映された画像が表示されるまでの時間が長くなる。 However, when the memory 210 storing display unevenness correction data is provided on the source substrate 20 as in the liquid crystal display device 9 (see FIG. 13) disclosed in the pamphlet of International Publication No. 2010/146929, the display by the timing controller 140 is performed. When the unevenness correction data is read, a read error may occur. The reason why the read error occurs is that an error occurs in data transmission due to the influence of wiring delay and noise caused by the length of the wiring distance between the memory 210 on the source board 20 and the timing controller 140 on the control board 10. It is. Such a data transmission error is likely to occur particularly when high-speed communication is performed. Therefore, it is conceivable to perform communication at a low speed. However, if the communication speed is lowered, the time required for reading the display unevenness correction data becomes longer. Therefore, the time from the start of the apparatus (at the time of power-on) until the display of the image reflecting the correction by the display unevenness correction data is displayed. Becomes longer.
　そこで、本発明は、表示むら補正データの伝送エラー等を生ずることなく起動後（電源オン後）に速やかに表示むら補正データによる補正が反映された画像を表示できる表示装置を実現することを目的とする。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize a display device that can promptly display an image in which correction by display unevenness correction data is reflected after startup (after power-on) without causing display unevenness correction data transmission error or the like. And
　本発明の第１の局面は、表示パネルと、前記表示パネルを駆動する駆動回路と、表示信号を含む表示制御信号を前記駆動回路に供給するタイミングコントローラとを備える表示装置であって、
　個々の表示パネル毎に設定される固有データを保持するための２つの記憶部である第１の記憶部および第２の記憶部を有し、
　前記第１の記憶部は、前記タイミングコントローラを搭載するコントロール基板に設けられ、
　前記第２の記憶部は、前記コントロール基板以外の基板に設けられ、
　前記タイミングコントローラは、
　　前記第１の記憶部から読み出した固有データに基づいて入力映像信号を補正することによって、前記表示信号を生成し、
　　前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致していなければ、前記第２の記憶部に保持されている固有データで前記第１の記憶部を更新することを特徴とする。 A first aspect of the present invention is a display device comprising a display panel, a drive circuit that drives the display panel, and a timing controller that supplies a display control signal including a display signal to the drive circuit,
A first storage unit and a second storage unit, which are two storage units for holding unique data set for each individual display panel;
The first storage unit is provided on a control board on which the timing controller is mounted,
The second storage unit is provided on a substrate other than the control substrate,
The timing controller is
Generating the display signal by correcting the input video signal based on the unique data read from the first storage unit;
If the unique data held in the first storage unit does not match the unique data held in the second storage unit, the unique data held in the second storage unit The first storage unit is updated.
　本発明の第２の局面は、本発明の第１の局面において、
　前記第２の記憶部は、前記駆動回路を搭載する基板に設けられていることを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The second storage unit is provided on a substrate on which the driving circuit is mounted.
　本発明の第３の局面は、本発明の第２の局面において、
　前記表示パネルは、前記表示信号に相当する映像信号を伝送するための複数の映像信号線を含み、
　前記第２の記憶部は、前記複数の映像信号線を駆動する映像信号線駆動回路を搭載する基板に設けられていることを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
The display panel includes a plurality of video signal lines for transmitting a video signal corresponding to the display signal,
The second storage unit is provided on a substrate on which a video signal line driving circuit for driving the plurality of video signal lines is mounted.
　本発明の第４の局面は、本発明の第１の局面において、
　前記タイミングコントローラと前記第１の記憶部との間での固有データの伝送と前記タイミングコントローラと前記第２の記憶部との間での固有データの伝送とは同じバスラインを用いて行われることを特徴とする。 According to a fourth aspect of the present invention, in the first aspect of the present invention,
The transmission of unique data between the timing controller and the first storage unit and the transmission of unique data between the timing controller and the second storage unit are performed using the same bus line. It is characterized by.
　本発明の第５の局面は、本発明の第１の局面において、
　前記コントロール基板には、前記タイミングコントローラと前記第１の記憶部との間での固有データの伝送に用いられる第１のバスラインと、前記タイミングコントローラと前記第２の記憶部との間での固有データの伝送に用いられる第２のバスラインとが設けられていることを特徴とする。 According to a fifth aspect of the present invention, in the first aspect of the present invention,
The control board includes a first bus line used for transmission of unique data between the timing controller and the first storage unit, and between the timing controller and the second storage unit. And a second bus line used for transmission of the unique data.
　本発明の第６の局面は、本発明の第５の局面において、
　前記第２のバスラインよりも前記第１のバスラインの方が、固有データの伝送が高速に行われることを特徴とする。 A sixth aspect of the present invention is the fifth aspect of the present invention,
The first bus line transmits the unique data at a higher speed than the second bus line.
　本発明の第７の局面は、本発明の第６の局面において、
　前記第１のバスラインを用いた固有データの伝送に関するインタフェースにはＳＰＩが採用され、
　前記第２のバスラインを用いた固有データの伝送に関するインタフェースにはＩ２Ｃが
採用されていることを特徴とする。 A seventh aspect of the present invention is the sixth aspect of the present invention,
An SPI is adopted as an interface related to transmission of specific data using the first bus line,
I2C is adopted as an interface related to transmission of specific data using the second bus line.
　本発明の第８の局面は、本発明の第１の局面において、
　前記第１の記憶部および前記第２の記憶部には、固有データの誤り検出符号が保持されており、
　前記タイミングコントローラは、前記第１の記憶部に保持されている誤り検出符号と前記第２の記憶部に保持されている誤り検出符号とを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
In the first storage unit and the second storage unit, an error detection code of unique data is held,
The timing controller is held in the first storage unit by comparing the error detection code held in the first storage unit with the error detection code held in the second storage unit. It is determined whether or not the unique data stored in the second storage unit matches the unique data.
　本発明の第９の局面は、本発明の第１の局面において、
　前記第１の記憶部および前記第２の記憶部には、個々の表示パネルを識別するための識別情報が保持されており、
　前記タイミングコントローラは、前記第１の記憶部に保持されている識別情報と前記第２の記憶部に保持されている識別情報とを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする。 According to a ninth aspect of the present invention, in the first aspect of the present invention,
In the first storage unit and the second storage unit, identification information for identifying individual display panels is held,
The timing controller is held in the first storage unit by comparing the identification information held in the first storage unit with the identification information held in the second storage unit. It is characterized in that it is determined whether or not the unique data matches the unique data held in the second storage unit.
　本発明の第１０の局面は、本発明の第１の局面において、
　前記タイミングコントローラは、前記第１の記憶部および前記第２の記憶部のそれぞれに保持されている一部の固有データを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする。 According to a tenth aspect of the present invention, in the first aspect of the present invention,
The timing controller compares the specific data held in each of the first storage unit and the second storage unit with a part of the unique data held in the first storage unit. It is determined whether or not the unique data held in the second storage unit matches.
　本発明の第１１の局面は、本発明の第１の局面において、
　前記タイミングコントローラは、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致していなければ、前記第１の記憶部の更新が行われている期間中、前記表示パネルに特定の画像が表示されるように表示信号を前記駆動回路に供給することを特徴とする。 According to an eleventh aspect of the present invention, in the first aspect of the present invention,
The timing controller updates the first storage unit if the unique data held in the first storage unit and the unique data held in the second storage unit do not match. A display signal is supplied to the driving circuit so that a specific image is displayed on the display panel during a period of time.
　本発明の第１２の局面は、本発明の第１の局面において、
　前記固有データは、前記表示パネルでの表示むらの発生を抑止するためのデータであることを特徴とする。 According to a twelfth aspect of the present invention, in the first aspect of the present invention,
The unique data is data for suppressing the occurrence of display unevenness on the display panel.
　本発明の第１の局面によれば、個々の表示パネル毎に設定される固有データを保持するための構成要素として２つの記憶部（第１の記憶部および第２の記憶部）が表示装置に設けられる。詳しくは、第１の記憶部は、固有データに基づいて入力映像信号を補正する機能を有するタイミングコントローラが搭載されたコントロール基板に設けられ、第２の記憶部は、コントロール基板以外の基板に設けられる。このような構成において、第１の記憶部に保持されている固有データと第２の記憶部に保持されている固有データとが一致していなければ、第２の記憶部に保持されている固有データを用いて第１の記憶部が更新される。このため、コントロール基板の交換の際、交換作業者にとって、交換後のコントロール基板の第１の記憶部に固有データを格納するという作業が不要となる。ここで、タイミングコントローラでは、第１の記憶部から読み出された固有データを用いて入力映像信号に補正を施す処理が行われるので、第２の記憶部からの固有データの読み出しに高速での通信を採用する必要がない。このため、第２の記憶部からの固有データの読み出しを伝送エラーを生ずることなく確実に行うことが可能となる。また、第１の記憶部からの固有データの読み出しは短時間で行われるので、表示装置の起動後には、固有データを用いた補正処理が速やかに行われる。以上より、固有データの伝送エラー等を生ずることなく起動後に速やかに固有データによる補正が反映された画像を表示できる表示装置が実現される。 According to the first aspect of the present invention, two storage units (a first storage unit and a second storage unit) are display devices as components for holding unique data set for each display panel. Provided. Specifically, the first storage unit is provided on a control board on which a timing controller having a function of correcting an input video signal based on unique data is mounted, and the second storage unit is provided on a board other than the control board. It is done. In such a configuration, if the unique data held in the first storage unit does not match the unique data held in the second storage unit, the unique data held in the second storage unit The first storage unit is updated using the data. For this reason, when exchanging the control board, it is not necessary for the exchange operator to store the unique data in the first storage unit of the control board after the exchange. Here, the timing controller performs a process of correcting the input video signal using the unique data read from the first storage unit, so that the unique data can be read from the second storage unit at a high speed. There is no need to employ communication. For this reason, it is possible to reliably read the unique data from the second storage unit without causing a transmission error. Further, since the unique data is read from the first storage unit in a short time, the correction process using the unique data is promptly performed after the display device is activated. As described above, a display device capable of displaying an image in which correction by the unique data is reflected promptly after activation without causing a transmission error of the unique data or the like is realized.
　本発明の第２の局面によれば、駆動回路を搭載する基板（厳密には、駆動回路に直接的に接続された基板）に第２の記憶部が設けられる。これに関し、駆動回路を搭載する基板は、ソースドライバＩＣ（映像信号線を駆動するための集積回路）を介して表示パネルと圧着接続されていることが多い。このため、駆動回路を搭載する基板が交換対象となった場合、単純な作業での修理は無理であり専用の圧着設備を用いて修理作業を行う必要が生じるが、そのような圧着設備が揃っていれば、交換作業者にとって第２の記憶部に固有データを格納する作業は大きな負担にはならない。 According to the second aspect of the present invention, the second storage unit is provided on the substrate on which the drive circuit is mounted (strictly, the substrate directly connected to the drive circuit). In this regard, a substrate on which a drive circuit is mounted is often crimped to a display panel via a source driver IC (an integrated circuit for driving video signal lines). For this reason, when the board on which the drive circuit is mounted is to be replaced, it is impossible to repair by simple work, and it is necessary to perform repair work using dedicated crimping equipment. If so, the work of storing the unique data in the second storage unit is not a heavy burden for the exchange operator.
　本発明の第３の局面によれば、本発明の第２の局面と同様の効果が得られる。 According to the third aspect of the present invention, the same effect as in the second aspect of the present invention can be obtained.
　本発明の第４の局面によれば、本発明の第１の局面と同様の効果が得られる。 According to the fourth aspect of the present invention, the same effect as in the first aspect of the present invention can be obtained.
　本発明の第５の局面によれば、第１の記憶部からの固有データの読み出しと第２の記憶部からの固有データの読み出しとを並行して行うことが可能となる。このため、装置の起動から第２の記憶部からの固有データの読み出しが完了するまでの期間が短縮される。従って、コントロール基板の交換が行われた際、装置の起動から第１の記憶部内のデータの書き換え（更新）が完了するまでの期間が短縮される。これにより、コントロール基板の交換が行われた際に、固有データによる補正が反映された画像が速やかに表示される。 According to the fifth aspect of the present invention, the reading of the unique data from the first storage unit and the reading of the unique data from the second storage unit can be performed in parallel. For this reason, the period from the start of the apparatus to the completion of reading of the unique data from the second storage unit is shortened. Therefore, when the control board is replaced, the period from the start of the apparatus to the completion of rewriting (updating) of data in the first storage unit is shortened. As a result, when the control board is replaced, an image reflecting the correction based on the unique data is promptly displayed.
　本発明の第６の局面によれば、第２のバスラインを用いたデータ伝送（タイミングコントローラと第２の記憶部との間での固有データの伝送）を低速で行うことにより、固有データの伝送エラーの発生をより確実に抑止することが可能となる。 According to the sixth aspect of the present invention, by performing data transmission (transmission of unique data between the timing controller and the second storage unit) using the second bus line at a low speed, It is possible to more reliably suppress the occurrence of transmission errors.
　本発明の第７の局面によれば、タイミングコントローラと第２の記憶部との間での固有データの伝送に関するインタフェースにはＩ２Ｃが採用される。Ｉ２Ｃはデータ伝送に必要な信号線の本数が少ないので、コントロール基板のコストや全体的なコストが低減される。また、信号線が少なくなることに起因して、基板の設計難易度が低下する。 According to the seventh aspect of the present invention, I2C is adopted as an interface related to transmission of specific data between the timing controller and the second storage unit. Since the number of signal lines required for data transmission is small in I2C, the cost of the control board and the overall cost are reduced. In addition, the difficulty in designing the substrate is reduced due to a decrease in the number of signal lines.
　本発明の第８の局面によれば、第１の記憶部に保持されている固有データと第２の記憶部に保持されている固有データとが一致しているか否かを判断するための処理が簡易な処理となるので、データの比較に要する時間が短縮される。また、比較されるデータの量が少なくなるので、表示装置の起動時のデータ処理の負荷が軽減され、消費電力低減やＥＭＩ軽減の効果が期待される。 According to the eighth aspect of the present invention, the process for determining whether or not the unique data held in the first storage unit matches the unique data held in the second storage unit Since this is a simple process, the time required for data comparison is reduced. Further, since the amount of data to be compared is reduced, the data processing load at the time of starting the display device is reduced, and an effect of reducing power consumption and EMI is expected.
　本発明の第９の局面によれば、本発明の第８の局面と同様の効果が得られる。 According to the ninth aspect of the present invention, the same effect as in the eighth aspect of the present invention can be obtained.
　本発明の第１０の局面によれば、本発明の第８の局面と同様の効果が得られる。 According to the tenth aspect of the present invention, the same effect as in the eighth aspect of the present invention can be obtained.
　本発明の第１１の局面によれば、コントロール基板の交換が行われた際には、装置の起動後に表示パネルに特定の画像が表示される。このため、コントロール基板の交換作業者が、第１の記憶部内のデータの更新処理が正常に行われていることや当該処理が終了したことを目視によって容易に確認することが可能となる。 According to the eleventh aspect of the present invention, when the control board is replaced, a specific image is displayed on the display panel after the apparatus is started. For this reason, the operator who replaces the control board can easily visually confirm that the data update process in the first storage unit is normally performed and that the process has been completed.
　本発明の第１２の局面によれば、固有データの伝送エラー等を生ずることなく起動後に速やかに表示むらのない画像を表示できる表示装置が実現される。 According to the twelfth aspect of the present invention, a display device capable of displaying an image without display unevenness immediately after startup without causing a transmission error of unique data or the like is realized.
本発明の第１の実施形態に係る液晶表示装置の全体構成を示すブロック図である。1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. 上記第１の実施形態に係る液晶表示装置の機能構成を示すブロック図である。It is a block diagram which shows the function structure of the liquid crystal display device which concerns on the said 1st Embodiment. 上記第１の実施形態において、液晶表示装置の起動後の処理の流れを説明するためのフローチャートである。6 is a flowchart for explaining a flow of processing after activation of the liquid crystal display device in the first embodiment. 上記第１の実施形態において、各種処理の処理時間について説明するための図である。It is a figure for demonstrating the processing time of various processes in the said 1st Embodiment. 上記第１の実施形態の変形例において、液晶表示装置の起動後の処理の流れを説明するためのフローチャートである。10 is a flowchart for explaining a flow of processing after activation of the liquid crystal display device in a modification of the first embodiment. 上記第１の実施形態の変形例において、特殊パターンの画像の表示について説明するための図である。In the modification of the said 1st Embodiment, it is a figure for demonstrating the display of the image of a special pattern. 本発明の第２の実施形態に係る液晶表示装置の全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the liquid crystal display device which concerns on the 2nd Embodiment of this invention. 上記第２の実施形態において、各種処理の処理時間について説明するための図である。It is a figure for demonstrating the processing time of various processes in the said 2nd Embodiment. 上記第２の実施形態の変形例に係る液晶表示装置の全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the liquid crystal display device which concerns on the modification of the said 2nd Embodiment. 上記第２の実施形態の変形例において、各種処理の処理時間について説明するための図である。It is a figure for demonstrating the processing time of various processes in the modification of the said 2nd Embodiment. 第２のメモリをゲート基板に設けた構成例を示すブロック図である。It is a block diagram which shows the structural example which provided the 2nd memory in the gate substrate. 第２のメモリを表示パネルを構成する基板に設けた構成例を示すブロック図である。It is a block diagram which shows the structural example which provided the 2nd memory in the board | substrate which comprises a display panel. 国際公開２０１０／１４６９２９号パンフレットに開示された液晶表示装置の全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the liquid crystal display device disclosed by the international publication 2010/146929 pamphlet.
＜１．第１の実施形態＞
＜１．１　構成＞
　図１は、本発明の第１の実施形態に係る液晶表示装置１の全体構成を示すブロック図である。この液晶表示装置１は、タイミングコントローラ１４０を搭載するコントロール基板１０と、ソースドライバＩＣ２３０を搭載するソース基板２０（厳密には、ソースドライバＩＣ２３０に直接的に接続されたソース基板２０）と、液晶パネル（表示パネル）４０とによって構成されている。なお、図１に示す液晶表示装置１には２枚のソース基板２０が設けられているが、ソース基板２０の数については特に限定されない。ソース基板２０に搭載されているソースドライバＩＣ２３０は、液晶パネル４０に接続されている。コントロール基板１０とソース基板２０とは、コントロール基板１０のコネクタ１２０とソース基板２０のコネクタ２２０とを介して接続されている。コントロール基板１０のコネクタ１２０とソース基板２０のコネクタ２２０とは、ＦＦＣ（フレキシブルフラットケーブル）３０によって接続されている。コントロール基板１０のコネクタ１３０は、外部から供給される各種信号（後述する入力映像信号ＤＩＮやタイミング信号群ＴＧ：図２参照）を伝送する信号線に接続されている。 <1. First Embodiment>
<1.1 Configuration>
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device 1 according to the first embodiment of the present invention. The liquid crystal display device 1 includes a control substrate 10 on which a timing controller 140 is mounted, a source substrate 20 on which a source driver IC 230 is mounted (strictly speaking, a source substrate 20 directly connected to the source driver IC 230), a liquid crystal panel (Display panel) 40. In addition, although the two source substrates 20 are provided in the liquid crystal display device 1 illustrated in FIG. 1, the number of the source substrates 20 is not particularly limited. A source driver IC 230 mounted on the source substrate 20 is connected to the liquid crystal panel 40. The control board 10 and the source board 20 are connected via the connector 120 of the control board 10 and the connector 220 of the source board 20. The connector 120 of the control board 10 and the connector 220 of the source board 20 are connected by an FFC (flexible flat cable) 30. The connector 130 of the control board 10 is connected to a signal line for transmitting various signals (input video signal DIN and timing signal group TG, which will be described later) supplied from the outside.
　本実施形態においては、液晶表示装置１には、個々の液晶パネル４０毎に設定される固有データである表示むら補正データを保持するための構成要素として２つのメモリ（第１のメモリ１１０および第２のメモリ２１０）が設けられている。具体的には、図１に示すように、第１のメモリ１１０はコントロール基板１０に設けられ、第２のメモリ２１０はソース基板２０の１つに設けられている。第１のメモリ１１０および第２のメモリ２１０は、不揮発性の書き換え可能なメモリ（例えば、フラッシュメモリ，ＥＥＰＲＯＭなど）である。第１のメモリ１１０には、表示むら補正データに加えて、機種毎に共通的に用いられるデータである共通データも格納される。共通データとしては、ガンマ補正用データ、ＱＳ駆動用のテーブル、各種処理用のルックアップテーブル、液晶駆動用のタイミング設定用レジスタ値などが挙げられる。なお、本実施形態においては、第１のメモリ１１０によって第１の記憶部が実現され、第２のメモリ２１０によって第２の記憶部が実現されている。 In the present embodiment, the liquid crystal display device 1 includes two memories (a first memory 110 and a first memory 110) as components for holding display unevenness correction data that is unique data set for each liquid crystal panel 40. Two memories 210) are provided. Specifically, as shown in FIG. 1, the first memory 110 is provided on the control board 10, and the second memory 210 is provided on one of the source boards 20. The first memory 110 and the second memory 210 are nonvolatile rewritable memories (for example, flash memory, EEPROM, etc.). In addition to display unevenness correction data, the first memory 110 also stores common data that is data commonly used for each model. Common data includes gamma correction data, a QS drive table, a lookup table for various processes, a timing setting register value for liquid crystal drive, and the like. In the present embodiment, a first storage unit is realized by the first memory 110, and a second storage unit is realized by the second memory 210.
　図１に関し、コントロール基板１０において表示むら補正データの伝送に用いられるバスラインには符号１５０を付し、コントロール基板１０において表示信号の伝送に用いられるバスラインには符号１９０を付し、ソース基板２０において表示むら補正データの伝送に用いられるバスラインには符号２５０を付し、ソース基板２０において表示信号の伝送に用いられるバスラインには符号２９０を付している。なお、以下においては、表示むら補正データの伝送に用いられるバスラインのことを「表示むら補正データ用バスライン」といい、表示信号の伝送に用いられるバスラインのことを「表示信号用バスライン」という。コントロール基板１０において、表示むら補正データ用バスライン１５０は第１のメモリ１１０とコネクタ１２０とタイミングコントローラ１４０とに接続され、表示信号用バスライン１９０はコネクタ１２０とタイミングコントローラ１４０とに接続されている。第２のメモリ２１０が設けられているソース基板２０において、表示むら補正データ用バスライン２５０は第２のメモリ２１０とコネクタ２２０とに接続され、表示信号用バスライン２９０はコネクタ２２０とソースドライバＩＣ２３０とに接続されている。本実施形態においては、タイミングコントローラ１４０と第１のメモリ１１０との間での表示むら補正データの伝送とタイミングコントローラ１４０と第２のメモリ２１０との間での表示むら補正データの伝送とは同じ表示むら補正データ用バスラインを用いて行われる。 1, reference numeral 150 denotes a bus line used for transmission of display unevenness correction data in the control board 10, and reference numeral 190 denotes a bus line used for transmission of a display signal in the control board 10. In FIG. 20, reference numeral 250 is assigned to a bus line used for transmission of display unevenness correction data, and reference numeral 290 is assigned to a bus line used for transmission of display signals on the source substrate 20. In the following description, a bus line used for transmission of display unevenness correction data is referred to as a “display unevenness correction data bus line”, and a bus line used for display signal transmission is referred to as a “display signal bus line”. " In the control board 10, the display unevenness correction data bus line 150 is connected to the first memory 110, the connector 120, and the timing controller 140, and the display signal bus line 190 is connected to the connector 120 and the timing controller 140. . In the source substrate 20 provided with the second memory 210, the display unevenness correction data bus line 250 is connected to the second memory 210 and the connector 220, and the display signal bus line 290 is connected to the connector 220 and the source driver IC 230. And connected to. In this embodiment, the transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and the transmission of display unevenness correction data between the timing controller 140 and the second memory 210 are the same. The display unevenness correction data bus line is used.
　以上のような構成において、この液晶表示装置１の起動後（電源オン後）、タイミングコントローラ１４０は、第１のメモリ１１０から共通データを読み出し、第１のメモリ１１０および第２のメモリ２１０の双方から表示むら補正データを読み出す。但し、コントロール基板１０の交換直後に第１のメモリ１１０から読み出されるデータは、個々の液晶パネル４０毎に設定されている表示むら補正データではない。タイミングコントローラ１４０は、第１のメモリ１１０から読み出した表示むら補正データと第２のメモリ２１０から読み出した表示むら補正データとを比較し、両者が一致しなければ、第２のメモリ２１０から読み出した表示むら補正データを用いて第１のメモリ１１０を更新する。 In the configuration as described above, after the liquid crystal display device 1 is started (after power is turned on), the timing controller 140 reads the common data from the first memory 110, and both the first memory 110 and the second memory 210 are read. The display unevenness correction data is read out from. However, the data read from the first memory 110 immediately after the replacement of the control board 10 is not display unevenness correction data set for each liquid crystal panel 40. The timing controller 140 compares the display unevenness correction data read from the first memory 110 with the display unevenness correction data read from the second memory 210, and if they do not match, the timing controller 140 reads from the second memory 210. The first memory 110 is updated using the display unevenness correction data.
　タイミングコントローラ１４０には、表示むらの発生が抑止されるよう表示むら補正データを用いて入力映像信号ＤＩＮに補正を施す機能（以下「表示むら補正機能」という。）が設けられている。タイミングコントローラ１４０は、表示むら補正データ用バスライン１５０を介して読み出した表示むら補正データを用いて入力映像信号ＤＩＮに補正を施し、補正によって得られた表示信号を表示信号用バスライン１９０，２９０を介してソースドライバＩＣ２３０に与える。その表示信号に基づいて画像表示が行われる。なお、ここでは表示むら補正機能がタイミングコントローラ１４０に内蔵されていることを前提に説明するが、コントロール基板１０上において表示むら補正機能を実現する集積回路がタイミングコントローラ１４０とは別に設けられていても良い。 The timing controller 140 is provided with a function (hereinafter referred to as “display unevenness correction function”) for correcting the input video signal DIN using display unevenness correction data so that occurrence of display unevenness is suppressed. The timing controller 140 corrects the input video signal DIN using the display unevenness correction data read out through the display unevenness correction data bus line 150, and the display signal obtained by the correction is displayed on the display signal bus lines 190 and 290. To the source driver IC 230. Image display is performed based on the display signal. Here, the description will be made on the assumption that the display unevenness correction function is built in the timing controller 140, but an integrated circuit for realizing the display unevenness correction function is provided separately from the timing controller 140 on the control board 10. Also good.
　ここで、図２を参照しつつ、本実施形態に係る液晶表示装置１の動作について詳しく説明する。図２は、液晶表示装置１の機能構成を示すブロック図である。なお、この機能構成については、後述する第２の実施形態においても同様である。図２に示すように、この液晶表示装置１は、機能的には、タイミングコントローラ１４０，映像信号線駆動回路２３，走査信号線駆動回路４０２，および表示部４００によって構成されている。映像信号線駆動回路２３は、複数のソースドライバＩＣ２３０によって構成されている。走査信号線駆動回路４０２は、アモルファスシリコン，多結晶シリコン，微結晶シリコン，酸化物半導体（例えば、酸化インジウムガリウム亜鉛）などを用いて、表示部４００を含む液晶パネル４０内に形成されている。すなわち、本実施形態においては、走査信号線駆動回路４０２と表示部４００とは同一基板（液晶パネル４０を構成する２枚の基板のうちの一方の基板）上に形成されている。但し、液晶パネル４０を構成する基板とは異なる基板に走査信号線駆動回路４０２が設けられていても良い。 Here, the operation of the liquid crystal display device 1 according to the present embodiment will be described in detail with reference to FIG. FIG. 2 is a block diagram showing a functional configuration of the liquid crystal display device 1. This functional configuration is the same in the second embodiment described later. As shown in FIG. 2, the liquid crystal display device 1 is functionally configured by a timing controller 140, a video signal line driving circuit 23, a scanning signal line driving circuit 402, and a display unit 400. The video signal line drive circuit 23 includes a plurality of source driver ICs 230. The scanning signal line driver circuit 402 is formed in the liquid crystal panel 40 including the display portion 400 using amorphous silicon, polycrystalline silicon, microcrystalline silicon, an oxide semiconductor (for example, indium gallium zinc oxide), or the like. That is, in this embodiment, the scanning signal line drive circuit 402 and the display unit 400 are formed on the same substrate (one of the two substrates constituting the liquid crystal panel 40). However, the scanning signal line driver circuit 402 may be provided on a substrate different from the substrate constituting the liquid crystal panel 40.
　表示部４００には、複数本（ｍ本）の映像信号線ＳＬ１～ＳＬｍと複数本（ｎ本）の走査信号線ＧＬ１～ＧＬｎとが配設されている。映像信号線ＳＬ１～ＳＬｍと走査信号線ＧＬ１～ＧＬｎとの各交差点に対応して、画素を形成する画素形成部４０１が設けられている。すなわち、表示部４００には、複数個（ｎ×ｍ個）の画素形成部４０１が含まれている。上記複数個の画素形成部４０１はマトリクス状に配置されてｎ行×ｍ列の画素マトリクスを構成している。各画素形成部４０１には、対応する交差点を通過する走査信号線ＧＬにゲート端子が接続されると共に当該交差点を通過する映像信号線ＳＬにソース端子が接続されたスイッチング素子である薄膜トランジスタ（ＴＦＴ）４１と、その薄膜トランジスタ４１のドレイン端子に接続された画素電極４２と、上記複数個の画素形成部４０１に共通的に設けられた共通電極４５および補助容量電極４６と、画素電極４２と共通電極４５とによって形成される液晶容量４３と、画素電極４２と補助容量電極４６とによって形成される補助容量４４とが含まれている。液晶容量４３と補助容量４４とによって画素容量４７が構成されている。なお、図２における表示部４００内には、１つの画素形成部４０１に対応する構成要素のみを示している。また、画素形成部４０１の構成は図２に示す構成には限定されず、例えば、補助容量４４および補助容量電極４６が設けられていない構成を採用することもできる。 The display unit 400 is provided with a plurality (m) of video signal lines SL1 to SLm and a plurality (n) of scanning signal lines GL1 to GLn. A pixel forming portion 401 for forming pixels is provided corresponding to each intersection of the video signal lines SL1 to SLm and the scanning signal lines GL1 to GLn. That is, the display unit 400 includes a plurality (n × m) of pixel forming units 401. The plurality of pixel forming portions 401 are arranged in a matrix to form a pixel matrix of n rows × m columns. Each pixel formation portion 401 has a thin film transistor (TFT) which is a switching element having a gate terminal connected to the scanning signal line GL passing through the corresponding intersection and a source terminal connected to the video signal line SL passing through the intersection. 41, the pixel electrode 42 connected to the drain terminal of the thin film transistor 41, the common electrode 45 and the auxiliary capacitance electrode 46 provided in common to the plurality of pixel forming portions 401, the pixel electrode 42 and the common electrode 45 And a storage capacitor 44 formed by the pixel electrode 42 and the storage capacitor electrode 46. The liquid crystal capacitor 43 and the auxiliary capacitor 44 constitute a pixel capacitor 47. Note that only components corresponding to one pixel formation portion 401 are shown in the display portion 400 in FIG. In addition, the configuration of the pixel formation portion 401 is not limited to the configuration illustrated in FIG. 2, and for example, a configuration in which the auxiliary capacitor 44 and the auxiliary capacitor electrode 46 are not provided may be employed.
　タイミングコントローラ１４０は、入力映像信号ＤＩＮおよび水平同期信号や垂直同期信号などのタイミング信号群ＴＧを受け取り、表示信号としてのデジタル映像信号ＤＶと、映像信号線駆動回路２３の動作を制御するためのソーススタートパルス信号ＳＳＰ，ソースクロック信号ＳＣＫ，およびラッチストローブ信号ＬＳと、走査信号線駆動回路４０２の動作を制御するためのゲートスタートパルス信号ＧＳＰおよびゲートクロック信号ＧＣＫとを出力する。その際、上述したように、表示むら補正データを用いて入力映像信号ＤＩＮに補正を施すことによってデジタル映像信号ＤＶ（表示信号）が生成される。 The timing controller 140 receives an input video signal DIN and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal, and controls a digital video signal DV as a display signal and an operation of the video signal line driving circuit 23. A start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS, and a gate start pulse signal GSP and a gate clock signal GCK for controlling the operation of the scanning signal line driver circuit 402 are output. At this time, as described above, the digital video signal DV (display signal) is generated by correcting the input video signal DIN using the display unevenness correction data.
　映像信号線駆動回路２３は、タイミングコントローラ１４０から出力されるデジタル映像信号ＤＶ，ソーススタートパルス信号ＳＳＰ，ソースクロック信号ＳＣＫ，およびラッチストローブ信号ＬＳを受け取り、映像信号線ＳＬ１～ＳＬｍに駆動用映像信号を印加する。このとき、映像信号線駆動回路２３では、ソースクロック信号ＳＣＫのパルスが発生するタイミングで、映像信号線ＳＬ１～ＳＬｍに印加すべき電圧を示すデジタル映像信号ＤＶが順次に保持される。そして、ラッチストローブ信号ＬＳのパルスが発生するタイミングで、上記保持されたデジタル映像信号ＤＶがアナログ電圧に変換される。その変換されたアナログ電圧は、駆動用映像信号として全ての映像信号線ＳＬ１～ＳＬｍに一斉に印加される。 The video signal line drive circuit 23 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the timing controller 140, and drives the video signal lines SL1 to SLm to drive video signals. Is applied. At this time, the video signal line driving circuit 23 sequentially holds the digital video signal DV indicating the voltage to be applied to the video signal lines SL1 to SLm at the timing when the pulse of the source clock signal SCK is generated. The held digital video signal DV is converted into an analog voltage at the timing when the pulse of the latch strobe signal LS is generated. The converted analog voltage is applied simultaneously to all the video signal lines SL1 to SLm as drive video signals.
　走査信号線駆動回路４０２は、タイミングコントローラ１４０から出力されるゲートスタートパルス信号ＧＳＰおよびゲートクロック信号ＧＣＫに基づいて、アクティブな走査信号の走査信号線ＧＬ１～ＧＬｎへの印加を１垂直走査期間を周期として繰り返す。 Based on the gate start pulse signal GSP and the gate clock signal GCK output from the timing controller 140, the scanning signal line driving circuit 402 applies an active scanning signal to the scanning signal lines GL1 to GLn for one vertical scanning period. Repeat as.
　以上のようにして、走査信号線ＧＬ１～ＧＬｎに走査信号が印加され、映像信号線ＳＬ１～ＳＬｍに駆動用映像信号が印加されることにより、表示むらを生ずることなく、入力映像信号ＤＩＮに基づく画像が表示部４００に表示される。 As described above, the scanning signals are applied to the scanning signal lines GL1 to GLn, and the driving video signals are applied to the video signal lines SL1 to SLm. An image is displayed on the display unit 400.
　なお、本実施形態においては、映像信号線駆動回路２３と走査信号線駆動回路４０２とによって、液晶パネル４０を駆動する駆動回路が実現されている。また、デジタル映像信号ＤＶとソーススタートパルス信号ＳＳＰとソースクロック信号ＳＣＫとラッチストローブ信号ＬＳとゲートスタートパルス信号ＧＳＰとゲートクロック信号ＧＣＫとによって、表示制御信号が実現されている。 In the present embodiment, a drive circuit for driving the liquid crystal panel 40 is realized by the video signal line drive circuit 23 and the scanning signal line drive circuit 402. The display control signal is realized by the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, the gate start pulse signal GSP, and the gate clock signal GCK.
＜１．２　起動後の処理の流れ＞
　次に、図３に示すフローチャートを参照しつつ、本実施形態に係る液晶表示装置１の起動後の処理の流れについて説明する。液晶表示装置１の起動後（電源オン後）、まず、タイミングコントローラ１４０が第１のメモリ１１０からのデータ（共通データおよび表示むら補正データ）の読み出しを行う（ステップＳ１００）。その際、例えば、最初に共通データの読み出しが行われ、その後に表示むら補正データの読み出しが行われる。第１のメモリ１１０からのデータの読み出しの終了後、表示むら補正データを用いた補正が行われつつ画像表示が行われる（ステップＳ１１０）。なお、この画像表示と並行して、タイミングコントローラ１４０による第２のメモリ２１０からの表示むら補正データの読み出しが行われる。 <1.2 Processing flow after startup>
Next, the flow of processing after the liquid crystal display device 1 according to this embodiment is started will be described with reference to the flowchart shown in FIG. After activation of the liquid crystal display device 1 (after power-on), first, the timing controller 140 reads data (common data and display unevenness correction data) from the first memory 110 (step S100). At that time, for example, the common data is read first, and then the display unevenness correction data is read. After the reading of data from the first memory 110 is completed, image display is performed while correction using the display unevenness correction data is performed (step S110). In parallel with this image display, the display unevenness correction data is read from the second memory 210 by the timing controller 140.
　第２のメモリ２１０からの表示むら補正データの読み出しの完了後、タイミングコントローラ１４０は、第１のメモリ１１０から読み出した表示むら補正データと第２のメモリ２１０から読み出した表示むら補正データとを比較する（ステップＳ１２０）。なお、ここでは表示むら補正データに関して全データの比較が行われるものと仮定する。そして、両者が一致しているか否かの判断が行われる（ステップＳ１３０）。その結果、両者が一致していれば、そのまま画像表示が継続される。この場合、ステップＳ１１０での画像表示の際に、既に表示むら補正データを用いた補正が反映された画像が表示される。一方、両者が一致していなければ、処理はステップＳ１４０に進む。 After the reading of the display unevenness correction data from the second memory 210 is completed, the timing controller 140 compares the display unevenness correction data read from the first memory 110 with the display unevenness correction data read from the second memory 210. (Step S120). Here, it is assumed that all data is compared with respect to display unevenness correction data. Then, a determination is made as to whether or not they match (step S130). As a result, if the two match, the image display is continued as it is. In this case, when the image is displayed in step S110, an image in which the correction using the display unevenness correction data is reflected is displayed. On the other hand, if the two do not match, the process proceeds to step S140.
　ステップＳ１４０では、タイミングコントローラ１４０は、第２のメモリ２１０から読み出した表示むら補正データを用いて、第１のメモリ１１０に保持されているデータの書き換えを行う。その後、表示むら補正機能の実行のために、タイミングコントローラ１４０は、第１のメモリ１１０から再度表示むら補正データを読み出す（ステップＳ１５０）。そして、表示むら補正データを用いた補正が行われつつ画像表示が行われる（ステップＳ１６０）。これにより、コントロール基板１０の交換が行われた場合にも、表示むら補正データを用いた補正が反映された画像が表示される。なお、再度電源オンされた後に表示むら補正データを用いた補正が反映された画像が表示されるようにしても良い。 In step S140, the timing controller 140 rewrites the data held in the first memory 110 using the display unevenness correction data read from the second memory 210. Thereafter, in order to execute the display unevenness correction function, the timing controller 140 reads the display unevenness correction data from the first memory 110 again (step S150). Then, image display is performed while correction using display unevenness correction data is performed (step S160). Thereby, even when the control board 10 is replaced, an image reflecting the correction using the display unevenness correction data is displayed. Note that an image reflecting correction using display unevenness correction data may be displayed after the power is turned on again.
＜１．３　データの比較について＞
　上述の説明においては、表示むら補正データに関して全データの比較が行われるものと仮定していた。しかしながら、データの比較に要する時間を短縮するために、以下に記す手法（第１～第３の手法）を採用することもできる。 <1.3 Comparison of data>
In the above description, it is assumed that all data is compared with respect to display unevenness correction data. However, in order to shorten the time required for data comparison, the following methods (first to third methods) can be employed.
＜１．３．１　第１の手法＞
　第１の手法は、誤り検出符号を用いる手法である。具体的には、第１のメモリ１１０に保持されている表示むら補正データのチェックサムを当該第１のメモリ１１０の特定アドレスに書き込んでおくとともに、第２のメモリ２１０に保持されている表示むら補正データのチェックサムを当該第２のメモリ２１０の特定アドレスに書き込んでおく。そして、上記ステップＳ１２０（図３参照）において、タイミングコントローラ１４０は、第１のメモリ１１０に保持されているチェックサムと第２のメモリ２１０に保持されているチェックサムとの比較を行う。タイミングコントローラ１４０は、その比較結果によって、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致しているか否かを判定する。 <1.3.1 First Method>
The first method uses an error detection code. Specifically, the checksum of the display unevenness correction data held in the first memory 110 is written to a specific address of the first memory 110 and the display unevenness held in the second memory 210 is written. The checksum of the correction data is written in a specific address of the second memory 210. In step S120 (see FIG. 3), the timing controller 140 compares the checksum held in the first memory 110 with the checksum held in the second memory 210. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
＜１．３．２　第２の手法＞
　第２の手法は、識別情報を用いる手法である。具体的には、個々の液晶パネルに固有の識別情報（例えば、パネルＩＤ，通し番号，データ作成日時など）を第１のメモリ１１０および第２のメモリ２１０のそれぞれの特定アドレスに予め書き込んでおく。そして、上記ステップＳ１２０（図３参照）において、タイミングコントローラ１４０は、第１のメモリ１１０に保持されている識別情報と第２のメモリ２１０に保持されている識別情報との比較を行う。タイミングコントローラ１４０は、その比較結果によって、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致しているか否かを判定する。 <1.3.2 Second Method>
The second method is a method using identification information. Specifically, identification information unique to each liquid crystal panel (for example, panel ID, serial number, date of data creation, etc.) is written in advance in specific addresses of the first memory 110 and the second memory 210, respectively. In step S120 (see FIG. 3), the timing controller 140 compares the identification information held in the first memory 110 with the identification information held in the second memory 210. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
＜１．３．３　第３の手法＞
　第３の手法は、表示むら補正データの一部についての比較を行う手法である。例えば、特定の範囲のデータについてのみ比較を行うことや、いくつかおきのアドレスのデータについてのみ比較を行うことが挙げられる。このように、上記ステップＳ１２０（図３参照）において、タイミングコントローラ１４０は、表示むら補正データに関して、一部のデータについてのみ比較を行う。タイミングコントローラ１４０は、その比較結果によって、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致しているか否かを判定する。 <1.3.3 Third Method>
The third method is a method of comparing a part of display unevenness correction data. For example, comparison is made only for data in a specific range, and comparison is made only for data at every other address. As described above, in step S120 (see FIG. 3), the timing controller 140 compares only some data with respect to the display unevenness correction data. The timing controller 140 determines whether the display unevenness correction data held in the first memory 110 matches the display unevenness correction data held in the second memory 210 based on the comparison result. .
＜１．３．４　第１～第３の手法による効果＞
　以上のような第１～第３の手法によれば、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致しているか否かを判断するための処理が簡易な処理となるので、データの比較に要する時間が短縮される。また、比較されるデータの量が少なくなるので、液晶表示装置１の起動時のデータ処理の負荷が軽減され、消費電力低減やＥＭＩ軽減の効果が期待される。 <1.3.4 Effects of the first to third methods>
According to the first to third methods as described above, the display unevenness correction data held in the first memory 110 and the display unevenness correction data held in the second memory 210 match. Since the process for determining whether or not is a simple process, the time required for data comparison is shortened. In addition, since the amount of data to be compared is reduced, the data processing load when the liquid crystal display device 1 is started up is reduced, and an effect of reducing power consumption and EMI is expected.
　ところで、液晶表示装置１の起動後の一定期間には、タイミングコントローラ１４０がデータの比較のために第１のメモリ１１０および第２のメモリ２１０にアクセスしている。このため、装置の起動後に表示むら補正機能の実行以外のデータ処理のために第１のメモリ１１０からのデータの読み出しを行う構成が採用されている場合、第１のメモリ１１０への当該データ処理のためのアクセスが上記一定期間にできなくなるという制約が生じ得る。この点、第１～第３の手法によれば、比較されるデータの量が少なくなるので、上述のような制約が生じるおそれが軽減される。なお、第１のメモリ１１０への表示むら補正機能の実行以外のデータ処理のためのアクセスの例としては、液晶パネル４０の表面温度が変化した際のＱＳ駆動用のパラメータの読み出しのためのアクセスや、表示モードの変更（例えば、２Ｄモード－３Ｄモード間の変更）が行われた際のガンマ補正用のパラメータやＱＳ駆動用のパラメータなどの読み出しのためのアクセスが挙げられる。 Incidentally, the timing controller 140 accesses the first memory 110 and the second memory 210 for data comparison for a certain period after the liquid crystal display device 1 is activated. For this reason, when a configuration is adopted in which data is read from the first memory 110 for data processing other than execution of the display unevenness correction function after the apparatus is activated, the data processing to the first memory 110 is performed. There may be a restriction that access for the mobile phone cannot be performed during the predetermined period. In this regard, according to the first to third methods, the amount of data to be compared is reduced, so that the possibility of the above-described restrictions being reduced. As an example of access for data processing other than execution of the display unevenness correction function to the first memory 110, access for reading parameters for QS driving when the surface temperature of the liquid crystal panel 40 changes. And an access for reading out a parameter for gamma correction and a parameter for QS driving when a display mode is changed (for example, a change between 2D mode and 3D mode).
＜１．４　処理時間＞
　図４は、各種処理の処理時間について説明するための図である。図４において、符号Ｌ１はコントロール基板１０上のメモリからの共通データの読み出しに要する時間の長さを表し、符号Ｌ２はソース基板２０上のメモリからの表示むら補正データの読み出しに要する時間の長さを表し、符号Ｌ３はコントロール基板１０上のメモリからの表示むら補正データの読み出しに要する時間の長さを表している（図８，図１０も同様）。なお、ここでの従来技術とは、国際公開２０１０／１４６９２９号パンフレットに開示されている技術（図１３に示した構成）のことである。また、従来技術においてもコントロール基板１０上のメモリ（図１３では不図示）から共通データの読み出しが行われるものと仮定する。 <1.4 Processing time>
FIG. 4 is a diagram for explaining processing times of various processes. In FIG. 4, symbol L1 represents the length of time required to read common data from the memory on the control board 10, and symbol L2 represents the length of time required to read display unevenness correction data from the memory on the source board 20. The symbol L3 represents the length of time required to read display unevenness correction data from the memory on the control board 10 (the same applies to FIGS. 8 and 10). Note that the conventional technique here is a technique disclosed in the pamphlet of International Publication No. 2010/146929 (configuration shown in FIG. 13). In the conventional technique, it is assumed that common data is read from a memory (not shown in FIG. 13) on the control board 10.
　タイミングコントローラ１４０とソース基板２０上のメモリとの間の配線距離は比較的長いので、両者間の通信でデータ伝送エラーを引き起こさないようにするためには比較的低い周波数でデータ伝送を行う必要がある。これに対して、第１のメモリ１１０とタイミングコントローラ１４０との間の配線距離は短いので、両者間では比較的高い周波数でデータ伝送を行うことができる。従って、コントロール基板１０上のメモリからの表示むら補正データの読み出しに要する時間の長さＬ３は、ソース基板２０上のメモリからの表示むら補正データの読み出しに要する時間の長さＬ２よりも短い。 Since the wiring distance between the timing controller 140 and the memory on the source substrate 20 is relatively long, it is necessary to perform data transmission at a relatively low frequency in order not to cause a data transmission error in communication between the timing controller 140 and the memory on the source substrate 20. is there. On the other hand, since the wiring distance between the first memory 110 and the timing controller 140 is short, data transmission can be performed at a relatively high frequency between the two. Accordingly, the length of time L3 required for reading the display unevenness correction data from the memory on the control board 10 is shorter than the length L2 of the time required for reading the display unevenness correction data from the memory on the source board 20.
　ここで、従来技術と本実施形態とを比較する。従来技術においても本実施形態においても、時点ｔ０（起動時点）から時点ｔ１までの期間に共通データの読み出しが行われる。従来技術においては、コントロール基板１０には表示むら補正データを格納するメモリは設けられていない。従って、従来技術においては、時点ｔ１から時点ｔ３までの期間をかけてソース基板２０上のメモリから表示むら補正データの読み出しが行われ、時点ｔ３に画像表示が開始される。これに対して、本実施形態においては、ソース基板２０だけでなくコントロール基板１０にも表示むら補正データを格納するメモリが設けられている。このような構成において、まず、コントロール基板１０上のメモリ（第１のメモリ１１０）からの表示むら補正データの読み出しが行われ、その後、ソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しが行われる。すなわち、本実施形態においては、時点ｔ１から時点ｔ２までの期間にコントロール基板１０上のメモリ（第１のメモリ１１０）から表示むら補正データの読み出しが行われ、時点ｔ２に画像表示が開始される。また、画像表示と並行して、時点ｔ２から時点ｔ４までの期間に、ソース基板２０上のメモリ（第２のメモリ２１０）から表示むら補正データの読み出しが行われる。そして、コントロール基板１０上のメモリ（第１のメモリ１１０）から読み出した表示むら補正データとソース基板２０上のメモリ（第２のメモリ２１０）から読み出した表示むら補正データとの比較が時点ｔ４以降に行われる。 Here, the prior art and this embodiment will be compared. In both the prior art and the present embodiment, common data is read during a period from time t0 (starting time) to time t1. In the prior art, the control board 10 is not provided with a memory for storing display unevenness correction data. Therefore, in the prior art, display unevenness correction data is read from the memory on the source substrate 20 over a period from time t1 to time t3, and image display is started at time t3. In contrast, in the present embodiment, not only the source substrate 20 but also the control substrate 10 is provided with a memory for storing display unevenness correction data. In such a configuration, first, display unevenness correction data is read from the memory on the control board 10 (first memory 110), and then read from the memory on the source board 20 (second memory 210). The display unevenness correction data is read out. That is, in the present embodiment, display unevenness correction data is read from the memory (first memory 110) on the control board 10 during a period from time t1 to time t2, and image display is started at time t2. . In parallel with the image display, display unevenness correction data is read from the memory (second memory 210) on the source substrate 20 during a period from time t2 to time t4. The display unevenness correction data read from the memory on the control board 10 (first memory 110) and the display unevenness correction data read from the memory on the source board 20 (second memory 210) are compared after time t4. To be done.
　以上のように、本実施形態においては、画像表示に必要な表示むら補正データの読み出しに要する時間が従来技術よりも短くなっている。 As described above, in the present embodiment, the time required for reading the display unevenness correction data necessary for image display is shorter than that of the prior art.
＜１．５　効果＞
　本実施形態に係る液晶表示装置１には、個々の液晶パネル４０毎に設定される固有データである表示むら補正データを保持するための構成要素として２つのメモリ（第１のメモリ１１０および第２のメモリ２１０）が設けられている。詳しくは、第１のメモリ１１０は表示むら補正機能を有するタイミングコントローラ１４０が搭載されたコントロール基板１０に設けられ、第２のメモリ２１０はソースドライバＩＣ２３０が搭載されたソース基板２０（厳密には、ソースドライバＩＣ２３０に直接的に接続されたソース基板２０）に設けられている。このような構成において、液晶表示装置１の起動の際、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致していなければ、第２のメモリ２１０に保持されている表示むら補正データを用いて第１のメモリ１１０が更新される。このため、コントロール基板１０の交換の際、交換作業者にとって、交換後のコントロール基板１０のメモリ（第１のメモリ１１０）に表示むら補正データを格納する作業は不要となる。ここで、本実施形態においては、タイミングコントローラ１４０では、第１のメモリ１１０から読み出された表示むら補正データを用いて入力映像信号ＤＩＮに補正を施す処理が行われるので、第２のメモリ２１０からの表示むら補正データの読み出しに高速での通信を採用する必要がない。このため、伝送エラーを生ずることなく第２のメモリ２１０からの表示むら補正データの読み出しを確実に行うことが可能となる。また、第１のメモリ１１０からの表示むら補正データの読み出しは短時間で行われるので、この液晶表示装置１の起動後には、速やかに表示むら補正機能が実行される。以上より、本実施形態によれば、表示むら補正データの伝送エラー等を生ずることなく起動後に速やかに表示むら補正データによる補正が反映された画像（表示むらのない画像）を表示できる液晶表示装置１が実現される。 <1.5 Effect>
The liquid crystal display device 1 according to the present embodiment includes two memories (a first memory 110 and a second memory) as components for holding display unevenness correction data that is unique data set for each liquid crystal panel 40. Memory 210). Specifically, the first memory 110 is provided on the control board 10 on which the timing controller 140 having a display unevenness correction function is mounted, and the second memory 210 is the source board 20 on which the source driver IC 230 is mounted (strictly speaking, It is provided on the source substrate 20) directly connected to the source driver IC 230. In such a configuration, when the liquid crystal display device 1 is activated, the display unevenness correction data held in the first memory 110 and the display unevenness correction data held in the second memory 210 must match. For example, the first memory 110 is updated using the display unevenness correction data held in the second memory 210. For this reason, when the control board 10 is replaced, the replacement operator does not need to store the display unevenness correction data in the memory (first memory 110) of the control board 10 after the replacement. Here, in the present embodiment, the timing controller 140 performs a process of correcting the input video signal DIN using the display unevenness correction data read from the first memory 110, and thus the second memory 210. It is not necessary to employ high-speed communication for reading the display unevenness correction data from. For this reason, it is possible to reliably read the display unevenness correction data from the second memory 210 without causing a transmission error. Further, since the display unevenness correction data is read from the first memory 110 in a short time, the display unevenness correction function is immediately executed after the liquid crystal display device 1 is started. As described above, according to the present embodiment, a liquid crystal display device capable of displaying an image (an image having no display unevenness) in which the correction based on the display unevenness correction data is reflected promptly after startup without causing a display unevenness correction data transmission error or the like. 1 is realized.
　また、ソース基板２０に第２のメモリ２１０が設けられる点に関し、ソース基板２０はソースドライバＩＣ２３０を介して液晶パネル４０と圧着接続されていることが多い。このため、ソース基板２０が交換対象となった場合、単純な作業での修理は無理であり専用の圧着設備を用いて修理作業を行う必要が生じるが、そのような圧着設備が揃っていれば、交換作業者にとって第２のメモリ２１０に表示むら補正データを格納する作業は大きな負担にはならない。 Further, regarding the point that the second memory 210 is provided on the source substrate 20, the source substrate 20 is often connected to the liquid crystal panel 40 via the source driver IC 230 by pressure bonding. For this reason, when the source substrate 20 is to be replaced, it is impossible to repair by a simple operation, and it is necessary to perform repair work using a dedicated crimping facility. The work of storing the display unevenness correction data in the second memory 210 is not a heavy burden for the replacement operator.
＜１．６　変形例＞
　上記第１の実施形態においては、コントロール基板１０の交換後に画像表示が行われた際、交換作業者は画面を見ても第１のメモリ１１０内のデータを書き換える処理（図３のステップＳ１４０の処理）が行われたのか否かを判断することができない。そこで、本変形例においては、その判断を容易に行うことができるよう、第１のメモリ１１０内のデータの書き換えが行われている期間には、例えば画面全体が緑色のべた画像など特殊パターンの画像が表示される。これを実現するために、タイミングコントローラ１４０は、第１のメモリ１１０に保持されている表示むら補正データと第２のメモリ２１０に保持されている表示むら補正データとが一致していない場合、第１のメモリ１１０内のデータの書き換え（更新）が行われている期間中、液晶パネル４０に特殊パターンの画像が表示されるようにデジタル映像信号ＤＶ（表示信号）を映像信号線駆動回路２３に供給する。 <1.6 Modification>
In the first embodiment, when an image is displayed after the control board 10 is replaced, the replacement operator rewrites the data in the first memory 110 even when viewing the screen (in step S140 in FIG. 3). It is not possible to determine whether or not processing has been performed. Therefore, in this modified example, during the period when the data in the first memory 110 is being rewritten, for example, a special pattern such as a solid image of the whole screen can be obtained. An image is displayed. To achieve this, the timing controller 140 determines that the display unevenness correction data held in the first memory 110 and the display unevenness correction data held in the second memory 210 do not match. The digital video signal DV (display signal) is sent to the video signal line drive circuit 23 so that the image of the special pattern is displayed on the liquid crystal panel 40 during the period when the data in the memory 110 of 1 is being rewritten (updated). Supply.
　図５は、本変形例に係る液晶表示装置の起動後の処理の流れを説明するためのフローチャートである。ステップＳ２３０までの処理の流れは、上記第１の実施形態におけるステップＳ１３０までの処理の流れと同様である。ステップＳ２３０で両者が一致している旨の判定がなされた場合、上記第１の実施形態と同様、画像表示が継続される。ステップＳ２３０で両者が一致していない旨の判定がなされた場合には、処理はステップＳ２４０に進む。 FIG. 5 is a flowchart for explaining the flow of processing after activation of the liquid crystal display device according to this modification. The flow of processing up to step S230 is the same as the flow of processing up to step S130 in the first embodiment. When it is determined in step S230 that both are the same, the image display is continued as in the first embodiment. If it is determined in step S230 that the two do not match, the process proceeds to step S240.
　ステップＳ２４０では、上述した特殊パターンの画像の表示が開始される。その後、タイミングコントローラ１４０は、第２のメモリ２１０から読み出した表示むら補正データを用いて、第１のメモリ１１０に保持されているデータの書き換えを行う（ステップＳ２５０）。データの書き換え完了後、表示むら補正機能の実行のために、タイミングコントローラ１４０は、第１のメモリ１１０から再度表示むら補正データを読み出す（ステップＳ２６０）。その後、特殊パターンの画像の表示が終了する（ステップＳ２７０）。そして、表示むら補正データを用いた補正が行われつつ画像表示（通常画像の表示）が行われる（ステップＳ２８０）。なお、本変形例においても、再度電源オンされた後に表示むら補正データを用いた補正が反映された画像が表示されるようにしても良い。 In step S240, the display of the special pattern image described above is started. After that, the timing controller 140 rewrites the data held in the first memory 110 using the display unevenness correction data read from the second memory 210 (step S250). After the data rewriting is completed, the timing controller 140 reads the display unevenness correction data from the first memory 110 again in order to execute the display unevenness correction function (step S260). Thereafter, the display of the special pattern image ends (step S270). Then, image display (display of a normal image) is performed while performing correction using display unevenness correction data (step S280). Also in this modification, an image reflecting correction using display unevenness correction data may be displayed after the power is turned on again.
　次に、図６を参照しつつ、本変形例における効果について説明する。通常時においては、装置の起動直後から表示むら補正データによる補正が反映された通常の画像が表示される。これに対して、コントロール基板１０の交換後においては、装置の起動直後には特殊パターンの画像６２が表示され、第１のメモリ１１０内のデータの書き換えの完了後に、表示むら補正データによる補正が反映された通常の画像６１が表示される。このように、本変形例によれば、コントロール基板１０の交換作業者が、第１のメモリ１１０内のデータの書き換え処理が正常に行われていることや当該処理が終了したことを目視によって容易に確認することが可能となる。 Next, effects of this modification will be described with reference to FIG. In a normal state, a normal image reflecting the correction based on the display unevenness correction data is displayed immediately after the apparatus is started. On the other hand, after the control board 10 is replaced, the special pattern image 62 is displayed immediately after the apparatus is started, and after the rewriting of the data in the first memory 110 is completed, the correction by the display unevenness correction data is performed. The reflected normal image 61 is displayed. As described above, according to the present modification, it is easy for the operator who replaces the control board 10 to visually confirm that the data rewrite processing in the first memory 110 is normally performed or that the processing is completed. It becomes possible to confirm.
＜２．第２の実施形態＞
　本発明の第２の実施形態について説明する。なお、以下においては、主に上記第１の実施形態と異なる点について説明し、上記第１の実施形態と同様の点については説明を省略する。 <2. Second Embodiment>
A second embodiment of the present invention will be described. In the following, differences from the first embodiment will be mainly described, and description of the same points as the first embodiment will be omitted.
＜２．１　構成＞
　図７は、本発明の第２の実施形態に係る液晶表示装置２の全体構成を示すブロック図である。上記第１の実施形態においては、タイミングコントローラ１４０と第１のメモリ１１０との間での表示むら補正データの伝送とタイミングコントローラ１４０と第２のメモリ２１０との間での表示むら補正データの伝送とは同じ表示むら補正データ用バスラインを用いて行われていた。これに対して、本実施形態においては、タイミングコントローラ１４０と第１のメモリ１１０との間での表示むら補正データの伝送とタイミングコントローラ１４０と第２のメモリ２１０との間での表示むら補正データの伝送とは異なる表示むら補正データ用バスラインを用いて行われる。具体的には、図７に示すように、本実施形態におけるコントロール基板１０には、表示むら補正データを伝送するためのバスラインとして、タイミングコントローラ１４０と第１のメモリ１１０との間での表示むら補正データの伝送に用いられる表示むら補正データ用バスライン１５１と、タイミングコントローラ１４０と第２のメモリ２１０との間での表示むら補正データの伝送に用いられる表示むら補正データ用バスライン１５２とが設けられている。 <2.1 Configuration>
FIG. 7 is a block diagram showing the overall configuration of the liquid crystal display device 2 according to the second embodiment of the present invention. In the first embodiment, transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and transmission of display unevenness correction data between the timing controller 140 and the second memory 210. Is performed using the same display unevenness correction data bus line. On the other hand, in the present embodiment, transmission of display unevenness correction data between the timing controller 140 and the first memory 110 and display unevenness correction data between the timing controller 140 and the second memory 210. This transmission is performed using a display irregularity correction data bus line different from the transmission of. Specifically, as shown in FIG. 7, the control board 10 according to the present embodiment displays information between the timing controller 140 and the first memory 110 as a bus line for transmitting display unevenness correction data. Display unevenness correction data bus line 151 used for transmission of unevenness correction data, and display unevenness correction data bus line 152 used for transmission of display unevenness correction data between timing controller 140 and second memory 210, Is provided.
　本実施形態においては、表示むら補正データ用バスライン１５１と表示むら補正データ用バスライン１５２とでは同じインタフェースを用いてデータ伝送が行われている。なお、ここでは、表示むら補正データ用バスライン１５１を用いた表示むら補正データの伝送および表示むら補正データ用バスライン１５２を用いた表示むら補正データの伝送の双方に関し、インタフェースにはＳＰＩ（Ｓｅｒｉａｌ　Ｐｅｒｉｐｈｅｒａｌ　Ｉｎｔｅｒｆａｃｅ）が採用されているものと仮定する。 In the present embodiment, the display unevenness correction data bus line 151 and the display unevenness correction data bus line 152 perform data transmission using the same interface. It should be noted that here, regarding both the transmission of the display unevenness correction data using the display unevenness correction data bus line 151 and the transmission of the display unevenness correction data using the display unevenness correction data bus line 152, the interface includes an SPI (Serial). It is assumed that Peripheral Interface) is adopted.
　上述のような構成が採用されているので、タイミングコントローラ１４０は、第１のメモリ１１０からの表示むら補正データの読み出しと第２のメモリ２１０からの表示むら補正データの読み出しとを並行して行うことが可能である。 Since the above-described configuration is employed, the timing controller 140 reads the display unevenness correction data from the first memory 110 and the display unevenness correction data from the second memory 210 in parallel. It is possible.
　なお、本実施形態においては、表示むら補正データ用バスライン１５１によって第１のバスラインが実現され、表示むら補正データ用バスライン１５２によって第２のバスラインが実現されている。 In the present embodiment, the first bus line is realized by the display unevenness correction data bus line 151, and the second bus line is realized by the display unevenness correction data bus line 152.
＜２．２　処理時間＞
　図８は、各種処理の処理時間について説明するための図である。本実施形態においても、時点ｔ０（起動時点）から時点ｔ１までの期間に共通データの読み出しが行われる。時点ｔ１になると、コントロール基板１０上のメモリ（第１のメモリ１１０）からの表示むら補正データの読み出しとソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しとが並行して行われる。コントロール基板１０上のメモリ（第１のメモリ１１０）からの表示むら補正データの読み出しは時点ｔ２に終了する。そして、時点ｔ２に画像表示が開始される。なお、ソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しは時点ｔ３に終了する。このように、ソース基板２０上のメモリからの表示むら補正データの読み出しが上記第１の実施形態よりも本実施形態の方が早く完了する。そして、コントロール基板１０上のメモリ（第１のメモリ１１０）から読み出した表示むら補正データとソース基板２０上のメモリ（第２のメモリ２１０）から読み出した表示むら補正データとの比較が時点ｔ３以降に行われる。 <2.2 Processing time>
FIG. 8 is a diagram for explaining processing times of various processes. Also in this embodiment, common data is read during a period from time t0 (starting time) to time t1. At time t1, reading of display unevenness correction data from the memory on the control board 10 (first memory 110) and reading of display unevenness correction data from the memory on the source board 20 (second memory 210) are performed. Done in parallel. Reading of display unevenness correction data from the memory (first memory 110) on the control board 10 ends at time t2. Then, image display is started at time t2. Note that the reading of display unevenness correction data from the memory (second memory 210) on the source substrate 20 ends at time t3. As described above, reading of display unevenness correction data from the memory on the source substrate 20 is completed earlier in the present embodiment than in the first embodiment. The display unevenness correction data read from the memory on the control board 10 (first memory 110) and the display unevenness correction data read from the memory on the source board 20 (second memory 210) are compared after time t3. To be done.
＜２．３　効果＞
　本実施形態によれば、装置の起動からソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しが完了するまでの期間が短縮される。このため、コントロール基板１０の交換が行われた際、装置の起動から第１のメモリ１１０内のデータの書き換えが完了するまでの期間を短縮することが可能となる。これにより、コントロール基板１０の交換が行われた際に、表示むらのない画像が速やかに表示される。 <2.3 Effects>
According to this embodiment, the period from the start of the apparatus to the completion of the reading of display unevenness correction data from the memory (second memory 210) on the source substrate 20 is shortened. For this reason, when the control board 10 is replaced, it is possible to shorten the period from the start of the apparatus to the completion of the rewriting of data in the first memory 110. Thereby, when the control board 10 is exchanged, an image without display unevenness is promptly displayed.
＜２．４　変形例＞
　図９は、上記第２の実施形態の変形例に係る液晶表示装置３の全体構成を示すブロック図である。コントロール基板１０には、表示むら補正データを伝送するためのバスラインとして、タイミングコントローラ１４０と第１のメモリ１１０との間での表示むら補正データの伝送に用いられる表示むら補正データ用バスライン１５１と、タイミングコントローラ１４０と第２のメモリ２１０との間での表示むら補正データの伝送に用いられる表示むら補正データ用バスライン１５３とが設けられている。本変形例においては、表示むら補正データ用バスライン１５１によって第１のバスラインが実現され、表示むら補正データ用バスライン１５３によって第２のバスラインが実現されている。 <2.4 Modification>
FIG. 9 is a block diagram showing an overall configuration of a liquid crystal display device 3 according to a modification of the second embodiment. The control board 10 has a display unevenness correction data bus line 151 used for transmission of display unevenness correction data between the timing controller 140 and the first memory 110 as a bus line for transmitting display unevenness correction data. And a display unevenness correction data bus line 153 used for transmission of display unevenness correction data between the timing controller 140 and the second memory 210. In the present modification, the first bus line is realized by the display unevenness correction data bus line 151, and the second bus line is realized by the display unevenness correction data bus line 153.
　上記第２の実施形態においては、表示むら補正データ用バスライン１５１と表示むら補正データ用バスライン１５２とでは同じインタフェースを用いてデータ伝送が行われていた。これに対して、本変形例においては、表示むら補正データ用バスライン１５１と表示むら補正データ用バスライン１５３とでは異なるインタフェースを用いてデータ伝送が行われる。具体的には、表示むら補正データ用バスライン１５１を用いた表示むら補正データの伝送に関するインタフェースにはＳＰＩが採用され、表示むら補正データ用バスライン１５３を用いた表示むら補正データの伝送に関するインタフェースにはＩ２Ｃ（Ｉｎｔｅｒ－Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）が採用されている。但し、表示むら補正データ用バスライン１５１と表示むら補正データ用バスライン１５３とで採用されるインタフェースの組み合わせは、これには限定されない。 In the second embodiment, the display unevenness correction data bus line 151 and the display unevenness correction data bus line 152 perform data transmission using the same interface. On the other hand, in this modification, data transmission is performed using different interfaces between the display unevenness correction data bus line 151 and the display unevenness correction data bus line 153. Specifically, an SPI is adopted as an interface related to transmission of display unevenness correction data using the display unevenness correction data bus line 151, and an interface related to transmission of display unevenness correction data using the display unevenness correction data bus line 153. I2C (Inter-Integrated Circuit) is adopted for the. However, the combination of interfaces employed in the display unevenness correction data bus line 151 and the display unevenness correction data bus line 153 is not limited to this.
　ＳＰＩは比較的高速での通信に用いられるインタフェースであり、Ｉ２Ｃは比較的低速での通信に用いられるインタフェースである。例えば、ＳＰＩでは３２ＭＨｚでのデータ通信が行われ、Ｉ２Ｃでは４００ＫＨｚでのデータ通信が行われる。このように、表示むら補正データ用バスライン１５３よりも表示むら補正データ用バスライン１５１の方が表示むら補正データの伝送が高速に行われることが好ましい。 SPI is an interface used for communication at a relatively high speed, and I2C is an interface used for communication at a relatively low speed. For example, data communication at 32 MHz is performed in SPI, and data communication at 400 KHz is performed in I2C. Thus, it is preferable that the display unevenness correction data bus line 151 transmit the display unevenness correction data at a higher speed than the display unevenness correction data bus line 153.
　図１０は、各種処理の処理時間について説明するための図である。なお、符号Ｌ４は、本変形例に係る構成でソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しに要する時間の長さを表している。本変形例においても、時点ｔ０（起動時点）から時点ｔ１までの期間に共通データの読み出しが行われる。時点ｔ１になると、コントロール基板１０上のメモリ（第１のメモリ１１０）からの表示むら補正データの読み出しとソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しとが並行して行われる。コントロール基板１０上のメモリ（第１のメモリ１１０）からの表示むら補正データの読み出しは時点ｔ２に終了する。そして、時点ｔ２に画像表示が開始される。なお、ソース基板２０上のメモリ（第２のメモリ２１０）からの表示むら補正データの読み出しは時点ｔ４以降に終了する。 FIG. 10 is a diagram for explaining processing times of various processes. Note that the symbol L4 represents the length of time required to read display unevenness correction data from the memory (second memory 210) on the source substrate 20 in the configuration according to this modification. Also in this modification, common data is read during a period from time t0 (starting time) to time t1. At time t1, reading of display unevenness correction data from the memory on the control board 10 (first memory 110) and reading of display unevenness correction data from the memory on the source board 20 (second memory 210) are performed. Done in parallel. Reading of display unevenness correction data from the memory (first memory 110) on the control board 10 ends at time t2. Then, image display is started at time t2. Note that the display unevenness correction data is read from the memory (second memory 210) on the source substrate 20 after time t4.
　本変形例によれば、上記第１の実施形態や上記第２の実施形態と同様、第１のメモリ１１０からの表示むら補正データの読み出しは短時間で行われるので、起動後に速やかに表示むら補正データによる補正が反映された画像（表示むらのない画像）を表示できる液晶表示装置３が実現される。また、データ伝送に必要な信号線の本数がＳＰＩよりもＩ２Ｃの方が少ないので、本変形例によれば、コントロール基板１０のコストが低減される。また、コントロール基板１０とソース基板２０とを接続するために必要な信号線も少なくなるので、全体的なコスト低減を図ることが可能となる。さらに、信号線が少なくなることに起因して、基板の設計難易度が低下する。さらにまた、第２のメモリ２１０からの表示むら補正データの読み出しが低速で行われるので、より確実に伝送エラーの発生が抑止される。 According to this modification, the display unevenness correction data is read from the first memory 110 in a short time as in the first embodiment and the second embodiment. A liquid crystal display device 3 that can display an image (an image with no display unevenness) reflecting the correction by the correction data is realized. In addition, since the number of signal lines required for data transmission is smaller in I2C than in SPI, according to the present modification, the cost of the control board 10 is reduced. In addition, since the number of signal lines required for connecting the control board 10 and the source board 20 is reduced, the overall cost can be reduced. Furthermore, the difficulty in designing the substrate is reduced due to the decrease in the number of signal lines. Furthermore, since the display unevenness correction data is read from the second memory 210 at a low speed, the occurrence of a transmission error is more reliably suppressed.
＜３．その他＞
　上記各実施形態および上記各変形例においては、第２のメモリ２１０はソース基板２０に設けられていた。しかしながら、本発明はこれに限定されない。例えば、走査信号線ＧＬを駆動するための集積回路であるゲートドライバＩＣ５２０が搭載されたゲート基板５０（厳密には、走査信号線ＧＬを駆動するための集積回路であるゲートドライバＩＣ５２０に直接的に接続されたゲート基板５０）を備えた構成の液晶表示装置４において、図１１に示すように第２のメモリ５１０をゲート基板５０に設けるようにしても良い。また、図１２に示すように、液晶パネル４０を構成する基板に第２のメモリ４１０を設けるようにしても良い。そのほか、電源用の基板やバックライト用の基板などに第２のメモリを設けるようにしても良い。以上のように、第１のメモリ１１０をコントロール基板１０に設けるとともにコントロール基板１０以外の基板に第２のメモリを設けるようにすれば良い。 <3. Other>
In each of the above embodiments and each of the above modifications, the second memory 210 is provided on the source substrate 20. However, the present invention is not limited to this. For example, the gate substrate 50 on which the gate driver IC 520 which is an integrated circuit for driving the scanning signal line GL is mounted (strictly speaking, the gate driver IC 520 which is an integrated circuit for driving the scanning signal line GL is directly connected to the gate substrate 50 In the liquid crystal display device 4 configured to include the connected gate substrate 50), the second memory 510 may be provided on the gate substrate 50 as shown in FIG. In addition, as shown in FIG. 12, the second memory 410 may be provided on a substrate constituting the liquid crystal panel 40. In addition, the second memory may be provided on a power supply substrate, a backlight substrate, or the like. As described above, the first memory 110 may be provided on the control board 10 and the second memory may be provided on a board other than the control board 10.
　また、上記各実施形態および上記各変形例においては、第１のメモリ１１０および第２のメモリ２１０に保持されるデータが表示むら補正データである場合を例に挙げて説明したが、本発明はこれに限定されない。個々の装置毎（パネル毎）に設定される固有データであれば、第１のメモリ１１０および第２のメモリ２１０に保持されるデータは表示むら補正データ以外のデータであっても良い。 Further, in each of the embodiments and each of the modifications described above, the case where the data held in the first memory 110 and the second memory 210 is display unevenness correction data has been described as an example. It is not limited to this. As long as the unique data is set for each individual device (each panel), the data held in the first memory 110 and the second memory 210 may be data other than display unevenness correction data.
　さらに、上記各実施形態および上記各変形例においては、液晶表示装置を例に挙げて説明した。しかしながら、本発明はこれに限定されず、液晶表示装置以外の表示装置（例えば、有機ＥＬ表示装置）にも本発明を適用することができる。 Further, in each of the above embodiments and each of the above modifications, the liquid crystal display device has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to display devices other than liquid crystal display devices (for example, organic EL display devices).
　１～５…液晶表示装置
　１０…コントロール基板
　２０…ソース基板
　３０…ＦＦＣ（フレキシブルフラットケーブル）
　４０…液晶パネル
　１１０…第１のメモリ
　１２０，１３０，２２０…コネクタ
　１４０…タイミングコントローラ
　１５０～１５３…（コントロール基板内の）表示むら補正データ用バスライン
　１９０…（コントロール基板内の）表示信号用バスライン
　２１０，４１０，５１０…第２のメモリ
　２３０…ソースドライバＩＣ
　２５０…（ソース基板内の）表示むら補正データ用バスライン
　２９０…（ソース基板内の）表示信号用バスライン
　４００…表示部 DESCRIPTION OF SYMBOLS 1-5 ... Liquid crystal display device 10 ... Control board 20 ... Source board 30 ... FFC (flexible flat cable)
40 ... Liquid crystal panel 110 ... First memory 120, 130, 220 ... Connector 140 ... Timing controller 150-153 ... Display unevenness correction data bus line (in control board) 190 ... Display signal bus (in control board) Lines 210, 410, 510 ... second memory 230 ... source driver IC
250... Display unevenness correction data bus line (in the source substrate) 290... Display signal bus line (in the source substrate) 400.

Claims (12)

  1. 　表示パネルと、前記表示パネルを駆動する駆動回路と、表示信号を含む表示制御信号を前記駆動回路に供給するタイミングコントローラとを備える表示装置であって、
    　個々の表示パネル毎に設定される固有データを保持するための２つの記憶部である第１の記憶部および第２の記憶部を有し、
    　前記第１の記憶部は、前記タイミングコントローラを搭載するコントロール基板に設けられ、
    　前記第２の記憶部は、前記コントロール基板以外の基板に設けられ、
    　前記タイミングコントローラは、
    　　前記第１の記憶部から読み出した固有データに基づいて入力映像信号を補正することによって、前記表示信号を生成し、
    　　前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致していなければ、前記第２の記憶部に保持されている固有データで前記第１の記憶部を更新することを特徴とする、表示装置。     A display device comprising: a display panel; a drive circuit that drives the display panel; and a timing controller that supplies a display control signal including a display signal to the drive circuit,
    A first storage unit and a second storage unit, which are two storage units for holding unique data set for each individual display panel;
    The first storage unit is provided on a control board on which the timing controller is mounted,
    The second storage unit is provided on a substrate other than the control substrate,
    The timing controller is
    Generating the display signal by correcting the input video signal based on the unique data read from the first storage unit;
    If the unique data held in the first storage unit does not match the unique data held in the second storage unit, the unique data held in the second storage unit A display device, wherein the first storage unit is updated.
  2. 　前記第２の記憶部は、前記駆動回路を搭載する基板に設けられていることを特徴とする、請求項１に記載の表示装置。 The display device according to claim 1, wherein the second storage unit is provided on a substrate on which the driving circuit is mounted.
  3. 　前記表示パネルは、前記表示信号に相当する映像信号を伝送するための複数の映像信号線を含み、
    　前記第２の記憶部は、前記複数の映像信号線を駆動する映像信号線駆動回路を搭載する基板に設けられていることを特徴とする、請求項２に記載の表示装置。     The display panel includes a plurality of video signal lines for transmitting a video signal corresponding to the display signal,
    The display device according to claim 2, wherein the second storage unit is provided on a substrate on which a video signal line driving circuit that drives the plurality of video signal lines is mounted.
  4. 　前記タイミングコントローラと前記第１の記憶部との間での固有データの伝送と前記タイミングコントローラと前記第２の記憶部との間での固有データの伝送とは同じバスラインを用いて行われることを特徴とする、請求項１に記載の表示装置。 The transmission of unique data between the timing controller and the first storage unit and the transmission of unique data between the timing controller and the second storage unit are performed using the same bus line. The display device according to claim 1, wherein:
  5. 　前記コントロール基板には、前記タイミングコントローラと前記第１の記憶部との間での固有データの伝送に用いられる第１のバスラインと、前記タイミングコントローラと前記第２の記憶部との間での固有データの伝送に用いられる第２のバスラインとが設けられていることを特徴とする、請求項１に記載の表示装置。 The control board includes a first bus line used for transmission of unique data between the timing controller and the first storage unit, and between the timing controller and the second storage unit. The display device according to claim 1, further comprising a second bus line used for transmission of the unique data.
  6. 　前記第２のバスラインよりも前記第１のバスラインの方が、固有データの伝送が高速に行われることを特徴とする、請求項５に記載の表示装置。 6. The display device according to claim 5, wherein the first bus line transmits the unique data at a higher speed than the second bus line.
  7. 　前記第１のバスラインを用いた固有データの伝送に関するインタフェースにはＳＰＩが採用され、
    　前記第２のバスラインを用いた固有データの伝送に関するインタフェースにはＩ２Ｃが
    採用されていることを特徴とする、請求項６に記載の表示装置。     An SPI is adopted as an interface related to transmission of specific data using the first bus line,
    The display device according to claim 6, wherein I2C is adopted as an interface related to transmission of specific data using the second bus line.
  8. 　前記第１の記憶部および前記第２の記憶部には、固有データの誤り検出符号が保持されており、
    　前記タイミングコントローラは、前記第１の記憶部に保持されている誤り検出符号と前記第２の記憶部に保持されている誤り検出符号とを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする、請求項１に記載の表示装置。     In the first storage unit and the second storage unit, an error detection code of unique data is held,
    The timing controller is held in the first storage unit by comparing the error detection code held in the first storage unit with the error detection code held in the second storage unit. 2. The display device according to claim 1, wherein it is determined whether the unique data stored in the second storage unit matches the unique data stored in the second storage unit.
  9. 　前記第１の記憶部および前記第２の記憶部には、個々の表示パネルを識別するための識別情報が保持されており、
    　前記タイミングコントローラは、前記第１の記憶部に保持されている識別情報と前記第２の記憶部に保持されている識別情報とを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする、請求項１に記載の表示装置。     In the first storage unit and the second storage unit, identification information for identifying individual display panels is held,
    The timing controller is held in the first storage unit by comparing the identification information held in the first storage unit with the identification information held in the second storage unit. The display device according to claim 1, wherein it is determined whether or not the unique data matches the unique data held in the second storage unit.
  10. 　前記タイミングコントローラは、前記第１の記憶部および前記第２の記憶部のそれぞれに保持されている一部の固有データを比較することによって、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致しているか否かを判定することを特徴とする、請求項１に記載の表示装置。 The timing controller compares the specific data held in each of the first storage unit and the second storage unit with a part of the unique data held in the first storage unit. The display device according to claim 1, wherein it is determined whether or not the unique data held in the second storage unit matches.
  11. 　前記タイミングコントローラは、前記第１の記憶部に保持されている固有データと前記第２の記憶部に保持されている固有データとが一致していなければ、前記第１の記憶部の更新が行われている期間中、前記表示パネルに特定の画像が表示されるように表示信号を前記駆動回路に供給することを特徴とする、請求項１に記載の表示装置。 The timing controller updates the first storage unit if the unique data held in the first storage unit and the unique data held in the second storage unit do not match. 2. The display device according to claim 1, wherein a display signal is supplied to the driving circuit so that a specific image is displayed on the display panel during a period of time.
  12. 　前記固有データは、前記表示パネルでの表示むらの発生を抑止するためのデータであることを特徴とする、請求項１に記載の表示装置。 The display device according to claim 1, wherein the unique data is data for suppressing occurrence of display unevenness on the display panel.
PCT/JP2016/068493 2015-06-29 2016-06-22 Display device WO2017002677A1 (en)

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