WO2016209025A2 - Unité de rétroéclairage utilisant une diode électroluminescente multi-cellule - Google Patents

Unité de rétroéclairage utilisant une diode électroluminescente multi-cellule Download PDF

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Publication number
WO2016209025A2
WO2016209025A2 PCT/KR2016/006768 KR2016006768W WO2016209025A2 WO 2016209025 A2 WO2016209025 A2 WO 2016209025A2 KR 2016006768 W KR2016006768 W KR 2016006768W WO 2016209025 A2 WO2016209025 A2 WO 2016209025A2
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WO
WIPO (PCT)
Prior art keywords
light emitting
layer
emitting cell
semiconductor layer
cell
Prior art date
Application number
PCT/KR2016/006768
Other languages
English (en)
Korean (ko)
Other versions
WO2016209025A3 (fr
Inventor
송영준
정정화
김은주
Original Assignee
서울반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020150091420A external-priority patent/KR20170001436A/ko
Priority claimed from KR1020150101214A external-priority patent/KR102429939B1/ko
Priority claimed from KR1020150103840A external-priority patent/KR102451722B1/ko
Priority claimed from KR1020150108262A external-priority patent/KR102454170B1/ko
Priority to JP2017549369A priority Critical patent/JP2018528598A/ja
Priority to DE212016000126.4U priority patent/DE212016000126U1/de
Priority to EP16814738.7A priority patent/EP3316244B1/fr
Priority to CN201690000752.0U priority patent/CN208990251U/zh
Application filed by 서울반도체 주식회사 filed Critical 서울반도체 주식회사
Priority to US15/354,292 priority patent/US9769897B2/en
Publication of WO2016209025A2 publication Critical patent/WO2016209025A2/fr
Publication of WO2016209025A3 publication Critical patent/WO2016209025A3/fr
Priority to US15/678,739 priority patent/US10091850B2/en
Priority to US15/873,769 priority patent/US10051705B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K99/00—Subject matter not provided for in other groups of this subclass
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S2/00—Systems of lighting devices, not provided for in main groups F21S4/00 - F21S10/00 or F21S19/00, e.g. of modular construction
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages

Definitions

  • the present invention relates to a backlight unit using a multicell light emitting diode, and more particularly, to a backlight unit capable of driving a small current using a multicell light emitting diode configured to increase the effective light emitting area of each light emitting cell.
  • the liquid crystal display implements an image by controlling the transmittance of the backlight light source.
  • a cold cathode fluorescent lamp (CCFL) is mainly used, and in recent years, many light emitting diodes having advantages such as power amount, lifespan, and environmental characteristics have been used.
  • the light source required for the liquid crystal display is divided into an edge type backlight unit and a direct type backlight unit according to the position of the light emitting diode.
  • the edge type backlight unit includes a light guide plate to arrange light emitting diodes as light sources on the side of the light guide plate, and emits light emitted from the light source to the liquid crystal panel through the light guide plate.
  • Such an edge type backlight unit can reduce the number of light emitting diodes, and does not require high quality deviations between light emitting diodes, thereby reducing manufacturing costs and developing low power products.
  • the edge-type backlight unit has a disadvantage in that it is difficult to overcome the difference in contrast between the edge portion and the central region of the liquid crystal display, and thus there is a limit in implementing high image quality.
  • the direct type backlight unit light emitting diodes are positioned under the liquid crystal panel so that light can be irradiated directly to the front surface of the liquid crystal panel from a surface light source having almost the same area as the liquid crystal panel. Accordingly, it is possible to implement such that there is no difference in contrast between the edge portion and the central region of the liquid crystal panel, and there is an advantage of realizing high image quality.
  • the direct type backlight unit fails to backlight the relatively large area evenly, a large number of light emitting diodes must be densely arranged, thereby increasing power consumption.
  • the liquid crystal panel is non-uniformly backlighted, which makes it difficult to secure homogeneity of the screen.
  • the direct type backlight unit controls the driving current supplied to the LED arrays which are a plurality of LED groups through driving circuits for driving the plurality of LEDs.
  • the LED backlight unit increases, a plurality of LEDs or LED arrays arranged adjacent to each other may be short-circuited as the LED driving circuits and the LED arrays corresponding thereto greatly increase.
  • the driving circuit is damaged due to overheating, stability and reliability of the backlight unit may be degraded.
  • FIG. 1 is a block diagram illustrating a backlight unit using an LED according to the prior art. Referring to FIG. 1, a problem according to the prior art will be described in more detail. As shown in FIG. 1, the backlight unit 1 according to the related art includes a backlight control module 2 and a backlight module 5.
  • the backlight control module 2 includes a plurality of LED arrays 6a constituting the driving power generator 3 and the backlight module 5 that generate / output a DC driving power using an input power Vin input from the outside. 6n) and a drive control section 4 for controlling the respective operations.
  • the driving power generator 3 generally generates and outputs a DC voltage such as 12V, 24V, 48V as a driving power source.
  • the backlight module 5 is an optical unit for improving the efficiency of the light emitted from the plurality of LED arrays (6a-6n) and the plurality of LED arrays (6a-6n) each of which is configured by connecting a plurality of LEDs in series It is configured to include (not shown).
  • a backlight module 5 is illustrated in which n LED arrays 6a to 6n each including five LEDs connected in series are connected in parallel to each other.
  • the LEDs according to the related art used generally have a forward voltage level between 3 V and 6.5 V, and therefore, these general LEDs are connected to the driving power generation unit 3 as described above to individually control / drive.
  • the driving controller 4 controls the backlight module 5 by PWM controlling the driving power supplied to the backlight module 5 according to the dimming signal Dim input from the outside. It may be configured to control the brightness of all the LED array (6a ⁇ 6n) constituting. Alternatively, in the backlight unit 1 according to the related art, the driving controller 4 drives a current flowing through a specific LED array among the n LED arrays 6a to 6n according to a dimming signal Dim input from the outside. By adjusting the size of, it can be configured to control the brightness of a particular LED array.
  • LEDs used in the backlight unit 1 according to the related art are generally single-cell LEDs and have device characteristics that are driven with a small voltage and high current.
  • a single-cell LED as described above can operate with a drive current of 250-500 mA with a drive voltage of 3.6V. Therefore, in order to control the driving of the backlight module 5 composed of such a single-cell LED, the peripheral circuits including the driving control unit 4 according to the prior art should be composed of large-capacity electronic elements capable of handling a large current. Therefore, there is a problem that the manufacturing cost of the backlight unit 1 increases.
  • An object of the present invention is to provide a backlight unit that is small in size and includes light emitting diodes and emits light of the same intensity.
  • Another object of the present invention is to provide a backlight unit capable of improving performance degradation due to a droop phenomenon of a light emitting diode at a high current.
  • An object of the present invention is to provide a backlight module capable of driving a small current using a MJT LED having a plurality of light emitting cells and a backlight unit including the same.
  • another object of the present invention is to provide an MJT LED chip and a method of manufacturing the same that can increase the effective light emitting area of each light emitting cell.
  • the present invention enables the low-current driving of the backlight module using the MJT LED as described above, thereby improving the stability and reliability of the driving circuit for controlling the driving of the backlight module, and can reduce the manufacturing cost
  • Another object is to provide a backlight unit.
  • the present invention is to provide a backlight unit capable of driving a small current driving the backlight module using the MJT LED, thereby improving the power efficiency and light efficiency, and can prevent the droop phenomenon caused by the large current driving. It is done.
  • another object of the present invention is to provide a backlight unit by minimizing the number of LEDs required by configuring the backlight module using the MJT LED as described above, and capable of driving control for each MJT LED.
  • the problem to be solved by the present invention is to provide a backlight unit including a backlight module using a multi-cell light emitting diode with high stability and reliability while the light emitted from each light emitting diode in the direct type backlight unit uniformly irradiated to the liquid crystal panel.
  • a backlight unit includes a base and a plurality of light emitting diode packages disposed on the bottom surface of the base, wherein the light emitting diode package includes at least one light emitting diode, and the light emitting diode includes: a first A conductive semiconductor layer; A mesa positioned on the first conductive semiconductor layer and including an active layer and a second conductive semiconductor layer; A reflective electrode structure on the mesa; A current opening covering the mesa and the first conductive semiconductor layer, the first opening exposing the reflective electrode structure and electrically connected to the first conductive semiconductor layer and insulated from the reflective electrode structure and the mesa.
  • an upper insulating layer covering the current spreading layer, wherein the upper insulating layer exposes the current spreading layer to expose a second opening defining a first electrode pad region and an upper region of the exposed reflective electrode structure. It may have a third opening that defines the second electrode pad region.
  • the light emitting diode further includes a diffusion barrier reinforcement layer positioned on the reflective electrode structure within the first opening of the current spreading layer, and the diffusion barrier reinforcement layer is exposed through the third opening of the upper insulating layer.
  • a diffusion barrier reinforcement layer positioned on the reflective electrode structure within the first opening of the current spreading layer, and the diffusion barrier reinforcement layer is exposed through the third opening of the upper insulating layer.
  • the diffusion barrier reinforcement layer may be formed of the same material as the current dispersion layer.
  • the current spreading layer may include an ohmic contact layer, a metal reflective layer, a diffusion barrier layer and an antioxidant layer, wherein the diffusion barrier layer comprises at least one metal layer selected from the group consisting of Cr, Ti, Ni, Mo, TiW, and W.
  • the antioxidant layer may include Au, Ag or an organic material layer.
  • the diffusion barrier layer may include at least two pairs of Ti / Ni or Ti / Cr.
  • the current spreading layer may further include an adhesive layer located on the antioxidant layer.
  • the reflective electrode structure may include a reflective metal part; Capping metal parts; And an anti-oxidation metal portion, wherein the reflective metal portion has an inclined side surface such that an upper surface thereof has a narrower area than the lower surface, the capping metal portion covers an upper surface and a side surface of the reflective metal portion, and the reflective metal portion is formed with the capping metal portion. It may have a stress relaxation layer at the interface.
  • the mesa may have an elongate branch portion extending in parallel to each other in one direction and a connection portion where the branch portions are connected to each other, and the first opening may be positioned on the connection portion.
  • the mesa may be a plurality, and the plurality of mesas may have an elongated shape extending in parallel to each other in one direction.
  • the light emitting diode may further include an ohmic contact structure positioned on the first conductive semiconductor layer between the mesas and electrically connected to the current spreading layer.
  • the light emitting diode further includes a lower insulating layer positioned between the mesa and the current spreading layer to insulate the current spreading layer from the mesa, wherein the lower insulating layer is located in an upper region of the mesa and the reflective electrode. It may have a fourth opening that exposes the structure.
  • the first opening may have a wider width than the fourth opening so that all of the fourth openings are exposed.
  • the diffusion barrier reinforcement layer may be further included in the first opening and the fourth opening, and the diffusion barrier reinforcement layer may be exposed through the third opening.
  • the lower insulating layer may include a silicon oxide layer, and the upper insulating layer may include a silicon nitride layer.
  • the optical member may further include an optical member including a light incident surface on which light emitted from the light emitting diode is incident and a light exit surface on which light is emitted so as to have a directing angle greater than that of light emitted from the light emitting diode.
  • the light emitting device may further include a wavelength converter including a phosphor and covering a lower surface of the first conductive semiconductor layer with a uniform thickness.
  • the wavelength converter may extend from a lower surface of the first conductive semiconductor layer to cover the side surface of the light emitting diode, and the wavelength converter may be formed of a single crystal phosphor.
  • the light emitting diode package may include a plurality of light emitting diodes, and the plurality of light emitting diodes may be connected in series.
  • the light emitting diode may further include a substrate disposed on a lower surface of the first conductivity type semiconductor layer, and the plurality of light emitting diodes may share a single substrate.
  • the lower surface of the base and the upper surface of the light emitting diode may face each other.
  • the backlight unit includes a printed circuit board including a plurality of blocks; And a backlight module including a plurality of MJT LEDs disposed on the plurality of blocks, wherein the MJT LEDs include: a growth substrate; A plurality of light emitting cells arranged on the substrate, each of the light emitting cells including a first semiconductor layer, an active layer, and a second semiconductor layer; A plurality of upper electrodes arranged on the plurality of light emitting cells and formed of the same material and electrically connected to first semiconductor layers of corresponding light emitting cells, respectively; And a first pad and a second pad arranged on the upper electrodes, one or more of the upper electrodes being electrically connected to a second semiconductor layer of an adjacent light emitting cell, and the other of the upper electrodes being Insulated from a second semiconductor layer of an adjacent light emitting cell, the light emitting cells are connected in series by the upper electrodes, the first pad is electrically connected to an input light emitting cell of the series connected
  • the backlight unit further includes a first interlayer insulating layer aligned between the light emitting cells and the upper electrodes, and the upper electrodes include side surfaces having an inclination angle of 10 degrees to 45 degrees with respect to a surface of the first interlayer insulating layer. can do.
  • the upper electrode may have a thickness in the range of 2000 kPa to 10000 kPa.
  • the backlight unit further includes lower electrodes aligned on the second semiconductor layer of each light emitting cell, wherein the first interlayer insulating layer exposes a portion of the lower electrode on each light emitting cell, and the second semiconductor layer of the adjacent light emitting cell.
  • the upper electrode (s) electrically connected to the second electrode may be connected to the exposed lower electrode through the first interlayer insulating layer.
  • Each of the lower electrodes may include a side surface having an inclination angle of about 10 degrees to about 45 degrees with respect to the surface of the second semiconductor layer.
  • the lower electrode may have a thickness of 2000 kPa to 10000 kPa.
  • the first interlayer insulating layer may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the exposed lower electrode surface.
  • the first interlayer insulating film may have a thickness of 2000 kPa to 20000 kPa.
  • the backlight unit further includes a second interlayer insulating layer covering the upper electrodes, wherein the second interlayer insulating layer is connected to a lower electrode aligned on a second semiconductor layer of an input light emitting cell and a first semiconductor layer of an output light emitting cell.
  • the upper electrode may be exposed, and the first pad and the second pad may be connected to the lower electrode and the upper electrode through the second interlayer insulating layer, respectively.
  • the second interlayer insulating layer may include a side surface having an inclination angle of 10 degrees to 60 degrees with respect to the upper electrode surface.
  • the second interlayer insulating film may have a thickness of 2000 kPa to 20000 kPa.
  • Each of the light emitting cells may have a via hole exposing a portion of the first semiconductor layer, and the upper electrodes may be connected to a first semiconductor layer of a corresponding light emitting cell through the via hole.
  • Lateral tilt angles of the films exposed through the via holes may be in the range of 10 degrees to 60 degrees.
  • the upper electrode may occupy an area of 30% or more and less than 100% of the total area of the MJT LED.
  • the upper electrode may have a plate or sheet shape having a width-to-width ratio in the range of 1: 3 to 3: 1.
  • At least one of the upper electrodes may have a larger width or width than that of the corresponding light emitting cell.
  • Sides of the films exposed by the mesa etching may have an inclination angle of 10 degrees to 60 degrees with respect to the substrate.
  • the backlight unit further includes a backlight control module for providing a driving voltage to the plurality of MJT LEDs in the backlight module, wherein the block includes at least one MJT LED, and the backlight control module includes the plurality of MJT LEDs.
  • Each drive can be controlled independently.
  • the backlight control module may include a driving power generator; And a driving controller.
  • the driving power generation unit independently provides the driving voltage to each of the plurality of MJT LEDs in the backlight module, and the driving controller dimming the at least one MJT LED by PWM controlling the dimming signal of the backlight control module. It may be characterized by performing the control.
  • the driving controller may generate a dimming control signal in which a pulse width is modulated or a duty ratio is modulated.
  • the driving controller may be configured to independently detect and control driving current of each of the plurality of MJT LEDs in the backlight module.
  • the driving controller may perform dimming control of the at least one MJT LED by controlling a driving current of at least one MJT LED among the plurality of MJT LEDs according to a dimming signal.
  • the first pad of the MJT LED may be connected to the driving power generator, and the second pad of the MJT LED may be connected to a driving controller.
  • the plurality of blocks may be M ⁇ N, and the plurality of blocks may form an M ⁇ N matrix array.
  • At least one block of the plurality of blocks may include a plurality of the MJT LEDs.
  • the backlight unit further includes a plurality of FETs electrically connected to the plurality of MJT LEDs and a FET controller for controlling on and off of the FETs, wherein the number of the plurality of FETs is the plurality of FETs. It may be equal to the number of MJT LEDs.
  • the FET controller may include at least one or more of the plurality of FETs.
  • the number of FETs not included in the FET controller among the plurality of FETs may be less than the number of MJT LEDs.
  • the FET controller may include all of the plurality of FETs.
  • the backlight unit according to an embodiment of the present invention, a printed circuit board including a plurality of blocks; And a backlight module including a plurality of MJT LEDs disposed on the plurality of blocks, the backlight control module providing a driving voltage to the plurality of MJT LEDs in the backlight module, wherein the block is at least one. It includes a MJT LED, the backlight control module may be characterized in that to independently control the driving of each of the plurality of MJT LEDs.
  • the backlight control module may include a driving power generator; And a driving controller.
  • the driving power generation unit independently provides the driving voltage to each of the plurality of MJT LEDs in the backlight module, and the driving controller dimming the at least one MJT LED by PWM controlling the dimming signal of the backlight control module. It may be characterized by performing the control.
  • the driving controller may generate a dimming control signal in which a pulse width is modulated or a duty ratio is modulated.
  • the driving controller may be configured to independently detect and control driving current of each of the plurality of MJT LEDs in the backlight module.
  • the driving controller may perform dimming control of the at least one MJT LED by controlling a driving current of at least one MJT LED among the plurality of MJT LEDs according to a dimming signal.
  • An anode end of the MJT LED may be connected to the driving power generation unit, and a cathode end of the MJT LED may be connected to a driving control unit.
  • Each of the plurality of blocks may include the one optical member.
  • the horizontal length of the block may be 60 mm or less.
  • the vertical length of the block may be 55 mm or less.
  • the plurality of blocks may be M ⁇ N, and the plurality of blocks may form an M ⁇ N matrix array.
  • At least one block of the plurality of blocks may include a plurality of the MJT LEDs.
  • the MJT LED includes first to Nth light emitting cells (N is a natural number of 2 or more), and the Nth light emitting cells are the same as the N-1 light emitting cells, the first light emitting cells, and the second light emitting cells. It can be electrically connected to the structure.
  • the first to Nth light emitting cells may be connected to each other in series and driven by a driving voltage of 2.5 V to 4 V, respectively, and the MJT LED may be driven to a driving voltage of at least 10 V or more.
  • the MJT LEDs are positioned on the growth substrate and spaced apart from each other, and include a lower semiconductor layer, an upper semiconductor layer positioned on the lower semiconductor layer, and an active layer positioned between the lower semiconductor layer and the lower semiconductor layer.
  • the wiring has a first connection portion electrically connected to the first light emitting cell and a second connection portion electrically connected to the second light emitting cell, and one surface of the lower semiconductor layer exposes the lower semiconductor layer.
  • the display device may include an exposed area, and the first connection part may contact the first transparent electrode layer, and the second connection part may be electrically connected to the lower semiconductor layer of the second light emitting cell through the exposed area.
  • a portion of the first transparent electrode layer may be connected to the second light emitting cell.
  • a portion of the first transparent electrode layer may be positioned on the side surface of the lower semiconductor layer of the second light emitting cell through the first light emitting cell and the second light emitting cell.
  • the width of the portion of the first transparent electrode layer positioned on the side surface of the lower semiconductor layer of the second light emitting cell is wider than the width of the portion of the wiring disposed on the side surface of the lower semiconductor layer of the second light emitting cell. Can be.
  • a width of a portion of the first transparent electrode layer positioned between the first light emitting cell and the second light emitting cell may be wider than a width of a portion of the wiring disposed between the first light emitting cell and the second light emitting cell.
  • the first transparent electrode layer may space the wiring and the insulating layer from each other.
  • a portion of the insulating layer may be positioned on a portion of the growth substrate positioned between the first light emitting cell and the second light emitting cell.
  • the display device may further include a current blocking layer disposed between the first light emitting cell and the first transparent electrode layer to separate a part of the first transparent electrode layer from the first light emitting cell.
  • the first transparent electrode layer may be positioned between the second connection portion and the lower semiconductor layer of the second light emitting cell.
  • the distance between the upper surface of the printed circuit board and the lower surface of the floodlight plate may be 18 mm or more.
  • the driving control unit may include a switch control unit electrically connecting or insulating the plurality of MJT LEDs to each other.
  • the switch controller may connect the plurality of MJT LEDs in series and / or in parallel.
  • the backlight module may include a phosphor, and further include a wavelength conversion layer covering the MJT LED, and the light emitted from the MJT LED and transmitted through the wavelength conversion layer may have an NTSC color gamut of 70% or more.
  • the area of the block may be smaller as the number of light emitting cells in the MJT LED increases.
  • a backlight unit includes a printed circuit board including a plurality of blocks; And a backlight module including a plurality of MJT LEDs disposed on the plurality of blocks, wherein the MJT LEDs are spaced apart from each other on a growth substrate, respectively, on the lower semiconductor layer and the lower semiconductor layer.
  • First and second light emitting cells including an upper semiconductor layer and an active layer positioned between the lower semiconductor layer and the lower semiconductor layer; A first transparent electrode layer on the first light emitting cell and electrically connected to the first light emitting cell; A wiring electrically connecting the first light emitting cell to a second light emitting cell; An insulation layer spaced apart from the side surface of the first light emitting cell; And the wiring has a first connection portion electrically connected to the first light emitting cell and a second connection portion electrically connected to the second light emitting cell, and one surface of the lower semiconductor layer exposes the lower semiconductor layer.
  • a portion of the first transparent electrode layer may be connected to the second light emitting cell.
  • a portion of the first transparent electrode layer may be positioned on the side surface of the lower semiconductor layer of the second light emitting cell through the first light emitting cell and the second light emitting cell.
  • the width of the portion of the first transparent electrode layer positioned on the side surface of the lower semiconductor layer of the second light emitting cell is wider than the width of the portion of the wiring disposed on the side surface of the lower semiconductor layer of the second light emitting cell. Can be.
  • a width of a portion of the first transparent electrode layer positioned between the first light emitting cell and the second light emitting cell may be wider than a width of a portion of the wiring disposed between the first light emitting cell and the second light emitting cell.
  • the first transparent electrode layer may space the wiring and the insulating layer from each other.
  • a portion of the insulating layer may be located on a portion of the growth substrate positioned between the first light emitting cell and the second light emitting cell.
  • the display device may further include a current blocking layer disposed between the first light emitting cell and the first transparent electrode layer to separate a part of the first transparent electrode layer from the first light emitting cell.
  • the first transparent electrode layer may be positioned between the second connection portion and the lower semiconductor layer of the second light emitting cell.
  • the backlight unit further includes a plurality of FETs electrically connected to the plurality of MJT LEDs and a FET controller for controlling on and off of the FETs, wherein the number of the plurality of FETs is the plurality of FETs. It may be equal to the number of MJT LEDs.
  • the FET controller may include at least one or more of the plurality of FETs.
  • the number of FETs not included in the FET controller among the plurality of FETs may be less than the number of MJT LEDs.
  • the FET controller may include all of the plurality of FETs.
  • a backlight unit a printed circuit board including a plurality of blocks;
  • a backlight module including a plurality of multicell light emitting diodes disposed on the plurality of blocks;
  • a backlight control module providing a driving voltage to the plurality of multicell light emitting diodes and independently controlling driving of each of the plurality of multicell light emitting diodes;
  • the Wow May be the same as each other, and the half width of the light emitted through the one or more first optical members When greater than or equal to, the intensity of light emitted through the first optical member may be 100% or more.
  • the backlight unit according to an embodiment of the present invention, a printed circuit board including a plurality of blocks; A backlight module including a plurality of multicell light emitting diodes disposed on the plurality of blocks; A backlight control module providing a driving voltage to the plurality of multicell light emitting diodes and independently controlling driving of each of the plurality of multicell light emitting diodes; And at least one first optical member covering the plurality of multicell light emitting diodes, wherein each of the plurality of blocks includes at least one multicell light emitting diode, wherein each of the plurality of blocks includes at least one multicell light emitting diode.
  • Orientation angle May be equal to Equation 1.
  • I a half width of light emitted from the multicell light emitting diode without the first optical member
  • the backlight control module may include a driving power generation unit for independently providing the driving voltage to each of the plurality of multicell LEDs; And a driving controller controlling dimming of the at least one multicell light emitting diode by controlling PWM according to a dimming signal of the backlight control module.
  • the driving controller may generate a dimming control signal in which a pulse width is modulated or a duty ratio is modulated, and may be configured to independently detect and control driving current of each of the plurality of multicell LEDs.
  • the driving controller may perform dimming control of the at least one multicell light emitting diode by controlling a driving current of at least one multicell light emitting diode among the plurality of multicell light emitting diodes according to a dimming signal.
  • an anode end of the multicell light emitting diode may be connected to the driving power generator, and the multicell light emitting diode cathode may be connected to the driving controller.
  • the display apparatus may further include a second optical member disposed on the printed circuit board to correspond to the plurality of multicell light emitting diodes.
  • the second optical member may include a light incident surface receiving light from the multicell light emitting diode and a light emitting surface emitting light at a light directing angle wider than that of the multicell light emitting diode.
  • the first optical member may be formed by molding a resin on the multicell LED.
  • the plurality of blocks may be M X N pieces, and the plurality of blocks may form an M X N matrix array.
  • the multi-cell light emitting diode includes first to Nth light emitting cells (N is a natural number of 2 or more), and an electrical connection structure between the Nth light emitting cell and the N-1 light emitting cell is the first and second light emitting cells. It may be the same as the electrical connection structure of the light emitting cell.
  • the apparatus may further include a plurality of FETs electrically connected to the plurality of multicell light emitting diodes, and a FET controller configured to control on and off of the FETs.
  • the plurality of FETs may include the plurality of multicell light emitting diodes. It may be the same number as the diode.
  • the FET controller may control at least one or more of the plurality of FETs, and one or more FETs not controlled by the FET controller may be smaller than the number of the plurality of multicell light emitting diodes.
  • the FET controller can control all of the plurality of FETs.
  • the optical sheet may further include an optical sheet for improving uniformity of light emitted through the at least one first optical member.
  • the backlight unit according to an embodiment of the present invention, a printed circuit board including a plurality of blocks; A backlight module including a plurality of multicell light emitting diodes disposed on the plurality of blocks; And at least one first optical member covering the plurality of multicell light emitting diodes, wherein each of the plurality of multicell light emitting diodes is spaced apart from each other on a growth substrate, respectively, on the lower semiconductor layer and the lower semiconductor layer.
  • First and second light emitting cells including an upper semiconductor layer positioned at an active layer and an active layer positioned between the lower semiconductor layer and the upper semiconductor layer; A first transparent electrode layer on the first light emitting cell and electrically connected to the first light emitting cell; A wiring electrically connecting the first light emitting cell to the second light emitting cell; And an insulating layer separating the wiring from the side of the first light emitting cell, wherein the wiring is a first connection part electrically connected to the first light emitting cell and a second connection part electrically connected to the second light emitting cell. And an exposed area exposing the lower semiconductor layer on one surface of the lower semiconductor layer, wherein the first connection part contacts the first transparent electrode layer, and the second connection part is formed through the exposed area.
  • each of the plurality of multicell light emitting diodes is independently controlled, and the major axis of each of the plurality of blocks , Shorten this When the half width of the light emitted through the at least one first optical member is Greater than or equal to, May be less than or equal to
  • a printed circuit board including a plurality of blocks;
  • a backlight module including a plurality of multicell light emitting diodes disposed on the plurality of blocks; And at least one first optical member covering the plurality of multicell light emitting diodes, wherein each of the plurality of multicell light emitting diodes is spaced apart from each other on a growth substrate, respectively, on the lower semiconductor layer and the lower semiconductor layer.
  • First and second light emitting cells including an upper semiconductor layer positioned at an active layer and an active layer positioned between the lower semiconductor layer and the upper semiconductor layer; A first transparent electrode layer on the first light emitting cell and electrically connected to the first light emitting cell; A wiring electrically connecting the first light emitting cell to the second light emitting cell; And an insulating layer separating the wiring from the side of the first light emitting cell, wherein the wiring is a first connection part electrically connected to the first light emitting cell and a second connection part electrically connected to the second light emitting cell. And an exposed area exposing the lower semiconductor layer on one surface of the lower semiconductor layer, wherein the first connection part contacts the first transparent electrode layer, and the second connection part is formed through the exposed area.
  • Equation 2 is electrically connected to the lower semiconductor layer of the light emitting cell, and the operation of each of the plurality of multicell light emitting diodes is independently controlled, and directing angle of light emitted through the one or more first optical members ) May be equal to Equation 2.
  • I a half width of light emitted from the multicell light emitting diode without the first optical member
  • a part of the first transparent electrode layer may be connected to the second light emitting cell, and the lower semiconductor layer of the second light emitting cell may pass through the first light emitting cell and the second light emitting cell on the first light emitting cell. It may be located on the side.
  • a width of a portion of the first transparent electrode layer positioned on the side surface of the lower semiconductor layer of the second light emitting cell may be wider than a width of the portion of the first transparent electrode layer positioned on the side of the lower semiconductor layer of the second light emitting cell. Can be.
  • a width of a portion of the first transparent electrode layer positioned between the first light emitting cell and the second light emitting cell may be wider than a width of a portion of the wiring disposed between the first light emitting cell and the second light emitting cell.
  • the first transparent electrode layer may space the wiring and the insulating layer from each other.
  • a portion of the insulating layer may be positioned on a portion of the growth substrate positioned between the first light emitting cell and the second light emitting cell.
  • the display device may further include a current blocking layer positioned between the first light emitting cell and the first transparent electrode layer to separate a part of the first transparent electrode layer from the first light emitting cell.
  • the first transparent electrode layer may be positioned between the second connection portion and the lower semiconductor layer of the second light emitting cell.
  • the backlight unit since the backlight unit includes light emitting diodes having a high directivity angle and a large luminous flux, the size of the backlight unit may be reduced, and light of the same intensity may be emitted while including fewer light emitting diodes. have.
  • the light emitting diode package includes a plurality of light emitting diodes connected in series and the backlight unit includes the light emitting diode package, performance degradation due to the droop phenomenon of the light emitting diode at a high current may be improved.
  • the backlight module using the MJT LED having the small current driving characteristics, the effect that the small current driving of the backlight module and the backlight unit including the same can be expected.
  • the power efficiency and the light efficiency of the backlight unit is improved, it is expected that the effect that can prevent the droop phenomenon caused by the large current driving.
  • an effect of increasing the effective light emitting area of each light emitting cell of the MJT LED chip may be expected by electrically contacting one of the connection portions of the wiring to the inclined side of the light emitting cell.
  • the backlight module using the MJT LED having a small current driving characteristics, there is an effect that the small current driving of the backlight module and the backlight unit including the same. Accordingly, the number of discrete FETs can be reduced.
  • each light emitting cell of the MJT LED chip can be increased by electrically contacting one of the connection portions of the wiring to the inclined side of the light emitting cell.
  • FIG. 1 is a block diagram of a backlight unit using an LED according to the prior art.
  • FIG. 2 is a perspective view illustrating a backlight unit according to a first embodiment of the present invention.
  • FIG. 3 is a view showing a light emitting diode of a backlight unit according to a first embodiment of the present invention, (a) is a plan view, (b) is a cross-sectional view taken along the cut line AA, (c) is a cut along the cut line BB The cross section taken is shown.
  • FIG. 4 is a view showing a wavelength conversion portion formed on a light emitting diode according to a first embodiment of the present invention.
  • FIG. 5 is a view showing a light emitting diode of a backlight unit according to a second embodiment of the present invention, (a) is a plan view, (b) is a cross-sectional view taken along the cut line AA, (c) is a cut along the cut line BB The cross section taken is shown.
  • FIG. 6 is a schematic block diagram of a backlight unit using an MJT LED according to a third embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view for describing an MJT LED module according to a third embodiment of the present invention.
  • FIG. 8 is a schematic perspective view for explaining the MJT LED according to the third embodiment of the present invention.
  • FIG. 9 is a schematic diagram for comparing a backlight unit according to a third embodiment of the present invention.
  • FIG. 10 is a photograph for describing a backlight unit according to another embodiment of the present invention.
  • FIG. 11 is a plan view illustrating a light emitting diode of a backlight unit according to a third embodiment of the present invention.
  • FIG. 12 to 15 are cross-sectional views of the plan view of FIG. 10 taken along a specific line.
  • 16 is an equivalent circuit diagram illustrating light emitting cells according to a third exemplary embodiment of the present invention.
  • FIG. 17 is a perspective view taken along the line C2-C3 of FIG. 10.
  • FIG. 18 is a circuit diagram modeled to connect ten light emitting cells in series according to a third embodiment of the present invention.
  • 19 is a circuit diagram illustrating that light emitting cells are configured in a series / parallel form according to a third embodiment of the present invention.
  • FIG. 20 is a schematic plan view for explaining an MJT LED chip according to a fourth embodiment of the present invention.
  • FIG. 21 is a schematic cross-sectional view taken along cut line B-B of FIG. 20 to illustrate an MJT LED chip according to a fourth embodiment of the present invention.
  • FIG. 22 is a schematic cross-sectional view for describing an MJT LED chip according to a fifth embodiment of the present invention.
  • Figure 23 is a schematic diagram for comparing the conventional backlight unit (a) and the backlight unit (b) of the present invention.
  • FIG. 24 is a view illustrating a backlight module including a square block in which a lens for local dimming is formed in the MJT LED of the present invention.
  • 25 is a view showing that the illumination intensity of the light emitted from the MJT LED in which the lens for local dimming is formed in each block is superimposed on the backlight module of the present invention.
  • FIG. 26 illustrates a lens for local dimming formed in each block having a rectangular shape in the backlight module of the present invention.
  • FIG. 27 is a diagram for calculating a range of directivity angles of light emitted through a lens with respect to a half width of illuminance in the present invention.
  • FIG. 28 is a graph showing the relationship between the full width at half maximum according to the distance change from the light source to the lens of the present invention.
  • FIG. 2 is a perspective view illustrating a backlight unit according to a first embodiment of the present invention.
  • the backlight unit may include a base 200 and a light emitting diode package 110.
  • the base 200 supports the light emitting diode package 110.
  • the base 200 may include a wire (not shown).
  • the base 200 may include a printed circuit board (not shown).
  • the light emitting diode package 110 may be disposed on the base 200. There may be a plurality of light emitting diode packages 110. The plurality of light emitting diode packages 110 may be electrically connected to the wiring of the base 200 to receive a current. For example, when the base 200 includes a printed circuit board, the LED packages 110 may be electrically connected to the printed circuit board.
  • the backlight unit may further include a diffusion plate 300.
  • the diffusion plate 300 may be located on the LED package 110.
  • the diffusion plate 300 may be spaced apart from the base 200.
  • the diffusion plate 300 may diffuse the light emitted from the light emitting diode package 110 so that the color and brightness of each area of the display device such as a liquid crystal display may be uniformly seen.
  • the backlight unit of the present invention is a direct type in which light emitted from the light emitting diode package 110 is incident on a lower surface of the diffuser plate 300 or a light guide plate of light emitted from the light emitting diode package 110. It may include an edge type that is incident perpendicular to the side of the (not shown). In case of the edge type, unlike the direct type, since the exit surface of the LED package 110 should face the side of the light guide plate, the base 200 has a partially bent shape, and one surface of the base 200 opposite to the side surface of the light guide plate is formed.
  • the light emitting diode package 110 may be disposed on the light emitting diode package 110.
  • the light emitting diode used in the present invention is a direction in which the components of the light emitting diode grow toward the base 200.
  • the bottom surface of the base 200 and the top surface of the light emitting diode may face each other. That is, the vertical direction of FIG. 2 and the vertical direction of FIGS. 3 and 4 are opposite directions. Therefore, the light emitting diode package 110 may be located on the bottom surface of the base 200, and furthermore, the diffusion plate 300 may be located under the light emitting diode package 110. Accordingly, other configurations will be described below.
  • FIG. 3 is a view showing a light emitting diode of a backlight unit according to a first embodiment of the present invention, (a) is a plan view, (b) is a cross-sectional view taken along the cut line AA, (c) is a cut along the cut line BB The cross section taken is shown.
  • the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a reflective electrode structure 25, a lower insulating layer 37, and current dispersion. Layer 39, a diffusion barrier reinforcement layer 40, and an upper insulating layer 41.
  • the first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 are grown on the substrate 21.
  • the substrate 100 may be a substrate capable of growing a gallium nitride-based semiconductor layer, and may be, for example, a sapphire substrate, a silicon carbide substrate, a gallium nitride (GaN) substrate, a spinel substrate, or the like.
  • the substrate 21 may be a patterned substrate, such as a patterned sapphire substrate.
  • the substrate 21 may be removed from the LED chip before or after being divided into individual LED chip units.
  • the present invention is not limited thereto, and the substrate 21 may not be removed.
  • the first conductive semiconductor layer 23 may include, for example, an n-type gallium nitride based layer, and the second conductive semiconductor layer 27 may include a p-type gallium nitride based layer.
  • the active layer 25 may be a single quantum well structure or a multi-quantum well structure, and may include a well layer and a barrier layer.
  • the well layer may be selected in its composition according to the wavelength of light required, for example AlGaN, GaN or InGaN.
  • the reflective electrode structure 35 may include a reflective metal part, a capping metal part, and an anti-oxidation metal part.
  • the reflective metal part may include a reflective layer, and may include a stress relaxation layer between the capping metal part and the capping metal part.
  • the stress relieving layer relieves stress due to the difference in coefficient of thermal expansion of the reflective metal portion and the capping metal portion.
  • the reflective metal part may be formed of, for example, Ni / Ag / Ni / Au, and may have a total thickness of about 1600 mm 3.
  • the reflective metal portion may be made of Ni / Ag, ITO / Ag or ITO / DBR (DBR: distributed Bragg reflector).
  • the reflective metal portion is formed such that the side is inclined as shown, that is, the bottom portion has a relatively wider shape.
  • Such a reflective metal portion may be formed using an electron-beam evaporation method.
  • the capping metal part covers the upper and side surfaces of the reflective metal part to protect the reflective metal part.
  • the capping metal portion may be formed using a sputtering technique or by using an electron-beam evaporation method (eg, planetary e-beam evaporation) which rotates and vacuum-deposits the substrate 21.
  • the capping metal portion may include Ni, Pt, Ti, or Cr, and may be formed, for example, by depositing about 5 pairs of Ni / Pt or about 5 pairs of Ni / Ti.
  • the capping metal part may include TiW, W, or Mo.
  • the stress relaxation layer may be variously selected according to the metal material of the reflective layer and the capping metal part.
  • the stress relaxation layer when the reflective layer is Al or Al alloy, and the capping metal part includes W, TiW or Mo, the stress relaxation layer is a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr, or Cu, It may be a composite layer of Ni, Pt, Ti, Rh, Pd or Au.
  • the stress relaxation layer may be a single layer of Ag or Cu or a composite layer of Ni, Au, Cu or Ag.
  • the stress relaxation layer is a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or Cu, Ni, Pt , Ti, Rh, Pd, Cr or Au may be a composite layer.
  • the stress relaxation layer may be a single layer of Cu, Cr, Rh, Pd, TiW, Ti, or a composite layer of Ni, Au or Cu.
  • the anti-oxidation metal portion includes Au to prevent oxidation of the capping metal portion, and may be formed of, for example, Au / Ni or Au / Ti. Ti is preferred because of good adhesion of an oxide layer such as SiO 2.
  • the anti-oxidation metal portion may also be formed using an electron-beam evaporation method (eg, planetary e-beam evaporation) which sputters or rotates by tilting the substrate and vacuum evaporates.
  • the mesa may be disposed on the first conductivity-type semiconductor layer 21.
  • the mesa includes the active layer 25 and the second conductivity type semiconductor layer 27.
  • the active layer 25 is positioned between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27.
  • the reflective electrode structure 35 is positioned on the mesa.
  • the lower insulating layer 37 may be formed of an oxide film such as SiO 2, a nitride film such as SiNx, or an insulating film of MgF 2 using a technique such as chemical vapor deposition (CVD).
  • the lower insulating layer 37 may be formed to have a thickness of, for example, 4000 to 12000 ⁇ s.
  • the lower insulating layer 37 may be formed as a single layer, but is not limited thereto and may be formed as a multilayer.
  • the lower insulating layer 37 may be formed of a distributed Bragg reflector (DBR) in which the low refractive material layer and the high refractive material layer are alternately stacked.
  • DBR distributed Bragg reflector
  • an insulating reflective layer with high reflectance can be formed by stacking layers such as SiO2 / TiO2 or SiO2 / Nb2O5.
  • the lower insulating layer 37 may have openings 37a exposing the first conductivity type semiconductor layer 23 and openings 37b exposing the reflective electrode structure 35.
  • the openings 37b are located confined to the top of the mesa, in particular can be located on the connection of the mesa.
  • the current spreading layer 39 covers the mesa and the first conductivity type semiconductor layer 23.
  • the current spreading layer 39 has an opening located in the mesa upper region and exposing the reflective electrode structure 35.
  • the current spreading layer 39 may be in ohmic contact with the first conductivity type semiconductor layer 23 through the openings 37a of the lower insulating layer 37. Meanwhile, the current spreading layer 39 is insulated from the mesa and the reflective electrodes 35 by the lower insulating layer 37.
  • the opening of the current spreading layer 39 has a larger area than the opening 37b of the lower insulating layer 37 to prevent the current spreading layer 39 from connecting to the reflective electrode structures 35. Therefore, the opening sidewall of the current spreading layer 39 is located on the lower insulating layer 37.
  • the current spreading layer 39 is formed over almost the entire area of the substrate 21 except for the openings of the current spreading layer 39. Therefore, the current can be easily distributed through the current spreading layer 39.
  • the current spreading layer 39 may include an ohmic contact layer, a metal reflective layer, a diffusion barrier layer, and an antioxidant layer.
  • the current spreading layer 39 may be in ohmic contact with the first conductive semiconductor layer 23 by the ohmic contact layer.
  • Ti, Cr, Ni, or the like may be used as the ohmic contact layer.
  • the metal reflective layer reflects the light incident to the current dispersion layer to increase the reflectance of the light emitting diode. Al may be used as the metal reflective layer.
  • the diffusion barrier layer protects the metal reflective layer by preventing diffusion of metal atoms.
  • the diffusion barrier layer can prevent diffusion of metal atoms in the solder paste such as Sn.
  • the diffusion barrier layer may comprise Cr, Ti, Ni, Mo, TiW or W or a combination thereof. Mo, TiW and W may be formed in a single layer. Meanwhile, Cr, Ti, and Ni may be formed in pairs. In particular, the diffusion barrier layer may include at least two pairs of Ti / Ni or Ti / Cr. On the other hand, the antioxidant layer is formed to prevent the oxidation of the diffusion barrier layer, it may include Au.
  • the reflectance of the current spreading layer 39 may be 65 to 75%. Accordingly, in addition to the light reflection by the reflective electrode structure 35, the light reflection by the current spreading layer 39 can be obtained, and therefore, the light traveling through the mesa sidewall and the first conductivity-type semiconductor layer 23. Can be reflected.
  • the current spreading layer 39 may further include an adhesive layer positioned on the antioxidant layer.
  • the adhesive layer may comprise Ti, Cr, Ni or Ta.
  • the adhesive layer may be used to improve the adhesion between the current spreading layer 39 and the upper insulating layer 41 and may be omitted.
  • the current spreading layer 39 may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.
  • the diffusion barrier reinforcement layer 40 is spaced apart from the current spreading layer 39.
  • the diffusion barrier reinforcing layer 40 may be located in the opening 39a of the current spreading layer 39 and in the opening 37b of the lower insulating layer 37.
  • the upper insulating layer 41 is disposed on the current spreading layer 39.
  • the upper insulating layer 41 exposes the current spreading layer 39 to define the first electrode pad region 43a, and the reflective electrode structure 35 is exposed to expose the second electrode pad region 43b.
  • the opening 41a may have an elongated shape in a direction perpendicular to the branch portions of the mesa.
  • the opening 41b of the upper insulating layer 41 has a smaller area than the opening 39a of the current spreading layer 39, and thus the upper insulating layer 41 can cover the sidewall of the opening 39a. have.
  • the opening 41b exposes the diffusion barrier reinforcement layer 40.
  • the reflective electrode structure 35 may be sealed by the upper insulating layer 41 and the diffusion barrier reinforcing layer 40.
  • the upper insulating layer 41 may be formed in the chip isolation region to cover the side surface of the first conductivity-type semiconductor layer 23. Accordingly, it is possible to prevent moisture or the like from penetrating through the upper and lower interfaces of the first conductivity type semiconductor layer 23.
  • the upper insulating layer 41 may be formed of a silicon nitride film to prevent diffusion of metal elements of the solder paste, and may be formed to a thickness of 1 ⁇ m or more and 2 ⁇ m or less. If it is less than 1 ⁇ m, it is difficult to prevent diffusion of metal elements of the solder paste.
  • a Sn diffusion barrier plating layer (not shown) is added on the first electrode pad region 43a and the second electrode pad region 43b by using an electroless plating technique such as electroless nickel immersion gold (ENIG). It can be formed as.
  • EIG electroless nickel immersion gold
  • the first electrode pad region 43a is electrically connected to the first conductive semiconductor layer 23 through the current spreading layer 39, and the second electrode pad region 43b is the diffusion preventing reinforcement layer 40 and the reflective electrode.
  • the structure 35 is electrically connected to the second conductivity-type semiconductor layer 27.
  • the first electrode pad region 43a and the second electrode pad region 43b are used to mount a light emitting diode to a printed circuit board through solder paste. Therefore, in order to prevent the first electrode pad region 43a and the second electrode pad region 43b from being shorted by the solder paste, the distance between the electrode pads is preferably about 300 ⁇ m or more.
  • FIG. 4 is a view showing a wavelength conversion portion formed on a light emitting diode according to a first embodiment of the present invention.
  • the wavelength converter 45 may cover the top surface of the light emitting diode 100 with a uniform thickness.
  • the wavelength converter 45 may cover the lower surface of the first conductivity type semiconductor layer 23 with a uniform thickness.
  • the wavelength converter 45 may cover the bottom surface of the substrate 21.
  • the wavelength converter 45 may be formed by coating a resin containing a phosphor on the light emitting diode 100 by using a printing technique, or by coating a phosphor powder on the substrate 21 by using an aerosol spraying device.
  • the wavelength converter 45 may extend from a lower surface of the first conductivity type semiconductor layer 23 to cover the side surface of the light emitting diode 100. Accordingly, wavelength conversion may be possible even for light emitted through the side surface of the light emitting diode 100.
  • the wavelength converter 45 may be used in a form in which a phosphor is supported on a resin, but is not limited thereto.
  • the phosphor may be supported on glass, or the phosphor may be used in a form in which a separate ceramic is supported.
  • the wavelength converter 45 may not be formed of the above-described resin, glass, or a separate ceramic, but may be made of only phosphor. Accordingly, the light absorption by the resin, glass, separate ceramics can be removed, the light extraction efficiency can be increased. In addition, since the thickness of the wavelength converter 45 may be reduced, the size of the light emitting diode to the backlight unit may be reduced, and light extraction efficiency may be further improved. In addition, the wavelength converter 45 may be formed of only a single crystal phosphor. In this case, in addition to the above-described effects, it is possible to adjust the light to be concentrated in the desired directivity angle, the degree of wavelength conversion by the phosphor may appear uniformly according to a specific direction.
  • the light emitting diode may further include an adhesive layer (not shown) between the wavelength converter 45 and the first conductivity type semiconductor layer 23.
  • the adhesive layer has strong adhesion with the wavelength converter 45 and the first conductivity type semiconductor layer 23, respectively. Through this, the separation of the wavelength converter 45 from the first conductivity type semiconductor layer 23 can be prevented.
  • FIG. 5 is a view showing a light emitting diode of a backlight unit according to a second embodiment of the present invention, (a) is a plan view, (b) is a cross-sectional view taken along the cut line AA, (c) is a cut along the cut line BB The cross section taken is shown.
  • the light emitting diode according to the present embodiment includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, a reflective electrode structure 25, and an ohmic contact structure ( 29), a lower insulating layer 37, a current spreading layer 39, a diffusion barrier reinforcing layer 40, and an upper insulating layer 41. While the light emitting diode according to the present embodiment is described, the same description as in the first embodiment is omitted.
  • An ohmic contact structure 29 is formed on the first conductive semiconductor layer 21.
  • the ohmic contact structure 29 may be formed between the mesas and at edges along the longitudinal direction of the mesas.
  • the ohmic contact structure 29 may be formed of a material in ohmic contact with the first conductivity-type semiconductor layer 21, and may include, for example, Ti / Al.
  • the ohmic contact structure may have a stacked structure of Ti / Al / Ti / Au.
  • the plurality of ohmic contact structures 29 are illustrated and described as being spaced apart from each other, one ohmic contact structure 29 connected to each other may be formed on the first conductivity type semiconductor layer 21. .
  • the openings 37a exposing the first conductive semiconductor layer 23 expose the ohmic contact structure 29 together with the first conductive semiconductor layer 23.
  • the ohmic contact structures 29 positioned at the edges of the substrate 21 of the ohmic contact structures 29 may be entirely exposed by the openings 37a.
  • an area exposed to the openings 37a to prevent the ohmic contact structure 29 and the reflective electrode structure 35 from being shorted. are located away from the areas between the openings 37a.
  • the current spreading layer 39 is electrically connected to the ohmic contact structure 29 and the first conductivity type semiconductor layer 23 through the openings 37a of the lower insulating layer 37.
  • the ohmic contact structures 29 spaced apart from each other may be electrically connected to each other through the current spreading layer 39.
  • the current spreading layer 39 can cover the sides of the ohmic contact structures 29, so that light incident on the sides of the ohmic contact structures 29 can be reflected at the current spreading layer 39. .
  • the current spreading layer 39 covers most of the region on the substrate 21, and thus, the resistance thereof is low so that current can be easily dispersed in the ohmic contact structures 29.
  • the diffusion barrier reinforcing layer 40 is spaced apart from the current spreading layer 39 and connects to the reflective electrode structures 35 exposed through the opening 37b.
  • the reflective electrode structures 35 spaced apart from each other by the diffusion barrier reinforcing layer 40 may be electrically connected to each other.
  • the diffusion barrier reinforcement layer 40 is insulated from the ohmic contact structures 29 by the lower insulating layer 37.
  • the current spreading layer 39 and the diffusion barrier reinforcing layer 40 may cover 80% or more of the total chip area.
  • FIG. 6 is a schematic block diagram of a backlight unit using an MJT LED according to a third embodiment of the present invention.
  • the term "MJT LED chip” means a multi-cell LED chip in which a plurality of light emitting cells are connected to each other by wirings in one LED chip.
  • the MJT LED chip may include N light emitting cells (N is a positive integer of 2 or more), and N may be variously set as necessary.
  • the forward voltage of each light emitting cell may be preferably 3V to 3.6V, but is not limited thereto. Therefore, the forward voltage of the MJT LED chip (or MJT LED) is proportional to the number of light emitting cells included in the MJT LED chip.
  • the MJT LED chip according to the present invention may be configured according to the specification of a driving power generation unit (for example, a DC converter) used in a backlight unit. It may be configured to have a driving voltage of 6 ⁇ 36V, but is not limited thereto.
  • the driving current of the MJT LED chip is very small compared to the conventional single-cell LED, for example, may be preferably between 20mA to 40mA, but is not limited thereto.
  • MJT LED refers to a light emitting device or LED package in which the MJT LED chip according to the present invention is mounted.
  • MJT LED module refers to a component combining one MJT LED and one corresponding optical member.
  • the corresponding optical member may be disposed directly on the MJT LED, or may be disposed on a printed circuit board on which the MJT LED is mounted. Regardless of the arrangement of the optical members, when one optical member corresponding to one MJT LED is referred to as a combination, it is referred to as an MJT LED module.
  • backlight module refers to a lighting module in which a plurality of MJT LEDs are disposed on a printed circuit board, and a plurality of optical members corresponding to each of the plurality of MJT LEDs are disposed. Therefore, the term “backlight module” may refer to a lighting module in which a plurality of MJT LED modules are mounted on a printed circuit board according to a predetermined rule.
  • the backlight module may be a direct type backlight module, but the present invention is not limited thereto, and the backlight module according to the present embodiment may be used as a light source for surface illumination in another embodiment. Therefore, it will be apparent to those skilled in the art that the device belongs to the scope of the present embodiment, as long as it includes the technical gist of the backlight module according to the present embodiment despite its name.
  • This embodiment is an invention devised in view of the device characteristics of the MJT LED in order to solve the problems of the prior art as described above. That is, the present embodiment, in order to solve the problems caused by the small voltage large current driving characteristics of the single-cell LED according to the prior art, the large voltage small current driving characteristics of the MJT LED (for example, a driving voltage of 6 ⁇ 36V And a driving current of 20 to 40 mA), and to solve the problems according to the prior art as described above by configuring the backlight module using the MJT LED.
  • the large voltage small current driving characteristics of the MJT LED for example, a driving voltage of 6 ⁇ 36V And a driving current of 20 to 40 mA
  • the MJT LED may include any number of light emitting cells, and has a characteristic that the forward voltage varies according to the number of light emitting cells included.
  • the MJT LED since the MJT LED includes a plurality of light emitting cells, a wide range can be irradiated compared to a conventional single-cell LED, and since it is composed of one MJT LED chip, it is easy to design and apply optical members thereof Do.
  • the present invention is configured to achieve the purpose of the present embodiment by configuring a backlight module using a plurality of MJT LED module, and configure the backlight unit to control each MJT LED constituting the backlight module independently. do.
  • the backlight unit 1000 may include a backlight control module 800 and a backlight module 700. Furthermore, the backlight unit according to the present invention may further include a field effect transistor (FET) (not shown) and a floodlight plate (not shown).
  • FET field effect transistor
  • the backlight control module 800 may include a driving power generator 810 and a backlight module 700 that generate / output DC driving power using an input power Vin input from the outside.
  • the driving control unit 820 controls an operation of each of the plurality of MJT LEDs 500 (on / off control and dimming control).
  • the driving power generator 810 is configured to generate a stable DC voltage such as 12V, 24V, 48V, and the like as a driving power to provide the plurality of MJT LEDs 500 constituting the backlight module 700.
  • the input power Vin supplied to the driving power generation unit 810 may be 220V or 110V commercial AC power.
  • the driving power generator 810 may be configured to be substantially the same as the driving power generator 810 of the related art shown in FIG. 1.
  • the backlight module 700 may include a plurality of MJT LEDs 500 and an optical member corresponding to each MJT LED 500 on a printed circuit board (not shown in FIG. 6). Can be arranged on a regular basis (eg, in the form of a matrix).
  • the printed circuit board 510 may include a plurality of blocks 510b.
  • Block 510b refers to a partial area of the printed circuit board including an area in which the plurality of MJT LEDs are mounted when the plurality of MJT LEDs are mounted on the printed circuit board.
  • one block 510b may include at least one MJT LED. More specifically, one block 510b may include one MJT LED.
  • the present invention is not limited thereto, and one block 510b may include a plurality of MJT LEDs.
  • the plurality of blocks 510b may be arranged in M in the horizontal direction and N in the vertical direction to form an MxN matrix array. As shown in FIG. 5, for example, 45 blocks 510b may constitute a 9 ⁇ 5 matrix arrangement.
  • the horizontal length L1 of each block 510b may be 60 mm or less.
  • the vertical length L2 of each of the blocks 510b may be 55 mm or less.
  • M MJT LEDs 500 are disposed in a horizontal direction, and N MJT LEDs 500 are disposed in a vertical direction to form an M ⁇ N matrix array. Assume that it is configured. At this time, each MJT LED may be located in a one-to-one correspondence with the blocks.
  • the MJT LED disposed at the top left is referred to as the 1-1 MJT LED 500_11 and the MJT LED disposed at the bottom right is referred to as the M-N MJT LED 500_MN.
  • the MJT LEDs 500 in the backlight module 700 of the embodiment shown in FIG. 6 with the prior art shown in FIG. 1 are not connected in series or in parallel or in parallel / parallel with each other. Rather, they are configured to be independently connected to the driving power generator 810 and the driving controller 820. That is, in the embodiment shown in FIG. 6, an anode end of each MJT LED 500 is independently connected to a driving power generation unit 810, and a cathode end of each MJT LED 500 is independently a driving control unit ( 820).
  • the blocks may be configured to be independently connected to the driving power generator 810 and the driving controller 820, respectively.
  • the driving controller 820 can independently control the operation of each of the plurality of MJT LEDs 500 constituting the backlight module 700. More specifically, the driving controller 820 according to the present exemplary embodiment is configured to control the dimming level of a specific MJT LED among the plurality of MJT LEDs 500 according to the dimming signal Dim. When each MJT LED and each block correspond one to one, the driving controller 820 may independently control the operation of each of the plurality of blocks.
  • the driving controller 820 includes a PWM control means (not shown), and controls the driving power supplied to a specific MJT LED, which is a dimming control target, of the MJT LEDs 500 to control a pulse width modulation (PWM). Thereby performing dimming control.
  • PWM pulse width modulation
  • each of the plurality of MJT LEDs 500 may independently drive each of the driving power generators 810. It is connected to and configured to receive driving power independently. Therefore, dimming control by such a PWM control method becomes possible.
  • the driving controller 820 may control the duty ratio of the driving power to 0 to 100%.
  • the driving controller 820 may generate a predetermined duty ratio (eg, 60%) based on the generated driving power according to the dimming signal Dim. ) And dimming control of the 1-1 MJT LED 500_11 may be performed by providing the pulse width modulated driving power to the 1-1 MJT LED 500_11. At this time, other MJT LEDs other than the 1-1 MJT LED 500_11 may be supplied with driving power having a duty ratio of 100% that is not pulse width modulated.
  • a predetermined duty ratio eg, 60%
  • a normal duty ratio duty ratio, for example, 80% has a default when there is no separate dimming control
  • the driving power source described above may be a DC driving voltage.
  • the PWM control means itself for PWM control of the driving power source adopts a well-known technique, and further description thereof will be omitted.
  • the driving control unit 820 includes a driving current detecting means (not shown) and a driving current control means (not shown), which is a dimming control target of the MJT LEDs 500. It can be configured to perform dimming control by controlling the drive current supplied to a particular MJT LED.
  • each of the plurality of MJT LEDs 500 is independently connected to the driving controller 820. . Therefore, dimming control of the driving current control method for each MJT LED can be performed.
  • the driving current detecting means and the driving current controlling means included in the driving controller 820 correspond to each of the MJT LEDs 500 in a one-to-one manner. Therefore, as described above, when the backlight module 700 includes the M ⁇ N MJT LEDs 500, the MxN driving current detecting means and the driving current controlling means are included in the driving controller 820.
  • the driving controller 820 detects a driving current currently flowing through the MN MJT LED 500_MN by using a driving current detecting means, and dimming signal. Dimming control for the MN MJT LED 500_MN is performed by changing the value of the driving current flowing through the MN MJT LED 500_MN according to (Dim) (for example, at 100% of the maximum driving current).
  • the driving controller 820 may control the driving current to 0 to 100%.
  • the MJT LEDs other than the MN MJT LED 500_MN may flow normal driving currents (ie, 80% of the maximum driving current, which is basically set when there is no dimming control), and thus, the MN MJT Local dimming for only the LED 500_MN is possible.
  • dimming control at the same dimming level and / or at different dimming levels for each MJT LED is possible through simultaneous drive current control for a plurality of MJT LEDs.
  • each of the MJT LEDs 500 does not need to be independently supplied with driving power, the anode end of each of the MJT LEDs 500 is different from the embodiment shown in FIG. 6.
  • Each of the driving power lines connected to the generation unit 810 may be configured to be connected in parallel.
  • the driving current detecting means and the driving current controlling means themselves adopt well-known techniques, and thus detailed descriptions thereof will be omitted.
  • the driving controller 820 of the present embodiment may include a plurality of switch controllers (not shown).
  • the switch controller may be located between the plurality of MJT LEDs. Specifically, the switch controller may be located between one MJT LED and an adjacent MJT LED. More specifically, the switch controller may be located between one MJT LED and the other MJT LEDs. That is, the switch controller may be located between one MJT LED and the other MxN-1 MJT LEDs among the MxN MJT LEDs, which corresponds to all MJT LEDs included in the backlight module 700 as well as the one MJT LED. can do.
  • Each switch controller can electrically connect two MJT LEDs connected by the switch controller, and can electrically insulate the two MJT LEDs. Therefore, a plurality of MJT LEDs may be connected in series and / or in parallel through a switch controller. Accordingly, the desired backlight module 700 structure can be easily implemented.
  • the backlight unit according to the present invention may further include a FET 511.
  • the FET controller 512 for controlling the FET 511 may also be included.
  • the FET control unit (drive IC) 512 senses the set voltage and controls the on or off of the FET 511.
  • the set voltage may be a voltage applied to a resistor (not shown) connected to one terminal of the FET 511.
  • the FET 511 When the FET 511 is on, no current is applied to the MJT LED. If the FET 511 is on, the current may be applied to the MJT LED.
  • the FET may be located on the bottom surface of the printed circuit board, and specifically, may be positioned adjacent to each MJT LED underneath.
  • the FETs 511 may be arranged identically to the arrangement of the MJT LEDs.
  • the present invention is not limited thereto, and the arrangement of the MJT LEDs and the arrangement of FETs may be different.
  • the FET controller 512 may be located on the bottom surface of the printed circuit board, but is not limited thereto.
  • FET 511 may be connected to the MJT LEDs.
  • the number of MJT LEDs and the number of FETs 511 are the same, and the MJT LEDs and the FETs 511 may be connected one to one.
  • MJT LED according to the present invention is capable of driving a large voltage, small current.
  • the FET 511 used in the present invention can be smaller in size than the conventional FET 511. Accordingly, since a printed circuit board having a size smaller than that of the conventional printed circuit board can be used, the backlight module can be miniaturized and manufacturing cost can be reduced.
  • the FET 511 can be miniaturized, unlike a conventional backlight unit in which the FET controller 512 and the FET 511 are spaced apart from each other, at least a part of the FET 511 is included in the FET controller 512. It may be.
  • the FET controller 512 may include all of the FETs 511 used in the backlight unit. Accordingly, since the number of FETs 511 that are not included in the FET controller 512 in the FET 511 may be reduced or not present, the backlight module may be miniaturized and manufacturing costs may be reduced. . For example, when there are 640 MJT LEDs, the number of FETs not included in the FET control unit 512 may be used in fewer than 640. Accordingly, the size of the printed circuit board can be reduced, for example, can be reduced by more than 70%.
  • the backlight unit according to the present embodiment may further include a floodlight plate (not shown).
  • the floodlight plate may be located above the backlight module 700.
  • the floodlight plate may be positioned above the printed circuit board 510 of the backlight module 700.
  • the floodlight plate may serve to diffuse light emitted from the MJT LED of the backlight module 700.
  • the distance between the bottom surface of the floodlight plate and the top surface of the printed circuit board may be 18 mm or more.
  • FIG. 7 is a schematic cross-sectional view for explaining the MJT LED module according to an embodiment of the present invention
  • Figure 8 is a perspective view for explaining the MJT LED used in the MJT LED module.
  • a detailed configuration of the MJT LED 100 and the MJT LED module according to the present invention will be described with reference to FIGS. 7 and 8.
  • the MJT LED module includes an MJT LED 100 and an optical member 530.
  • the MJT LED 500 is mounted on the printed circuit board 510, and the corresponding optical member 530 is mounted on the printed circuit board 510 at a position where the corresponding optical member 530 is matched with the MJT LED 500.
  • each block of the printed circuit board 510 may include one optical member.
  • the optical member 530 may be directly connected to the MJT LED 100.
  • the optical member 530 may be formed by molding a resin on the MJT LED.
  • the backlight module 500 may be configured as described above.
  • the printed circuit board 510 includes conductive land patterns on which upper surfaces of the MJT LEDs 500 are bonded.
  • the printed circuit board 510 may include a reflective film on an upper surface thereof.
  • the printed circuit board 510 may be a metal-core PCB (MCPCB) based on a metal having good thermal conductivity.
  • the printed circuit board 510 may be based on an insulating substrate material such as FR4.
  • a heat sink may be disposed under the printed circuit board 510 to dissipate heat generated by the MJT LED 100.
  • the MJT LED 100 includes a housing 521 and a wavelength conversion layer 525 covering the MJT LED chip 523 and the MJT LED chip 523 mounted on the housing 521. ) May be included. MJT LED 500 also includes lead terminals (not shown) supported in housing 521.
  • the housing 521 constituting the package body may be made by injection molding a plastic resin such as PA or PPA.
  • the housing 521 may be molded to support the lead terminals by an injection molding process, and may also have a cavity 521a for mounting the MJT LED chip 523.
  • the cavity 521a defines the light exit area of the MJT LED 500.
  • the lead terminals are spaced apart from each other in the housing 521 and extend outside the housing 521 to be bonded to land patterns on the printed circuit board 510.
  • the MJT LED chip 123 is mounted on the bottom of the cavity 521a and electrically connected to the lead terminals.
  • the MJT LED chip 523 may be a gallium nitride-based MJT LED emitting ultraviolet or blue light. Detailed configuration of the MJT LED chip 523 according to the present embodiment will be described later.
  • the wavelength conversion layer 125 covers the MJT LED chip 123.
  • the wavelength conversion layer 525 may be formed by mounting the MJT LED chip 523 and then filling the cavity 521a with a molding resin containing a phosphor.
  • the wavelength conversion layer 525 may fill the cavity 521a of the housing 121 and the upper surface may be substantially flat or convex.
  • a molding resin having an optical member shape may be further formed on the wavelength conversion layer 125.
  • the MJT LED chip 523 having the conformal phosphor coating layer formed thereon may be mounted on the housing 521. That is, the conformal coating layer of the phosphor may be applied on the MJT LED chip 523, and the MJT LED chip 523 having the phosphor coating layer may be mounted on the housing 521.
  • the MJT LED chip 523 having a conformal coating layer may be molded by a transparent resin. Furthermore, this molding resin can have an optical member shape, and thus can function as a primary optical member.
  • the wavelength conversion layer 525 converts the light emitted from the MJT LED chip 523 to implement mixed color light, for example, white light.
  • the wavelength conversion layer 525 may include a KSF-based and / or UCD-based phosphor. Therefore, the light emitted from the MJT LED chip 523 and transmitted through the wavelength conversion layer 525 may have an NTSC color gamut of 70% or more.
  • the MJT LED 500 is designed to have a light directivity distribution of a mirror symmetrical structure, and in particular, may be designed to have a light directivity distribution of a rotationally symmetrical structure.
  • the axis of the MJT LED toward the center of the light directing distribution is defined as the optical axis (L). That is, the MJT LED 500 is designed to have a light directivity distribution that is symmetrical about the optical axis L.
  • the cavity 521a of the housing 521 may be formed to have a mirror symmetrical structure, and the optical axis L may be defined as a straight line passing through the center of the cavity 521a.
  • the optical member 530 is configured to include a light incident surface that receives light from the MJT LED 500 and a light emitting surface that emits light at a light directing angle wider than the light directing angle of the MJT LED 500. It evenly distributes the light emitted from).
  • FIG. 11 is a plan view illustrating a light emitting diode of a backlight unit according to a third embodiment of the present invention.
  • 12 is a cross-sectional view taken along line B1-B2 of FIG. 11
  • FIG. 13 is a cross-sectional view taken along line C1-C2 of FIG. 11
  • FIG. 14 is a cross-sectional view taken along line D1-D2 of FIG. 11.
  • FIG. 15 is a cross-sectional view taken along the line E1-E2 of FIG. 11.
  • 16 is an equivalent circuit diagram of light emitting cells modeled according to a third exemplary embodiment of the present invention.
  • the light emitting diode may include a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a lower electrode, a cell region, a first interlayer insulating layer, an upper electrode, a second interlayer insulating layer, and a first layer.
  • a pad and a second pad may be included in the light emitting diode according to the present embodiment.
  • the substrate 101 may have a material of sapphire, silicon carbide, or GaN, and any substrate may be used as long as it can induce growth of a thin film to be formed.
  • the first semiconductor layer 110 may have an n-type conductivity.
  • the active layer 120 may have a multi-quantum well structure, and the second semiconductor layer 130 is formed on the active layer 120.
  • the second semiconductor layer 130 has a p-type conductivity.
  • a buffer layer (not shown) may be further formed between the substrate 101 and the first semiconductor layer 110 to facilitate single crystal growth of the first semiconductor layer 110.
  • the lower electrodes 151, 152, 153, and 154 are disposed on the second semiconductor layer 130.
  • a plurality of cell regions 161, 162, 163, and 164 may be defined by forming the lower electrodes 151, 152, 153, and 154.
  • the lower electrodes 151, 152, 153, and 154 may be applicable to any metal that performs ohmic contact with the second semiconductor layer 130.
  • the lower electrodes 151, 152, 153, and 154 may include Ni, Cr, or Ti, and may be formed of a composite metal layer of Ti / Al / Ni / Au.
  • the lower electrodes 151, 152, 153, and 154 may have a thickness in the range of 2000 ⁇ s to 10000 ⁇ s. If the thickness of the lower electrodes 151, 152, 153, and 154 is less than 2000 ⁇ s, the reflection of light from the lower electrodes 151, 152, 153, and 154 toward the substrate 101 may not be smooth, and the lower electrode 151 may have a thin film form. , 152, 153 and 154 leaks of light. In addition, when the thickness of the lower electrodes 151, 152, 153, and 154 exceeds 10000 ⁇ s, excessive time is consumed in the process of forming the lower electrodes such as thermal deposition.
  • the lower electrodes 151, 152, 153, and 154 may have an inclination angle b of 10 degrees to 45 degrees with respect to the surface of the second semiconductor layer 130.
  • the inclination angles b of the lower electrodes 151, 152, 153 and 154 are less than 10 degrees, the efficiency of reflection of light is reduced due to the very gentle inclination.
  • the uniformity of the thickness on the lower electrode surface cannot be secured due to the low inclination angle. If the inclination angle b of the lower electrodes 151, 152, 153, and 154 exceeds 45 degrees, cracks may occur in a later formed film due to the high inclination angle.
  • the region in which the lower electrodes 151, 152, 153, and 154 are formed defines four cell regions 161, 162, 163, and 164.
  • the second semiconductor layer 130 is exposed in the space between the cell regions 161, 162, 163, and 164.
  • the number of cell regions 161, 162, 163, and 164 may be formed corresponding to the number of light emitting cells included in the MJT LED to be formed. Therefore, the number of cell regions can be variously changed.
  • the four cell regions 161, 162, 163, and 164 are electrically completely separated from each other. Accordingly, independent first semiconductor layers 111, 112, 113, and 114, active layers 121, 122, 123, and 124, and second semiconductor layers 131, 132 for each of the cell regions 161, 162, 163, and 164. , 133, 134 and lower electrodes 151, 152, 153, and 154 are formed. Accordingly, the first lower electrode 151 is exposed on the first cell region 161, and the first semiconductor layer 111 is exposed through the via hole 140. In addition, the second lower electrode 152 is exposed on the second cell region 162, and the first semiconductor layer 112 is exposed through the via hole 140. Similarly, the third lower electrode 153 and the first semiconductor layer 113 are exposed on the third cell region 163, and the fourth lower electrode 154 and the first semiconductor layer 114 are exposed on the fourth cell region 164. ) Is exposed.
  • the light emitting cell is formed by stacking the first semiconductor layers 111, 112, 113, and 114, the active layers 121, 122, 123, and 124, and the second semiconductor layers 131, 132, 133, and 134. Refers to the structure. Therefore, one light emitting cell is formed in one cell area.
  • first semiconductor layers 111, 112, 113, and 114 have an n-type conductivity
  • second semiconductor layers 131, 132, 133, and 134 are modeled as having a p-type conductivity
  • the lower electrodes 151, 152, 153, and 154 formed on the second semiconductor layers 131, 132, 133, and 134 may be referred to as anode electrodes of the light emitting cells.
  • the first interlayer insulating layer 170 includes upper surfaces of the lower electrodes 151, 152, 153, and 154, first semiconductor layers 111, 112, 113, and 114, active layers 121, 122, 123, and 124, and a second layer.
  • the semiconductor layers 131, 132, 133, and 134 are disposed to cover side surfaces thereof. A portion of the first semiconductor layers 111, 112, 113, and 114 and the lower electrodes 151, 152, 153, and 154 are exposed.
  • the first cell region 161 two preformed via holes are opened to expose the first semiconductor layer 111, and a part of the first lower electrode 151 formed on the preformed second semiconductor layer 131. Is exposed.
  • the first semiconductor layer 112 exposed through the pre-formed via hole is exposed, and the second lower electrode 152 of the second lower electrode 152 is etched by etching the portion of the first interlayer insulating layer 170. Some are exposed.
  • the first semiconductor layer 113 is exposed through the via hole in the third cell region 163, and a part of the third lower electrode 153 is exposed through etching of a portion of the first interlayer insulating layer 170.
  • the fourth cell region 164 the first semiconductor layer 114 is exposed through the via hole, and a portion of the fourth lower electrode 154 is exposed through etching of a portion of the first interlayer insulating layer 170.
  • the first interlayer insulating layer 170 is formed on the entire surface of the substrate 101, and the first semiconductor layer 111, 112, in the via hole is formed for each cell region 161, 162, 163, and 164 through selective etching. A portion of the lower electrodes 151, 152, 153 and 154 on the 113 and 114 and the second semiconductor layers 131, 132, 133 and 134 are exposed. The remaining area is shielded by the first interlayer insulating film 170.
  • the first interlayer insulating layer 170 may be formed of an insulating material having a predetermined light transmittance.
  • the first interlayer insulating layer 170 may include SiO 2.
  • the first interlayer insulating layer 170 may have a thickness of 2000 ⁇ to 20000 ⁇ .
  • the thickness of the first interlayer insulating film 170 is less than 2000 GPa, it is difficult to ensure insulation characteristics due to the low thickness.
  • the first interlayer insulating layer 170 is formed on the sidewalls of the via hole 140 or the mesa region, since the first interlayer insulating layer 170 has a predetermined slope, dielectric breakdown of the first interlayer insulating layer 170 having a low thickness may occur.
  • the photoresist pattern serving as an etching mask may also be removed in the process of selectively etching the first interlayer insulating layer 170. Therefore, a process error may occur in which an etching at an unwanted site may be performed.
  • the first interlayer insulating layer 170 may have an inclination angle of 10 degrees to 60 degrees with respect to the exposed lower electrode surface.
  • the inclination angle of the first interlayer insulating layer 170 is less than 10 degrees, an area of the exposed lower electrode surface is reduced, or a substantial thickness of the first interlayer insulating layer 170 is reduced, thereby making it difficult to secure insulation characteristics. . That is, in the case of the first interlayer insulating layer 170, the lower electrode is electrically insulated from another conductive layer formed on the upper layer. Therefore, the first interlayer insulating film 170 should have a sufficient thickness, and the lower electrode should be exposed with a certain area for other electrical connection. If the first interlayer insulating film 170 has a very low inclination, the area of the lower electrode exposed to implement the first interlayer insulating film 170 of a constant thickness should be reduced. In addition, when the area of the exposed lower electrode is to be secured to a predetermined value or more, insulation breakdown may occur due to the low thickness of the first interlayer insulating layer 170.
  • the inclination angle of the first interlayer insulating film 170 exceeds 60 degrees, when another film quality is formed on the first interlayer insulating film 170, the quality of the film may be deteriorated due to the inclination angle. Is generated.
  • the upper electrodes 181, 182, 183, and 184 are formed by dividing into four regions.
  • the first upper electrode 181 is formed over a portion of the first cell region 161 and the second cell region 162.
  • the second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163.
  • the third upper electrode 183 is formed over the portion of the third cell region 163 and the portion of the fourth cell region 164
  • the fourth upper electrode 184 is formed on the portion of the fourth cell region 164. Is formed.
  • each of the upper electrodes 181, 182, 183, and 184 is formed by shielding spaces between adjacent cell regions.
  • the upper electrodes 181, 182, 183, and 184 may cover at least 30%, further at least 50%, or at least 90% of the space between the cell regions. However, since the upper electrodes 181, 182, 183, and 184 are spaced apart from each other, the upper electrodes 181, 182, 183, and 184 cover less than 100% of the area between the light emitting diodes.
  • the entirety of the upper electrodes 181, 182, 183, and 184 may occupy at least 30%, further, at least 50%, or at least 90% of the total area of the MJT LED.
  • the upper electrodes 181, 182, 183, and 184 are spaced apart from each other, thus occupying less than 100% of the total area of the MJT LED.
  • the upper electrodes 181, 182, 183, and 184 have a plate or sheet shape having a width to width ratio in a range of 1: 3 to 3: 1.
  • at least one of the upper electrodes 181, 182, 183, and 184 has a larger width or width than that of the corresponding light emitting cell (cell area).
  • the first upper electrode 181 is formed on the first interlayer insulating layer 170 of the first cell region 161 and is formed on the first semiconductor layer 111 opened through the via hole. In addition, the first upper electrode 181 exposes a portion of the first lower electrode 151 of the first cell region 161 and is disposed on the exposed second lower electrode 152 of the second cell region 162. Is formed.
  • the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole in the second cell region 162 while being physically separated from the first upper electrode 181.
  • the region is formed on the first interlayer insulating film 170.
  • the first upper electrode 181 electrically connects the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162.
  • the second lower electrode 152 on the second cell region 162 is electrically shorted as a whole in one cell region despite the presence of the via hole. Therefore, the first semiconductor layer 111 of the first cell region 161 is electrically connected to the second semiconductor layer 132 of the second cell region 162 through the second lower electrode 152.
  • the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162 and extends to the third lower electrode 153 of the third cell region 163. It is formed.
  • the third upper electrode 183 physically separated from the second upper electrode 182 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163.
  • the second upper electrode 182 is electrically connected to the first semiconductor layer 112 exposed through the via hole of the second cell region 162 and the third lower electrode 153 of the third cell region 163. Electrically connected. Therefore, the first semiconductor layer 112 of the second cell region 162 may maintain the equipotential with the second semiconductor layer 133 of the third cell region 163.
  • the third upper electrode 183 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163 and extends to the fourth lower electrode 154 of the fourth cell region 164. It is formed. Therefore, the first semiconductor layer 113 of the third cell region 163 and the second semiconductor layer 134 of the fourth cell region 164 are electrically connected to each other.
  • the fourth upper electrode 184 which is physically separated from the third upper electrode 183, is electrically connected to the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164.
  • the fourth upper electrode 184 is formed on the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164.
  • the first upper electrode 181 which is physically separated from the fourth upper electrode 184, is formed on the first semiconductor layer 111 exposed through the via hole on the first cell region 161. A portion of the first lower electrode 151 of the region 161 is exposed.
  • the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162 form an equipotential through the first upper electrode 181.
  • the first semiconductor layer 112 of the second cell region 162 and the second semiconductor layer 133 of the third cell region 163 form an equipotential through the second upper electrode 182.
  • the first semiconductor layer 113 of the third cell region 163 forms an equipotential with the second semiconductor layer 134 of the fourth cell region 164 through the third upper electrode 183.
  • the first lower electrode 151 electrically connected to the second semiconductor layer 131 is exposed.
  • the formation of the equipotential may affect the resistance of the upper electrodes 181, 182, 183, 184 and the contact resistances of the upper electrodes 181, 182, 183, 184 and the lower electrodes 151, 152, 153, 154.
  • the neglected state assumes an ideal electrical connection. Therefore, in actual operation of the device, a drop in voltage due to resistance components of the upper electrodes 181, 182, 183, and 184 and the lower electrodes 151, 152, 153, and 154, which is a kind of metal wiring, may occur.
  • the upper electrodes 181, 182, 183, and 184 may be formed of any material that can form ohmic contact with the first semiconductor layers 111, 112, 113, and 114.
  • any material capable of forming ohmic contact with the lower electrodes 151, 152, 153, and 154 may be used as the upper electrodes 181, 182, 183, and 184.
  • the upper electrodes 181, 182, 183, and 184 may include a metal layer including Ni, Cr, Ti, Rh, or Al, or a conductive oxide layer such as ITO as an ohmic contact layer.
  • 184 may include a reflective layer such as Al, Ag, Rh or Pt.
  • light generated in each of the active layers 121, 122, 123, and 124 is reflected toward the substrate 101 at the lower electrodes 151, 152, 153, and 154.
  • the light transmitted through the spaces between the cell areas 161, 162, 163, and 164 may shield the spaces between the cell areas 161, 162, 163, and 164. 183, 184.
  • the thickness of the upper electrodes 181, 182, 183, and 184 may range from 2000 kPa to 10000 kPa. When the thickness of the upper electrodes 181, 182, 183, and 184 is less than 2000 microns, reflection of light from the upper electrodes 181, 182, 183, and 184 toward the substrate 101 may not be smooth, and the upper electrode 181 may be a thin film. , 182, 183, 184 leaks of light. In addition, when the thickness of the upper electrodes 181, 182, 183, and 184 exceeds 10000 mm 3, excessive time is consumed in the upper electrode forming process such as thermal deposition.
  • the upper electrodes 181, 182, 183, and 184 may have an inclination angle of 10 degrees to 45 degrees with respect to the surface of the first interlayer insulating layer 170.
  • the inclination angles of the upper electrodes 181, 182, 183, and 184 are less than 10 degrees, the efficiency of reflection of light is reduced due to the very gentle inclination.
  • the uniformity of the thickness on the upper electrode surface cannot be secured due to the low inclination angle. If the inclination angles of the upper electrodes 181, 182, 183, and 184 exceed 45 degrees, cracks of the film formed later may occur due to the high inclination angle.
  • the adjustment of the inclination angle of the upper electrodes 181, 182, 183, and 184 with respect to the surface of the first interlayer insulating film 170 is performed by changing the angle of the substrate with respect to the arrangement of the substrate and the moving direction of the metal atoms in a process such as thermal deposition. It can be achieved through.
  • each upper electrode Reference numerals 181, 182, 183, and 184 may be modeled as the cathode electrodes of the light emitting cells, and may be simultaneously modeled as wirings connected to the lower electrodes, which are anode electrodes of the light emitting cells formed in the adjacent cell regions. That is, in the light emitting cell formed on the cell region, the upper electrode may be modeled as a wiring electrically connected to the anode electrode of the light emitting cell of the adjacent cell region while forming the cathode electrode.
  • the first upper electrode 181 to the third upper electrode 183 are formed over at least two cell regions. Thus, the space between adjacent cell regions is shielded. In the case of the upper electrodes, light that may leak between adjacent cell regions is reflected through the substrate and is electrically connected to the first semiconductor layer of each cell region. In addition, it is electrically connected to the second semiconductor layer in the adjacent cell region.
  • the first light emitting cell D1 is formed in the first cell region 161, the second light emitting cell D2 is in the second cell region 162, the third light emitting cell D3 is in the third cell region 163, and the fourth light emission is performed.
  • Cell D4 is formed in fourth cell region 164.
  • the first semiconductor layers 111, 112, 113, and 114 of the cell regions 161, 162, 163, and 164 are modeled as n-type semiconductors
  • the second semiconductor layers 131, 132, 133, and 134 are modeled as n-type semiconductors. Is modeled as a p-type semiconductor.
  • the first upper electrode 181 is electrically connected to the first semiconductor layer 111 of the first cell region 161, extends to the second cell region 162, and the second of the second cell region 162. It is electrically connected to the semiconductor layer 132. Therefore, the first upper electrode 181 is modeled as a wiring connecting the cathode terminal of the first light emitting cell D1 and the anode terminal of the second light emitting cell D2.
  • the second upper electrode 182 is modeled as a wiring connecting the cathode terminal of the second light emitting cell D2 and the anode terminal of the third light emitting cell D3, and the third upper electrode 183 is formed of the third light emitting cell D3. It is modeled as a wiring connecting the cathode terminal and the anode terminal of the fourth light emitting cell D4.
  • the fourth upper electrode 184 is modeled as a wiring forming a cathode terminal of the fourth light emitting cell D4.
  • the anode terminal of the first light emitting cell D1 and the cathode terminal of the fourth light emitting cell D4 are electrically open to an external power source, and the remaining light emitting cells D2 and D3 form a structure connected in series. If the light emitting operation is to be performed, the anode terminal of the first light emitting cell D1 should be connected to the positive power supply voltage V +, and the cathode terminal of the fourth light emitting cell D4 should be connected to the negative power supply voltage V ⁇ . Therefore, a light emitting cell connected to the positive power supply voltage V + may be referred to as an input light emitting cell, and a light emitting cell connected to the negative power supply voltage V ⁇ may be referred to as an output light emitting cell.
  • an upper electrode is formed to shield only a part of the cell region.
  • An upper electrode shielding between the electrically connected cell regions is formed in a cell region forming a connection relationship other than the above.
  • upper electrodes are shielded through the second interlayer insulating layer 190, and a portion of the first lower electrode 151 and a portion of the fourth upper electrode 184 are exposed. This means that only the anode terminal of the first light emitting cell D1 is exposed and only the cathode terminal of the fourth light emitting cell is exposed.
  • the first lower electrode 151 electrically connected to the second semiconductor layer 131 is opened.
  • the remaining area is covered with the second interlayer insulating film 190 over the second cell area 162.
  • the second cell region 162 and the third cell region 163 are completely covered with the second interlayer insulating layer 190.
  • the fourth upper electrode 184 of the fourth cell region 164 is exposed, and the first lower electrode 151 of the first cell region 161 is exposed.
  • Exposure of the fourth upper electrode 184 and the first lower electrode 151 is performed through selective etching of the second interlayer insulating layer 190.
  • the second interlayer insulating layer 190 is selected from an insulator capable of protecting a lower layer from an external environment.
  • SiN or the like which has insulation properties and can block changes in temperature or humidity may be used.
  • the thickness of the second interlayer insulating layer 190 may have a predetermined range. For example, when the second interlayer insulating layer 190 has SiN, the second interlayer insulating layer 190 may have a thickness of 2000 ⁇ s to 20,000 ⁇ s.
  • the thickness of the second interlayer insulating film 190 is less than 2000 GPa, it is difficult to ensure insulation characteristics due to the low thickness. In addition, the low thickness causes problems in protecting the underlying membrane from external moisture or chemical penetration.
  • the thickness of the second interlayer insulating layer 190 exceeds 20000 ⁇ , selective etching of the second interlayer insulating layer 190 through the formation of the photoresist pattern becomes difficult.
  • the second interlayer insulating layer 190 may have an inclination angle of about 10 degrees to about 60 degrees with respect to the surface of the fourth upper electrode 184 or the first lower electrode 151 exposed below.
  • the inclination angle of the second interlayer insulating layer 190 is less than 10 degrees, a substantial area of the exposed fourth upper electrode 184 or the first lower electrode 151 is reduced. In addition, if the area of the exposed portion is increased to secure a substantial area, there is a problem in that insulation characteristics cannot be secured due to the low inclination angle.
  • the quality of another film formed on the second interlayer insulating layer 190 may be degraded or cracks may occur due to the rapid profile or the inclination.
  • deterioration of characteristics occurs during the light emission operation due to the continuous supply of power.
  • the first pad 210 may be formed over the first cell region 161 and the second cell region 162. As a result, the first pad 210 achieves electrical contact with the first lower electrode 151 of the first cell region 161 exposed in FIG. 25.
  • the second pad 220 may be formed to be spaced apart from the first pad 210 by a predetermined distance, and may be formed over the third cell region 163 and the fourth cell region 164.
  • the second pad 220 is electrically connected to the fourth upper electrode 184 of the fourth cell region 164 exposed in FIG. 25.
  • a first pad 210 is formed over the first cell region 161 and the second cell region 162.
  • the first pad 210 is formed on the first lower electrode 151 exposed in the first cell region 161.
  • the second interlayer insulating layer 190 is formed. Therefore, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161 through the first lower electrode 151.
  • a first pad 210 is formed on the second cell region 162, and a second pad 220 is formed on the third cell region 163 to be spaced apart from the first pad 210. .
  • electrical contact with the lower electrode or the upper electrode of the first pad 210 or the second pad 220 is blocked.
  • a second pad 220 is formed over the third cell region 163 and the fourth cell region 164.
  • the fourth upper electrode 184 and the second pad 220 opened in the fourth cell region 164 are electrically connected to each other. Therefore, the second pad 220 is electrically connected to the first semiconductor layer 114 of the fourth cell region 164.
  • a second pad 220 is formed on the fourth cell region 164, and a first pad 210 is formed on the first cell region 161 to be spaced apart from the second pad 220.
  • the first pad 210 is formed on the first lower electrode 151 of the first cell region 161 and is electrically connected to the second semiconductor layer 131.
  • 17 is a perspective view taken along the line C2-C3 of FIG. 11.
  • the first semiconductor layer 113 of the third cell region 163 is electrically connected to the third upper electrode 183.
  • the third upper electrode 183 shields a space between the third cell region 163 and the fourth cell region 164 and is electrically connected to the fourth lower electrode 154 of the fourth cell region 164. do.
  • the first pad 210 and the second pad 220 are spaced apart from each other, and are formed on the second interlayer insulating layer 190.
  • the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161, and the second pad 220 is formed of the fourth cell region 164. 1 is electrically connected to the semiconductor layer 111.
  • the first pad 210 and the second pad 220 may have a first layer including Ti, Cr, or Ni and a second layer including Al, Cu, Ag, or Au thereon.
  • the first pad 210 and the second pad 220 may be formed using a lift-off process.
  • a pattern through a conventional photolithography process may be formed, and may be formed through dry etching or wet etching using the same as an etching mask.
  • the etchant during dry etching and wet etching may be set differently according to the material of the metal to be etched.
  • first pad 210 and the second pad 220 may be simultaneously formed through one process.
  • a pad barrier layer (not shown) of a conductive material may be formed on the first pad 210 or the second pad 220.
  • the pad barrier layer is provided to prevent diffusion of metal that may occur during bonding or soldering to the pads 210 and 220.
  • the pad barrier layer may be composed of Cr, Ni, Ti W, TiW, Mo, Pt or a composite layer thereof.
  • the first semiconductor layers 111, 112, 113, and 114 of each cell region are modeled as n-type semiconductors, and the second semiconductor layers 131, 132, 133, and 134 are p. Modeled as a semiconductor.
  • the first lower electrode 151 formed on the second semiconductor layer 131 of the first cell region 161 is modeled as an anode electrode of the first light emitting cell D1. Therefore, the first pad 210 may be modeled as a wire connected to the anode electrode of the first light emitting cell D1.
  • the fourth upper electrode 184 electrically connected to the first semiconductor layer 114 of the fourth cell region 164 is modeled as a cathode electrode of the fourth light emitting cell D4. Accordingly, the second pad 220 may be understood as a wire connected to the cathode electrode of the fourth light emitting cell D4.
  • the first lower electrode 152 of the first light emitting cell D1 connected to the positive power supply voltage V + is electrically connected to the first pad 210, and the negative is connected to the power supply voltage V ⁇ .
  • the fourth upper electrode 184 of the fourth light emitting cell D4 is electrically connected to the second pad 220.
  • four light emitting cells are formed to be separated from each other, and an anode terminal of one light emitting cell is electrically connected to a cathode terminal of another light emitting cell through a lower electrode and an upper electrode.
  • four light emitting cells are just one embodiment, and various numbers of light emitting cells may be formed according to the present invention.
  • FIG. 18 is a circuit diagram modeled to connect ten light emitting cells in series according to a third embodiment of the present invention.
  • ten cell regions 301 to 310 are defined.
  • the first semiconductor layer, the active layer, the second semiconductor layer, and the lower electrode in each cell region 301-310 are separated from other cell regions.
  • Each of the lower electrodes is formed on the second semiconductor layer to form anodes of the light emitting cells D1 to D10.
  • the first interlayer insulating layer and the upper electrodes are disposed on the lower electrodes.
  • the upper electrodes shield the spaced spaces between adjacent cell regions, and serve as a wiring to achieve electrical connection between anode electrodes of adjacent light emitting cells.
  • a second interlayer insulating film is formed on the upper electrodes, the lower electrode of the first light emitting cell D1, which is an input light emitting cell connected to the positive power supply voltage V + on the current path, is exposed and connected to the negative power supply voltage V ⁇ .
  • the upper electrode of the tenth light emitting cell D10 which is an output light emitting cell, is opened.
  • a first pad 320 is formed to connect the anode terminals of the first light emitting cells D1.
  • a second pad 330 is formed to connect the cathode terminals of the tenth light emitting cell D10.
  • connection of the light emitting cells may be configured in a structure of a series / parallel form.
  • 19 is a circuit diagram illustrating that light emitting cells are configured in a series / parallel form according to a third embodiment of the present invention.
  • a plurality of light emitting cells D1 to D8 have a series connection and have a structure in parallel with adjacent light emitting cells.
  • Each of the light emitting cells D1 to D8 is formed independently of each other through the definition of the cell regions 401 to 408.
  • the anode electrodes of the light emitting cells D1 to D8 are formed through the lower electrode.
  • wirings between the cathode electrodes of the light emitting cells D1 to D8 and the anode electrodes of the adjacent light emitting cells are formed through the formation of the upper electrode and appropriate wiring.
  • the lower electrode is formed on the second semiconductor layer, and the upper electrode is formed while shielding the spaced space between adjacent cell regions.
  • first pad 410 to which the positive power supply voltage V + is supplied is electrically connected to the lower electrode formed on the second semiconductor layer of the first light emitting cell D1 or the third light emitting cell D3.
  • the second pad 420 to which is supplied is electrically connected to an upper electrode which is a cathode terminal of the sixth light emitting cell D6 or the eighth light emitting cell D8.
  • the input light emitting cell corresponds to the first light emitting cell D1 and the third light emitting cell D3, and the output light emitting cell corresponds to the sixth light emitting cell D6 and the eighth light emitting cell D8.
  • each light emitting cell is reflected toward the substrate at the lower electrode and the upper electrode, and the flip chip type light emitting cells are electrically connected to each other through the wiring of the upper electrode on one substrate. Is connected.
  • the upper electrode is shielded from the outside through the second interlayer insulating film.
  • the first pad to which the positive power supply voltage is supplied is electrically connected to the lower electrode of the light emitting cell that is closest to the positive power supply voltage.
  • the second pad to which the negative power supply voltage is supplied is electrically connected to the upper electrode of the light emitting cell that is closest to the negative power supply voltage.
  • the flip chip type a plurality of chips are mounted on the sub-mount substrate, and the process inconvenience of implementing two terminals for an external power source through wiring arranged on the sub-mount substrate is solved.
  • the spacing between the cell regions can be shielded through the upper electrode to maximize the reflection of light toward the substrate.
  • the second interlayer insulating film protects a plurality of laminated structures disposed between the substrate and the second interlayer insulating film from external temperature and humidity. Therefore, a structure that can be directly mounted on a substrate without the intervention of a separate packaging means is realized.
  • FIG. 20 is a schematic plan view illustrating an MJT LED chip according to a fourth embodiment of the present invention
  • FIG. 21 illustrates a cutout BB of FIG. 20 to describe an MJT LED chip according to a fourth embodiment of the present invention.
  • the MJT LED chip 123 may include a growth substrate 51, light emitting cells S1 and S2, transparent electrode layers 61 and 62, an insulating layer 60b, and an insulating protective layer 63. ) And a wiring 65.
  • the MJT LED chip 123 may include a buffer layer 53.
  • the entire MJT LED chip 123 may include a current blocking layer 60a.
  • the growth substrate 51 may be an insulating or conductive substrate, for example, a sapphire substrate, a gallium nitride substrate, a silicon carbide (SiC) substrate, or a silicon substrate.
  • the growth substrate 51 may be a growth substrate having an uneven pattern on the top surface, such as a patterned sapphire substrate. The uneven pattern may effectively reflect light toward the growth substrate among the light emitted from the light emitting cells, thereby improving the light extraction efficiency.
  • the first light emitting cell S1 and the second light emitting cell S2 are spaced apart from each other on the single growth substrate 51.
  • Each of the first and second light emitting cells S1 and S2 is interposed between the lower semiconductor layer 55, the upper semiconductor layer 59 positioned on one region of the lower semiconductor layer, and the lower semiconductor layer and the upper semiconductor layer. It has a laminated structure 56 including an active layer 57.
  • the lower and upper semiconductor layers are described as being n-type and p-type, respectively, but vice versa.
  • the lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (Al, In, Ga) N.
  • the active layer 57 is composed of a composition element and a composition ratio so as to emit light of a desired wavelength such as ultraviolet or blue light, and the lower semiconductor layer 55 and the upper semiconductor layer 59 have a larger band gap than the active layer 57. Is formed.
  • the lower semiconductor layer 55 and / or the upper semiconductor layer 59 may be formed as a single layer, as shown, but may be formed in a multilayer structure.
  • the active layer 57 may have a single quantum well or multiple quantum well structures.
  • the first and second light emitting cells S1 and S2 may have an inclined side surface, and an inclination angle of the side surface may be, for example, within a range of 15 degrees to 80 degrees with respect to the upper surface of the growth substrate 51.
  • the active layer 57 and the upper semiconductor layer 59 are positioned on the lower semiconductor layer 55. At least a portion of the upper surface of the lower semiconductor layer 55 may be covered by the active layer 57, and the remaining portion may be exposed without being covered by the active layer 57.
  • the upper surface of the lower semiconductor layer 55 may include an exposed region R. As shown in FIG. The exposed region R is not covered by the active layer 57 and the upper semiconductor layer 59, and is a region where a portion of the upper surface of the lower semiconductor layer 55, specifically, the lower semiconductor layer 55 is exposed.
  • the exposed region R may be disposed in parallel with a side of the lower semiconductor layer 55 facing the adjacent light emitting cell.
  • the present invention is not limited thereto, and the active layer 57 and the upper semiconductor layer 59 may be surrounded by at least a portion thereof.
  • first light emitting cell S1 and the second light emitting cell S2 are similar as shown in FIG. 5.
  • first light emitting cell S1 and the second light emitting cell S2 may have the same gallium nitride-based semiconductor stacked structure, and may have inclined side surfaces of the same structure.
  • a buffer layer 53 may be interposed between the light emitting cells S1 and S2 and the growth substrate 51.
  • the buffer layer 53 is adopted to mitigate lattice mismatch between the growth substrate 51 and the lower semiconductor layer 55 to be formed thereon.
  • the transparent electrode layers 61 and 62 are positioned on the light emitting cells S1 and S2. That is, the first transparent electrode layer 61 is positioned on the first light emitting cell S1, and the second transparent electrode layer 62 is positioned on the second light emitting cell S2.
  • the transparent electrode layers 61 and 62 may be positioned on the upper surface of the upper semiconductor layer 59 to be connected to the upper semiconductor layer 59, and may have an area smaller than that of the upper semiconductor layer 59. That is, the transparent electrode layers 61 and 62 may be recessed from the edge of the upper semiconductor layer 59. Accordingly, it is possible to prevent current from being concentrated through the sidewalls of the light emitting cells S1 and S2 at the edges of the transparent electrode layers 61 and 62.
  • a portion of the first transparent electrode layer 61 may be connected to the second light emitting cell S2. Specifically, a part of the first transparent electrode layer 61 passes through the first light emitting cell S1 and the second light emitting cell S2 from the first light emitting cell S1, and lower part of the second light emitting cell S2. It may be located on the side of the semiconductor layer 55. Therefore, even when the wiring 65 is disconnected, current may flow through the first transparent electrode layer 61, thereby improving electrical stability of the MJT LED chip.
  • the first transparent electrode layer 61 may further extend to be positioned on the exposed region R of the upper surface of the lower semiconductor layer 55. The first transparent electrode layer 61 may be spaced apart from the active layer 57 and the upper semiconductor layer 59 of the second light emitting cell S2.
  • the insulating layer 60b covers a part of the side surface of the first light emitting cell S1. As shown in FIGS. 20 and 21, the insulating layer 60b may extend into an area between the first light emitting cell S1 and the second light emitting cell S2, and further, the second light emitting cell S2. A portion of the side surface of the lower semiconductor layer 55 may be covered.
  • the insulating layer 60b is formed of an insulating material, and in particular, may include a distributed Bragg reflector in which layers having different refractive indices are alternately stacked. However, it is not limited thereto. However, when the insulating layer 60b includes a distributed Bragg reflector having multiple layers, the occurrence of defects such as pinholes in the insulating layer 60b can be effectively suppressed.
  • the wiring 65 electrically connects the first light emitting cell S1 and the second light emitting cell S2.
  • the wiring 65 includes a first connecting portion 65p and a second connecting portion 65n.
  • the first connecting portion 65p is electrically connected to the first transparent electrode layer 61 on the first light emitting cell S1, and the second connecting portion 65n is connected to the lower semiconductor layer 55 of the second light emitting cell S2. Electrically connected.
  • the first connection part 65p may be disposed close to an edge of one side of the first light emitting cell S1, but is not limited thereto.
  • the first connection part 65p may be disposed in a central area of the first light emitting cell S1.
  • the second connector 65n may be electrically connected to the lower semiconductor layer 55 of the second light emitting cell S2.
  • the second connection part 65n may be electrically connected to the upper surface of the lower semiconductor layer 55 of the second light emitting cell S2 through the exposure area R.
  • the first transparent electrode layer 61 may be positioned between the second connection portion 65n and the lower semiconductor layer 55 of the second light emitting cell S2. In this case, the first transparent electrode layer 61 may be positioned on the side surface of the lower semiconductor layer 55 of the second light emitting cell S2, and may also be located in the exposed region R of the lower semiconductor layer 55. Can be.
  • the inclined side surface of the second light emitting cell S2 may be in contact with the inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2.
  • the second connector 65n may be in electrical contact with the inclined side surface of the lower semiconductor layer 55 while extending to both sides along the circumference of the second light emitting cell S2.
  • the first light emitting cell S1 and the second light emitting cell S2 are connected in series by the first and second connection parts 65p and 65n of the wiring 65.
  • the wiring 65 may contact the transparent electrode layers 61 and 62 in all regions overlapping the transparent electrode layers 61 and 62.
  • a portion of the insulating layer is located between the transparent electrode layer and the wiring, but in this embodiment, the wiring 65 and the transparent electrode layers 61 and 62 can directly contact without any insulating material therebetween.
  • the width of the portion of the first transparent electrode layer 61 positioned on the side surface of the lower semiconductor layer 55 of the second light emitting cell S2 is the second light emission of the wiring 65. It may be wider than the width of the portion located on the side of the lower semiconductor layer 55 of the cell (S2). Accordingly, since the current in the region where the side surface of the second light emitting cell S2 and the wiring 65 contact each other can be easily dispersed, the uniformity of emission of the MJT LED chip can be improved.
  • the width of the portion of the first transparent electrode layer 61 located between the first light emitting cell S1 and the second light emitting cell S2 is equal to the width of the first light emitting cell S1 and the second light emitting cell of the wiring 65. It may be wider than the width of the portion located between (S2).
  • the insulating protective layer 63 is etched using an etching solution such as hydrofluoric acid, the insulating layer 60b including the oxide film may be damaged by the etching solution. In this case, since the insulating layer 60b does not insulate the wiring 65 from the first light emitting cell S1, a short circuit may occur.
  • the first transparent electrode layer 61 is positioned on the insulating layer 60b and is disposed between the first light emitting cell S1 and the second light emitting cell S2 of the first transparent electrode layer 61. Since the width of the portion positioned is wider than the width of the portion positioned between the first light emitting cell S1 and the second light emitting cell S2 in the wiring 65, the insulating layer 60b under the transparent conductive layer 62. This can be protected from etching damage. Therefore, a short circuit by the wiring 65 is prevented.
  • first connection portion 65p and the second connection portion 65n of the wiring 65 are illustrated as connected to each other through two paths, but may be connected through one path.
  • the insulating layer 60b when the insulating layer 60b has a reflective characteristic like a distributed Bragg reflector, the insulating layer 60b is limited in the area substantially the same as the area of the wiring 65 in an area not more than twice the area of the wiring 65. It is desirable to.
  • the insulating layer 60b blocks the light emitted from the active layer 57 from being absorbed by the wiring 65, but if excessively wide, it can block the light from being emitted to the outside, so the area needs to be limited. have.
  • the insulating protective layer 63 may be located outside the wiring 65 region.
  • the insulating protection layer 63 covers the first and second light emitting cells S1 and S2 outside the wiring 65 region.
  • the insulating protective layer 63 may be formed of a silicon oxide film (SiO 2) or a silicon nitride film.
  • the insulating protective layer 63 has an opening that exposes the first transparent electrode layer 61 on the first light emitting cell S1 and the lower semiconductor layer of the second light emitting cell S2 together, and the wiring 65 is in this opening. Can be located.
  • the side surface of the insulating protective layer 63 and the side surface of the wiring 65 may face each other and may contact each other.
  • One side surface of the insulating protective layer 63 may be positioned on the exposed region R, and may be in contact with the side surface of the wiring 65.
  • the side surface of the insulating protective layer 63 and the side surface of the wiring 65 may be spaced apart from each other.
  • the second connecting portion 65n electrically contacts the upper surface of the lower semiconductor layer 55, that is, the surface that is not inclined
  • the thickness of the second connecting portion 65n disposed on the upper surface of the lower semiconductor layer 55. May be constant. Accordingly, the reliability of the wiring can be improved.
  • the insulating protective layer 63 contacts the wiring 65 on the side surface of the lower semiconductor layer 55 of the second light emitting cell S2 and the upper surface of the lower semiconductor layer 55 which is not inclined, the insulating protective layer 63 and the wiring The interface area of 65 may be substantially constant. Therefore, the defective rate of the MJT LED can be reduced.
  • the current blocking layer 60a and the insulating layer 60b may have the same material and the same structure, and thus may be formed together by the same process.
  • the wiring 65 is arrange
  • the present invention is not limited to two light emitting cells, and more light emitting cells are provided.
  • the wirings 65 may electrically connect the lower semiconductor layers 55 and the transparent electrode layers 61 of adjacent light emitting cells to form a series array of light emitting cells. A plurality of such arrays may be formed, and the plurality of arrays may be connected in reverse parallel to each other and may be driven by being connected to an AC power source.
  • a bridge rectifier (not shown) connected to the series array of light emitting cells may be formed, and the light emitting cells may be driven under an AC power supply by the bridge rectifier.
  • the bridge rectifier may be formed by connecting the light emitting cells having the same structure as the light emitting cells S1 and S2 using the wirings 65.
  • each MJT LED As the number of light emitting cells in each MJT LED increases, the area of each block of the printed circuit board may decrease. Accordingly, while the droop phenomenon is lowered by more light emitting cells, a backlight unit capable of implementing various light emitting arrangements may be provided by many MJT LEDs.
  • FIG. 22 is a schematic cross-sectional view for describing an MJT LED chip according to a fifth embodiment of the present invention.
  • the MJT LED chip of FIG. 22 is similar to the MJT LED chip described with reference to FIG. 20 except that the MJT LED chip further includes a current blocking layer 60a.
  • the current blocking layer 60a may be positioned on each of the light emitting cells S1 and S2, and is disposed between the transparent electrode layers 61 and 62 and the light emitting cells S1 and S2. Specifically, the current blocking layer 60a is positioned between the first light emitting cell S1 and the first transparent electrode layer 61 to separate a part of the first transparent electrode layer 61 from the first light emitting cell S1. Can be. Therefore, a part of the transparent electrode layers 61 and 62 is located on the current blocking layer 60a.
  • the current blocking layer 60a may be located near the edges of each of the light emitting cells S1 and S2, but is not limited thereto.
  • the current blocking layer 60a may be located in the center area of each of the light emitting cells S1 and S2.
  • the current density around the wiring 65 may be improved by the current blocking layer 60a, the current dispersion efficiency of the MJT LED chip may be improved.
  • the current blocking layer 60a is formed of an insulating material, and in particular, may include a distributed Bragg reflector in which layers having different refractive indices are alternately stacked.
  • the insulating layer 60b may be formed of the same structure and the same material as the current blocking layer 60a, but is not limited thereto.
  • the insulating layer 60b may be formed of a different material by a process different from that of the current blocking layer 60a.
  • the insulating layer 60b may be continuously connected to the current blocking layer 60a, but the present invention is not necessarily limited thereto.
  • the insulating layer 60b and the current blocking layer 60a may be spaced apart from each other.
  • the current blocking layer 60a may be formed by depositing an insulating material layer and patterning it using a photo and etching process. Alternatively, the current blocking layer 60a may be formed of a layer of insulating material using a lift off technique. In particular, the current blocking layer 60a may be formed of a distributed Bragg reflector in which layers having different refractive indices, for example, SiO 2 and TiO 2 are alternately stacked. As illustrated in FIG. 13, the current blocking layer 60a and the insulating layer 60b may be connected to each other, but the present invention is not limited thereto.
  • the current blocking layer 60a may be positioned over the entire region where the wiring 65 and the transparent electrode layers 61 and 62 overlap, and further, the entire region in which the wiring 65 and the first light emitting cell S1 overlap.
  • the current blocking layer 60a and the insulating layer 60b may be disposed on the substrate.
  • the current blocking layer 60a has a reflective characteristic such as a distributed Bragg reflector
  • the current blocking layer 60a is located within a region almost equal to that of the wiring 65 in an area not more than twice the area of the wiring 65. It is desirable to.
  • the current blocking layer 60a blocks the light emitted from the active layer 57 from being absorbed by the wiring 65, but when excessively wide, the current blocking layer 60a can block the light from being emitted to the outside, so the area must be limited. There is.
  • the transparent electrode layers 61 and 62 are connected to the upper semiconductor layer 59, and some of the transparent electrode layers 61 and 62 are positioned on the current blocking layer 60a and the insulating layer 60b. do.
  • the first connecting portion 65p of the wiring 65 may be connected to the first transparent electrode layer 61 in the upper region of the current blocking layer 60a.
  • FIG. 23 is a schematic diagram for comparing the conventional backlight unit (a) and the backlight unit (b) according to an embodiment of the present invention.
  • a conventional backlight unit (a) includes a plurality of LED chips having a single light emitting cell, and the plurality of LED chips are connected in series and / or in parallel to form at least one array 110a. And may be driven in units of each array 110a.
  • the backlight unit (b) according to an embodiment of the present invention may be driven independently without the MJT LEDs connected to each other in series or in parallel or in series / parallel.
  • the conventional backlight unit (a) has nine arrays (110a), while the backlight unit (b) of the present invention may include 45 blocks.
  • a conventional backlight unit of FIG. 23A is used as a comparative example, and the backlight unit of the present invention of FIG. 23B is an embodiment.
  • the backlight units of the comparative example and the example were all driven at a DC converter voltage of 24V, and the IC driving voltage was 3V.
  • the driving voltage of the single light emitting cell LED chip of the comparative example was 3.6V and the loss voltage of each array was 3V.
  • the driving voltage of one MJT LED of the embodiment was 3.3V
  • the loss voltage of each block 110b was 1.2V.
  • the backlight unit of the comparative example is driven at 0.4A, and the backlight unit of the embodiment may be driven at 0.075A. Therefore, the droop phenomenon occurring at high current can be reduced.
  • the driving power of the comparative example is 75.6W
  • the driving power of the embodiment is 70.87W
  • the loss power of the comparative example is 10.8W
  • the loss power of the embodiment was 4.05W
  • the driving efficiency calculated based on this is 85.7%, respectively.
  • Comparative Example Comparative Example
  • 94.2% Example. Therefore, it can be seen that the driving efficiency of the backlight unit according to the present invention is high.
  • FIG. 24 is a view illustrating a backlight module including a square block in which a lens for local dimming is formed in the MJT LED of the present invention.
  • FIG. 24A illustrates a backlight module in which a half width is formed as the width of the block
  • FIG. 24B is a view illustrating a backlight module in which the half width is larger than the width of the block.
  • FIG. 24C illustrates a backlight module having a half width smaller than a width of a block.
  • one MJT LED is disposed in one block of the display module, and a lens for local dimming may be applied to each MJT LED.
  • the lens is directly applied to the MJT LED, the illuminance of light through the lens is as shown in the right side of FIG. In this case, the half width of the illuminance of the light emitted from one block may be equal to the width of one block.
  • the half width of the light emitted from one block may be the diagonal length of the square-shaped block.
  • the minimum half width of the light emitted from one block is equal to the width of the square block. If, Can be.
  • the half width range of the light intensity to which the lens as the optical member is applied is Greater than or equal to, May be less than or equal to
  • the full width at half maximum is a range in consideration of the uniformity of the entire blocks.
  • the lens is formed directly on the wavelength conversion layer 125 included in the MJT LED, as shown in FIG. 4, and may be formed separately from the optical member 130 shown in FIG. 7. That is, in the embodiment of the present invention by using a lens formed directly on the MJT LED, the lens may be formed integrally with the MJT LED.
  • 25 is a view showing that the illumination intensity of the light emitted from the MJT LED in which the lens for local dimming is formed in each block is superimposed on the backlight module of the present invention.
  • the intensity of light emitted through the lens formed in each block is 100%.
  • the square shape has a half width equal to the diagonal length of the block. , The intensity of light emitted through each lens is more than 100%, and the half width is The light intensity may be in the range of 50% to 100%.
  • the uniformity of light in the entire block may be improved. Even when the uniformity may be about 50%.
  • the uniformity may be improved by applying an optical sheet to the backlight unit to improve the uniformity.
  • the uniformity of light in the entire block can be further improved by about 20-30%.
  • FIG. 26 illustrates a lens for local dimming formed in each block having a rectangular shape in the backlight module of the present invention.
  • Figure 26 (a) is the length of each side And Lens is applied to a backlight module having a rectangular block of It is a figure which shows that.
  • Figure 26 (b) is the diagonal length of the block so that the full width at half maximum can include one block It is a figure which shows that.
  • (C) of FIG. 26 illustrates a case where the half width is minimum in consideration of the uniformity of light. Can be.
  • the half width of the illuminance is Greater than or equal to May be less than or equal to
  • the length of each side of the block And is a size for setting the size of a block, but may be a distance between MJT LEDs included in each block. That is, the length of one side of the block Distance between the MJT LEDs , The length of the other side Distance between the MJT LEDs Can be.
  • FIG. 27 is a diagram for calculating a range of directivity angles of light emitted through a lens with respect to a half width of illuminance in the present invention.
  • FWHM full width at half maximum
  • OD diffusion surface
  • ⁇ angle of light emitted from the light source to the lens
  • the directivity angle when the lens is not applied is the half width of the MJT LED, and the directivity angle of the light when the lens is applied is set by the above description by setting the half width range in consideration of the uniformity of light. It can be expressed as Equation 2.
  • FIG. 28 is a graph showing the relationship between the full width at half maximum according to the distance change from the light source to the lens of the present invention.
  • the full width at half maximum according to the distance change from the light source to the lens using the relationship as described above is shown in Table 1, and can be displayed as a graph as shown in FIG.
  • the difference in illuminance of light may be shown in FIG. 33 (b).

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Abstract

L'invention concerne, selon un mode de réalisation, une unité de rétroéclairage comprenant : une base; et une pluralité de boîtiers de diodes électroluminescentes disposés sur la surface inférieure de la base, chaque boîtier de diode électroluminescente comprenant au moins une diode électroluminescente qui comprend : une couche à semi-conducteur de premier type conducteur; une structure mésa située sur la couche à semi-conducteur de premier type conducteur et comprenant une couche active et une couche à semiconducteur de deuxième type conducteur; une structure d'électrode réfléchissante située sur la structure mesa; une couche d'étalement de courant recouvrant la structure mesa et la couche à semi-conducteur de premier type conducteur, la couche d'étalement de courant ayant une première ouverture pour exposer la structure d'électrode réfléchissante et étant électriquement connectée à la couche à semi-conducteur de premier type conducteur et isolée de la structure d'électrode réfléchissante et de la structure mesa; et une couche isolante supérieure recouvrant la couche d'étalement de courant et la couche isolante supérieure ayant : une deuxième ouverture pour exposer la couche d'étalement de courant afin de limiter une première zone de plaquette d'électrode; et une troisième ouverture pour exposer une zone supérieure de la structure d'électrode réfléchissante exposée afin de limiter une seconde zone de plaquette d'électrode.
PCT/KR2016/006768 2015-06-26 2016-06-24 Unité de rétroéclairage utilisant une diode électroluminescente multi-cellule WO2016209025A2 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2017549369A JP2018528598A (ja) 2015-06-26 2016-06-24 マルチセル発光ダイオードを用いたバックライトユニット
DE212016000126.4U DE212016000126U1 (de) 2015-06-26 2016-06-24 Hintergrundbeleuchtungseinheit unter Verwendung von Mehrzellen-Leuchtdioden
EP16814738.7A EP3316244B1 (fr) 2015-06-26 2016-06-24 Unité de rétroéclairage utilisant une diode électroluminescente multi-cellule
CN201690000752.0U CN208990251U (zh) 2015-06-26 2016-06-24 利用多单元发光二极管的背光部件
US15/354,292 US9769897B2 (en) 2015-06-26 2016-11-17 Backlight unit using multi-cell light emitting diode
US15/678,739 US10091850B2 (en) 2015-06-26 2017-08-16 Backlight unit using multi-cell light emitting diode
US15/873,769 US10051705B2 (en) 2015-06-26 2018-01-17 Backlight unit using multi-cell light emitting diode

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
KR1020150091420A KR20170001436A (ko) 2015-06-26 2015-06-26 발광 다이오드 패키지를 포함하는 백라이트 유닛
KR10-2015-0091420 2015-06-26
KR10-2015-0095536 2015-07-03
KR20150095536 2015-07-03
KR10-2015-0101214 2015-07-16
KR1020150101214A KR102429939B1 (ko) 2015-07-16 2015-07-16 Mjt led를 이용한 백라이트 모듈 및 이를 포함하는 백라이트 유닛
KR10-2015-0103840 2015-07-22
KR1020150103840A KR102451722B1 (ko) 2015-07-03 2015-07-22 Mjt led를 이용한 백라이트 모듈 및 이를 포함하는 백라이트 유닛
KR10-2015-0108262 2015-07-30
KR1020150108262A KR102454170B1 (ko) 2015-07-30 2015-07-30 멀티셀 발광 다이오드를 이용한 백라이트 모듈을 포함하는 백라이트 유닛

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CN109494288A (zh) * 2018-11-05 2019-03-19 江门市中阳光电科技有限公司 发光装置
JP2019079979A (ja) * 2017-10-26 2019-05-23 豊田合成株式会社 半導体発光素子とその製造方法
US10418510B1 (en) * 2017-12-22 2019-09-17 Facebook Technologies, Llc Mesa shaped micro light emitting diode with electroless plated N-contact

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KR101142965B1 (ko) * 2010-09-24 2012-05-08 서울반도체 주식회사 웨이퍼 레벨 발광 다이오드 패키지 및 그것을 제조하는 방법
JP5777879B2 (ja) * 2010-12-27 2015-09-09 ローム株式会社 発光素子、発光素子ユニットおよび発光素子パッケージ
KR101314425B1 (ko) * 2012-03-09 2013-10-04 이동원 디밍 가능한 엘이디 조명장치
KR102061318B1 (ko) * 2012-10-08 2019-12-31 서울반도체 주식회사 Led 연속구동을 위한 led 구동장치 및 구동방법
KR20140117791A (ko) * 2013-03-27 2014-10-08 서울바이오시스 주식회사 발광 다이오드 및 그것을 제조하는 방법
KR102103882B1 (ko) * 2013-07-29 2020-04-24 서울바이오시스 주식회사 발광 다이오드 및 그것을 갖는 발광 다이오드 모듈
KR20150025797A (ko) * 2013-08-30 2015-03-11 엘지이노텍 주식회사 발광소자 패키지 및 이를 포함하는 차량용 조명 장치
KR101546929B1 (ko) * 2013-09-24 2015-08-25 서울바이오시스 주식회사 발광 다이오드 및 그것을 갖는 발광 다이오드 모듈

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019079979A (ja) * 2017-10-26 2019-05-23 豊田合成株式会社 半導体発光素子とその製造方法
US10418510B1 (en) * 2017-12-22 2019-09-17 Facebook Technologies, Llc Mesa shaped micro light emitting diode with electroless plated N-contact
CN109494288A (zh) * 2018-11-05 2019-03-19 江门市中阳光电科技有限公司 发光装置

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