WO2016202040A1 - 一种基于pcie子卡热插拔的方法及装置 - Google Patents

一种基于pcie子卡热插拔的方法及装置 Download PDF

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WO2016202040A1
WO2016202040A1 PCT/CN2016/077846 CN2016077846W WO2016202040A1 WO 2016202040 A1 WO2016202040 A1 WO 2016202040A1 CN 2016077846 W CN2016077846 W CN 2016077846W WO 2016202040 A1 WO2016202040 A1 WO 2016202040A1
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daughter card
pcie
interrupt
pcie daughter
card
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PCT/CN2016/077846
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English (en)
French (fr)
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田桂良
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2418—Signal interruptions by means of a message

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  • the present application relates to, but is not limited to, the field of PCIE bus technology, and in particular, to a method and apparatus for hot plugging based on a PCIE (Peripheral Component Interconnect Express) subcard.
  • PCIE Peripheral Component Interconnect Express
  • the PCIE bus is a high-speed external device interconnect bus. It was first promoted and promoted by Intel Intel. Its final design is to replace the bus transmission interface inside the existing computer system. This includes not only the display interface but also the CPU. (Central Processing Unit, central processing unit), PCI (Peripheral Component Interconnect), HDD (Hard Disk Drive), network (Network) and other application interfaces.
  • CPU Central Processing Unit
  • PCI Peripheral Component Interconnect
  • HDD Hard Disk Drive
  • Network Network
  • the PCIE bus application has been widely used.
  • the interface daughter card technology has been widely applied to the core router.
  • EPLD Erasable Programmable Logic Device
  • the hardware hot plug technology is very mature, but from the software point of view, the daughter card of the PCIE interface needs to be scanned by the motherboard before it can be accessed normally, and the subcard is hot swapped.
  • TLPs Transmission Line Pulses
  • the embodiment of the invention provides a method and a device for hot plugging based on a PCIE daughter card, which solves the problems of hot plug scanning and abnormal processing in the related art.
  • a method for hot plugging based on a PCIE daughter card including the following steps:
  • the interrupt processing function checks whether the interrupt is caused by the insertion interrupt caused by the PCIE daughter card insertion or the pullout interrupt caused by the PCIE daughter card being pulled out.
  • the interrupt processing function is processed by the interrupt processing function and the polling thread, so that the insertion event information is reported to the upper layer software after the PCIE daughter card is initialized;
  • the pull-out interrupt is processed by the interrupt processing function and the polling thread to delete the port information corresponding to the PCIE daughter card.
  • the interrupt processing function and the polling thread run in a motherboard or a CPU.
  • processing, by the interrupt processing function and the polling thread, processing the insertion interrupt including:
  • the interrupt processing function causes the PCIE daughter card to enter a waiting queue, and starts to wake up the waiting queue;
  • the polling thread executes an online power-on flow of the PCIE daughter card, so that the PCIE daughter card completes initialization.
  • processing the insertion interrupt by the interrupt processing function and the polling thread further includes:
  • the polling thread clears the result of the online power-on process of the PCIE daughter card
  • the polling thread resets and links the PCIE daughter card, and reports the PCIE daughter card insertion event information to the upper layer software.
  • the online power-on process of the PCIE daughter card by the polling thread includes:
  • the PCIE sub-card information is reported to the upper-layer software.
  • the upper layer software performs initialization processing on the PCIE daughter card according to the PCIE daughter card information.
  • processing, by the interrupt processing function and the polling thread, processing the pull-out interrupt includes:
  • the interrupt processing function reports the PCIE daughter card pull-out event to the upper layer software, and wakes up the waiting queue of the PCIE daughter card;
  • the polling thread executes an online power-off process of the PCIE daughter card to delete the port information corresponding to the PCIE daughter card.
  • the performing, by the polling thread, the online power-off process of the PCIE daughter card includes:
  • the port information corresponding to the PCIE daughter card is deleted.
  • the method further includes: when an abnormality occurs in the hot plug port of the PCIE daughter card, the abnormal hot plug port of the PCIE daughter card is processed by the interrupt processing function or the polling thread;
  • the abnormal hot plug port of the PCIE daughter card is processed by the interrupt processing function or the polling thread when the abnormality of the hot plug port of the PCIE daughter card is detected, including the following steps:
  • the pullout event information simulated by the PCIE daughter card is reported to the upper layer software by simulating a hot pull operation.
  • the method further includes:
  • the PCIE daughter card is subjected to positioning processing by recording the port information of the PCIE daughter card and the flag information in the hot plugging process by the interrupt processing function.
  • a device for hot plugging based on a PCIE daughter card including:
  • the interrupt processing function checks whether the interrupt is caused by the insertion interrupt caused by the insertion of the PCIE daughter card, or the pullout interrupt caused by the PCIE daughter card being pulled out;
  • Inserting an interrupt processing module configured to: when the result of the check is an interrupt, the interrupt processing function and the polling thread process the insert interrupt, so that the PCIE daughter card is initialized, and the insertion event information is reported to the upper layer software;
  • the interrupt processing module is pulled out, and is set to: when the check result is an pull-out interrupt, the pull-out interrupt is processed by the interrupt processing function and the polling thread, so as to delete the port information corresponding to the PCIE daughter card.
  • an embodiment of the present invention further provides a computer readable storage medium, where a computer can be stored. Executing instructions that implement the above-described PCIE subcard hot plug based method when the computer executable instructions are executed by the processor.
  • the beneficial effects of the embodiments of the present invention are: implementing the PCIE daughter card hot plugging function, being compatible with the online power-on and power-off function, and timely and effectively processing the abnormality generated during the plugging and unplugging process, and adding a hot plug problem positioning means, Helps quickly troubleshoot PCIE daughter card hot swap failures.
  • FIG. 1 is a flowchart of a method for hot plugging based on a PCIE subcard according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a device for hot plugging based on a PCIE daughter card according to an embodiment of the present invention
  • FIG. 3 is a flowchart of a PCIE daughter card hot plug interrupt processing process according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of processing a PCIE daughter card hot plug thread according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of abnormal processing of a PCIE hot swap port according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for hot plugging based on a high speed external device interconnect bus (PCIE) daughter card according to an embodiment of the present invention. As shown in FIG. 1, the method includes the following steps:
  • Step S101 After the PCIE subcard is hot plugged and caused an interrupt trigger, the interrupt processing function checks whether the interrupt is caused by the insertion interrupt caused by the PCIE daughter card insertion or the pullout interrupt caused by the PCIE daughter card being pulled out;
  • Step S102 If the result of the check is an interrupt, the interrupt processing function is processed by the interrupt processing function and the polling thread, so that the insertion event information is reported to the upper layer software after the PCIE daughter card is initialized;
  • Step S103 If the check result is an pull-out interrupt, the pull-out interrupt is processed by the interrupt processing function and the polling thread, so as to delete the port information corresponding to the PCIE daughter card.
  • the interrupt processing function and the polling thread run in a motherboard or a CPU.
  • the processing of the insertion interrupt by the interrupt processing function and the polling thread includes: the interrupt processing function causing the PCIE daughter card to enter a waiting queue, and starting to wake up the waiting queue; starting at an interrupt processing function During the wake-up process of the waiting queue, the polling thread performs an online power-on process of the PCIE daughter card, so that the PCIE daughter card completes initialization.
  • the process of performing the online power-on of the PCIE sub-card by the polling thread includes: reporting the PCIE sub-card information to the upper layer after detecting that the power-on command is sent and the PCIE sub-card link is completed.
  • the processing of the insertion interrupt by the interrupt processing function and the polling thread further includes: after the initialization of the PCIE daughter card and the wakeup of the waiting queue, the polling thread is online on the PCIE daughter card. The result of the electrical flow is cleared; the polling thread resets and links the PCIE daughter card, and then reports the PCIE daughter card insertion event information to the upper layer software.
  • the processing of the pull-out interrupt by the interrupt processing function and the polling thread includes: the interrupt processing function reporting the PCIE daughter card pull-out event to the upper layer software, and waking up the waiting queue of the PCIE daughter card; After the interrupt processing function wakes up the waiting queue of the PCIE daughter card, the polling thread executes the online power-off process of the PCIE daughter card to delete the port information corresponding to the PCIE daughter card.
  • the process of performing the online power-off of the PCIE sub-card by the polling thread includes: deleting the port information corresponding to the PCIE sub-card after the power-off command is sent, and disconnecting the PCIE sub-card chain The link to the road.
  • the method provided by the embodiment of the present invention further includes: when an abnormality occurs in the hot plug port of the PCIE daughter card, the abnormal hot plug port of the PCIE daughter card is processed by the interrupt processing function or the polling thread;
  • the step includes: when the abnormal hot plug port of the PCIE daughter card is processed by the interrupt processing function, if the bridge error information cannot be repaired, the hot plug of the abnormal PCIE daughter card is turned off. The port is pulled out; when the abnormal hot plug port of the PCIE daughter card is processed by the polling thread, the pullout event information simulated by the PCIE daughter card is reported to the upper layer software by simulating a hot pull operation.
  • the method provided by the embodiment of the present invention further includes: determining, by the interrupt processing function, the port information of the PCIE daughter card and the flag information during hot plugging, to determine the PCIE daughter card. Bit processing.
  • FIG. 2 is a schematic diagram of a device for hot plugging based on a PCIE daughter card according to an embodiment of the present invention.
  • the apparatus includes: an inspection module 201, an insertion interrupt processing module 202, and an extraction interrupt processing module 203.
  • the checking module 201 is configured to: after the PCIE sub-card hot plug causes an interrupt trigger, the interrupt processing function checks whether the interrupt is caused by an insertion interrupt caused by a PCIE daughter card insertion or an interrupt interrupt caused by a PCIE daughter card being pulled out. ;
  • the insertion interrupt processing module 202 is configured to: when the check result is an insertion interrupt, the insertion interrupt is processed by the interrupt processing function and the polling thread, so that the insertion event information is reported to the PCIE daughter card after initialization Upper layer software;
  • the pull-out interrupt processing module 203 is configured to: when the check result is an pull-out interrupt, the pull-out interrupt is processed by the interrupt processing function and the polling thread, so as to delete the port information corresponding to the PCIE daughter card.
  • FIG. 3 is a flowchart of a PCIE daughter card hot plug interrupt processing according to an embodiment of the present invention.
  • an interrupt type is checked, and only a wakeup queue is generated when an interrupt is generated;
  • the upper-layer software requires rapid awareness (satisfying the fast-cut service requirement), so the interrupt event is reported and the wakeup queue is sent.
  • the embodiment of the present invention adopts an object-oriented manner, and treats each PCIE subcard as an object, which includes important identifiers, function pointers, and sub-requirements in the hot plug process.
  • Information such as the uplink port device number and waiting queue for the card.
  • the bridge device information (domain, bus, device, function) mounted by the daughter card;
  • the daughter card can reset the identifier
  • the scan function is mounted
  • Scanflag 1 means the subcard has been scanned; 0 means the device has been unloaded or deleted;
  • Hotplug Generates or simulates a hot swap action for 1 (does not distinguish between insert and unplug). After the mark is scanned, or the pullout action/power-down action is cleared, it is cleared.
  • the wakeup queue is sent after the hot plug interrupt is received in the interrupt processing. In the polling thread, if the queue is wakeup, the hot swap event is triggered.
  • FIG. 4 is a flowchart of processing a PCIE daughter card hot plug thread according to an embodiment of the present invention.
  • the PCIE daughter card hot plug is triggered by an interrupt mode.
  • the interrupt is interrupted and inserted.
  • the interrupt processing is different; the interrupt processing function and the thread communicate through the message queue; in the thread, the PCIE daughter card online information, the EPLD_OK signal, and the PCIE link state are used as the basis for the PCIE daughter card state change, in four scenarios ( Inserting, unplugging, online power-on, online power-off)
  • the PCIE daughter card online power-on process the PCIE daughter card online power-off process, the PCIE daughter card insertion action processing flow, the PCIE daughter card pull-out action processing flow, and the fault tolerance process in the PCIE daughter card hot-plug thread processing.
  • the PCIE daughter card is powered on. After the power-on command is issued, the PCIE daughter card EPLD_OK signal is generated, and the PCIE daughter card link is completed. The scan flag is 0, so a scan occurs. Simultaneously set scanflag to 1, indicating that a scan has occurred. After scanning, the PCIE daughter card information is imported into the sysfs (/sys/bsp/board/subcard/slotX) file, and the upper layer software can read and initialize the PCIE daughter card.
  • the PCIE daughter card is powered off online. After the power-off command is issued, the PCIE daughter card EPLD_OK The signal is not detected first. Before the scanflag is 1, the device is deleted and the hotplug is cleared.
  • the PCIE daughter card insertion action processing flow the delay of the insertion interrupt is delayed, about 3 to 5 s. Therefore, when the insertion action occurs, the polling thread first detects the PCIE daughter card online online & & the daughter card EPLD_OK signal, and a PCIE child occurs. When the interrupt is generated and the queue is awake, it is judged whether it has been scanned before (scanflag is 1). If yes, the device information is cleared, that is, the result of the online power-on process scan of the daughter card is deleted.
  • the processing process of the PCIE daughter card pullout operation may have a delay in the pullout of the pullout interrupt.
  • the PCIE daughter card is first taken offline to delete the device; the interrupt signal comes in the interrupt processing flow. Reported in time, the scanflag in the thread is 0.
  • PCIE error messages occur due to link line jitter, transients, etc. These error messages must be processed in a timely manner.
  • the wrong sub-card device is parsed in the cache error processing flow, and the recovery is attempted. If the recovery is not completed after a certain period of time, the port is first closed; when the hot-swap polling thread detects that a certain condition is met. , then open this port.
  • the fault tolerance process in the PCIE hot plug thread processing includes two fault tolerance mechanisms: first, the thread continuously polls the port state. If the PCIE daughter card is found to be online and the EPLD_OK signal is normal, but the port is closed, the hotplug is set to 1, Simulate a pull-out action, delete the device and report the pull-out interrupt. The next poll will be scanned again according to the hotplug, and the scan will re-report the interrupt. This process generally does not occur during PCIE daughter card operation. Second, during the PCIE daughter card operation, the PCIE daughter card link is down (link down), recording the current event, simulating a hot swap, rescanning, and reporting the interrupt. This process can occur during board operation, resulting in a current interruption.
  • FIG. 5 is a flowchart of a PCIE hot-swap port exception processing according to an embodiment of the present invention.
  • the exception handling function of the PCIE daughter card hot-swap port is mounted in a cache error processing mechanism.
  • the loop repair mechanism When there is an error in PCIE, first determine if there will be a bridge error. If there is, try to repair the bridge error message. Use the loop repair mechanism. If it cannot be repaired after 5s, the port is hot swapped. Port, then the port is closed. If the repair is successful, nothing will be done.
  • the embodiment of the present invention further includes the hot plugging problem of the PCIE subcard.
  • the sfs mode is used to save the scanned PCIE subcard device information, and the important flag information (hotplug, scanflag, etc.) and interrupt in the hot plug process.
  • Information such as port status changes and error messages when the daughter card is abnormal is recorded in the form of a file, which makes it easy and quick to locate the problem. That is to say, the status of the PCIE sub-card port is recorded in real time through the log (log), and the change and status of the flag identifier during the insertion and removal process are recorded in the sysfs mode, so that the problem in the hot plugging process of the PCIE sub-card can be quickly and effectively located.
  • the implementation method of the embodiment of the present invention includes two contents, one is that the interrupt context and the thread context are combined to implement scanning and deleting of the PCIE daughter card hot swap, and the other is the abnormality generated during the hot plug process. Effective and timely processing.
  • the first thing to consider is the way and timing of dynamic scanning and deletion of PCIE daughter card hot swap.
  • the scan action is triggered by the report interrupt.
  • the scan takes a long time and should not be processed in the interrupt context. Therefore, the scan thread is used for scanning.
  • the PCIE daughter card is unplugged, the device is dynamically deleted.
  • the embodiment of the present invention is also compatible with the online power-on and power-off operation of the PCIE daughter card, that is, if the interrupt cannot be reported, the PCIE daughter card is scanned or deleted as needed.
  • the embodiment of the present invention can implement the hot plugging function of the PCIE daughter card, is compatible with the online power-on and power-off function, and timely and effectively processes the abnormality generated during the plugging and unplugging process, and adds a hot plug problem positioning means. Helps quickly troubleshoot PCIE daughter card hot swap failures.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, which are implemented by the processor to implement the above method based on PCIE subcard hot plugging.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • This application is not limited to any specific combination of hardware and software.
  • the embodiment of the invention provides a method and a device for hot plugging based on a PCIE daughter card, which implements a hot plug function of a PCIE daughter card, is compatible with an online power-on and power-off function, and timely and effectively processes an abnormality generated during the plugging and unplugging process, and
  • the hot plug problem location method has been added to help quickly troubleshoot PCIE daughter card hot swap failure.

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Abstract

一种基于PCIE子卡热插拔的方法，包括以下步骤：PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；若检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；若检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。上述方法实现了PCIE子卡热插拔功能，兼容在线上下电功能，且对于插拔过程中产生的异常进行及时有效处理。

Description

一种基于PCIE子卡热插拔的方法及装置 技术领域
本申请涉及但不限于PCIE总线技术领域，特别涉及一种基于PCIE(Peripheral Component Interconnect Express，高速外部设备互连总线)子卡热插拔的方法及装置。
背景技术
PCIE总线是一种高速外部设备互连总线，它最早由英特尔Intel所提倡和推广，它最终的设计目的是为了取代现有计算机系统内部的总线传输接口，这不只包括显示接口，还囊括了CPU(Central Processing Unit，中央处理器)、PCI(Peripheral Component Interconnect，外部设备互联)、HDD(Hard Disk Drive，硬盘驱动器)、网络(Network)等多种应用接口。
目前，PCIE总线应用已非常广泛，接口子卡技术已广泛应用于核心路由器上，接口卡的EPLD(Erasable Programmable Logic Device，可擦除可编辑逻辑器件)与母板CPU采用PCIE总线连接时，需要软硬件支持热插拔技术，硬件方面热插拔技术已很成熟，但从软件角度看，PCIE接口的子卡需要母板对其进行扫描后，才能正常访问，且在子卡热插拔的时候，会产生大量错误TLP(Transmission Line Pulse，传输线脉冲)，由于TLP污染等问题，可能使CPU产生误操作处理，导致异常。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种基于PCIE子卡热插拔的方法及装置，解决了相关技术中热插拔扫描和异常处理的问题。
根据本发明实施例的一个方面，提供了一种基于PCIE子卡热插拔的方法，包括以下步骤：
PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；
若检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
若检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
可选地，所述中断处理函数和所述轮询线程运行在母板或CPU中。
可选地，所述由中断处理函数和轮询线程处理所述插入中断，包括：
所述中断处理函数使所述PCIE子卡进入等待队列，并开始对所述等待队列进行唤醒处理；
在中断处理函数开始对所述等待队列进行唤醒处理期间，所述轮询线程执行所述PCIE子卡的在线上电流程，以便所述PCIE子卡完成初始化。
可选地，所述由中断处理函数和轮询线程处理所述插入中断，还包括：
在所述PCIE子卡完成初始化以及所述等待队列被唤醒后，所述轮询线程对所述PCIE子卡在线上电流程的结果进行清除；
所述轮询线程对所述PCIE子卡进行复位及链接处理，再将所述PCIE子卡插入事件信息上报给上层软件。
可选地，所述轮询线程执行所述PCIE子卡的在线上电流程包括：
当检测到上电命令下发以及所述PCIE子卡链路完成链接后，将所述PCIE子卡信息上报给上层软件；
所述上层软件根据所述PCIE子卡信息，对所述PCIE子卡进行初始化处理。
可选地，所述由中断处理函数和轮询线程处理所述拔出中断包括：
所述中断处理函数向上层软件上报所述PCIE子卡拔出事件，并唤醒所述PCIE子卡的等待队列；
在所述中断处理函数唤醒所述PCIE子卡的等待队列后，所述轮询线程执行所述PCIE子卡的在线下电流程，以删除所述PCIE子卡对应的端口信息。
可选地，所述轮询线程执行所述PCIE子卡的在线下电流程包括：
当检测到下电命令下发后，删除所述PCIE子卡对应的端口信息。
可选地，
所述方法还包括：当检测到所述PCIE子卡的热插拔端口出现异常时，由所述中断处理函数或轮询线程处理所述PCIE子卡的异常热插拔端口；
其中，所述当检测到所述PCIE子卡的热插拔端口出现异常时，由所述中断处理函数或轮询线程处理所述PCIE子卡的异常热插拔端口，包括以下步骤：
当由所述中断处理函数处理所述PCIE子卡的异常热插拔端口时，在不能修复桥片错误信息的情况下，关闭所述出现异常的PCIE子卡的热插拔端口；
当由所述轮询线程处理所述PCIE子卡的异常热插拔端口时，通过模拟一次热拔出动作，将所述PCIE子卡模拟的拔出事件信息上报给上层软件。
可选地，所述方法还包括：
由所述中断处理函数通过记录所述PCIE子卡的端口信息及热插拔过程中的flag信息，对所述PCIE子卡进行定位处理。
根据本发明实施例的另一方面，提供了一种基于PCIE子卡热插拔的装置，包括：
检查模块，设置为：在PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；
插入中断处理模块，设置为：当检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
拔出中断处理模块，设置为：当检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可 执行指令，所述计算机可执行指令被处理器执行时实现上述基于PCIE子卡热插拔的方法。
本发明实施例的有益效果在于：实现了PCIE子卡热插拔功能，兼容在线上下电功能，且对于插拔过程中产生的异常进行及时有效处理，而且，加入了热插拔问题定位手段，有助于快速排查PCIE子卡热插拔故障。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1是本发明实施例提供的一种基于PCIE子卡热插拔的方法流程图；
图2是本发明实施例提供的一种基于PCIE子卡热插拔的装置示意图；
图3是本发明实施例提供的PCIE子卡热插拔中断处理流程图；
图4是本发明实施例提供的PCIE子卡热插拔线程处理流程图；
图5是本发明实施例提供的PCIE热插拔端口异常处理流程图。
本发明的实施方式
以下结合附图对本发明实施例进行详细说明，应当理解，以下所说明的实施例仅用于说明和解释本申请，并不用于限定本申请。
图1显示了本发明实施例提供的一种基于高速外部设备互连总线(PCIE)子卡热插拔的方法流程图，如图1所示，所述方法包括以下步骤：
步骤S101：PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；
步骤S102：若检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
步骤S103：若检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
其中，所述中断处理函数和所述轮询线程运行在母板或CPU中。
其中，所述由中断处理函数和轮询线程处理所述插入中断包括：所述中断处理函数使所述PCIE子卡进入等待队列，并开始对所述等待队列进行唤醒处理；在中断处理函数开始对所述等待队列进行唤醒处理期间，所述轮询线程执行所述PCIE子卡的在线上电流程，以便所述PCIE子卡完成初始化。
其中，所述轮询线程执行所述PCIE子卡的在线上电流程包括：当检测到上电命令下发以及所述PCIE子卡链路完成链接后，将所述PCIE子卡信息上报给上层软件；所述上层软件根据所述PCIE子卡信息，对所述PCIE子卡进行初始化处理。
其中，所述由中断处理函数和轮询线程处理所述插入中断还包括：在所述PCIE子卡完成初始化以及所述等待队列被唤醒后，所述轮询线程对所述PCIE子卡在线上电流程的结果进行清除；所述轮询线程对所述PCIE子卡进行复位及链接处理，再将所述PCIE子卡插入事件信息上报给上层软件。
其中，所述由中断处理函数和轮询线程处理所述拔出中断包括：所述中断处理函数向上层软件上报所述PCIE子卡拔出事件，并唤醒所述PCIE子卡的等待队列；在所述中断处理函数唤醒所述PCIE子卡的等待队列后，所述轮询线程执行所述PCIE子卡的在线下电流程，以删除所述PCIE子卡对应的端口信息。其中，所述轮询线程执行所述PCIE子卡的在线下电流程包括：当检测到下电命令下发后，删除所述PCIE子卡对应的端口信息，并断开所述PCIE子卡链路的链接。
本发明实施例提供的方法还包括：当检测到所述PCIE子卡的热插拔端口出现异常时，由所述中断处理函数或轮询线程处理所述PCIE子卡的异常热插拔端口；其中，该步骤包括：当由所述中断处理函数处理所述PCIE子卡的异常热插拔端口时，在不能修复桥片错误信息的情况下，关闭所述出现异常的PCIE子卡的热插拔端口；当由所述轮询线程处理所述PCIE子卡的异常热插拔端口时，通过模拟一次热拔出动作，将所述PCIE子卡模拟的拔出事件信息上报给上层软件。
本发明实施例提供的方法还包括：由所述中断处理函数通过记录所述PCIE子卡的端口信息及热插拔过程中的flag信息，对所述PCIE子卡进行定 位处理。
图2显示了本发明实施例提供的一种基于PCIE子卡热插拔的装置示意图。如图2所示，所述装置包括：检查模块201、插入中断处理模块202以及拔出中断处理模块203。
所述检查模块201，设置为：在PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；
所述插入中断处理模块202，设置为：当检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
所述拔出中断处理模块203，设置为：当检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
图3显示了本发明实施例提供的PCIE子卡热插拔中断处理流程图，如图3所示，在中断处理函数中，检查中断类型，在插入中断产生时只唤醒(wakeup)队列；在拔出中断产生时上层软件要求迅速感知(满足快切业务要求)，故先上报拔出中断事件，再wakeup队列。
为保存和表示子卡热插拔事件，本发明实施例采用面向对象的方式，将每个PCIE子卡看作一个对象，该对象包含热插拔过程中所需要的重要标识、函数指针、子卡对应的上行口设备号、等待队列等信息。
struct hotplug_subcard
{
子卡槽位号；
子卡挂载的桥片设备信息(domain,bus,device,function)；
插入中断标识；
拔出中断标识；
扫描标识scanflag；
子卡可复位标识；
线程名称；
扫描函数挂载；
删除设备挂载；
子卡link状态标识；
扫描队列waitque；
}；
其中的重要信息介绍如下：
scanflag：为1表示该子卡已经被扫描；为0表示已卸载或删除设备；
hotplug：为1发生或模拟了一次热插拔动作(不区分插入还是拔出)，该标识发生扫描之后，或者拔出动作/下电动作处理完后清0。
waitque：在中断处理中收到热插拔中断后要wakeup队列，在轮询线程中检查如果队列被wakeup了，就触发对热插拔事件的处理。
图4显示了本发明实施例提供的PCIE子卡热插拔线程处理流程图，如图4所示，PCIE子卡热插拔是由中断方式触发，在中断处理函数中，拔出中断和插入中断的处理有差别；中断处理函数和线程通过消息队列来进行通讯；在线程中，以PCIE子卡在线信息、EPLD_OK信号、PCIE link状态作为PCIE子卡状态变化的依据，在四种场景下(插入、拔出、在线上电、在线下电)有不同的处理流程，还要考虑流程的重叠和兼容处理。其中，包括PCIE子卡在线上电流程、PCIE子卡在线下电流程、PCIE子卡插入动作处理流程、PCIE子卡拔出动作处理流程以及PCIE子卡热插拔线程处理中的容错流程。
所述PCIE子卡在线上电流程：上电命令下发后，PCIE子卡EPLD_OK信号会产生，并且PCIE子卡链路完成链接(link up)，此时扫描标识scanflag为0，故发生一次扫描，同时置scanflag为1，表示已发生扫描。扫描后把PCIE子卡信息导入到sysfs(/sys/bsp/board/subcard/slotX)文件中，上层软件读取后即可完成初始化PCIE子卡。
所述PCIE子卡在线下电流程：下电命令下发后，PCIE子卡EPLD_OK 信号首先检测不到，之前scanflag为1，故删除设备，热插拔hotplug清0。
所述PCIE子卡插入动作处理流程：插入中断的上报有延时，大概3～5s，所以插入动作发生时，轮询线程首先检测到PCIE子卡在线online&&子卡EPLD_OK信号，发生了一次PCIE子卡在线上电流程的扫描；当中断产生且唤醒队列后，先判断之前是否扫描过(scanflag是否为1)，如果是，则清除设备信息，即删除子卡在线上电流程扫描的结果，清scanflag；然后要复位子卡(在插入扫描动作前复位能提高子卡扫描稳定性)，hotplug置1；等待PCIE子卡EPLD_OK信号且link up后，再进行一次扫描，扫描后会将插入事件上报给上层软件处理。
所述PCIE子卡拔出动作处理流程：拔出中断的上报可能有延时，有延时时还会先走PCIE子卡在线下电流程，删除设备；中断信号来临时，在中断处理流程中及时上报，线程中scanflag为0。
在PCIE子卡热插拔过程中，由于链接线路抖动、瞬断等导致出现PCIE错误信息，这些错误信息必须及时得到处理。首先在缓存错误(cache error)处理流程中解析出错误的子卡设备，尝试恢复，过一段时间仍未恢复的，就先将此端口关闭；在热插拔轮询线程中检测符合一定条件时，再将此端口打开。
所述PCIE热插拔线程处理中的容错流程包括两种容错机制：第一种，线程不断轮询端口状态，如果发现PCIE子卡在线且EPLD_OK信号正常，但端口关闭，则置hotplug为1，模拟一次拔出动作，删除设备并上报拔出中断，下一个轮询中根据hotplug会再扫描一次，扫描到就重新上报插入中断。此过程一般不会发生在PCIE子卡运行过程中。第二种，在PCIE子卡运行过程中发生了PCIE子卡链路断开(link down)，记录当前事件，模拟一次热插拔，重新扫描并上报中断。此过程可能发生在单板运行过程中，导致断流。
图5显示了本发明实施例提供的PCIE热插拔端口异常处理流程图，如图5所示，将PCIE子卡热插拔端口的异常处理函数挂载到cache error处理机制中。当有PCIE发生错误时，首先判断是否会有桥片错误，如果有，则尝试去修复桥片错误信息，采用循环修复机制，在5s后如果还不能修复，且该端口是子卡热插拔端口，则将该端口关闭。若修复成功，则不做什么。
本发明实施例还包括PCIE子卡热插拔问题定位：通过sysfs方式，将扫描到的PCIE子卡设备信息保存下来，并将热插拔过程中重要的flag信息(hotplug、scanflag等)、中断信息、子卡异常时的端口状态变化以及错误信息等都以文件形式记录下来，能方便快捷地定位问题。也就是说，通过日志(log)实时记录PCIE子卡端口状态、通过sysfs方式记录插拔过程中flag标识的变化及状态等，能够有效快速定位PCIE子卡热插拔过程中的问题。
综上所述：本发明实施例的实现方法包括两块内容，一是中断上下文和线程上下文结合来实现对PCIE子卡热插拔的扫描与删除，二是对在热插拔过程产生的异常进行有效及时的处理。首先要考虑的是PCIE子卡热插拔的动态扫描与删除的方式与时机。PCIE子卡在插入母板时会通过上报中断来触发扫描动作，扫描耗时较长，不宜在中断上下文处理，故配合轮询线程方式来进行扫描。在PCIE子卡拔出时，要动态删除设备。本发明实施例还兼容PCIE子卡在线上下电操作，即在无法上报中断的情况下，根据需要对PCIE子卡扫描或删除。
综上所述，本发明实施例可以实现PCIE子卡热插拔功能，兼容在线上下电功能，且对于插拔过程中产生的异常进行及时有效处理，而且，加入了热插拔问题定位手段，有助于快速排查PCIE子卡热插拔故障。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被处理器执行时实现上述基于PCIE子卡热插拔的方法。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本申请不限制于任何特定形式的硬件和软件的结合。
尽管上文对本申请进行了详细说明，但是本申请不限于此，本技术领域 技术人员可以根据本申请的原理进行各种修改。因此，凡按照本申请原理所作的修改，都应当理解为落入本申请的保护范围。
工业实用性
本发明实施例提供一种基于PCIE子卡热插拔的方法及装置，实现了PCIE子卡热插拔功能，兼容在线上下电功能，且对于插拔过程中产生的异常进行及时有效处理，而且，加入了热插拔问题定位手段，有助于快速排查PCIE子卡热插拔故障。

Claims (10)

  1. 一种基于高速外部设备互联总线PCIE子卡热插拔的方法，包括以下步骤：
    PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致的拔出中断；
    若检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
    若检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
  2. 根据权利要求1所述的方法，其中，所述中断处理函数和所述轮询线程运行在母板或中央处理器CPU中。
  3. 根据权利要求1所述的方法，其中，所述由所述中断处理函数和轮询线程处理所述插入中断包括：
    所述中断处理函数使所述PCIE子卡进入等待队列，并开始对所述等待队列进行唤醒处理；
    在中断处理函数开始对所述等待队列进行唤醒处理期间，所述轮询线程执行所述PCIE子卡的在线上电流程，以便所述PCIE子卡完成初始化。
  4. 根据权利要求3所述的方法，其中，所述由所述中断处理函数和轮询线程处理所述插入中断还包括：
    在所述PCIE子卡完成初始化以及所述等待队列被唤醒后，所述轮询线程对所述PCIE子卡在线上电流程的结果进行清除；
    所述轮询线程对所述PCIE子卡进行复位及链接处理，再将所述PCIE子卡插入事件信息上报给上层软件。
  5. 根据权利要求3所述的方法，其中，所述轮询线程执行所述PCIE子卡的在线上电流程包括：
    当检测到上电命令下发以及所述PCIE子卡链路完成链接后，将所述PCIE子卡信息上报给上层软件；
    所述上层软件根据所述PCIE子卡信息，对所述PCIE子卡进行初始化处理。
  6. 根据权利要求1所述的方法，其中，所述由所述中断处理函数和轮询线程处理所述拔出中断包括：
    所述中断处理函数向上层软件上报所述PCIE子卡拔出事件，并唤醒所述PCIE子卡的等待队列；
    在所述中断处理函数唤醒所述PCIE子卡的等待队列后，所述轮询线程执行所述PCIE子卡的在线下电流程，以删除所述PCIE子卡对应的端口信息。
  7. 根据权利要求6所述的方法，其中，所述轮询线程执行所述PCIE子卡的在线下电流程包括：
    当检测到下电命令下发后，删除所述PCIE子卡对应的端口信息。
  8. 根据权利要求1至7任一项所述的方法，所述方法还包括：当检测到所述PCIE子卡的热插拔端口出现异常时，由所述中断处理函数或轮询线程处理所述PCIE子卡的异常热插拔端口；
    其中，所述当检测到所述PCIE子卡的热插拔端口出现异常时，由所述中断处理函数或轮询线程处理所述PCIE子卡的异常热插拔端口，包括以下步骤：
    当由所述中断处理函数处理所述PCIE子卡的异常热插拔端口时，在不能修复桥片错误信息的情况下，关闭所述出现异常的PCIE子卡的热插拔端口；
    当由所述轮询线程处理所述PCIE子卡的异常热插拔端口时，通过模拟一次热拔出动作，将所述PCIE子卡模拟的拔出事件信息上报给上层软件。
  9. 根据权利要求1至7任一项所述的方法，所述还包括：
    由所述中断处理函数通过记录所述PCIE子卡的端口信息及热插拔过程中的flag信息，对所述PCIE子卡进行定位处理。
  10. 一种基于PCIE子卡热插拔的装置，包括：
    检查模块，设置为：在PCIE子卡热插拔造成中断触发后，由中断处理函数检查中断是由PCIE子卡插入导致的插入中断，还是由PCIE子卡拔出导致 的拔出中断；
    插入中断处理模块，设置为：当检查结果为插入中断，则由所述中断处理函数和轮询线程处理所述插入中断，以便所述PCIE子卡初始化后，将插入事件信息上报给上层软件；
    拔出中断处理模块，设置为：当检查结果为拔出中断，则由所述中断处理函数和轮询线程处理所述拔出中断，以便删除所述PCIE子卡对应的端口信息。
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