WO2016197947A1

WO2016197947A1 - Paging address space management method and controller

Info

Publication number: WO2016197947A1
Application number: PCT/CN2016/085279
Authority: WO
Inventors: 朱爽
Original assignee: 华为技术有限公司
Priority date: 2015-06-12
Filing date: 2016-06-08
Publication date: 2016-12-15
Also published as: CN104951406B; CN104951406A

Abstract

Provided are a paging address space management method and controller. The paging address space management method comprises: determining an address page (301); determining a target peripheral address space (302); determining an address page satisfying a first preset requirement as a first target address page (303); and establishing a mapping between each of the first target address page and the target peripheral address space (304). The method can determine the first target address page satisfying the first preset requirement according to a size of the target peripheral address space in a peripheral device, and the established mapping is a correspondence between the address space of the first target address page and the effective target peripheral address space accessible to the peripheral device, thereby avoiding a waste of address resources resulting from mapping to a controller an address space in a peripheral device and inaccessible to the controller.

Description

Paging address space management method and controller

This application claims the priority of the Chinese patent application filed on June 12, 2015, the Chinese Patent Office, the application number is CN201510324059.0, and the invention name is "a paging address space management method and controller". The citations are incorporated herein by reference.

Technical field

The present invention relates to a computer system, and more particularly to a paging address space management method and controller.

Background technique

Referring to FIG. 1, the structure of a computer system provided by the prior art is illustrated. As shown in FIG. 1, the computer system includes, but is not limited to, a processor 100, a controller 101, and a memory 102, which is a computer. The basic unit of the system, the computer system needs to move data from or write data to the memory 102, and the external device 103 is used to communicate with the external system or supplement the additional functions of the computer system, the controller 101 Is for connecting the processor 100 and the external device 103, and the controller 101 further provides a storage method of the memory 102 to enable the controller 101 to assist the processor 100 and the external device 103 to access the memory 102;

Referring to FIG. 2, in the prior art, the address space of the controller 101 is divided into a plurality of independently stored storage units, and the controller 101 predetermines a memory address mapping of each of the storage units and each external device 103. Relationship, that is, the controller 101 predetermines a memory address mapping relationship, which includes a one-to-one correspondence between each storage unit and each external device, as shown in FIG. 2, that is, the address mapping relationship includes The mapping relationship between the storage unit 1 and the external device 1, the mapping relationship between the storage unit 2 and the external device 2, and the like, each of the storage units has a fixed start address and an end address, and the controller 101 can be based on the address of each storage unit. Selecting a suitable external device for establishing the memory address mapping relationship, because the controller 101 has determined the memory address mapping relationship, enabling the controller 101 to directly read and write the memory of the external device 103 to enable reading No additional software overhead is incurred during the process;

A disadvantage of the prior art is that the address range size of each of the storage units is fixed, and once a certain storage unit allocates an external device 103, even if the external device 103 cannot run out of the storage list The address resource of the element, but the remaining address of the storage unit cannot be used, thereby causing waste of the address resource of the controller 101; and if the address space of a certain external device 103 is larger than the address of the storage unit corresponding to the external device 103 In the case of space, the controller 101 cannot successfully attach the external device 103.

Summary of the invention

The embodiment of the invention provides a paging address space management method and a controller, which can effectively save the address resource of the controller and avoid waste of the controller address resource;

A first aspect of the embodiments of the present invention provides a paging address space management method, including:

Determining address paging, which is divided by the address space of the controller to form;

Determining a target peripheral address space, where the external device requests a peripheral address space that is currently mapped to the address space, and the address space is used to map to the address space The target peripheral address space is accessed;

Determining that the address page that meets the first preset condition is paged as a first target address, and the first preset condition is that a sum of address spaces of all the first target address pages is greater than or equal to the target peripheral address space ;

Establishing a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the first target address page according to the mapping relationship On the address space.

With reference to the first aspect of the embodiments of the present invention, in a first implementation manner of the first aspect of the embodiment of the present invention,

Before the determining the address paging, the method further includes:

The address space is divided to form a plurality of the address pages, the sum of the address spaces of all the address pages is equal to the address space, and the address space of each of the address pages is a power of two.

With reference to the first aspect of the embodiments of the present invention or the first implementation manner of the first aspect of the embodiments of the present invention,

Determining a free address page that is an address page that does not currently have a mapping relationship with an external device's peripheral address space;

After the determining the target peripheral address space, the method further includes:

If it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, the determining that the address paging satisfying the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages.

With reference to the first aspect of the embodiment of the present invention or the first implementation manner of the first aspect of the embodiment of the present invention, in a third implementation manner of the first aspect of the embodiment of the present invention,

After the determining the address paging, the method further includes:

Determining a free address page and an occupied address page, the occupied address page is an address page that has been mapped to an external device's peripheral address space, and the free address page is not currently associated with an external device's peripheral address space. Address paging of the mapping relationship;

If the sum of the address spaces of all the free address pages is determined to be smaller than the target peripheral address space, the method further includes:

Determining, in all of the occupied address pages, a second target address page that satisfies a second preset condition, where the second preset condition is an address page in the occupied address page whose access frequency is less than a preset value;

Dissolving the mapping relationship between the second target address page and the peripheral address space that has been established;

The determining that the address paging that meets the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages and in the second target address page.

With the implementation of the first aspect of the embodiment of the present invention, in a fourth implementation manner of the first aspect of the embodiment of the present invention,

After the mapping between each of the first target address pages and the target peripheral address space is established, the method further includes:

Mapping the target peripheral address space to the address space of the first target address page according to the mapping relationship;

Determining a virtual address of each of the first target address pages;

The virtual addresses of each of the first target address pages are rearranged to form a continuous virtual address segment.

A second aspect of the embodiments of the present invention provides a controller, including:

a first determining unit, configured to determine address paging, where the address paging is divided by an address space of the controller to form;

a second determining unit, configured to determine a target peripheral address space, where the target peripheral address space is a peripheral device requesting an external address space that is currently mapped to the address space, where the address space is used to map to Accessing the target peripheral address space on the address space;

a third determining unit, configured to determine that the address paging that meets the first preset condition is a first target address paging, and the first preset condition is that a sum of address spaces of all the first target address paging is greater than or equal to The target peripheral address space;

a mapping unit, configured to establish a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the first A destination address is paged over the address space.

With reference to the second aspect of the embodiments of the present invention, in a first implementation manner of the second aspect of the embodiment of the present invention,

a dividing unit, configured to divide the address space to form a plurality of the address pages, a sum of address spaces of all the address pages is equal to the address space, and an address space of each of the address pages is a power of 2 .

With reference to the second aspect of the embodiment of the present invention or the first implementation manner of the second aspect of the embodiment of the present invention, in a second implementation manner of the second aspect of the embodiment of the present invention,

a fourth determining unit, configured to determine a free address page, where the free address page is an address page that does not currently have a mapping relationship with an external device address space of the external device;

The third determining unit is further configured to: if it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, determine, in all the free address pages, that the first preset condition is met The first target address is paged.

With reference to the second aspect of the embodiment of the present invention or the first implementation manner of the second aspect of the embodiment of the present invention, in a third implementation manner of the second aspect of the embodiment of the present invention,

a fifth determining unit, configured to determine a free address page and an occupied address page, wherein the occupied address page is an address page that has been mapped to a peripheral device address space of an external device, and the free address page is currently not external The peripheral address space of the device establishes the address paging of the mapping relationship;

a sixth determining unit, configured to determine, in all of the occupied address pages, a second target that satisfies a second preset condition, if it is determined that a sum of address spaces of all the free address pages is smaller than the target peripheral address space Address paging, the second preset condition is an address paging of the occupied address paging whose access frequency is less than a preset value;

a seventh determining unit, configured to cancel the mapping relationship between the second target address paging and the peripheral address space;

The third determining unit is further configured to determine, in all of the free address pagings and the second target address paging, the first target address paging that satisfies the first preset condition.

With reference to the first implementation manner of the second aspect of the embodiment of the present invention, the third implementation manner of the second aspect of the embodiment of the present invention further includes:

An eighth determining unit, configured to map the target peripheral address space to the address space of the first target address paging according to the mapping relationship;

a ninth determining unit, configured to determine a virtual address of each of the first target address pages;

And a tenth determining unit, configured to rearrange the virtual addresses of each of the first target addresses to form a continuous virtual address segment.

The embodiment of the invention discloses a paging address space management method and a controller. The paging address space management method includes: determining address paging, determining a target peripheral address space, and determining the address that satisfies a first preset condition. The paging is paged for the first target address, and the first preset condition is that the sum of the address spaces of all the first target address pages is greater than or equal to the target peripheral address space, and each of the first target address pages is established. The mapping relationship of the target peripheral address space. The embodiment is capable of determining, according to the size of the target peripheral address space of the external device, the first target address paging that satisfies the first preset condition, and the mapping relationship establishes the address of the first target address paging The correspondence between the effective target peripheral address space that the space and the external device can be accessed, thereby avoiding mapping the address space in the external device that cannot be accessed by the controller to the controller. The waste of the address resources effectively ensures the reasonable configuration of the address resources of the controller and saves the address resources of the controller.

DRAWINGS

1 is a schematic structural diagram of a computer system shown in the prior art;

2 is a schematic structural view of a controller shown in the prior art;

3 is a flow chart of steps of a preferred embodiment of a paging address space management method according to an embodiment of the present invention;

4 is a schematic structural diagram of hardware of a system on chip according to an embodiment of the present invention;

FIG. 5 is a flow chart of another preferred embodiment of a paging address space management method according to an embodiment of the present invention;

6 is a diagram showing an example of an address space of an external device;

FIG. 7 is a schematic diagram of mapping relationship between each of the first target address paging and the target peripheral address space according to an embodiment of the present invention;

FIG. 8 is another schematic diagram of mapping relationship between each of the first target address paging and the target peripheral address space according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a continuous virtual address segment according to an embodiment of the present invention;

FIG. 10 is a flowchart of another preferred embodiment of a paging address space management method according to an embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of an embodiment of a controller according to an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of another embodiment of a controller according to an embodiment of the present disclosure;

FIG. 13 is a schematic structural diagram of another embodiment of a controller according to an embodiment of the present disclosure;

FIG. 14 is a schematic structural diagram of another embodiment of a controller according to an embodiment of the present invention.

detailed description

An embodiment of the present invention provides a paging address space management method. The following describes a paging address space management method provided by this embodiment in detail with reference to FIG. 3:

301. Determine an address page;

A controller of the computer system determines an address space of the controller, the address page being divided by the address space to form such that a sum of address spaces of all determined address pages is equal to the address space;

In this embodiment, the number of the address pages that have been determined is not limited, and the size of the address space of each of the address pages is not limited, as long as the address space can be divided into the address points. The page is OK.

302. Determine a target peripheral address space.

The target peripheral address space is a peripheral address space that the external device requests to establish a mapping relationship with the address space;

The address space is used to access the target peripheral address space mapped to the address space;

Specifically, when an external device accesses the computer system, the controller may determine a target peripheral address space of the currently accessed external device, thereby enabling the controller to establish the controller and the target. Setting a mapping relationship of the address space, and further performing a corresponding access operation on the target peripheral address space according to the mapping relationship;

More specifically, the target peripheral address space shown in this embodiment is an effective storage space of the external device, that is, a part of the address space of the external device cannot be accessed by the controller. For example, a reserved area set by an external device or the like; another part is accessible by the controller. In this embodiment, an address space of an external device that the controller can access is collectively referred to as a peripheral address space.

303. Determine that the address paging that meets the first preset condition is a paging of the first target address.

The controller is preset with the first preset condition;

The first preset condition is that a sum of address spaces of all the first target address pages is greater than or equal to the target peripheral address space;

In this embodiment, the timing at which the controller specifically sets the first preset condition is not limited.

304. Establish a mapping relationship between each of the first target address pages and the target peripheral address space.

The controller establishes a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used by the controller to map the target peripheral address space according to the mapping relationship to The first target address is paged on the address space.

The controller is capable of mapping a physical address of the target peripheral address space on an address space mapped to the first target address page according to the mapping relationship to a virtual address to enable a processor to perform reading.

In this embodiment, the size of the address space of each of the determined first target addresses is not used. Definitely, as long as the sum of the address spaces of all the first target address pages is greater than or equal to the target peripheral address space, for example, the determined address spaces of all the first target address pages may all be the same size They can all be different, and they can be the same.

The paging address space management method shown in this embodiment can determine the address space of the controller as address paging, so that the controller can determine that the first preset is satisfied according to the size of the target peripheral address space of the external device. The first target address of the condition is paged, and the mapping relationship in the embodiment establishes an address space of the first target address page and a valid target peripheral address space that the external device can be accessed by the controller. The correspondence between the addresses, thereby avoiding the waste of address resources caused by mapping the address space that cannot be accessed by the controller in the external device to the controller, that is, mapping to the controller address in this embodiment The target peripheral address space in the space can be accessed by the controller, which effectively ensures the reasonable configuration of the address resource of the controller and saves the address resource of the controller.

The paging address space management method provided by the embodiment of the present invention is described in detail below with reference to a specific application scenario. The following is a description of the specific application scenario as an on-chip system. It should be clarified that the paging provided by the embodiment of the present invention is provided. The address space management method can also be applied to other computer systems, and the following description is merely for the purpose of illustration and not limitation;

First, the structure of the system on chip applied in this embodiment will be described with reference to FIG. 4;

As shown in FIG. 4, the role of the controller is to convert commands from the on-chip system internal bus that are accessed by external devices into instructions that the external device can "understand".

A typical peripheral bus, such as a PCI/PCI-E bus, a Rapid IO bus, etc., and a description of the peripheral bus, please refer to the prior art, which is not limited in this embodiment.

The controller can be split into two parts, one is a bridge, and the other is a physical line sequence controller.

The bridge is responsible for docking the on-chip system internal bus;

The physical line sequence controller is responsible for docking the control line sequence of the specific external device.

The paging address space management method will be described in detail below with reference to FIG. 4 and FIG. 5:

501, dividing the address space to form a plurality of the address pages;

Specifically, the bridge of the controller divides an address space of the controller to form a plurality of the address pages;

The sum of the address spaces of all the address pages is equal to the address space;

Preferably, the address space of each of the address pages in this embodiment is a power of 2.

In this embodiment, the size of the address space of each of the address pages is not limited, as long as the address space of each of the address pages is a power of two.

502. Determine address paging;

For the specific implementation process of step 502 in this embodiment, please refer to step 301 shown in FIG. 3, which is not specifically described in this embodiment.

503. Determine a free address page;

The free address page is an address page that does not currently have a mapping relationship with an external device address space of the external device;

The free address page is paged for an unoccupied address.

504. Determine a target peripheral address space.

As shown in FIG. 4, the total space of the external device currently accessing the system on chip is 150 MB, and the target peripheral address space that can be accessed by the controller is 136 MB.

Then, when the external device accesses the system on chip, the controller can determine that the target peripheral address space is 136 MB;

Preferably, when determining the target peripheral address space, the method used in this embodiment may be:

When the external device accesses the system on chip, the system on chip performs a self-test on the external device;

The commonly used self-test algorithms include a simple self-test method, a nine-step method, and a checkerboard step method. For details of the self-test implementation, please refer to the prior art, which is not described in detail in this embodiment.

During the self-test, if the system on chip determines that there is a reserved area in the peripheral address space of the external device, skip the reserved area to determine the target peripheral address space in the external device;

The peripheral address space of the external device connected to the system on chip in this embodiment can be seen as shown in FIG. 6; the range of the peripheral address space of the external device is from the start address to the end address shown in FIG. 6;

The peripheral address space is provided with a plurality of reserved areas that are not mapped. The reserved areas divide the peripheral address space shown in FIG. 6 into five segments of different sizes (segment 1, segment 2, segment 3, segment 4, and Paragraph 5);

More specifically, as shown in FIG. 6, segment 1 is 32 MB, segment 2 is 16 MB, and segment 3 is 8 MB. Segment 4 is 48MB and segment 5 is 32MB;

The system on chip can determine that the target peripheral address space is 136MB.

It should be clarified that, in this embodiment, the target peripheral address space segmentation setting is taken as an example for illustration and not limitation. Of course, the determined target peripheral address space may not be segmented but the entire segment is set. of;

In this embodiment, the external device is self-tested by the system on chip to determine the target peripheral address space as an example, which is not limited, as long as the controller of the system on chip can determine the target peripheral address space. can.

505. Determine that a sum of address spaces of all the free address pages is greater than the target peripheral address space.

In this embodiment, the sum of the address spaces of all the free address pages is larger than the target peripheral address space as an example.

506. Determine, in all the free address pages, the first target address page that meets the first preset condition;

That is, when the sum of the address spaces of all the free address pages is larger than the target peripheral address space, the controller may select the first target address page among the free address pages;

The sum of the address spaces of the first target address page selected in the free address page is greater than or equal to the target peripheral address space.

507. Establish a mapping relationship between each of the first target address pages and the target peripheral address space.

In this embodiment, the mapping relationship is as shown in FIG. 7 , and the mapping relationship is not illustrated in the embodiment.

Specifically, as shown in FIG. 7, for a segment smaller than 16 MB (segment 3), one or more copies of the first target address page of 4 MB are selected for mapping, that is, segment 3 and two copies of 4 MB in this embodiment A target address paging establishes a mapping relationship;

For segments greater than or equal to 16 MB (segment 1, segment 2, segment 4, and segment 5), one or more 16 MB first destination address pages are selected for mapping, that is, segment 1 and two 16 MB in this embodiment. The first target address is divided into pages to establish a mapping relationship, and the segment 2 is mapped to a 16 MB first target address page, and the segment 4 is mapped to three 16 MB first target addresses. 5 establishes a mapping relationship with two 16MB first target address pages;

It should be clarified that the specific mapping relationship shown in this embodiment is described by way of example, and is not limited, as long as the sum of the address spaces of all the first target address pages is greater than or equal to the target peripheral address. Space can be;

In this embodiment, the address space size of the first target address page corresponding to a target peripheral address space is the same as an example, and is not limited. In a specific application, each part corresponding to a target peripheral address space The size of the address space of a target address page may be different or partially the same, and is not limited.

508. Map the target peripheral address space to the address space of the first target address page according to the mapping relationship.

The controller maps the target peripheral address space to the address space of the first target address page according to the mapping relationship, that is, mapping the physical address of the target peripheral address space of the external device by using the mapping relationship a virtual address that can be read by the processor;

That is, as shown in FIG. 8, the controller can establish a mapping relationship between the physical address of the target peripheral address space of the external device and the first target address paging, so that the processor can read by reading the mapping relationship. Take the target peripheral address space of the external device.

509. Determine a virtual address of each of the first target address pages.

In this embodiment, the controller can determine the virtual address of each of the first target address pages.

510. Rearrange the virtual addresses of each of the first target address pages to form a continuous virtual address segment.

The controller rearranges the virtual addresses of the first target address pages to form a virtual address segment as shown in FIG. 9. In this embodiment, the virtual addresses of the first target address pages are sorted according to the order. The rule is not limited to form the virtual address segment, and the controller may select a better sorting rule according to different services of the external device, as long as the virtual address segment formed after the rearrangement is continuous The address segment, such that the virtual address segment perceived by the processor is continuous, ie can.

It should be clarified that steps 509 to 510 in this embodiment are selectable steps, that is, in actual applications, the first target address pages may be rearranged through steps 509 to 510, or may not be used for each A target address is paged for rearrangement, which may be determined according to actual needs. For example, when the first target address page corresponding to the target peripheral address space is itself continuous, paging of each first target address is not required. rearrange.

The paging address space management method provided in this embodiment can avoid the waste of address resources caused by mapping an address space that cannot be accessed by the controller in the external device to the controller, and the selected The size of the address space of the first target address page can be matched with the target peripheral address space, which effectively saves the address resource of the controller. In this embodiment, the controller is further capable of rearranging the first target address pages to form a continuous virtual address segment, thereby reducing the burden on the system when accessing the non-contiguous virtual address segments.

The paging address space management method capable of reducing system logic resources provided by the embodiment of the present invention is described in detail below with reference to FIG. 10:

1001, dividing the address space to form a plurality of the address pages;

1002, determining address paging;

The

steps

1001 and 1002 in this embodiment are specifically shown in FIG. 5 to step 501 to step 502, and are not described in detail in this embodiment.

1003. Determine a free address page and an occupied address page;

The occupied address page is an address page that has been mapped to a peripheral address space of an external device, that is, the occupied address page is occupied by other external devices, and the processor cannot read the occupied address by reading. The paging determines the physical address of the target peripheral address space of the external device currently accessing the system;

1004. Determine a target peripheral address space.

Step 1004 in this embodiment is specifically shown in step 504 shown in FIG. 5.

1005. Determine a sum of address spaces of all the free address pages that are smaller than the target peripheral address space.

The controller determines that the sum of the address spaces of the free address pages is smaller than the target peripheral address space, proceed to step 1006;

1006. Determine, in all the occupied address pages, a second target address page that meets the second preset condition;

The second preset condition is an address page of the occupied address paging whose access frequency is less than a preset value;

That is, when the sum of the address spaces of all the free address pages is smaller than the target peripheral address space, the controller counts the access frequency of all occupied address page address spaces to determine the occupied address. Address paging in the paging that is less than the preset value.

1007. Release the mapping relationship between the second target address paging and the peripheral address space.

1008. Determine, in all of the free address pagings and the second target address paging, the first target address paging that satisfies the first preset condition.

The controller uses the second target address paging whose access frequency is less than a preset value to establish the mapping relationship, so that the logic resources of the controller can be utilized well, and the logic of the controller is avoided. The idleness of resources.

1009. Establish a mapping relationship between each of the first target address pages and the target peripheral address space.

1010. Map the target peripheral address space to the address space of the first target address page according to the mapping relationship;

1011. Determine a virtual address of each of the first target address pages;

1012. Rearrange the virtual addresses of each of the first target address pages to form a continuous virtual address segment.

For the specific implementation process of the steps 1009 to 1012 in this embodiment, please refer to the steps 507 to 510 shown in FIG. 5, which are not specifically described in this embodiment.

The controller provided in this embodiment is capable of avoiding waste of address resources caused by mapping an address space that cannot be accessed by the controller in the external device to the controller, and the first selected The size of the address space of the target address page can be matched with the target peripheral address space, which effectively saves the address resource of the controller. In this embodiment, the controller is further capable of each first item The address address is paged to rearrange to form a continuous virtual address segment, reducing the burden on the system when accessing the non-contiguous virtual address segment, and because the controller will access the frequency less than the preset value The two target address paging is used to establish the mapping relationship, so that the logical resources of the controller can be utilized well, and the logical resources of the controller are prevented from being idle.

The specific structure of the controller is described in detail below with reference to FIG. 11:

As shown in FIG. 11, the controller includes:

a first determining unit 1101, configured to determine address paging, where the address paging is divided by an address space of a controller to form;

The second determining unit 1102 is configured to determine a target peripheral address space, where the target peripheral address space is a peripheral device requesting an external address space that is currently mapped to the address space, where the address space is used for mapping Accessing to the target peripheral address space on the address space;

a third determining unit 1103, configured to determine that the address paging that meets the first preset condition is a first target address paging, and the first preset condition is that a sum of address spaces of all the first target address paging is greater than or Equal to the target peripheral address space;

The establishing unit 1104 is configured to establish a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the The first destination address is paged on the address space.

The controller shown in this embodiment is capable of determining an address space of the controller as address paging, thereby enabling the controller to determine the content satisfying the first preset condition according to a size of a target peripheral address space of the external device. The first target address is paged, and the mapping relationship in the embodiment establishes a correspondence between the address space of the first target address page and the effective target peripheral address space that the external device can be accessed by the controller. Therefore, the waste of address resources caused by mapping an address space that cannot be accessed by the controller to the controller in the external device is avoided, that is, in this embodiment, mapping to the address space of the controller The target peripheral address space can be accessed by the controller, which effectively ensures the reasonable configuration of the address resource of the controller and saves the address resource of the controller.

The specific structure of the controller capable of saving address resources is described in detail below with reference to FIG. 12:

The controller includes:

a dividing unit 1201, configured to divide the address space to form a plurality of the address pages, a sum of address spaces of all the address pages is equal to the address space, and an address space of each of the address pages is a power of 2 square;

a first determining unit 1202, configured to determine address paging, where the address paging is divided by an address space of the controller to form;

The second determining unit 1203 is configured to determine a target peripheral address space, where the target peripheral address space is a peripheral device requesting an external address space that is currently mapped to the address space, where the address space is used for mapping Accessing to the target peripheral address space on the address space;

The fourth determining unit 1204 is configured to determine a free address page, where the free address page is an address page that does not currently have a mapping relationship with a peripheral address space of the external device;

The third determining unit 1205 is configured to: if it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, determine, in all the free address pages, that the first preset condition is met Describe the first target address page;

The establishing unit 1206 is configured to establish a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the The first target address is paged on the address space;

The eighth determining unit 1207 is configured to map the target peripheral address space to the address space of the first target address paging according to the mapping relationship;

a ninth determining unit 1208, configured to determine a virtual address of each of the first target address pages;

The tenth determining unit 1209 is configured to rearrange the virtual addresses of each of the first target address pages to form a continuous virtual address segment.

The controller provided in this embodiment is capable of avoiding waste of address resources caused by mapping an address space that cannot be accessed by the controller in the external device to the controller, and the first selected The size of the address space of the target address page can be matched with the target peripheral address space, which effectively saves the address resource of the controller. In this embodiment, the controller is further capable of rearranging the first target address pages to form a continuous virtual address segment, thereby reducing the burden on the system when accessing the non-contiguous virtual address segments.

The specific structure of the controller for avoiding the idleness of the logic resources is described in detail below with reference to FIG. 13:

The controller includes:

a dividing unit 1301, configured to divide the address space to form a plurality of the address pages, a sum of address spaces of all the address pages is equal to the address space, and an address space of each of the address pages is a power of 2 square;

a first determining unit 1302, configured to determine address paging, where the address paging is divided by an address space of the controller to form;

a second determining unit 1303, configured to determine a target peripheral address space, where the target peripheral address space is an external device requesting a peripheral address space currently mapping with the address space, where the address space is used for mapping Accessing to the target peripheral address space on the address space;

The fifth determining unit 1304 is configured to determine a free address page and an occupied address page, where the occupied address page is an address page that has been mapped to a peripheral device address space of the external device, where the free address page is currently not associated with The peripheral address space of the external device establishes the address paging of the mapping relationship;

a sixth determining unit 1305, configured to determine, in all the occupied address pages, a second that satisfies a second preset condition, if it is determined that a sum of address spaces of all the free address pages is smaller than the target peripheral address space The target address is paged, and the second preset condition is an address page in the occupied address page whose access frequency is less than a preset value;

The seventh determining unit 1306 is configured to release the mapping relationship between the second target address paging and the peripheral address space.

The third determining unit 1307 is configured to determine, in all the free address pagings and the second target address paging, the first target address paging that meets the first preset condition.

The establishing unit 1308 is configured to establish a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the The first destination address is paged on the address space.

The eighth determining unit 1309 is configured to map the target peripheral address space to the address space of the first target address paging according to the mapping relationship;

a ninth determining unit 1310, configured to determine a virtual address of each of the first target address pages;

The tenth determining unit 1311 is configured to rearrange the virtual addresses of each of the first target address pages to form a continuous virtual address segment.

The controller provided in this embodiment is capable of avoiding waste of address resources caused by mapping an address space that cannot be accessed by the controller in the external device to the controller, and the first selected The size of the address space of the target address page can be matched with the target peripheral address space, which effectively saves the address resource of the controller. In this embodiment, the controller is further capable of rearranging the first target address pages to form a continuous virtual address segment, thereby reducing the burden on the system when accessing the non-contiguous virtual address segments, and The controller uses the second target address paging whose access frequency is less than a preset value to establish the mapping relationship, so that the logical resources of the controller can be utilized well, and the logical resources of the controller are avoided. Idle.

11 to 13 above illustrate the specific structure of the controller from the perspective of the functional module. The specific structure of the controller is described in detail below from the perspective of the entity as shown in FIG. 14:

As shown in Figure 14, the controller 140 includes a bridge 1401 and a physical line sequence controller 1402;

The bridge 1401 is responsible for docking an internal bus of the computer system;

The physical line sequence controller 1402 is configured to interface with a control line sequence of a specific external device;

Specifically, the bridge 1401 is configured to determine address paging, where the address paging is divided by an address space of the controller to form;

More specifically, the bridge 1401 is also used to:

Dividing the address space to form a plurality of the address pages, addresses of all of the address pages The sum of the spaces is equal to the address space, and the address space of each of the address pages is a power of two.

More specifically, the bridge 1401 is also used to:

If it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, the first target address page that satisfies the first preset condition is determined in all of the free address pages.

More specifically, the bridge 1401 is also used to:

Determining, in all of the occupied address pages, a second target address page that satisfies a second preset condition, if the sum of the address spaces of all the free address pages is smaller than the target peripheral address space, the second The preset condition is that the access frequency in the occupied address paging is less than a preset address paging;

More specifically, the bridge 1401 is also used to:

Determining a virtual address of each of the first target address pages;

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative For example, the division of the unit is only a logical function division, and the actual implementation may have another division manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be Ignore, or not execute. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents of the technical solutions of the embodiments of the present invention.

Claims

A paging address space management method, comprising:

Determining address paging, which is divided by the address space of the controller to form;

Determining a target peripheral address space, where the external device requests a peripheral address space that is currently mapped to the address space, and the address space is used to map to the address space The target peripheral address space is accessed;

Determining that the address page that meets the first preset condition is paged as a first target address, and the first preset condition is that a sum of address spaces of all the first target address pages is greater than or equal to the target peripheral address space ;

Establishing a mapping relationship between each of the first target address pages and the target peripheral address space, where the mapping relationship is used to map the target peripheral address space to the first target address page according to the mapping relationship On the address space.
The paging address space management method according to claim 1, wherein before the determining the address paging, the method further comprises:

The address space is divided to form a plurality of the address pages, the sum of the address spaces of all the address pages is equal to the address space, and the address space of each of the address pages is a power of two.
The paging address space management method according to claim 1 or 2, wherein after the determining the address paging, the method further comprises:

Determining a free address page that is an address page that does not currently have a mapping relationship with an external device's peripheral address space;

After the determining the target peripheral address space, the method further includes:

If it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, the determining that the address paging satisfying the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages.
The paging address space management method according to claim 1 or 2, wherein after the determining the address paging, the method further comprises:

Determining a free address page and an occupied address page, the occupied address page is an address page that has been mapped to a peripheral device address space of the external device, and the free address page is currently not The peripheral address space of the device establishes the address page of the mapping relationship;

After the determining the target peripheral address space, the method further includes:

If the sum of the address spaces of all the free address pages is determined to be smaller than the target peripheral address space, the method further includes:

Determining, in all of the occupied address pages, a second target address page that satisfies a second preset condition, where the second preset condition is an address page in the occupied address page whose access frequency is less than a preset value;

Dissolving the mapping relationship between the second target address page and the peripheral address space that has been established;

The determining that the address paging that meets the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages and in the second target address page.
The paging address space management method according to claim 1, wherein after the mapping of each of the first target address pages and the target peripheral address space is established, the method further includes:

Mapping the target peripheral address space to the address space of the first target address page according to the mapping relationship;

Determining a virtual address of each of the first target address pages;

The virtual addresses of each of the first target address pages are rearranged to form a continuous virtual address segment.
A controller, comprising:

a first determining unit, configured to determine address paging, where the address paging is divided by an address space of the controller to form;

a second determining unit, configured to determine a target peripheral address space, where the target peripheral address space is a peripheral device requesting an external address space that is currently mapped to the address space, where the address space is used to map to Accessing the target peripheral address space on the address space;

a third determining unit, configured to determine that the address paging that meets the first preset condition is a first target address paging, and the first preset condition is that a sum of address spaces of all the first target address paging is greater than or equal to The target peripheral address space;

a establishing unit, configured to establish each of the first target address paging and the target peripheral address space Mapping relationship, the mapping relationship is used to map the target peripheral address space to the address space of the first target address page according to the mapping relationship.
The controller according to claim 6, further comprising:

a dividing unit, configured to divide the address space to form a plurality of the address pages, a sum of address spaces of all the address pages is equal to the address space, and an address space of each of the address pages is a power of 2 .
The controller according to claim 6 or 7, further comprising:

a fourth determining unit, configured to determine a free address page, where the free address page is an address page that does not currently have a mapping relationship with an external device address space of the external device;

The third determining unit is further configured to: if it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, determine, in all the free address pages, that the first preset condition is met The first target address is paged.
The controller according to claim 6 or 7, further comprising:

a fifth determining unit, configured to determine a free address page and an occupied address page, wherein the occupied address page is an address page that has been mapped to a peripheral device address space of an external device, and the free address page is currently not external The peripheral address space of the device establishes the address paging of the mapping relationship;

a sixth determining unit, configured to determine, in all of the occupied address pages, a second target that satisfies a second preset condition, if it is determined that a sum of address spaces of all the free address pages is smaller than the target peripheral address space Address paging, the second preset condition is an address paging of the occupied address paging whose access frequency is less than a preset value;

a seventh determining unit, configured to cancel the mapping relationship between the second target address paging and the peripheral address space;

The third determining unit is further configured to determine, in all of the free address pagings and the second target address paging, the first target address paging that satisfies the first preset condition.
The controller according to claim 6, further comprising:

An eighth determining unit, configured to map the target peripheral address space to the address space of the first target address paging according to the mapping relationship;

a ninth determining unit, configured to determine a virtual address of each of the first target address pages;

a tenth determining unit, configured to rearrange virtual addresses of each of the first target addresses A continuous virtual address segment.
A system comprising a processor, a controller and a memory;

The controller is configured to determine an address page, the address page is divided by an address space of the controller to form, and a target peripheral address space is determined, where the target peripheral address space is an external device requesting a mapping with the address space. a peripheral address space of the relationship, the address space is used to access the target peripheral address space mapped to the address space; determining the address paging that satisfies the first preset condition as the first target Address paging, the first preset condition is that a sum of address spaces of all the first target address pages is greater than or equal to the target peripheral address space; establishing each of the first target address pages and the target peripheral A mapping relationship of the address space, the mapping relationship is used to map the target peripheral address space to the address space of the first target address page according to the mapping relationship.
The system according to claim 11, wherein said controller is further configured to:

The address space is divided to form a plurality of the address pages, the sum of the address spaces of all the address pages is equal to the address space, and the address space of each of the address pages is a power of two.
The system according to claim 11 or 12, wherein after the controller is configured to determine address paging, the controller is further configured to:

Determining a free address page that is an address page that does not currently have a mapping relationship with an external device's peripheral address space;

After determining the target peripheral address space, the controller is further configured to:

If it is determined that the sum of the address spaces of all the free address pages is greater than the target peripheral address space, the determining that the address paging satisfying the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages.
The system according to claim 11 or 12, wherein after the determining the address paging, the controller is further configured to:

Determining a free address page and an occupied address page, the occupied address page is an address page that has been mapped to an external device's peripheral address space, and the free address page is not currently associated with an external device's peripheral address space. Address paging of the mapping relationship;

After determining the target peripheral address space, the controller is further configured to:

If it is determined that the sum of the address spaces of all the free address pages is smaller than the target peripheral address space,

Determining, in all of the occupied address pages, a second target address page that satisfies a second preset condition, where the second preset condition is an address page in the occupied address page whose access frequency is less than a preset value;

Dissolving the mapping relationship between the second target address page and the peripheral address space that has been established;

The determining that the address paging that meets the first preset condition is the first target address paging comprises:

The first target address page that satisfies the first preset condition is determined in all of the free address pages and in the second target address page.
The system according to claim 11, wherein after the establishing a mapping relationship between each of the first target address pages and the target peripheral address space, the controller is further configured to:

Mapping the target peripheral address space to the address space of the first target address page according to the mapping relationship;

Determining a virtual address of each of the first target address pages;

The virtual addresses of each of the first target address pages are rearranged to form a continuous virtual address segment.
A computer storage medium, comprising a program, when the program is executed, the method of any one of claims 1-5 is performed.