CN103970680A - Memory management method and device and embedded system - Google Patents
Memory management method and device and embedded system Download PDFInfo
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Abstract
The embodiment of the invention discloses a memory management method and device and an embedded system. The method includes the steps that when current memory residual resources of a memory in an SOC are larger than or equal to K and an idle physical memory block of which the space is larger than or equal to K does not exist in the memory in the SOC, N idle physical memory blocks in the memory of the SOC are used for constructing virtual memory blocks of which the virtual addresses are continuous and the size of the space is K, and the virtual memory blocks are distributed, wherein K represents the size of memory space to be applied, the size of total space of the N idle physical memory blocks is K, N is an integer larger than or equal to 2, and the physical address of the physical memory blocks is continuous; in the initial process, the memory of the SOC is a whole idle memory block. Thus, the discrete idle physical memory blocks are combined into the virtual memory blocks of which the addresses are continuous, and therefore distribution of space with the continuous addresses is achieved.
Description
Technical field
The present invention relates to field of computer technology, more particularly, relate to EMS memory management process, device and embedded system.
Background technology
Embedded system can be applicable in several scenes, relates to the management to internal memory in the system level chip in embedded system (System On Chip, SOC) sheet in several scenes.
In existing mode, can use internal memory in dynamical fashion management SOC sheet.But after system operation a period of time, often can there is discrete physical address section.Under some scene, although current internal memory surplus resources is more than or equal to the memory headroom size of application, because physical address section is spatially disperseed, cannot realize the distribution in continuation address space, thereby cause internal memory application failure.
By way of example, the size of supposing a physical address is b, current physical address section P001～P100, and P200～P400 is idle available, also, current internal memory surplus resources is 300b.Memory headroom size (also can be described as byte number) to be applied for can be expressed as K, suppose that K=240b is less than 300b, but because the address of P001～P100 and P200～P400 is discontinuous (being also to disperse on space), thereby cannot distribute, will cause like this internal memory application failure.
Summary of the invention
In view of this, the object of the embodiment of the present invention is to provide EMS memory management process, device and embedded system, although be more than or equal to the memory headroom size of application to solve current internal memory surplus resources, but because physical memory space spatially disperses, cannot realize the distribution in contiguous memory space, thereby cause the problem of internal memory application failure.
For achieving the above object, the embodiment of the present invention provides following technical scheme:
According to the first aspect of the embodiment of the present invention, a kind of EMS memory management process, comprising:
Be more than or equal to K in response to the current internal memory surplus resources of internal memory in system level chip SOC sheet, simultaneously, in internal memory, Existential Space size is not more than or equal to the idle physical memory piece of K in described SOC sheet, use the N in internal memory idle physical memory piece in described SOC sheet to build the virtual memory piece that virtual address is continuous, space size is K, and distribute described virtual memory piece as memory headroom to be applied for;
Described K represents the space size of memory headroom to be applied for; The gross space size of described N idle physical memory piece equals described K, and described N is more than or equal to 2 integer; Physical address in described physical memory piece is continuous; Described in when initial, save as a monoblock free memory block in SOC sheet.
In conjunction with first aspect, in the implementation of the first energy, also comprise: the idle physical memory piece that is greater than K in response to Existential Space size in internal memory in described SOC sheet, the idle physical memory piece that described space size is greater than to K is divided into m idle physical memory piece, and in described m idle physical memory piece, Existential Space size equals the idle physical memory piece of K; Described m is more than or equal to 2; Distribute idle physical memory piece that described space size equals K as memory headroom described to be applied for.
In conjunction with first aspect or the possible implementation of first aspect the first, in the possible implementation of the second, also comprise: in response to memory block release command, determine whether the memory block that described memory block release command is specified is physical memory piece; If the memory block of specifying is physical memory piece, directly discharge the memory block of described appointment; If the memory block of specifying is not physical memory piece, discharge the each physical memory piece comprising in the memory block of described appointment.
In conjunction with the possible implementation of first aspect the second, in the third possible implementation, after the each physical memory piece comprising in directly discharging the memory block of described appointment or discharging the memory block of described appointment, also comprise: determine that whether the physical memory piece adjacent with the physical memory piece discharging be idle, if idle, discharged physical memory piece and adjacent physical memory piece are merged, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
In conjunction with first aspect to any one in the third possible implementation of first aspect, in the 4th kind of possible implementation, N in described SOC sheet in an internal memory idle physical memory piece obtains in the following way: the gross space size at M idle physical memory piece is greater than described K, but when in described M idle physical memory piece, the gross space size of M-1 idle physical memory piece is less than described K arbitrarily, an idle physical memory piece in described M idle physical memory piece is divided into m idle physical memory piece, obtain M+m-1 idle physical memory piece, wherein, the gross space size of N idle physical memory piece in described M+m-1 idle physical memory piece equals described K, m is more than or equal to 2, M=N.
In conjunction with first aspect to any one in the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation, described structure comprises: set up the mapping relations between described N the physical address in idle physical memory piece and the virtual address in described virtual memory piece; Described mapping relations are saved to address mapping table.
In conjunction with the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, after discharging the each physical memory piece comprising in the memory block of described appointment, also comprise: upgrade described address mapping table.
According to the second aspect of the embodiment of the present invention, a kind of memory management device is provided, comprising:
The first memory management unit, for being more than or equal to K in response to the current internal memory surplus resources of internal memory in system level chip SOC sheet, simultaneously, in internal memory, Existential Space size is not more than or equal to the idle physical memory piece of K in described SOC sheet, use the N in internal memory idle physical memory piece in described SOC sheet to build the continuous virtual memory piece of virtual address, and distribute described virtual memory piece as memory headroom to be applied for; Described in when initial, save as a monoblock free memory block in SOC sheet;
Described K represents the space size of memory headroom to be applied for; The gross space size of described N idle physical memory piece equals described K, and described N is more than or equal to 2 integer; Physical address in described physical memory piece is continuous.
In conjunction with second aspect, in the possible implementation of the first, also comprise the second memory management unit, be used for: the idle physical memory piece that is greater than K in response to internal memory Existential Space size in described SOC sheet, the idle physical memory piece that described space size is greater than to K is divided into m idle physical memory piece, and in described m idle physical memory piece, Existential Space size equals the idle physical memory piece of K; Described m is more than or equal to 2; Distribute idle physical memory piece that described space size equals K as memory headroom described to be applied for.
In conjunction with second aspect or the possible implementation of second aspect the first, in the possible implementation of the second, also comprise internal memory release management unit, for: in response to memory block release command, determine whether the memory block that described memory block release command is specified is physical memory piece; If the memory block of specifying is physical memory piece, directly discharge the memory block of described appointment; If the memory block of specifying is not physical memory piece, discharge the each physical memory piece comprising in the memory block of described appointment.
In conjunction with the possible implementation of second aspect the second, in the third possible implementation, also comprise: idle physical block setting unit, after directly discharging the memory block of described appointment in described internal memory release management unit or discharging each physical memory piece that the memory block of described appointment comprises, determine that whether the physical memory piece adjacent with the physical memory piece discharging be idle, if idle, discharged physical memory piece and adjacent physical memory piece are merged, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
According to the third aspect of the embodiment of the present invention, a kind of embedded system is provided, comprise internal memory in SOC sheet, processor and if the third aspect is to the memory management device as described in any one in the third possible implementation of the third aspect.
Visible, in embodiments of the present invention, be more than or equal to the memory headroom size of application at current internal memory surplus resources, but in the situation that physical memory space spatially disperses (be also, the current internal memory surplus resources of physical memory is more than or equal to the size of memory headroom to be applied for, meanwhile, there is not the big or small idle physical memory piece that is more than or equal to memory headroom to be applied for), be the virtual memory piece of K by continuous idle physical memory piece structure virtual address, size.Like this, just discrete idle physical memory piece is formed to the continuous virtual memory piece in address, thereby realized the distribution in continuation address space.Solve because physical memory space spatially disperses, cannot realize the distribution in continuation address space, thereby caused the problem of internal memory application failure.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The memory management application scenarios schematic diagram that Fig. 1 provides for the embodiment of the present invention;
The EMS memory management process process flow diagram that Fig. 2 provides for the embodiment of the present invention;
The logical memory structural representation that Fig. 3 provides for the embodiment of the present invention;
Another process flow diagram of EMS memory management process that Fig. 4 a provides for the embodiment of the present invention;
The segmentation paging system Memory Storage schematic diagram that Fig. 4 b provides for the embodiment of the present invention;
The another process flow diagram of EMS memory management process that Fig. 5 provides for the embodiment of the present invention;
The another process flow diagram of EMS memory management process that Fig. 6 provides for the embodiment of the present invention;
The memory management apparatus structure schematic diagram that Fig. 7 provides for the embodiment of the present invention;
Another structural representation of memory management device that Fig. 8 provides for the embodiment of the present invention;
The Embedded System Structure schematic diagram that Fig. 9 provides for the embodiment of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embedded system can be applicable in several scenes, relates to the management to internal memory in the system level chip in embedded system (System On Chip, SOC) sheet in several scenes.
Be treated to example with base station baseband, inventor finds, in base band, be static manual management to memory management major part at present, namely the memory block size of all programs or service needed use is distributed by maximal value at system design stage, make Memory Allocation form, in reality, the memory block distributing according to advance notice distributes use.And in band processing system, number of users and the data volume in each frame, processed are different, even if cause for same program or business, the big or small fluctuation ratio of the memory block really needing under different situations is larger, therefore, static manual management mode can be wasted internal memory.
For solving the shortcoming of static manual management mode, inventor also finds, also has and uses dynamical fashion managing internal memory.But there are the following problems to use dynamical fashion managing internal memory:
But after system operation a period of time, often can there is discrete physical address section.Under some scene, although current internal memory surplus resources is more than or equal to the memory headroom size of application, because physical address section is spatially disperseed, cannot realize the distribution in continuation address space, thereby cause internal memory application failure.
By way of example, the size of supposing a physical address is b, current physical address section P001～P100, and P200～P400 is idle available, also, current internal memory surplus resources is 300b.The large I of memory headroom to be applied for is expressed as K, suppose that K=240b is less than 300b, but because the address of P001～P100 and P200～P400 is discontinuous (being also to disperse on space), thereby cannot distribute, will cause like this internal memory application failure.This discrete physical address section can be referred to as memory fragmentation.
Inventor finds, can solve in the following way memory fragmentation:
If it is looser to find that memory fragmentation distributes, fragment rate is more serious, and the operation low or interim interrupt routine idle in the situation that in core load, reclaims and all internal memories of initialization again.
Inventor finds, in the actual scene of base station baseband, can have thread and the business of operation in each subframe simultaneously, and this mode can cause business temporarily to be interrupted.And from actual simulated effect, every a few minutes internal memory clearly once, this means every a few minutes, individual user is just by flash certain hour, and this will affect communication quality.
The embodiment of the present invention provides a kind of EMS memory management process, to solve the memory fragmentation problem of dynamic memory management mode.
Above-mentioned EMS memory management process can for example, be carried out by the hardware (memory management device) that is independent of SOC, also can be realized by software.
Referring to Fig. 1, is a kind of memory management application scenarios that the embodiment of the present invention is set, and comprises internal memory 1, processor 2 (or being called core) and memory management device 3 in SOC sheet.In SOC sheet, internal memory 1 and processor 2 can form embedded system (or SOC (system on a chip)), and in other words, in SOC sheet, internal memory 1 and processor 2 can be encapsulated in a chip.In addition, in SOC sheet, internal memory 1, processor 2 and memory management device 3 also can form embedded system (or SOC (system on a chip)), and in other words, in SOC sheet, internal memory 1, processor 2 and memory management device 3 can be encapsulated in a chip.
In SOC sheet, internal memory 1, processor 2 can be communicated by letter by bus or other modes each other with memory management device 3, realize information mutual communication and the memory management to internal memory 1 in SOC sheet.
Internal memory 1 can be used for producing between storage of processor 2 operational stages in SOC sheet intermediate data, storage operation system, application program etc.Processor 2 has different functions or effect in different application scenarioss.Taking Base-Band Processing as example, processor 2 the most basic functions have been the one or more processing operations in Base-Band Processing.
It should be noted that, although show in a SOC sheet internal memory 1, processor 2 and a memory management device 3 in Fig. 1, in fact, an embedded system may comprise internal memory 1 in multiple processors 2 and multiple SOC sheet.Can adopt a memory management device 3 to manage internal memory 1 in multiple SOC sheets, also can adopt multiple memory management devices 3 to manage internal memory 1 in multiple SOC sheets.The present invention does not do concrete restriction.
Refer to Fig. 2, said method can comprise the steps:
S1, be more than or equal to K (K represents the space size of memory headroom to be applied for) in response to the current internal memory surplus resources of internal memory in SOC sheet, simultaneously, in above-mentioned SOC sheet, in internal memory, there is not the idle physical memory piece that is more than or equal to K, use the idle physical memory piece (N is more than or equal to 2 integer) of the N in internal memory in above-mentioned SOC sheet to build the virtual memory piece that virtual address is continuous, space size is K, and distribute above-mentioned virtual memory piece as memory headroom above-mentioned to be applied for.
The gross space size of above-mentioned N idle physical memory piece equals K.And the physical address in above-mentioned physical memory piece is continuous.
When initial, whole SOC sheet is interior saves as a large idle physical memory piece.In other words, when initial, the interior idle physical memory piece of a monoblock that saves as of SOC sheet.
Visible, in embodiments of the present invention, be more than or equal to the memory headroom size of application at current internal memory surplus resources, but in the situation that physical memory space spatially disperses (be also, the current internal memory surplus resources of physical memory is more than or equal to the size of memory headroom to be applied for, meanwhile, there is not the big or small idle physical memory piece that is more than or equal to memory headroom to be applied for), be the virtual memory piece of K by continuous idle physical memory piece structure virtual address, size.Like this, just discrete idle physical memory piece is formed to the continuous virtual memory piece in address, thereby realized the distribution in continuation address space.Solve because physical memory space spatially disperses, cannot realize the distribution in continuation address space, thereby caused the problem of internal memory application failure.
More specifically, what memory management device for example, showed to extraneous (user) is logical memory, provides logical address to the external world.
Refer to Fig. 3, the virtual address space that this logical memory comprises physical address space and expansion.Logical address in physical address space is actual is physical address, and logical address in virtual address space actual be virtual address.
The size of supposing a physical address is b byte, and in fact, in SOC sheet, internal memory is divided a storage unit with b byte, a physical address in the corresponding physical address space of each storage unit.
In other words, physical address space shines upon mutually with the interior internal memory of SOC sheet, and in SOC sheet, the space size of internal memory and the space size of physical address space equate.
And the space size of virtual address space is the more than a times or a times of physical address space.
By way of example, suppose that the space size of internal memory in SOC is 1G, corresponding, the space size of physical address space is also 1G.On this basis, one times or one times above virtual address space of expansion.Suppose, in physical address space, comprise A0001-A1000 logical address (physical address).The size of virtual address space is at least 1G, and it can at least comprise A1001-A2000 logical address (being also virtual address).
Certainly, for extraneous (for example, for user), logical memory accessible space size is 2G, and it comprises A0001-A2000 logical address.And for memory management device 2, physical memory space size is 1G.
Based on physical address space and virtual address space, existing lift a simply example for step S1, understand the above embodiment of the present invention and how to realize memory management to facilitate:
The size of supposing a physical address is b, and suppose in current SOC sheet have 2 idle physical memory pieces in internal memory, one of them idle physical memory piece is A0001～A0100 in range of physical addresses corresponding to physical address space, and another idle physical memory piece is A0201～A0400 in range of physical addresses corresponding to physical address space.Also, current internal memory surplus resources is 300b.In other words, the gross space of above-mentioned 2 idle physical memory pieces size is 300b.
Suppose, the space size of memory headroom to be applied for is also 300b just, is also that K equals current internal memory surplus resources, available above-mentioned 2 idle physical memory pieces build a virtual address continuously, size is the virtual memory piece of K.
But also there is in actual applications, the situation of " not lucky ":
Suppose, 3 idle physical memory pieces of current existence, the space size of these 3 idle physical memory pieces is respectively 100b, 200b, 200b.Also, current internal memory surplus resources is 500b.
And memory size to be applied for is 450b.
Also, the gross space size of above-mentioned 3 idle physical memory pieces is greater than K, but wherein the gross space size of wantonly 2 idle physical memory pieces is less than again K.
In such cases, can proceed as follows to obtain gross space size and equal N the idle physical memory piece of K:
One of them idle physical memory piece in M idle physical memory piece is divided into m idle physical memory piece (m is not less than 2), obtain M+m-1 idle physical memory piece, wherein, the gross space size of N idle physical memory piece in this M+m-1 idle physical memory piece equals above-mentioned K.
Still continue to use precedent, can cut apart an idle physical memory piece in above-mentioned idle physical memory piece 1-3 (being also M=3).
So that idle physical memory piece 3 is divided into example, can be divided into two (m) idle physical memory pieces, for the purpose of difference, can be called idle physical memory piece 4 and idle physical memory piece 5 by cutting apart these two idle physical memory pieces that obtain, wherein, idle physical memory piece 4 sizes are 150b, and idle physical memory piece 5 sizes are 50b.
In the time cutting apart, can adopt existing partitioning scheme, such as widely used TLSF (Two LevelSegregated Fit) algorithm, idle physical memory piece is cut apart.
Like this, 3 (M) individual idle physical memory piece has just become 4 (M+m-1) individual idle physical memory piece, and the gross space size of idle physical memory piece 1,2,4 equals K (450b).
Idle physical memory piece 1,2,4 is above-mentioned gross space size and equals N the idle physical memory piece of described K.Follow-up available free physical memory piece 1,2,4 structure virtual addresses (logical address) are continuous, size is the virtual memory piece of 450b.
More specifically, can select minimum idle physical memory piece number to build virtual memory piece.
For example, have 5 idle physical memory pieces, wherein the total idle size of 2 idle physical memory pieces is greater than K, and the total idle size of other 3 idle physical memory pieces is greater than K, selects above-mentioned 2 idle physical memory pieces to build virtual memory piece.
It should be noted that, for example user to external world, its institute " sees ", has distributed the memory block that address is continuous, size is K for oneself, user can not distinguish virtual memory piece and physical memory piece, can not distinguish virtual address and physical address.For user, virtual address and physical address are all logical addresses.
The available chained list of relation between physical memory piece or virtual memory piece represents.
In order to save time, improve search efficiency, physical address space and virtual address space can adopt independently chained list.
In other embodiments of the invention, the structure in above-mentioned all embodiment step S1 can comprise the steps:
Set up the mapping relations between above-mentioned N the physical address in idle physical memory piece and the logical address in above-mentioned virtual memory piece;
Above-mentioned mapping relations are saved to address mapping table.
More specifically, can set up the mapping relations between the physical address in each logical address and above-mentioned N the idle physical memory piece in above-mentioned virtual memory piece.
Or, also can set up initial physical address in N idle physical memory piece and finish the relation of the logical address in physical address and virtual memory piece.
By way of example, suppose that the size of internal memory in SOC sheet is 1G, altogether a corresponding A 0001-A1000 physical address.Virtual memory space comprises A1001-A2000 virtual address.In current SOC sheet, in internal memory, there are 2 idle physical memory pieces, one of them idle physical memory piece is A0001～A0100 in range of physical addresses corresponding to physical address space, and another idle physical memory piece is A0201～A0400 in range of physical addresses corresponding to physical address space.And the size of internal memory to be applied for is 300b.
Suppose, the initial logical address of distributing to user's virtual memory piece is A1001, and end logical address is A1300.
The logical address A1001 in the initial physical address A0001 of one of them idle physical memory piece and virtual memory piece can be set up to mapping relations, the logical address A1100 being finished in physical address A0100 and virtual memory piece sets up mapping relations, and the logical address A1101 in the initial physical address A0201 of another idle physical memory piece and virtual memory piece is set up to mapping relations, the logical address A1300 being finished in physical address A0400 and virtual memory piece sets up mapping relations.
Vice versa, also the logical address A1001 in above-mentioned virtual memory piece and A1200 can be set up to mapping relations with physical address A0201 and physical address A0400 respectively, and the logical address A1201 in virtual memory piece and A1300 are set up to mapping relations with physical address A0001 and A0100 respectively.
In other embodiments of the invention, the form of the address mapping table in above-mentioned all embodiment can be as shown in table 1 below:
Table 1
Now continue to use precedent explanation address mapping table.Suppose, logical address A1001 in the initial physical address A0001 of idle physical memory piece 1 and virtual memory piece is set up to mapping relations, the logical address A1100 being finished in physical address A0100 and virtual memory piece sets up mapping relations, and the logical address A1101 in the initial physical address A0201 of idle physical memory piece 2 and virtual memory piece is set up to mapping relations, the logical address A1300 being finished in physical address A0400 and virtual memory piece sets up mapping relations.Its record in address mapping table can be as shown in table 2 below.
Table 2
It should be noted that, owing to having recorded logic end address, the end physical address of physical memory piece can calculate and draw, therefore end of record (EOR) physical address in address mapping table not.
As user needs the data in access logic address, the logical address of wish access can be provided to internal memory management devices, memory management device can be converted to physical address by the logical address of above-mentioned wish access, thereby continuous virtual address space is mapped on discrete physical address space.
By way of example, suppose that the logical address of wish access is 0x1200, memory management device inquire address mapping table has individual list item in address mapping table, and logic start address is 0x1000, and logic end address is 0x1300, and physical address is 0x0200.The logical address of wish access drops between 0x1000～0x1300, illustrates, the logical address of this wish access belongs to virtual address space.
Memory management device can be converted to physical address by logical address according to following formula:
0x0200+(0x1200-0x1000)＝0x0400。
As the logical address of wish access does not fall between the arbitrary logic start address of address mapping table and logic end address, the logical address that can judge the access of user's wish belongs to physical address space, in fact this logical address is exactly physical address, now, does not need to carry out address translation.
Accordingly, the above-mentioned virtual memory piece of the distribution in above-mentioned steps S1 can specifically comprise:
Return to the initial logical address (or claiming initial virtual address) of described virtual memory piece.
As continue to use precedent, be to return to initial logical address A1001.
In other embodiments of the invention, still refer to Fig. 3, above-mentioned EMS memory management process also can comprise the steps:
S0, reception memory headroom application request.
In above-mentioned memory headroom application request, carry the space size of memory headroom to be applied for.
Step S1 carries out after step S0.
In other embodiments of the invention, still refer to Fig. 3, above-mentioned EMS memory management process also can comprise the steps:
S2, be greater than the idle physical memory piece of K in response to Existential Space size in internal memory in above-mentioned SOC sheet, the idle physical memory piece that above-mentioned space size is greater than to K is divided into m idle physical memory piece (m is not less than 2), and in this m idle physical memory piece, Existential Space size equals the idle physical memory piece of K.
It should be noted that, in the time that existence in physical memory is greater than the idle physical memory piece of K, obviously current internal memory surplus resources is greater than K.
S3, distribute the idle physical memory piece of the above-mentioned K of equaling as memory headroom to be applied for.
By way of example, suppose and in current physical memory, have 2 idle physical memory pieces, one of them idle physical memory piece (is difference, be called idle physical memory piece 1) in physical address be that A0001～A0100 (is also, size is 100b), physical address in another idle physical memory piece (for difference, being called idle physical memory piece 2) is A0201～A0400 (also, size is 200b).
Suppose that again memory size to be applied for is 90b, the size of idle physical memory piece 1, idle physical memory piece 2 is all greater than 90b.Therefore, idle physical memory piece 1 or idle physical memory piece 2 can be cut apart.
To cut apart idle physical memory piece 1 as example, can be divided into two idle physical memory pieces, a space size is 90b, another space size is 10b.Then the idle physical memory piece that is, 90b by space size is distributed to user.
Or, aforementioned having mentioned, when initial, SOC sheet is interior saves as a monoblock free memory block (space size of this free memory block is greater than K)., in internal memory application process, can, according to the size of the memory headroom of application, cut the idle physical memory piece of corresponding size from above-mentioned monoblock free memory block and distribute to user.
In the time cutting apart, can adopt existing partitioning scheme, such as widely used TLSF (Two LevelSegregated Fit) algorithm, the free memory block that cuts corresponding size according to the size of user's application is to user.
It should be noted that, in step S2 and S3, be not need to build continuous, the big or small virtual memory piece for K of virtual address.
More specifically, can specifically comprise " the distributing the idle physical memory piece of the above-mentioned K of equaling " in step S3: the initial physical address that returns to the idle physical memory piece of the above-mentioned K of equaling.
Obviously, equal the idle physical memory piece of k as existed, can directly distribute this idle physical memory piece that equals k as internal space above-mentioned to be applied for (also, directly returning to this and equal the initial physical address of the idle physical memory piece of K).
Be one of the step S0-S3 more embodiment of refinement below, refer to Fig. 4 a, it can comprise the steps:
Step 1: receive memory headroom application request;
Step 2: judge that whether current internal memory surplus resources is less than K, if so, goes to step 6, otherwise goes to step 3;
Step 3: judge in SOC sheet whether have the idle physical memory piece that is more than or equal to K in internal memory, if so, go to step 4, otherwise go to step 5;
Step 4: the idle physical memory piece that is more than or equal to K is processed into the idle physical memory piece that equals K, and returns to the initial physical address of the idle physical memory piece of the above-mentioned K of equaling.
More specifically, as Existential Space size equals the idle physical memory piece of K, directly return to the initial physical address of this free time physical memory piece.
As Existential Space size is only greater than the idle physical memory piece of K, it is cut apart, obtain space size and equal the idle physical memory piece of K, and return to space size and equal the initial physical address of the idle physical memory piece of K.Detail refers to aforementioned record herein, and therefore not to repeat here.
Step 5: N the idle physical memory piece that uses gross space size to equal K builds the virtual memory piece that virtual address is continuous, size is K, and distributes above-mentioned virtual memory piece as memory headroom above-mentioned to be applied for.
Detail refers to the description about step S1 herein, and therefore not to repeat here.
Step 6: refusal.
Inventor also finds, existing mode also can be used segmentation paging system memory management, refers to Fig. 4 b, in conjunction with MMU virtual address administrative unit, uses address mapping that discrete physical memory page is mapped on the continuous logical page (LPAGE) of logical memory piece, to eliminate fragment.As shown in Figure 4 b, under segmentation paging system Memory Storage, any one logical memory piece is to be all made up of the physical memory page of fixed size, has not so existed the idle Physical Page that cannot use.
Segmentation paging system memory management adopts the division (such as 4KB) of fixed size to internal memory, and the memory size of user's application is random number, therefore in same page, still has not little waste.For example, user applies for 5KB, for the logical memory block space size of its distribution is 8KB.And the address mapping table of this mode need to cover the address of each physical memory page, list item is huger, such as use 4KB page in 8MB space, need to safeguard 2K list item, and hard-wired area and time delay are all larger.
And in embodiments of the present invention, be to distribute according to the memory headroom size of user's application, therefore can not produce waste.And, in embodiments of the present invention, in the time not there is not the idle physical block of big or small K, just build virtual memory piece, adopt expansion virtual address space to reduce memory fragmentation, and adopt address mapping table to record the mapping relations between virtual memory piece and the physical memory piece of formation virtual memory piece, therefore, address mapping table in the present embodiment does not need to cover each physical memory page or each physical memory piece, and list item is relatively less, thereby hard-wired area and time delay are also less.
And the technical scheme that the embodiment of the present invention provides, can improve the utilization ratio of internal memory, avoids memory fragmentation to increase.According to simulation result, the in the situation that of LTE baseband system fragment rate 10% left and right, adopt scheme provided by the present invention, can make fragment rate drop to below 3%.Further, also having reduced under memory fragmentation distributes relatively loose, the more serious situation of fragment rate, the operation low or interim interrupt routine when idle in core load, reclaims and the Probability of the operation of all internal memories of initialization again.Thereby can reduce the temporary transient probability of happening interrupting of business, improve communication quality.
In practice, memory management device also may receive memory block release command, and this memory block release command can be used for instruction and discharges the memory block of specifying.Refer to Fig. 5, in above-mentioned all embodiment, above-mentioned EMS memory management process also can comprise the steps:
S5, in response to memory block release command, determine whether the memory block that above-mentioned memory block release command is specified is physical memory piece; In memory block release command, comprise the logic start address of the memory block of appointment.
If the memory block that S6 specifies is physical memory piece, directly discharge the memory block of above-mentioned appointment;
If the memory block that S7 specifies is not physical memory piece, discharge the each physical memory piece comprising in the memory block of above-mentioned appointment.
Can determine whether the memory block of specifying is physical memory piece by searching address mapping table.If the logic start address of specified memory piece is not in address mapping table, the memory block that can determine appointment is physical memory piece; Otherwise the memory block that can determine appointment is virtual memory piece.
In addition, the logic start address of virtual memory piece is all higher than the logic start address of physical memory piece.Therefore, also can directly distinguish according to address.
Aforementionedly also recorded, as comprised A0001-A1000 logical address in physical address space, virtual address space at least comprises A1001-A2000 logical address.Therefore, if logic start address is higher than logical address A1001, the memory block that can determine appointment is virtual memory piece, otherwise can determine that the memory block of appointment is physical memory piece.
In other embodiments of the invention, after the each physical memory piece comprising, refer to Fig. 6 in directly discharging the memory block of above-mentioned appointment or discharging the memory block of above-mentioned appointment, in above-mentioned all embodiment, above-mentioned EMS memory management process also can comprise the steps:
S8, determine that whether the physical memory piece adjacent with the physical memory piece that discharges be idle, if idle,, by the physical memory piece of above-mentioned release and the merging of above-mentioned adjacent physical memory piece, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
By way of example, the initial physical address of supposing the physical memory piece of release is A0101, and end physical address is A0200.The physical memory piece being adjacent has two, and one of them initial physical address is A0001, and end physical address is A0100, and another initial physical address is A0201, and end physical address is A0300.
If the physical memory piece being adjacent is not all idle condition, directly the physical memory piece of release is set to the free time.If the physical memory piece free time of A0001-A0100, and another adjacent physical memory piece is not idle, the physical memory piece of the physical memory piece discharging and A0001-A0100 is merged, the initial physical address of the physical memory piece after merging is that A0001, end physical address are A0200, and are set to the free time.
In the time merging, can adopt existing mode, such as widely used TLSF (Two LevelSegregated Fit) algorithm, therefore not to repeat here.
In other embodiments of the invention, still refer to Fig. 6, after discharging the each physical memory piece comprising in the memory block of above-mentioned appointment, in above-mentioned all embodiment, above-mentioned EMS memory management process also can comprise the steps:
S9, renewal address above mentioned mapping table.
The execution sequence of step S8 and step S9 is interchangeable, or executed in parallel.
The embodiment of the present invention is claimed memory management device also, and Fig. 7 shows 700 1 kinds of structures of memory management device, comprising:
The first memory management unit 71 for, be more than or equal to K in response to the current internal memory surplus resources of internal memory in system level chip SOC sheet, simultaneously, in internal memory, Existential Space size is not more than or equal to the idle physical memory piece of K in above-mentioned SOC sheet, use the N in internal memory idle physical memory piece in above-mentioned SOC sheet to build the continuous virtual memory piece of virtual address, and distribute above-mentioned virtual memory piece as memory headroom to be applied for;
Above-mentioned K represents the space size of memory headroom above-mentioned to be applied for; The gross space size of above-mentioned N idle physical memory piece equals K, and above-mentioned N is more than or equal to 2 integer; Physical address in above-mentioned physical memory piece is continuous.
When initial, whole SOC sheet is interior saves as a large idle physical memory piece.In other words, when initial, the interior idle physical memory piece of a monoblock that saves as of SOC sheet.
Particular content refers to aforementioned record herein, and therefore not to repeat here.
In other embodiments of the invention, still refer to Fig. 7, above-mentioned memory management device 700 also can comprise the second memory management unit 72, for:
Be greater than the idle physical memory piece of K in response to Existential Space size in internal memory in above-mentioned SOC sheet, the idle physical memory piece that above-mentioned space size is greater than to K is divided into m idle physical memory piece, and in above-mentioned m idle physical memory piece, Existential Space size equals the idle physical memory piece of K; Above-mentioned m is more than or equal to 2;
Distribute idle physical memory piece that above-mentioned space size equals K as memory headroom above-mentioned to be applied for.
Particular content refers to aforementioned record herein, and therefore not to repeat here.
In other embodiments of the invention, aspect building, the first memory management unit 71 in above-mentioned all embodiment can be used for:
Set up the mapping relations between above-mentioned N the physical address in idle physical memory piece and the virtual address in virtual memory piece;
Above-mentioned mapping relations are saved to address mapping table.
Particular content refers to aforementioned record herein, and therefore not to repeat here.
In other embodiments of the invention, refer to Fig. 8, the memory management device 700 in above-mentioned all embodiment also can comprise internal memory release management unit 73, for:
In response to memory block release command, determine whether the memory block that above-mentioned memory block release command is specified is physical memory piece; If the memory block of specifying is physical memory piece, directly discharge the memory block of above-mentioned appointment; If the memory block of specifying is not physical memory piece, discharge the each physical memory piece comprising in the memory block of above-mentioned appointment.
In other embodiments of the invention, still refer to Fig. 8, the memory management device 700 in above-mentioned all embodiment also can comprise:
Idle physical block setting unit 74, after directly discharging the memory block of above-mentioned appointment in above-mentioned internal memory release management unit 73 or discharging each physical memory piece that the memory block of above-mentioned appointment comprises, determine that whether the physical memory piece adjacent with the physical memory piece discharging be idle, if idle, discharged physical memory piece and adjacent physical memory piece are merged, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
In other embodiments of the invention, still refer to Fig. 8, the memory management device 700 in above-mentioned all embodiment also can comprise:
Updating block 75, after directly discharging the memory block of above-mentioned appointment in above-mentioned internal memory release management unit 73 or discharging each physical memory piece that the memory block of above-mentioned appointment comprises, upgrades address above mentioned mapping table.
Above-mentioned the first memory management unit 71, the second memory management unit 72, internal memory release management unit 73, idle physical block setting unit 74 and updating block 75 can be functional module, also can be hardware module, for example circuit module.
The embodiment of the present invention is claimed embedded system also, and it can comprise internal memory, processor and memory management device in SOC sheet.
Fig. 9 shows a kind of hardware configuration of above-mentioned embedded system, and wherein, memory management device can comprise physics memory management unit and address conversioning unit on hardware.
Physical memory administrative unit and address conversioning unit can be obtained by IP kernel (Intellectual Property core) design.
Although physical memory administrative unit and address conversioning unit belong to same equipment, can divide and be located at different places.The two can pass through bus communication.
In physical memory administrative unit or address conversioning unit and SOC sheet, internal memory, processor also can carry out communication by bus.
Wherein, physical memory administrative unit can further comprise again internal memory application processing unit and internal memory release processing unit.
Internal memory application processing unit can complete above-mentioned the first memory management unit, or, the function of the first memory management unit and the second memory management unit.
Internal memory discharges processing unit can complete above-mentioned internal memory release management unit, or, internal memory release management unit and idle physical block setting unit, or, internal memory release management unit and updating block, or, the function of internal memory release management unit, idle physical block setting unit and idle physical block setting unit.
More specifically, address conversioning unit can comprise shunt and address mapping table.Shunt and address mapping table are hardware device.
Wherein, shunt comprises an input port, two output ports.The input port of one of them output port link address mapping table, another output port connects internal memory in SOC sheet.
The input port of shunt is connected with the output port of processor.
In SOC sheet, internal memory comprises two input ports, and wherein, an output port of the output port of address mapping table and shunt is connected with two input ports of internal memory in SOC sheet.
Processor can be submitted to address conversioning unit the logical address of wish access to.Shunt in address conversioning unit can carry out shunt to it to be processed.
If the logical address of wish access is virtual address, this logical address is exported to address mapping table by shunt, by address mapping table, it carried out to address translation, converts thereof into physical address.
Suppose, the logical address of wish access is 0x1200, and in address mapping table, having individual list item, logic start address is 0x1000, and logic end address is 0x1300, and physical address is 0x0200.The logical address of wish access drops between 0x1000～0x1300.Can logical address be converted to physical address according to following formula: 0x0200+ (0x1200-0x1000)=0x0400.
After conversion, by address mapping table, the physical address after conversion is exported to internal memory in SOC sheet.
If the logical address of wish access is physical address, internal memory in SOC sheet directly exported to this logical address by shunt.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiment, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (12)
1. an EMS memory management process, is characterized in that, comprising:
Be more than or equal to K in response to the current internal memory surplus resources of internal memory in system level chip SOC sheet, simultaneously, in internal memory, Existential Space size is not more than or equal to the idle physical memory piece of K in described SOC sheet, use the N in internal memory idle physical memory piece in described SOC sheet to build the virtual memory piece that virtual address is continuous, space size is K, and distribute described virtual memory piece as memory headroom to be applied for;
Described K represents the space size of memory headroom to be applied for; The gross space size of described N idle physical memory piece equals described K, and described N is more than or equal to 2 integer; Physical address in described physical memory piece is continuous; Described in when initial, save as a monoblock free memory block in SOC sheet.
2. the method for claim 1, is characterized in that, also comprises:
Be greater than the idle physical memory piece of K in response to Existential Space size in internal memory in described SOC sheet, the idle physical memory piece that described space size is greater than to K is divided into m idle physical memory piece, and in described m idle physical memory piece, Existential Space size equals the idle physical memory piece of K; Described m is more than or equal to 2;
Distribute idle physical memory piece that described space size equals K as memory headroom described to be applied for.
3. method as claimed in claim 1 or 2, is characterized in that, also comprises:
In response to memory block release command, determine whether the memory block that described memory block release command is specified is physical memory piece;
If the memory block of specifying is physical memory piece, directly discharge the memory block of described appointment;
If the memory block of specifying is not physical memory piece, discharge the each physical memory piece comprising in the memory block of described appointment.
4. method as claimed in claim 3, is characterized in that, after the each physical memory piece comprising, also comprises in directly discharging the memory block of described appointment or discharging the memory block of described appointment:
Determine that whether the physical memory piece adjacent with the physical memory piece that discharges be idle, if idle, discharged physical memory piece and adjacent physical memory piece are merged, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
5. the method as described in claim 1-4 any one, is characterized in that, the idle physical memory piece of the N in described SOC sheet in internal memory obtains in the following way:
Gross space size at M idle physical memory piece is greater than described K, but when in described M idle physical memory piece, the gross space size of M-1 idle physical memory piece is less than described K arbitrarily, an idle physical memory piece in described M idle physical memory piece is divided into m idle physical memory piece, obtain M+m-1 idle physical memory piece, wherein, the gross space size of N idle physical memory piece in described M+m-1 idle physical memory piece equals described K; M is more than or equal to 2, M=N.
6. the method as described in claim 1-5 any one, is characterized in that, described structure comprises:
Set up the mapping relations between described N the physical address in idle physical memory piece and the virtual address in described virtual memory piece;
Described mapping relations are saved to address mapping table.
7. method as claimed in claim 6, is characterized in that, after discharging the each physical memory piece comprising in the memory block of described appointment, also comprises:
Upgrade described address mapping table.
8. a memory management device, is characterized in that, comprising:
The first memory management unit, for being more than or equal to K in response to the current internal memory surplus resources of internal memory in system level chip SOC sheet, simultaneously, in internal memory, Existential Space size is not more than or equal to the idle physical memory piece of K in described SOC sheet, use the N in internal memory idle physical memory piece in described SOC sheet to build the continuous virtual memory piece of virtual address, and distribute described virtual memory piece as memory headroom to be applied for; Described in when initial, save as a monoblock free memory block in SOC sheet;
Described K represents the space size of memory headroom to be applied for; The gross space size of described N idle physical memory piece equals described K, and described N is more than or equal to 2 integer; Physical address in described physical memory piece is continuous.
9. device as claimed in claim 8, is characterized in that, also comprises the second memory management unit, for:
Be greater than the idle physical memory piece of K in response to Existential Space size in internal memory in described SOC sheet, the idle physical memory piece that described space size is greater than to K is divided into m idle physical memory piece, and in described m idle physical memory piece, Existential Space size equals the idle physical memory piece of K; Described m is more than or equal to 2;
Distribute idle physical memory piece that described space size equals K as memory headroom described to be applied for.
10. install as claimed in claim 8 or 9, it is characterized in that, also comprise internal memory release management unit, for:
In response to memory block release command, determine whether the memory block that described memory block release command is specified is physical memory piece; If the memory block of specifying is physical memory piece, directly discharge the memory block of described appointment; If the memory block of specifying is not physical memory piece, discharge the each physical memory piece comprising in the memory block of described appointment.
11. as the device of claim 10, it is characterized in that, also comprises:
Idle physical block setting unit, after directly discharging the memory block of described appointment in described internal memory release management unit or discharging each physical memory piece that the memory block of described appointment comprises, determine that whether the physical memory piece adjacent with the physical memory piece discharging be idle, if idle, discharged physical memory piece and adjacent physical memory piece are merged, the physical memory piece after merging is set to the free time; Otherwise directly the physical memory piece of release is set to the free time.
12. 1 kinds of embedded systems, is characterized in that, comprise internal memory, processor and the memory management device as described in claim 8-11 any one in SOC sheet.
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Application publication date: 20140806 |