WO2016192178A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

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Publication number
WO2016192178A1
WO2016192178A1 PCT/CN2015/084279 CN2015084279W WO2016192178A1 WO 2016192178 A1 WO2016192178 A1 WO 2016192178A1 CN 2015084279 W CN2015084279 W CN 2015084279W WO 2016192178 A1 WO2016192178 A1 WO 2016192178A1
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WIPO (PCT)
Prior art keywords
switch tube
scan
signal
output end
pull
Prior art date
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Ceased
Application number
PCT/CN2015/084279
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English (en)
French (fr)
Inventor
肖军城
赵莽
颜尧
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/777,748 priority Critical patent/US9792845B2/en
Publication of WO2016192178A1 publication Critical patent/WO2016192178A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • the Gate Driver On Array is a driving circuit for forming a scan drive circuit on an array substrate of an existing thin film transistor liquid crystal display to realize progressive scan of the scan line.
  • the existing scan driving circuit includes a pull-down control module, a pull-down module, a downlink module, a reset control module, a bootstrap capacitor, and a reset control module.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of a next stage, and generate a corresponding reset signal of the scan line according to the clock signal of the next stage;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and transmit a clock signal of the current level according to the scan signal of the scan line, and The pull-down control signal of this level;
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • the scan driving circuit controls the pull-down control module, the pull-down module, the reset control module, and the reset module using a P-type metal oxide semiconductor type transistor or an N-type metal oxide semiconductor type transistor;
  • the pull-down control module is further configured to receive a scan signal of a next stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal of the next stage;
  • the reset control module is further configured to receive a clock signal of the upper stage, and generate a corresponding reset signal of the scan line according to the clock signal of the upper stage.
  • the pull-down control module includes a first switch tube, a control signal of the first switch tube inputs a scan signal of a low level, and an input end of the first switch tube The scan signal of the first stage is described; the output end of the first switch tube is connected to the pull-down module.
  • the pull-down module includes a second switch tube, and a control end of the second switch tube is connected to an output end of the first switch tube of the pull-down control module, the second An input end of the switch tube is connected to an output end of the first switch tube of the pull-down control module, and an output end of the second switch tube outputs a scan level signal of a low level of the scan line.
  • the reset control module includes a third switch tube, and the control end of the third switch tube inputs the scan signal of the low level, and the input end of the third switch tube The clock signal of the next stage is input, and the output end of the third switch tube outputs a reset signal of the scan line.
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, and a seventh switch tube;
  • a control end of the fourth switch tube is connected to an output end of the third switch tube, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube Connected to the control end of the fifth switch tube, the control end of the seventh switch tube, and the output end of the sixth switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube Connected to an output end of the second switch tube;
  • a control end of the sixth switch tube is connected to an output end of the second switch tube, and an input end of the sixth switch tube is connected to the constant voltage high level source;
  • the input end of the seventh switch tube is connected to the constant voltage high level source, and the output end of the seventh switch tube outputs a scan signal of the current stage of the scan line.
  • the down-transmission module includes an eighth switch tube, and a control end of the eighth switch tube is connected to an output end of the second switch tube, and the eighth switch tube is The input end is connected to the output end of the seventh switch tube, and the output end of the eighth switch tube outputs the clock signal of the current stage.
  • the downlink module further includes a tenth switch tube, and a control end of the tenth switch tube is connected to an output end of the second switch tube, and the tenth switch tube The input end is connected to the output end of the eighth switch tube, and the output end of the tenth switch tube outputs a pull-down control signal of the current stage.
  • one end of the first bootstrap capacitor is connected to an output end of the second switch tube, and the other end of the first bootstrap capacitor and the seventh switch tube The output is connected.
  • the scan driving circuit further includes a leakage preventing module, the leakage preventing module includes a ninth switching tube, and the control end of the ninth switching tube and the constant voltage low level a source connection, an input end of the ninth switch tube is connected to an output end of the second switch tube, and an output end of the ninth switch tube passes through an output of the first bootstrap capacitor and the seventh switch tube End connection.
  • the leakage preventing module includes a ninth switching tube, and the control end of the ninth switching tube and the constant voltage low level a source connection, an input end of the ninth switch tube is connected to an output end of the second switch tube, and an output end of the ninth switch tube passes through an output of the first bootstrap capacitor and the seventh switch tube End connection.
  • the reset module further includes a second bootstrap capacitor, one end of the second bootstrap capacitor is connected to the constant voltage high level source, and the second bootstrap capacitor The other end is connected to the output end of the fourth switch.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • a pull-down control module configured to receive a scan signal of a previous stage, and generate a scan level signal of a low level of the scan line according to the scan signal of the previous stage;
  • a pull-down module configured to pull down a scan signal of the corresponding scan line according to the scan level signal
  • a reset control module configured to receive a clock signal of a next stage, and according to the clock signal of the next stage, Generating a corresponding reset signal of the scan line;
  • a reset module configured to pull up a scan signal of the corresponding scan line according to the reset signal
  • a downlink module configured to generate and transmit a clock signal of the current stage and a pull-down control signal of the current stage according to the scan signal of the scan line;
  • a first bootstrap capacitor for generating a low level or a high level of a scan level signal of the scan line
  • a constant voltage low level source for providing the low level signal
  • a constant voltage high level source for providing the high level signal.
  • the pull-down control module includes a first switch tube, a control signal of the first switch tube inputs a scan signal of a low level, and an input end of the first switch tube The scan signal of the first stage is described; the output end of the first switch tube is connected to the pull-down module.
  • the pull-down module includes a second switch tube, and a control end of the second switch tube is connected to an output end of the first switch tube of the pull-down control module, the second An input end of the switch tube is connected to an output end of the first switch tube of the pull-down control module, and an output end of the second switch tube outputs a scan level signal of a low level of the scan line.
  • the reset control module includes a third switch tube, and the control end of the third switch tube inputs the scan signal of the low level, and the input end of the third switch tube The clock signal of the next stage is input, and the output end of the third switch tube outputs a reset signal of the scan line.
  • the reset module includes a fourth switch tube, a fifth switch tube, a sixth switch tube, and a seventh switch tube;
  • a control end of the fourth switch tube is connected to an output end of the third switch tube, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube Connected to the control end of the fifth switch tube, the control end of the seventh switch tube, and the output end of the sixth switch tube;
  • An input end of the fifth switch tube is connected to the constant voltage high level source, and an output end of the fifth switch tube is connected to an output end of the second switch tube;
  • a control end of the sixth switch tube is connected to an output end of the second switch tube, and an input end of the sixth switch tube is connected to the constant voltage high level source;
  • An input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube A scan signal of the current stage of the scan line is output.
  • the down-transmission module includes an eighth switch tube, and a control end of the eighth switch tube is connected to an output end of the second switch tube, and the eighth switch tube is The input end is connected to the output end of the seventh switch tube, and the output end of the eighth switch tube outputs the clock signal of the current stage.
  • the downlink module further includes a tenth switch tube, and a control end of the tenth switch tube is connected to an output end of the second switch tube, and the tenth switch tube The input end is connected to the output end of the eighth switch tube, and the output end of the tenth switch tube outputs a pull-down control signal of the current stage.
  • one end of the first bootstrap capacitor is connected to an output end of the second switch tube, and the other end of the first bootstrap capacitor and the seventh switch tube The output is connected.
  • the scan driving circuit further includes a leakage preventing module, the leakage preventing module includes a ninth switching tube, and the control end of the ninth switching tube and the constant voltage low level a source connection, an input end of the ninth switch tube is connected to an output end of the second switch tube, and an output end of the ninth switch tube passes through an output of the first bootstrap capacitor and the seventh switch tube End connection.
  • the leakage preventing module includes a ninth switching tube, and the control end of the ninth switching tube and the constant voltage low level a source connection, an input end of the ninth switch tube is connected to an output end of the second switch tube, and an output end of the ninth switch tube passes through an output of the first bootstrap capacitor and the seventh switch tube End connection.
  • the reset module further includes a second bootstrap capacitor, one end of the second bootstrap capacitor is connected to the constant voltage high level source, and the second bootstrap capacitor The other end is connected to the output end of the fourth switch.
  • the scan driving circuit of the present invention improves the reliability of the scan driving circuit by the setting of the pull-down control module and the reset control module, and the structure of the entire scan driving circuit is simple; The technical problem of the structure of the scan driving circuit is complicated and the reliability is low.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a scan driving circuit of the present invention
  • FIG. 2 is a detailed circuit configuration diagram of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 3 is a detailed circuit configuration diagram of a second preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 4 is a signal waveform diagram of a preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit 10 of the preferred embodiment is configured to perform a driving operation on the cascaded scan lines.
  • the scan driving circuit 10 includes a pull-down control module 11, a pull-down module 12, a reset control module 13, a reset module 14, and a downlink module 15.
  • the leakage prevention module 16 the first bootstrap capacitor C1, the constant voltage low level source VGL, and the constant voltage high level source VGH.
  • the pull-down control module 11 is configured to receive the scan signal G_N-1 of the previous stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal G_N-1 of the previous stage.
  • the pull-down module 12 is configured to pull down the scan signal G_N of the corresponding scan line according to the scan level signal.
  • the reset control module 13 is configured to receive the clock signal CK_N+1 of the next stage, and generate a reset signal of the corresponding scan line according to the clock signal CK_N+1 of the next stage.
  • the reset module 14 is configured to pull up the scan signal G_N of the corresponding scan line according to the reset signal.
  • the downlink module is configured to generate and transmit the clock signal CK_N of the current stage according to the scan signal G_N of the scan line.
  • the first bootstrap capacitor C1 is used to generate a low level or a high level of the scan level signal of the scan line.
  • the constant voltage low level source VGL is used to provide a low level signal; the constant voltage high level source VGH is used to provide a high level signal.
  • FIG. 2 is a structural diagram of a specific circuit of a first preferred embodiment of the scan driving circuit of the present invention.
  • the pull-down control module 11 includes a first switch tube PT1, and the control end of the first switch tube PT1 inputs a scan signal D2U of a low level, and the input end of the first switch tube PT1 inputs a scan signal of the previous stage.
  • G_N-1 the output end of the first switch PT1 is connected to the pull-down module 12, and the scan signal G_N-1 of the previous stage is output to the pull-down module 12.
  • the pull-down module 12 includes a second switch tube PT2, the control end of the second switch tube PT2 is connected to the output end of the first switch tube PT1, the input end of the second switch tube PT2 is connected to the output end of the first switch tube PT1, and the second Open The output terminal of the switch PT2 outputs a low-level scan signal G_N-1 of the previous scan line.
  • the reset control module 13 includes a third switch tube PT3, the control end of the third switch tube PT3 inputs a low level scan signal D2U, and the input end of the third switch tube PT3 inputs a clock signal CK_N+1 of the next stage, the third switch The output end of the tube PT3 outputs a reset signal of the scan line, that is, outputs the clock signal CK_N+1 of the next stage.
  • the reset module 14 includes a fourth switch tube PT4, a fifth switch tube PT5, a sixth switch tube PT6, a seventh switch tube PT7, and a second bootstrap capacitor C2.
  • the control end of the fourth switch tube PT4 is connected to the output end of the third switch tube PT3, the input end of the fourth switch tube PT4 is connected to the constant voltage low level source VGL, and the output end of the fourth switch tube PT4 is respectively connected to the fifth switch
  • the control end of the tube PT5, the control end of the seventh switch tube PT7, and the output end of the sixth switch tube PT6 are connected.
  • the input end of the fifth switch tube PT5 is connected to the constant voltage high level source VGH, and the output end of the fifth switch tube PT5 is connected to the output end of the second switch tube PT2.
  • the control end of the sixth switch tube PT6 is connected to the output end of the second switch tube PT2, and the input end of the sixth switch tube PT6 is connected to the constant voltage high level source VGH.
  • the input end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH, and the output end of the seventh switch tube PT7 outputs the scan signal G_N of the current stage of the scan line.
  • One end of the second bootstrap capacitor C2 is connected to the constant voltage high level source VGH, and the other end of the second bootstrap capacitor C2 is connected to the output end of the fourth switch tube PT4.
  • the output module 15 includes an eighth switch tube PT8, the control end of the eighth switch tube PT8 is connected to the output end of the second switch tube PT2, and the input end of the eighth switch tube PT8 is connected to the output end of the seventh switch tube PT7.
  • the output terminal of the eight-switch PT8 outputs the clock signal CK_N of the current stage.
  • One end of the first bootstrap capacitor C1 is connected to the output end of the second switch tube PT2, and the other end of the first bootstrap capacitor C1 is connected to the output end of the seventh switch tube PT7.
  • the leakage prevention module 16 includes a ninth switch tube PT9.
  • the control end of the ninth switch tube PT9 is connected to the constant voltage low level source VGL, and the input end of the ninth switch tube PT9 is connected to the output end of the second switch tube PT2.
  • the output end of the switch tube PT9 is connected to the output end of the seventh switch tube PT7 through the first bootstrap capacitor C1.
  • FIGS. 2 and 4. 4 is a signal waveform diagram of a preferred embodiment of the scan driving circuit of the present invention.
  • the clock signal CK_N is The four groups are cyclic outputs, that is, the waveforms of CK_N and CK_N+4 are the same.
  • the scan signal G_N-1 of the previous stage outputs a low-level signal.
  • the first switch PT1 of the pull-down control module 11 is in an on state under the control of the low-level scan signal D2U;
  • the output end of the tube PT1 inputs the scan signal G_N-1 of the previous stage to the input end of the second switch tube PT2 of the pull-down module 12 and the control terminal.
  • the control terminal of the second switching transistor PT2 of the pull-down module 12 inputs the low-level signal G_N-1, so the second switching transistor PT2 is in an on state, and the output terminal of the second switching transistor PT2 outputs a low-level signal G_N-1.
  • the control end of the sixth switch tube PT6 of the reset module 14 receives the low level signal G_N-1 outputted from the output end of the second switch tube PT2, so the sixth switch tube PT6 is turned on, and the control end of the fifth switch tube PT5 is turned on. And the control end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH through the sixth switch tube PT6, respectively, so the fifth switch tube PT5 and the seventh switch tube PT7 are disconnected.
  • the ninth switch tube PT9 of the leakage prevention module 16 is turned on under the control of the constant voltage low level source VGL, and the low level signal G_N-1 outputted by the second switch tube PT2 of the pull-down module 12 acts on the ninth switch tube PT9.
  • the first bootstrap capacitor C1 makes the potential of Q_N lower, so that G_N also outputs a low-level signal, and at the same time, the eighth switch tube PT8 of the module 15 is turned on, and is also turned on under the control of Q_N, and the eighth switch tube PT8
  • the output terminal outputs the low-level clock signal CK_N of the current stage to the driving circuit of the scan line of the previous stage.
  • the third switching transistor PT3 of the reset control module 13 inputs the clock signal CK_N+1 of the next stage under the control of the scanning signal U2D of the low level.
  • the output end of the third switch PT3 outputs the clock signal CK_N+1, that is, the reset signal to the reset module 14.
  • the fourth switch tube PT4 of the reset module 14 is turned on under the control of the reset signal, and the constant voltage low level source VGL is input to the control end of the fifth switch tube PT5 and the control end of the seventh switch tube PT7 through the fourth switch tube PT4.
  • the fifth switch tube PT5 and the seventh switch tube PT7 are turned on, and the high level signal of the constant voltage high level source VGH is input to the Q point through the fifth switch tube PT5, and Q_N is pulled high.
  • the high-level signal of the constant-voltage high-level source VGH is input to G_N through the seventh switch tube PT7, and G_N is pulled high, and at the same time, since the eighth switch tube PT8 is turned off, the clock signal CK_N also goes to the high level.
  • the setting of the second bootstrap capacitor C2 in the reset module 14 can better pull up the potential of the control end of the fifth switch tube PT5 and the control end of the seventh switch tube PT7, thereby better ensuring the Q_N point. Low Potential.
  • the pull-down control module 11 of the preferred embodiment further includes an eleventh switch tube PT11.
  • the control end of the eleventh switch tube PT11 inputs a low-level scan signal, and the input end of the eleventh switch tube PT11 is input.
  • the scan signal G_N+1 of the first stage is connected to the pull-down module 12 at the output end of the eleventh switch tube PT11.
  • the pull-down control module 11 can receive the scan signal G_N+1 of the next stage, and generate a scan level signal of a low level of the corresponding scan line according to the scan signal G_N+1 of the next stage.
  • the reset control module 13 of the preferred embodiment further includes a twelfth switch tube PT12.
  • the control end of the twelfth switch tube PT12 inputs a low level scan signal, and the input end of the twelfth switch tube PT12 is input to the upper level.
  • the clock signal CK_N-1, the output end of the twelfth switch tube PT12 outputs a reset signal of the scan line.
  • the reset control module 13 can receive the clock signal CK_N-1 of the previous stage and generate a reset signal of the corresponding scan line according to the clock signal CK_N-1 of the previous stage.
  • the drive scan circuit 10 of the preferred embodiment can also implement the function of reverse scan through the eleventh switch tube PT11 and the twelfth switch tube PT12.
  • the scan driving circuit 10 of the preferred embodiment uses a P-type metal oxide semiconductor type transistor control pull-down control module 11, a pull-down module 12, a reset control module 13, and a reset module 14.
  • the N-type metal oxide semiconductor type transistor can also be used here to control the pull-down control module 11, the pull-down module 12, the reset control module 13, and the reset module 14.
  • the scan driving circuit of the present invention improves the reliability of the scan driving circuit by the setting of the pull-down control module and the reset control module, and the structure of the entire scan driving circuit is simple.
  • FIG. 3 is a specific circuit structural diagram of a second preferred embodiment of the scan driving circuit of the present invention.
  • the scan driving circuit 20 of the preferred embodiment is based on the first preferred embodiment, and the control terminal of the second switching transistor PT2 of the pull-down module 22 is connected to the pull-down control signal S_N-1 of the previous stage.
  • the downlink module 25 further includes a tenth switch tube PT10, and the control end of the tenth switch tube PT10 is connected to the output end of the second switch tube PT2 through the ninth switch tube PT9, and the input end of the tenth switch tube PT10 The output end of the eighth switch tube PT8 is connected, and the output end of the tenth switch tube PT10 outputs the pull-down control signal S_N of the current stage.
  • the scan driving circuit 20 of the preferred embodiment realizes the delayed transmission of the scan signals of the scan lines of each stage by the pull-down control signal S_N, which avoids the leakage problem caused by the mismatch between the scan signal and the clock signal.
  • the scan driving circuit of the preferred embodiment further improves the reliability and stability of the scan driving current in the first preferred embodiment.
  • the scan driving circuit of the invention improves the reliability of the scan driving circuit by the setting of the pull-down control module and the reset control module, and the structure of the whole scan driving circuit is simple; the structure of the existing scan driving circuit is complicated and the reliability is low. Technical problem.

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Abstract

一种扫描驱动电路，用于对级联的扫描线进行驱动操作。该扫描驱动电路包括下拉控制模块（11）、下拉模块（12）、复位控制模块（13）、复位模块（14）、下传模块（15）、第一自举电容（C1）、恒压低电平源以及恒压高电平源。该扫描驱动电路的整体结构简单，且能耗较小。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。现有扫描驱动电路包括下拉控制模块、下拉模块、下传模块、复位控制模块、自举电容以及复位控制模块。
该扫描驱动电路在高温状态下工作时，容易出现延时以及漏电的问题，从而影响该扫描驱动电路的可靠性。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
对发明的公开
技术问题
本发明的目的在于提供一种结构简单且可靠性高的扫描驱动电路，以解决现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
问题的解决方案
技术解决方案
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及 本级的下拉控制信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号；
其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位控制模块以及所述复位模块；
所述下拉控制模块还用于接收下一级的扫描信号，并根据下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
所述复位控制模块还用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下一级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述复位模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第七开关管的控制端以及所述第六开关管的输出端连接；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端 与所述第二开关管的输出端连接；
所述第六开关管的控制端与所述第二开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端输出所述扫描线的本级的扫描信号。
在本发明所述的扫描驱动电路中，所述下传模块包括第八开关管，所述第八开关管的控制端与所述第二开关管的输出端连接，所述第八开关管的输入端与所述第七开关管的输出端连接，所述第八开关管的输出端输出所述本级的时钟信号。
在本发明所述的扫描驱动电路中，所述下传模块还包括第十开关管，所述第十开关管的控制端与所述第二开关管的输出端连接，所述第十开关管的输入端与所述第八开关管的输出端连接，所述第十开关管的输出端输出本级的下拉控制信号。
在本发明所述的扫描驱动电路中，所述第一自举电容的一端与所述第二开关管的输出端连接，所述第一自举电容的另一端与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述扫描驱动电路还包括防漏电模块，所述防漏电模块包括第九开关管，所述第九开关管的控制端与所述恒压低电平源连接，所述第九开关管的输入端与所述第二开关管的输出端连接，所述第九开关管的输出端通过所述第一自举电容与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号， 生成相应的所述扫描线的复位信号；
复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及本级的下拉控制信号；
第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
恒压低电平源，用于提供所述低电平信号；以及
恒压高电平源，用于提供所述高电平信号。
在本发明所述的扫描驱动电路中，所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
在本发明所述的扫描驱动电路中，所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
在本发明所述的扫描驱动电路中，所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下一级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
在本发明所述的扫描驱动电路中，所述复位模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第七开关管的控制端以及所述第六开关管的输出端连接；
所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
所述第六开关管的控制端与所述第二开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端 输出所述扫描线的本级的扫描信号。
在本发明所述的扫描驱动电路中，所述下传模块包括第八开关管，所述第八开关管的控制端与所述第二开关管的输出端连接，所述第八开关管的输入端与所述第七开关管的输出端连接，所述第八开关管的输出端输出所述本级的时钟信号。
在本发明所述的扫描驱动电路中，所述下传模块还包括第十开关管，所述第十开关管的控制端与所述第二开关管的输出端连接，所述第十开关管的输入端与所述第八开关管的输出端连接，所述第十开关管的输出端输出本级的下拉控制信号。
在本发明所述的扫描驱动电路中，所述第一自举电容的一端与所述第二开关管的输出端连接，所述第一自举电容的另一端与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述扫描驱动电路还包括防漏电模块，所述防漏电模块包括第九开关管，所述第九开关管的控制端与所述恒压低电平源连接，所述第九开关管的输入端与所述第二开关管的输出端连接，所述第九开关管的输出端通过所述第一自举电容与所述第七开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
发明的有益效果
有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路通过下拉控制模块以及复位控制模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
对附图的简要说明
附图说明
图1为本发明的扫描驱动电路的优选实施例的结构示意图；
图2为本发明的扫描驱动电路的第一优选实施例的具体电路结构图；
图3为本发明的扫描驱动电路的第二优选实施例的具体电路结构图；
图4为本发明的扫描驱动电路的优选实施例的信号波形图。
实施该发明的最佳实施例
本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的扫描驱动电路的优选实施例的结构示意图。本优选实施例的扫描驱动电路10用于对级联的扫描线进行驱动操作，该扫描驱动电路10包括下拉控制模块11、下拉模块12、复位控制模块13、复位模块14、下传模块15、防漏电模块16、第一自举电容C1、恒压低电平源VGL以及恒压高电平源VGH。
下拉控制模块11用于接收上一级的扫描信号G_N-1，并根据上一级的扫描信号G_N-1生成相应的扫描线的低电平的扫描电平信号。下拉模块12用于根据扫描电平信号，拉低相应的扫描线的扫描信号G_N。复位控制模块13用于接收下一级的时钟信号CK_N+1，并根据下一级的时钟信号CK_N+1，生成相应的扫描线的复位信号。复位模块14用于根据复位信号，拉升相应的扫描线的扫描信号G_N。下传模块用于根据扫描线的扫描信号G_N，生成并发送本级的时钟信号CK_N。第一自举电容C1用于生成扫描线的扫描电平信号的低电平或高电平。恒压低电平源VGL用于提供低电平信号；恒压高电平源VGH用于提供高电平信号。
请参照图2，图2为本发明的扫描驱动电路的第一优选实施例的具体电路结构图。在本优选实施例中，下拉控制模块11包括第一开关管PT1，第一开关管PT1的控制端输入低电平的扫描信号D2U，第一开关管PT1的输入端输入上一级的扫描信号G_N-1，第一开关管PT1的输出端与下拉模块12连接，向下拉模块12输出上一级的扫描信号G_N-1。
下拉模块12包括第二开关管PT2，第二开关管PT2的控制端与第一开关管PT1的输出端连接，第二开关管PT2的输入端与第一开关管PT1的输出端连接，第二开 关管PT2的输出端输出上一级扫描线的低电平的扫描信号G_N-1。
复位控制模块13包括第三开关管PT3，第三开关管PT3的控制端输入低电平的扫描信号D2U，第三开关管PT3的输入端输入下一级的时钟信号CK_N+1，第三开关管PT3的输出端输出扫描线的复位信号，即输出下一级的时钟信号CK_N+1。
复位模块14包括第四开关管PT4、第五开关管PT5、第六开关管PT6、第七开关管PT7以及第二自举电容C2。第四开关管PT4的控制端与第三开关管PT3的输出端连接，第四开关管PT4的输入端与恒压低电平源VGL连接，第四开关管PT4的输出端分别与第五开关管PT5的控制端、第七开关管PT7的控制端以及第六开关管PT6的输出端连接。
第五开关管PT5的输入端与恒压高电平源VGH连接，第五开关管PT5的输出端与第二开关管PT2的输出端连接。
第六开关管PT6的控制端与第二开关管PT2的输出端连接，第六开关管PT6的输入端与恒压高电平源VGH连接。
第七开关管PT7的输入端与恒压高电平源VGH连接，第七开关管PT7的输出端输出扫描线的本级的扫描信号G_N。
第二自举电容C2的一端与恒压高电平源VGH连接，第二自举电容C2的另一端与第四开关管PT4的输出端连接。
下传模块15包括第八开关管PT8，第八开关管PT8的控制端与第二开关管PT2的输出端连接，第八开关管PT8的输入端与第七开关管PT7的输出端连接，第八开关管PT8的输出端输出本级的时钟信号CK_N。
第一自举电容C1的一端与第二开关管PT2的输出端连接，第一自举电容C1的另一端与第七开关管PT7的输出端连接。
防漏电模块16包括第九开关管PT9，第九开关管PT9的控制端与恒压低电平源VGL连接，第九开关管PT9的输入端与第二开关管PT2的输出端连接，第九开关管PT9的输出端通过第一自举电容C1与第七开关管PT7的输出端连接。
下面结合图2和图4详细说明本优选实施例的扫描驱动电路的具体工作原理。图4为本发明的扫描驱动电路的优选实施例的信号波形图。其中时钟信号CK_N以 四组为循环输出，即CK_N和CK_N+4的波形是相同的。首先上一级的扫描信号G_N-1输出低电平信号，这时由于下拉控制模块11的第一开关管PT1在低电平的扫描信号D2U的控制下，处于导通状态；因此第一开关管PT1的输出端向下拉模块12的第二开关管PT2的输入端以及控制端输入上一级的扫描信号G_N-1。
下拉模块12的第二开关管PT2的控制端输入低电平信号G_N-1，因此第二开关管PT2处于导通状态，第二开关管PT2的输出端输出低电平信号G_N-1。
同时复位模块14的第六开关管PT6的控制端接收到第二开关管PT2的输出端输出的低电平信号G_N-1，因此第六开关管PT6导通，第五开关管PT5的控制端和第七开关管PT7的控制端分别通过第六开关管PT6与恒压高电平源VGH连接，因此第五开关管PT5和第七开关管PT7断开。
防漏电模块16的第九开关管PT9在恒压低电平源VGL的控制下导通，下拉模块12的第二开关管PT2输出的低电平信号G_N-1通过第九开关管PT9作用于第一自举电容C1上，使得Q_N的电位更低，这样G_N也输出低电平信号，同时下传模块15的第八开关管PT8，在Q_N的控制下也导通，第八开关管PT8的输出端输出本级的低电平的时钟信号CK_N至上一级的扫描线的驱动电路。
当下一级的时钟信号CK_N+1转为低电平时，复位控制模块13的第三开关管PT3在低电平的扫描信号U2D的控制下输入下一级的时钟信号CK_N+1。第三开关管PT3的输出端输出该时钟信号CK_N+1，即复位信号至复位模块14。
复位模块14的第四开关管PT4在复位信号的控制下导通，恒压低电平源VGL通过第四开关管PT4输入到第五开关管PT5的控制端以及第七开关管PT7的控制端，这时第五开关管PT5和第七开关管PT7导通，恒压高电平源VGH的高电平信号通过第五开关管PT5输入到Q点，将Q_N拉高。同时恒压高电平源VGH的高电平信号通过第七开关管PT7输入到G_N，将G_N拉高，同时由于第八开关管PT8断开，钟信号CK_N也转为高电平。
这样即完成了本优选实施例的扫描驱动电路10的低电平的扫描信号的级联输出过程。
优选的，复位模块14中的第二自举电容C2的设置，可以更好的拉高第五开关管PT5的控制端和第七开关管PT7的控制端的电位，从而可较好的保证Q_N点的低 电位。
优选的，本优选实施例的下拉控制模块11还包括第十一开关管PT11，该第十一开关管PT11的控制端输入低电平的扫描信号，第十一开关管PT11的输入端输入下一级的扫描信号G_N+1，第十一开关管PT11的输出端与下拉模块12连接。这样下拉控制模块11可接收下一级的扫描信号G_N+1，并根据下一级的扫描信号G_N+1生成相应的扫描线的低电平的扫描电平信号。
同时本优选实施例的复位控制模块13还包括第十二开关管PT12，该第十二开关管PT12的控制端输入低电平的扫描信号，第十二开关管PT12的输入端输入上一级的时钟信号CK_N-1，第十二开关管PT12的输出端输出扫描线的复位信号。这样复位控制模块13可接收上一级的时钟信号CK_N-1，并根据上一级的时钟信号CK_N-1，生成相应的扫描线的复位信号。
这样本优选实施例的驱动扫描电路10还可通过第十一开关管PT11和第十二开关管PT12实现反向扫描的功能。
优选的，本优选实施例的扫描驱动电路10使用的是P型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13以及复位模块14。当然这里还可使用N型金属氧化物半导体类型的晶体管控制下拉控制模块11、下拉模块12、复位控制模块13以及复位模块14。
本发明的扫描驱动电路通过下拉控制模块以及复位控制模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单。
请参照图3，如3为本发明的扫描驱动电路的第二优选实施例的具体电路结构图。本优选实施例的扫描驱动电路20在第一优选实施例的基础上，下拉模块22的第二开关管PT2的控制端与上一级的下拉控制信号S_N-1连接。同时下传模块25还包括第十开关管PT10，第十开关管PT10的控制端与通过第九开关管PT9，与第二开关管PT2的输出端连接，第十开关管PT10的输入端与第八开关管PT8的输出端连接，第十开关管PT10的输出端输出本级的下拉控制信号S_N。
本优选实施例的扫描驱动电路20通过引入的下拉控制信号S_N，实现各级扫描线的扫描信号的延时传递，避免了扫描信号和时钟信号不匹配造成的漏电问题。
因此本优选实施例的扫描驱动电路在第一优选实施例的进一步提高了扫描驱动电流的可靠性以及稳定性。
本发明的扫描驱动电路通过下拉控制模块以及复位控制模块的设置，提高了扫描驱动电路的可靠性，同时整个扫描驱动电路的结构简单；解决了现有的扫描驱动电路的结构复杂且可靠性低的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及本级的下拉控制信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号；
    其中所述扫描驱动电路使用P型金属氧化物半导体类型的晶体管或N型金属氧化物半导体类型的晶体管控制所述下拉控制模块、所述下拉模块、所述复位控制模块以及所述复位模块；
    所述下拉控制模块还用于接收下一级的扫描信号，并根据下一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    所述复位控制模块还用于接收上一级的时钟信号，并根据所述上一级的时钟信号，生成相应的所述扫描线的复位信号。
  2. 根据权利要求1所述的扫描驱动电路，其中所述下拉控制模块包括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
  3. 根据权利要求2所述的扫描驱动电路，其中所述下拉模块包括第二 开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
  4. 根据权利要求3所述的扫描驱动电路，其中所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下一级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
  5. 根据权利要求4所述的扫描驱动电路，其中所述复位模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
    所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第七开关管的控制端以及所述第六开关管的输出端连接；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
    所述第六开关管的控制端与所述第二开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端输出所述扫描线的本级的扫描信号。
  6. 根据权利要求5所述的扫描驱动电路，其中所述下传模块包括第八开关管，所述第八开关管的控制端与所述第二开关管的输出端连接，所述第八开关管的输入端与所述第七开关管的输出端连接，所述第八开关管的输出端输出所述本级的时钟信号。
  7. 根据权利要求6所述的扫描驱动电路，其中所述下传模块还包括第十开关管，所述第十开关管的控制端与所述第二开关管的输出端连接，所述第十开关管的输入端与所述第八开关管的输出端连接，所述第十开关管的输出端输出本级的下拉控制信号。
  8. 根据权利要求7所述的扫描驱动电路，其中所述第一自举电容的一端与所述第二开关管的输出端连接，所述第一自举电容的另一端与所述第七开关管的输出端连接。
  9. 根据权利要求8所述的扫描驱动电路，其中所述扫描驱动电路还包括防漏电模块，所述防漏电模块包括第九开关管，所述第九开关管的控制端与所述恒压低电平源连接，所述第九开关管的输入端与所述第二开关管的输出端连接，所述第九开关管的输出端通过所述第一自举电容与所述第七开关管的输出端连接。
  10. 根据权利要求9所述的扫描驱动电路，其中所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
  11. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
    下拉控制模块，用于接收上一级的扫描信号，并根据所述上一级的扫描信号生成相应的所述扫描线的低电平的扫描电平信号；
    下拉模块，用于根据所述扫描电平信号，拉低相应的所述扫描线的扫描信号；
    复位控制模块，用于接收下一级的时钟信号，并根据所述下一级的时钟信号，生成相应的所述扫描线的复位信号；
    复位模块，用于根据复位信号，拉升相应的所述扫描线的扫描信号；
    下传模块，用于根据所述扫描线的扫描信号，生成并发送本级的时钟信号以及本级的下拉控制信号；
    第一自举电容，用于生成所述扫描线的扫描电平信号的低电平或高电平；
    恒压低电平源，用于提供所述低电平信号；以及
    恒压高电平源，用于提供所述高电平信号。
  12. 根据权利要求11所述的扫描驱动电路，其中所述下拉控制模块包 括第一开关管，所述第一开关管的控制端输入低电平的扫描信号，所述第一开关管的输入端输入所述上一级的扫描信号；所述第一开关管的输出端与所述下拉模块连接。
  13. 根据权利要求12所述的扫描驱动电路，其中所述下拉模块包括第二开关管，所述第二开关管的控制端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输入端与所述下拉控制模块的第一开关管的输出端连接，所述第二开关管的输出端输出所述扫描线的低电平的扫描电平信号。
  14. 根据权利要求13所述的扫描驱动电路，其中所述复位控制模块包括第三开关管，所述第三开关管的控制端输入所述低电平的扫描信号，所述第三开关管的输入端输入所述下一级的时钟信号，所述第三开关管的输出端输出所述扫描线的复位信号。
  15. 根据权利要求14所述的扫描驱动电路，其中所述复位模块包括第四开关管、第五开关管、第六开关管以及第七开关管；
    所述第四开关管的控制端与所述第三开关管的输出端连接，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端分别与所述第五开关管的控制端、所述第七开关管的控制端以及所述第六开关管的输出端连接；
    所述第五开关管的输入端与所述恒压高电平源连接，所述第五开关管的输出端与所述第二开关管的输出端连接；
    所述第六开关管的控制端与所述第二开关管的输出端连接，所述第六开关管的输入端与所述恒压高电平源连接；
    所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端输出所述扫描线的本级的扫描信号。
  16. 根据权利要求15所述的扫描驱动电路，其中所述下传模块包括第八开关管，所述第八开关管的控制端与所述第二开关管的输出端连接，所述第八开关管的输入端与所述第七开关管的输出端连接，所述第八开关管的输出端输出所述本级的时钟信号。
  17. 根据权利要求16所述的扫描驱动电路，其中所述下传模块还包括第十开关管，所述第十开关管的控制端与所述第二开关管的输出端连接，所述第十开关管的输入端与所述第八开关管的输出端连接，所述第十开关管的输出端输出本级的下拉控制信号。
  18. 根据权利要求17所述的扫描驱动电路，其中所述第一自举电容的一端与所述第二开关管的输出端连接，所述第一自举电容的另一端与所述第七开关管的输出端连接。
  19. 根据权利要求18所述的扫描驱动电路，其中所述扫描驱动电路还包括防漏电模块，所述防漏电模块包括第九开关管，所述第九开关管的控制端与所述恒压低电平源连接，所述第九开关管的输入端与所述第二开关管的输出端连接，所述第九开关管的输出端通过所述第一自举电容与所述第七开关管的输出端连接。
  20. 根据权利要求19所述的扫描驱动电路，其中所述复位模块还包括第二自举电容，所述第二自举电容的一端与所述恒压高电平源连接，所述第二自举电容的另一端与所述第四开关管的输出端连接。
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