WO2016188055A1 - 一种插值滤波的方法及装置 - Google Patents
一种插值滤波的方法及装置 Download PDFInfo
- Publication number
- WO2016188055A1 WO2016188055A1 PCT/CN2015/094775 CN2015094775W WO2016188055A1 WO 2016188055 A1 WO2016188055 A1 WO 2016188055A1 CN 2015094775 W CN2015094775 W CN 2015094775W WO 2016188055 A1 WO2016188055 A1 WO 2016188055A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- phase deviation
- interpolation
- data
- phase
- list
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
Definitions
- the present invention relates to the field of communications, and in particular, to a method and apparatus for interpolation filtering.
- optical fiber In the development of transmission technology, optical fiber has proved to be an indispensable medium. How to transmit the most abundant information with the least amount of optical fiber. For this exploration, the development of optical transmission has basically gone through the following stages: space division multiplexing (SDM), time division multiplexing (TDM) and wavelength division. Use phase (WDM).
- SDM space division multiplexing
- TDM time division multiplexing
- WDM wavelength division. Use phase
- the interpolation coefficient requires real-time calculation
- the coefficient (or range of values) is uncertain when the jitter at both ends of the transceiver is uncertain.
- the embodiment of the present invention is to provide a method and an apparatus for interpolation filtering, which solves at least the problems existing in the prior art, and can implement flexible interpolation, good timing synchronization, and simple and scalable interpolation filtering.
- a method for interpolation filtering according to an embodiment of the present invention includes:
- the adjustment coefficient corresponding to the data is generated by using the interpolation coefficient list as a tap coefficient of the data and the data.
- the method further includes:
- the interpolation coefficient list corresponding to each phase deviation is stored for each phase deviation to obtain a relationship between the phase deviation and the interpolation coefficient list.
- the interpolation coefficient list corresponding to each phase deviation is stored corresponding to each phase deviation, and the relationship between the phase deviation and the interpolation coefficient list is included:
- Each phase deviation is a storage address, and the interpolation coefficient list corresponding to each phase deviation is stored in a storage address indicated by each phase deviation.
- determining the interpolation parameter list corresponding to the phase deviation of the data according to the relationship between the phase deviation pre-stored in the storage area and the interpolation coefficient list includes:
- the interpolation coefficient list corresponding to the phase interpolation of the data is acquired from the address of the storage area with the phase deviation of the data as an address.
- the method further includes:
- the depth of the storage area is determined according to the bit width of the value of the phase deviation.
- the method further includes:
- the width of the storage area is determined based on the sum of the bit widths of the interpolation coefficients corresponding to all phase deviations.
- An apparatus for interpolation filtering according to an embodiment of the present invention, where the apparatus includes: an obtaining module, a searching module, and a calculating module;
- the acquiring module is configured to acquire a phase deviation of the received data
- the searching module is configured to determine, according to a relationship between a phase deviation pre-stored in the storage area and a list of interpolation coefficients, an interpolation parameter list corresponding to a phase deviation of the data;
- the calculating module is configured to calculate, by using the interpolation coefficient list as a tap coefficient of the data, the adjustment data corresponding to the data to generate the data.
- the device further includes: a configuration module configured to traverse the values of all phase deviations; and each phase deviation is respectively calculated by each formula in the interpolation algorithm to obtain a list of interpolation coefficients of each phase deviation; corresponding phases The deviation stores the interpolation coefficient list corresponding to each phase deviation to obtain a relationship between the phase deviation and the interpolation coefficient list.
- the configuration module is specifically configured to traverse the values of all phase deviations; each phase deviation is respectively calculated by each formula in the interpolation algorithm to obtain a list of interpolation coefficients of each phase deviation; and each phase deviation is stored
- the address stores the interpolation coefficient list corresponding to each phase deviation in the storage address indicated by each phase deviation.
- the searching module is configured to acquire, from the address of the storage area, an interpolation coefficient list corresponding to the phase interpolation of the data by using the phase deviation of the data as an address.
- the apparatus further includes: a depth configuration module configured to determine a depth of the storage area according to a bit width of a value of the phase deviation.
- the apparatus further includes: a width configuration module configured to determine a width of the storage area according to a sum of bit widths of interpolation coefficients corresponding to all phase deviations.
- the acquisition module, the search module, the calculation module, the configuration module, the depth configuration module, and the width configuration module may use a central processing unit (CPU) and a digital number when performing processing.
- CPU central processing unit
- DSP Digital Singnal Processor
- FPGA Field-Programmable Gate Array
- a method and apparatus for interpolation filtering acquires a phase deviation of received data; and determines a list of interpolation parameters corresponding to a phase deviation of the data according to a relationship between a phase deviation pre-stored in the storage region and a list of interpolation coefficients And calculating, by using the interpolation coefficient list as a tap coefficient of the data and the data to generate adjustment data corresponding to the data.
- the embodiments of the present invention solve at least the problems in the prior art, and can implement flexible configuration of interpolation coefficients and reduce delays by adding a small amount of overhead, thereby facilitating expansion of subsequent versions.
- FIG. 1 is a schematic flowchart of a method for interpolation filtering according to Embodiment 1 of the present invention
- 2 is a real-time calculation formula of interpolation coefficients of a 100G wavelength division transmission system according to an embodiment of the present invention
- FIG. 3 is a circuit diagram of a conventional interpolation coefficient calculation method
- FIG. 4 is a schematic diagram of a block diagram of a clock recovery subsystem applying an interpolation filtering method according to Embodiment 2 of the present invention
- FIG. 5 is a schematic structural diagram of the interpolation filter shown in FIG. 4; FIG.
- FIG. 6 is a schematic structural diagram of an apparatus for interpolation and filtering according to Embodiment 3 of the present invention.
- FIG. 7 is a schematic structural diagram of another apparatus for interpolation filtering according to Embodiment 3 of the present invention.
- Embodiment 1 of the present invention provides a method for interpolation filtering, as shown in FIG. 1 , the method includes:
- S102 Determine, according to a relationship between a phase deviation pre-stored in the storage area and a list of interpolation coefficients, an interpolation parameter list corresponding to a phase deviation of the data;
- S103 Perform, by using the interpolation coefficient list as a tap coefficient of the data, the adjustment data corresponding to the data to generate the data.
- the sum of the bit widths of the interpolation coefficients determines the width of the storage area, and after determining the depth and width of the storage area, the relationship of all the phase deviations to the interpolation coefficient list is stored in the storage area.
- the method further includes: traversing the values of all the phase deviations; and calculating the interpolation coefficients of each phase deviation by calculating each phase deviation by each formula in the interpolation algorithm; The list of interpolation coefficients corresponding to the phase deviation is stored to obtain a relationship between the phase deviation and the interpolation coefficient list.
- the phase deviation of the received data is 8 bits, and any one of 000000000 to 11111111 is encoded. , that is, any one from 0 to 255; the interpolation algorithm of the 100G wavelength division transmission system includes five formulas, as shown in FIG.
- 0 is passed through h 0 (u), h 1 (u), h 2 (u), h 3 (u), h 4 (u), h 5 (u) are calculated by obtaining a list of interpolation coefficients when u is 0, and passing 1 through h 0 (u), h 1 (u), h 2 (u), h 3 (u), h 4 (u), h 5 (u) are calculated by obtaining a list of interpolation coefficients when u is 1, until 255 is passed through h 0 (u), h 1 (u), h 2 (u), h 3 (u), h 4 (u), h 5 (u) are calculated as a list of interpolation coefficients when u is 255, and 0 to 255 and their corresponding interpolation coefficients
- the list is stored in the storage area to obtain a relationship between the phase deviation and the list of interpolation coefficients.
- the interpolation coefficient list corresponding to each phase deviation is stored for each phase deviation, and the relationship between the phase deviation and the interpolation coefficient list includes: storing each phase deviation as a storage address, and storing the interpolation coefficient list corresponding to each phase deviation in each phase.
- the storage address represented by the deviation That is, in the storage area, the interpolation coefficient list corresponding to 0 is stored at address 00000000, the interpolation coefficient list corresponding to 1 is stored in 00000001, and the interpolation coefficient list corresponding to 2 is stored at address 00000010.
- the receiving end of the communication system obtains the phase deviation of the received data by: clock pre-filtering, phase-collecting, and loop filtering, wherein the clock pre-filtering is the code caused by the dispersion.
- Inter-band interference filtering, phase-checking completes the clock phase deviation check; loop filtering completes the clock phase deviation filtering, and obtains the phase deviation of the received interpolation filtering data.
- the acquisition of the phase deviation of the data is prior art and will not be described in detail herein.
- the phase deviation of the received data acquired in step S101 is matched with the relationship between the phase deviation stored in the storage area and the interpolation coefficient list, and the interpolation coefficient list of the phase deviation of the data is searched for.
- the phase deviation of the data is 00000000
- the list of interpolation coefficients corresponding to 0 is searched
- the list of interpolation coefficients corresponding to 9 is searched.
- the interpolation coefficient list corresponding to each phase deviation is stored for each phase deviation, and the relationship between the phase deviation and the interpolation coefficient list includes: storing each phase deviation as a storage address, and storing the interpolation coefficient list corresponding to each phase deviation in each phase.
- the interpolation coefficient list searched in S102 is used as the tap coefficient of the data, and the received data is adjusted by the tap coefficient to obtain the adjusted data for transmission, that is, the data of the receiving end is adjusted, so that the receiving end of the system It is consistent with the clock frequency of the data at the transmitting end to synchronize the clock source of the transceiver.
- the interpolation coefficient calculation method in the conventional interpolation filtering method is as shown in FIG. 3.
- the interpolation filter receives the phase deviation of the data, the phase deviation is passed through multiple multiplication methods.
- the calculation of h 0 (u) needs to be u, the coefficient one obtained by multiplying the third-order multiplier and multiplying by 0.32376, the coefficient two obtained by multiplying by the second-order multiplier and multiplying by 0.04416, and the coefficient three obtained by multiplying the first-order multiplier by 0.07683, After the coefficient one, the coefficient two and the coefficient three-phase add three coefficients, and the saturation truncation process is performed, the interpolation coefficient corresponding to u through h 0 (u) is obtained, so when it is necessary to obtain the list of interpolation coefficients corresponding to u
- the interpolation coefficients corresponding to h 0 (u), h 1 (u), h 2 (u), h 3 (u), h 4 (u), and h 5 (u) need to be calculated separately to obtain a list of interpolation
- the interpolation coefficient is calculated in real time, the system is complicated, and the interpolation is continuously shaken with the problem of the surrounding environment and the heat dissipation of the board level, and the interpolation is performed when the jitter of the transmitting and receiving ends is uncertain.
- the coefficient (or range of values) is uncertain; further, when the system needs to be upgraded, the hardware needs to be redesigned, which consumes a lot of human resources.
- the interpolation coefficient is pre-configured in the system.
- all the possible results of the interpolation coefficient calculation formula of the interpolation algorithm are traversed and stored in the storage area, thereby realizing the look-up table inside the chip instead of the real-time calculation, that is, the speed is increased, the power consumption is reduced, and the power is greatly enhanced.
- the storage area may be a random access memory (RAM).
- FIG. 4 is a schematic diagram of a block diagram of a clock recovery subsystem applying an interpolation filtering method according to Embodiment 4 of the present invention; the clock recovery subsystem occupies a very important position in 100G, as shown in FIG. 4, including four main parts, respectively : Clock pre-filtering, phase discrimination, loop filtering, and interpolation filters.
- the clock pre-filtering is to filter the inter-symbol interference caused by the dispersion; the phase-checking completes the check of the clock phase deviation; the loop filtering completes the filtering of the clock phase deviation; and the interpolation filter performs the interpolation based on the phase deviation.
- a specific implementation of the interpolation filtering method provided by the embodiment of the present invention can be implemented in an interpolation filter in the system.
- the structure of the interpolation filter is as shown in FIG. 5, which can explain the calculation method of the interpolation filter provided by the embodiment of the present invention; when the interpolation deviation u of the data is obtained, u is input into the RAM (256x26), and the table is checked.
- the mode obtains the calculated interpolation coefficient of u through h 0 (u), h 1 (u), h 2 (u), h 3 (u), h 4 (u), h 5 (u), that is, obtains u corresponding Interpolation list coefficient,
- the interpolation filter method provided by the embodiment of the present invention in a 100G optical transmission system is applicable.
- the implementation of the method can utilize the mature RAM IP core of the Application Specific Integrated Circuit (ASIC), and traverse all possible results of the interpolation coefficient calculation formula of the interpolation coefficient algorithm into the storage area RAM, thereby An internal implementation look-up table replaces the existing real-time calculations, which increases speed and power consumption while greatly enhancing flexibility.
- ASIC Application Specific Integrated Circuit
- bit width of the interpolation pointer (u in Figure 2) is determined according to the algorithm requirement of the interpolation coefficient. For example, 8 bit in 100G, this bit width determines the depth of RAM that needs to be customized;
- bit width of the interpolation coefficient is determined according to an algorithm of the interpolation coefficient, and the sum of the bit widths of the tap coefficients of each tap coefficient (ie, the interpolation coefficient in the interpolation coefficient list) (if the symmetric coefficient is used, the bit width can be reduced by about half),
- the bit width determines the width of the RAM;
- phase deviation u value is traversed into the algorithm formula (as shown in FIG. 3), and the interpolation coefficient list (the head coefficient of the tap coefficients) corresponding to each u value is combined as the RAM storage content.
- the result of calculating all the u values will be configured as the storage contents of the entire RAM at the time of power-on.
- the interpolation filter can find the corresponding interpolation coefficient list (tap coefficient) according to the u value as the address;
- the depth and width of the RAM can be appropriately reserved to facilitate more difficult situations in the future, such as the transceiver clock jitter exceeds the algorithm expectations, the interpolation pointer needs to be widened, the tap needs to be increased, etc., which may increase the RAM.
- the depth and width can also be replaced in later versions such as 100G upgrade to 400G or even 1T.
- the interpolation coefficient can be flexibly configured according to different working conditions
- an apparatus for interpolating filtering includes: an obtaining module 301, and a searching module 302. And a calculation module 303; wherein the obtaining module 301 is configured to acquire a phase deviation of the received data;
- the searching module 302 is configured to determine, according to the relationship between the phase deviation pre-stored in the storage area and the interpolation coefficient list, an interpolation parameter list corresponding to the phase deviation of the data;
- the calculating module 303 is configured to calculate, by using the interpolation coefficient list as a tap coefficient of the data, the adjustment data corresponding to the data to generate the data.
- the apparatus further includes: a configuration module 304 configured to traverse the values of all phase deviations; and each phase deviation is respectively calculated by each formula in the interpolation algorithm to obtain a list of interpolation coefficients of each phase deviation; Each phase deviation stores a list of interpolation coefficients corresponding to each phase deviation to obtain a relationship between the phase deviation and the interpolation coefficient list.
- a configuration module 304 configured to traverse the values of all phase deviations; and each phase deviation is respectively calculated by each formula in the interpolation algorithm to obtain a list of interpolation coefficients of each phase deviation;
- Each phase deviation stores a list of interpolation coefficients corresponding to each phase deviation to obtain a relationship between the phase deviation and the interpolation coefficient list.
- the configuration module 304 is configured to traverse the values of all the phase deviations; each phase deviation is respectively calculated by each formula in the interpolation algorithm to obtain a list of interpolation coefficients of each phase deviation; each phase deviation is a storage address, and each phase is The list of interpolation coefficients corresponding to the deviation is stored in the storage address indicated by each phase deviation.
- the searching module 302 is specifically configured to acquire the interpolation coefficient list corresponding to the phase interpolation of the data from the address of the storage area by using the phase deviation of the data as an address.
- the apparatus also includes a depth configuration module 305 configured to determine a depth of the storage region based on a bit width of a value of the phase deviation.
- the apparatus also includes a width configuration module 306 configured to determine a width of the storage region based on a sum of bit widths of interpolation coefficients corresponding to all phase offsets.
- the integrated modules described in the embodiments of the present invention may also be stored in a computer readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
- Make a computer device can be a personal computing The machine, server, or network device, etc.) performs all or part of the methods described in various embodiments of the present invention.
- the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
- ROM read-only memory
- RAM random access memory
- magnetic disk or an optical disk, and the like.
- a method and apparatus for interpolation filtering acquires a phase deviation of received data; and determines a list of interpolation parameters corresponding to a phase deviation of the data according to a relationship between a phase deviation pre-stored in the storage region and a list of interpolation coefficients And calculating, by using the interpolation coefficient list as a tap coefficient of the data and the data to generate adjustment data corresponding to the data.
- the embodiments of the present invention solve at least the problems in the prior art, and can implement flexible configuration of interpolation coefficients and reduce delays by adding a small amount of overhead, thereby facilitating expansion of subsequent versions.
Landscapes
- Complex Calculations (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
本发明公开了一种插值滤波的方法，获取接收到的数据的相位偏差；根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
Description
本发明涉及通信领域，尤其涉及一种插值滤波的方法及装置。
本申请发明人在实现本申请实施例技术方案的过程中，至少发现相关技术中存在如下技术问题：
在传输技术的发展中，光纤被证明是一种不可或缺的媒介。如何用最少量的光纤传输最丰富的信息，出于这种探索，光传输的发展基本经历了以下几个阶段：空分复用阶段(SDM)、时分复用阶段(TDM)和波分复用阶段(WDM)。
时至今日有线传输依然以波分系统为主。随着通信技术的发展，目前商用的40G波分传输逐渐演变到100G、400G传输，与此同时，在数据传输距离上也在不断的拓展。这样，波分系统在传输过程中会带来色度色散、偏振膜色散、强滤波效应等诸多问题需要解决，这些问题的解决需要用数字信号处理的方法，后面称之为100G DSP处理。
对于一般通信系统收发两端时候非同源时钟，所以收发两端的时钟频率总是存在一定偏差。而且该偏差随着周围环境和自身板级散热的问题而不停抖动。这样的情况下，我们需要根据实时检测出来的相位偏差做样点之间的插值。
根据上面描述，在做插值滤波器的时候主要存在以下两个问题：
1、插值系数要求实时计算；
2、收发两端抖动不确定的情况下系数(或者说取值范围)不确定；
3、当系统需要升级时，硬件需要重新设计。
基于以上分析，如何实现灵活配置，时序好收敛、方法简便可扩展的插值滤波，在现有技术中缺乏相应的解决机制。
发明内容
有鉴于此，本发明实施例希望提供一种插值滤波的方法及装置，至少解决了现有技术存在的问题，能够实现灵活配置，时序好收敛、方法简便可扩展的插值滤波。
本发明实施例的技术方案是这样实现的：
本发明实施例的一种插值滤波的方法，所述方法包括：
获取接收到的数据的相位偏差；
根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；
以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
上述方案中，所述方法还包括：
遍历所有的相位偏差的值；
将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；
对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
上述方案中，对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系包括：
以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。
上述方案中，根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表包括：
以所述数据的相位偏差作为地址从所述存储区域的所述地址获取所述数据的相位插值对应的插值系数列表。
上述方案中，所述方法还包括：
根据相位偏差的值的位宽确定所述存储区域的深度。
上述方案中，所述方法还包括：
根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度。
本发明实施例的一种插值滤波的装置，所述装置包括：获取模块、查找模块和计算模块；其中，
所述获取模块，配置为获取接收到的数据的相位偏差；
所述查找模块，配置为根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；
所述计算模块，配置为以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
上述方案中，所述装置还包括：配置模块，配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
上述方案中，所述配置模块，具体配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。
上述方案中，所述查找模块，具体配置为以所述数据的相位偏差作为地址从所述存储区域的所述地址获取所述数据的相位插值对应的插值系数列表。
上述方案中，所述装置还包括：深度配置模块，配置为根据相位偏差的值的位宽确定所述存储区域的深度。
上述方案中，所述装置还包括：宽度配置模块，配置为根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度。
所述获取模块、所述查找模块、所述计算模块、所述配置模块、所述深度配置模块、所述宽度配置模块在执行处理时，可以采用中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例的一种插值滤波的方法及装置，获取接收到的数据的相位偏差；根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。采用本发明实施例，至少解决了现有技术存在的问题，能够通过增加少量开销的情况下，实现插值系数的灵活配置，并减少时延，方便扩展后续版本。
图1为本发明实施例一提供的插值滤波的方法的流程示意图；
图2为本发明实施例提供的100G波分传输系统的插值系数实时计算公式；
图3为传统的插值系数计算方法电路图；
图4为本发明实施例二提供的应用插值滤波方法的时钟恢复子系统框图的示意图；
图5为图4所示的插值滤波器的结构示意图；
图6为本发明实施例三提供的一种插值滤波的装置的结构示意图；
图7为本发明实施例三提供的另一种插值滤波的装置的结构示意图。
下面结合附图对技术方案的实施作进一步的详细描述。
实施例一
本发明实施例一提供一种插值滤波的方法，如图1所示，该方法包括：
S101：获取接收到的数据的相位偏差；
S102：根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；
S103：以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
在接收端的系统中预设一用于预设所有的相位偏差与插值系数列表的关系的存储区域，其中，根据相位偏差的值的位宽确定所述存储区域的深度，根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度，在确定了存储区域的深度和宽度之后，在存储区域中存储所有的相位偏差与插值系数列表的关系。
在本发明实施例中，该方法还包括：遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
在接收端，接收到的数据的相位偏差存在各种可能的值，以100G波分传输系统为例，其接收到的数据的相位偏差为8bit，进行编码后为00000000至11111111中的任何一位，即从0至255中的任何一位；100G波分传输系统的插值算法包括5个公式，如图2所示，包括h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)，表示相位偏差为u时的第一、第二、第三、第四、
第五个插值系数的公式，将u值通过这几个公式的计算得到u值对应的插值系数列表。遍历0-255所有的相位偏差的值，将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表，具体的，依次将0通过h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)的计算得到u为0时的插值系数列表，将1通过h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)的计算得到u为1时的插值系数列表，直到将255通过h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)的计算得到u为255时的插值系数列表，将0至255及其对应的插值系数列表存储在存储区域中得到相位偏差与插值系数列表的关系。
这里，对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系包括：以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。也就是说，在存储区域中，在地址00000000存储u为0对应的插值系数列表，在00000001存储u为1对应的插值系数列表，在地址00000010存储u为2对应的插值系数列表。
在S101中，通信系统的接收端接收到数据后，通过：时钟预滤波、鉴相、环路滤波的处理获取到接收到的数据的相位偏差，其中，时钟预滤波是在将色散造成的码间干扰滤除，鉴相完成时钟相位偏差的检查；环路滤波完成时钟相位偏差的滤波，获取到接收到的进行插值滤波数据的相位偏差。这里，数据的相位偏差的获取为现有技术，在这里不做详细陈述。
在S102中，将步骤S101中获取的接收到的数据的相位偏差与上述存储区域中存储的相位偏差与插值系数列表的关系进行匹配，查找该数据的相位偏差的插值系数列表。当数据的相位偏差为00000000时，查找0对应的插值系数列表，当数据的相位偏差为00001001时查找9对应的插值系数列表。
这里，对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系包括：以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。以相位偏差为00000000、00001001为例，当当数据的相位偏差为00000000时，查找存储区域中地址为00000000位置处存储的插值系数列表，当数据的相位偏差为00001001时查找存储区域中地址为00001001位置处存储的插值系数列表。
在S103中，将S102中查找的插值系数列表作为该数据的抽头系数，通过该抽头系数将接收到的数据进行调整，得到调整的数据进行发送，即将接收端的数据进行调整，使得系统的接受端与发送端的数据的时钟频率保持一致，实现收发端的时钟源同步。
需要说明的是，以100G波分传输系统为例，传统的插值滤波方法中的插值系数计算方法如图3所示，当插值滤波器接收到数据的相位偏差后，将相位偏差通过多个乘法器实现公式h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)的计算，h0(u)的计算需要将u通过三阶乘法器并与0.32376相乘得到的系数一，通过二阶乘法器并与0.04416相乘得到的系数二，通过一阶乘法器并与0.07683相乘得到的系数三，将系数一、系数二和系数三相加得到三系数之后，并进行饱和截位处理之后得到u通过h0(u)对应的插值系数，因此，当需要得到u对应的插值系数列表时，需要分别计算h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)对应的插值系数，才能得到插值系数列表。在现有的插值滤波的方法中，插值系数为实时通过计算出来的，系统复杂，并且随着周围环境和自身板级散热的问题插值不停抖动，导致收发两端抖动不确定的情况下插值系数(或者取值范围)不确定；更进一步的，当系统需要升级时，硬件需要重新设计，则消耗大量的人力资源。
而本发明实施例提供的插值滤波的方法中，将插值系数预先配置在系
统中，将插值算法的插值系数计算公式的所有可能结果遍历后存入存储区域中，从而在芯片内部实现查表来代替实时计算，即提高了速度，降低了功耗，同时还极大增强了灵活性。这里，存储区域可为随机存取存储器(RAM，Random Access Memory)。
图4为本发明实施例四提供的应用插值滤波方法的时钟恢复子系统框图的示意图；时钟恢复子系统在100G中占据非常重要的位置，如图4所示，包括四个主要部分，分别是：时钟预滤波、鉴相、环路滤波以及插值滤波器。其中，时钟预滤波是在将色散造成的码间干扰滤除；鉴相完成时钟相位偏差的检查；环路滤波完成时钟相位偏差的滤波；插值滤波器完成基于相位偏差的插值。本发明实施例提供的插值滤波方法的具体实现可在该系统中的插值滤波器中实现。
该插值滤波器的结构示意图如图5所示，可说明本发明实施例提供的插值滤波的计算方式；当获取到数据的插值偏差u时，将u输入RAM(256x26)中，通过查表的方式获取u通过h0(u)、h1(u)、h2(u)、h3(u)、h4(u)、h5(u)的计算的插值系数，即获取到u对应的插值列表系数，
实施例二
在实际的应用中，适用于100G光传输系统中的本发明实施例提供的插值滤波器方法，
该方法的实现可利用专用集成电路(Application Specific Integrated Circuit，ASIC)成熟的RAM IP核，将插值系数的算法的插值系数的计算公式的所有可能结果遍历后存入存储区域RAM中，从而在芯片内部实现查表来代替现有的实时计算，即提高了速度，降低了功耗，同时还极大增强了灵活性。
具体描述如下：
首先，根据插值系数的算法需求，确定插值指针(图2中的u)的位宽，
如100G中的8bit，该位宽决定了需要定制的RAM的深度；
其次，根据插值系数的算法确定插值系数的位宽，每个抽头系数的抽头系数(即插值系数列表中的插值系数)的位宽总和(如果是对称系数，位宽可以减少约一半)，该位宽决定了RAM的宽度；
最后，将相位偏差u值遍历后代入算法公式(如图3)，将每个u值对应的插值系数列表(抽头系数的轴头系数)组合起来作为RAM存储内容。其中，可将所有u值计算出来的结果将作为整个RAM的存储内容在上电时配置进去。系统工作时插值滤波器根据u值作为地址就可以查找出相对应的插值系数列表(抽头系数)；
当然，RAM的深度和宽度可以适当的留一些裕量，以方便将来遇到更恶劣情况，比如说收发端时钟抖动超过算法预期，插值指针需要拓宽，抽头需要增加等等，这些将可能增加RAM的深度和宽度，当然，这些也可以在比如100G升级到400G甚至1T时的后期版本中替换。
通过增加上述处理流程和装置，增加少量开销的情况下，达到了以下效果：
1、插值系数可以根据不同工况灵活配置；
2、系统时延减少，对于100G这样大数据量系统来说，时延减少能够显著提高系统性能；
3、通过使用RAM还能使得系统功耗降低，因为对于RAM的控制要比控制一堆寄存器和组合如图3逻辑简单，时钟关断很方便；
4、后续版本如果想增大或者减小RAM，可以很方便的替换，不用重新设计电路。
实施例三
为实现上述一种插值滤波的方法及装置，本发明实施例还提供一种插值滤波的装置，如图6所示，所述装置包括：获取模块301、查找模块302
和计算模块303；其中，获取模块301，配置为获取接收到的数据的相位偏差；
查找模块302，配置为根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；
计算模块303，配置为以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
如图7所示，该装置还包括：配置模块304，配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
配置模块304，具体配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。
这里，查找模块302，具体配置为以所述数据的相位偏差作为地址从所述存储区域的所述地址获取所述数据的相位插值对应的插值系数列表。
该装置还包括：深度配置模块305，配置为根据相位偏差的值的位宽确定所述存储区域的深度。
该装置还包括：宽度配置模块306，配置为根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度。
本发明实施例所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算
机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
本发明实施例的一种插值滤波的方法及装置，获取接收到的数据的相位偏差；根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。采用本发明实施例，至少解决了现有技术存在的问题，能够通过增加少量开销的情况下，实现插值系数的灵活配置，并减少时延，方便扩展后续版本。
Claims (12)
- 一种插值滤波的方法，所述方法包括：获取接收到的数据的相位偏差；根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
- 根据权利要求1所述的方法，其中，所述方法还包括：遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
- 根据权利要求2所述的方法，其中，对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系包括：以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。
- 根据权利要求3所述的方法，其中，根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表包括：以所述数据的相位偏差作为地址从所述存储区域的所述地址获取所述数据的相位插值对应的插值系数列表。
- 根据权利要求1所述的方法，其中，所述方法还包括：根据相位偏差的值的位宽确定所述存储区域的深度。
- 根据权利要求1所述的方法，其中，所述方法还包括：根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度。
- 一种插值滤波的装置，所述装置包括：获取模块、查找模块和计算模块；其中，所述获取模块，配置为获取接收到的数据的相位偏差；所述查找模块，配置为根据存储区域中预先存储的相位偏差与插值系数列表的关系确定所述数据的相位偏差对应的插值参数列表；所述计算模块，配置为以所述插值系数列表作为所述数据的抽头系数与所述数据进行计算生成所述数据对应的调整数据。
- 根据权利要求7所述的装置，其中，所述装置还包括：配置模块，配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；对应各相位偏差将各相位偏差对应的插值系数列表进行存储得到相位偏差与插值系数列表的关系。
- 根据权利要求8所述的装置，其中，所述配置模块，配置为遍历所有的相位偏差的值；将各相位偏差分别通过插值算法中的每个公式的计算得到各相位偏差的插值系数列表；以各相位偏差为存储地址，将各相位偏差对应的插值系数列表分别存储在各相位偏差所表示的存储地址。
- 根据权利要求9所述的装置，其中，所述查找模块，配置为以所述数据的相位偏差作为地址从所述存储区域的所述地址获取所述数据的相位插值对应的插值系数列表。
- 根据权利要求7所述的装置，其中，所述装置还包括：深度配置模块，配置为根据相位偏差的值的位宽确定所述存储区域的深度。
- 根据权利要求7所述的装置，其中，所述装置还包括：宽度配置模块，配置为根据所有相位偏差对应的插值系数的位宽的总和确定所述存储区域的宽度。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510264521.2A CN106301664A (zh) | 2015-05-22 | 2015-05-22 | 一种插值滤波的方法及装置 |
| CN201510264521.2 | 2015-05-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2016188055A1 true WO2016188055A1 (zh) | 2016-12-01 |
Family
ID=57392390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2015/094775 Ceased WO2016188055A1 (zh) | 2015-05-22 | 2015-11-17 | 一种插值滤波的方法及装置 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106301664A (zh) |
| WO (1) | WO2016188055A1 (zh) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007080469A (ja) * | 2005-09-16 | 2007-03-29 | Sony Corp | 位相同期ループ回路、位相同期ループ回路のループフィルタゲイン制御方法並びに再生装置 |
| CN101278495A (zh) * | 2005-09-30 | 2008-10-01 | 富士通株式会社 | 过采样和横向均衡器 |
| CN103313315A (zh) * | 2012-03-14 | 2013-09-18 | 华为技术有限公司 | 速率转换装置及其方法、基站设备 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064900B (zh) * | 2010-12-28 | 2014-09-10 | 中兴通讯股份有限公司 | 一种时钟同步方法与装置 |
| KR101851712B1 (ko) * | 2012-01-31 | 2018-06-11 | 삼성전자주식회사 | 디지털 시변 필터를 이용한 다채널 오디오 신호 변환 장치, 이를 포함하는 전자 시스템, 및 디지털 시변 필터를 이용한 다채널 오디오 신호 변환 방법 |
-
2015
- 2015-05-22 CN CN201510264521.2A patent/CN106301664A/zh active Pending
- 2015-11-17 WO PCT/CN2015/094775 patent/WO2016188055A1/zh not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007080469A (ja) * | 2005-09-16 | 2007-03-29 | Sony Corp | 位相同期ループ回路、位相同期ループ回路のループフィルタゲイン制御方法並びに再生装置 |
| CN101278495A (zh) * | 2005-09-30 | 2008-10-01 | 富士通株式会社 | 过采样和横向均衡器 |
| CN103313315A (zh) * | 2012-03-14 | 2013-09-18 | 华为技术有限公司 | 速率转换装置及其方法、基站设备 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106301664A (zh) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7773606B2 (en) | Timing distribution within a network element while supporting multiple timing domains | |
| US10135543B2 (en) | Clock recovery method, device and system and computer storage medium | |
| US9967084B2 (en) | Synchronising devices using clock signal time difference estimation | |
| US11650619B2 (en) | Synchronising devices using clock signal delay estimation | |
| JP6310091B2 (ja) | 色度分散測定方法、装置およびデジタルコヒーレント受信機 | |
| JP2014238357A (ja) | 受信装置、時刻差算出方法、およびプログラム | |
| JP6165888B2 (ja) | １０ｇｂａｓｅ−ｔシステムにおけるデータ支援型タイミング回復のための方法および装置 | |
| CN110300450A (zh) | 一种利用自适应滤波器校正ieee 1588协议的时钟伺服方法 | |
| JP5592001B2 (ja) | 組込みクロック信号の多重化および逆多重化を含むデータ送信 | |
| CN114337725B (zh) | 非相干直接序列扩频信号位同步方法、装置、设备及介质 | |
| US10554379B2 (en) | Method for obtaining phase detection signal in clock recovery circuit and phase detector | |
| JP2008071349A (ja) | クロック信号発生方法及び装置、それを利用したクロック周波数制御方法及び装置 | |
| CN117318872B (zh) | 一种tdev时域噪声产生方法及装置 | |
| CN110661578B (zh) | 一种数据恢复方法及装置 | |
| WO2016188055A1 (zh) | 一种插值滤波的方法及装置 | |
| CN109286482B (zh) | 一种实现时钟恢复的方法及装置 | |
| US20220148623A1 (en) | Media Recording System | |
| CN107005395B (zh) | 一种时钟同步方法、接收器、发送器和系统 | |
| US10680793B2 (en) | Synchronising devices using clock signal delay comparison | |
| CN111464254B (zh) | 一种时钟同步方法、装置及电子设备 | |
| CN105323053A (zh) | 业务时钟透传的方法及装置 | |
| JP2015019372A (ja) | データ分析システム及び方法 | |
| CN114285509B (zh) | Aau群时延波动补偿方法、装置、电子设备及存储介质 | |
| Alpar | Dynamics of a new generalized fractional one-dimensional map: quasiperiodic to chaotic | |
| JP6454797B2 (ja) | 強フィルタリングの補償方法、装置及びコンピュータ記憶媒体 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15893125 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 15893125 Country of ref document: EP Kind code of ref document: A1 |