WO2016184291A1 - 一种帧头检测的方法及装置 - Google Patents

一种帧头检测的方法及装置 Download PDF

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Publication number
WO2016184291A1
WO2016184291A1 PCT/CN2016/079914 CN2016079914W WO2016184291A1 WO 2016184291 A1 WO2016184291 A1 WO 2016184291A1 CN 2016079914 W CN2016079914 W CN 2016079914W WO 2016184291 A1 WO2016184291 A1 WO 2016184291A1
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data
frame
frame header
length
sliding window
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PCT/CN2016/079914
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English (en)
French (fr)
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史学明
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中兴通讯股份有限公司
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Priority to EP16795778.6A priority Critical patent/EP3300290A4/en
Publication of WO2016184291A1 publication Critical patent/WO2016184291A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0608—Detectors therefor, e.g. correlators, state machines

Definitions

  • the present invention relates to, but is not limited to, a DWDM (Dens Wavelength Division Multiplexing) high-speed optical transmission system, and more particularly to a method and apparatus for frame header detection.
  • DWDM Dens Wavelength Division Multiplexing
  • the received data and the transmitted data are not synchronized due to the delay of the transceiver device, the dispersion of the channel, the signal processing, and the like.
  • data is transmitted in units of frames, and the frame structure includes a frame header, a pilot sequence, and data; at the receiving end, frame header detection, frame fixation, frame header deletion, and pilot sequence are performed.
  • the coherent receiver design also has frame positioning. Requirements. In addition to the influence of channels and devices, data buffers, interpolation values, etc. in digital signal processing (DSP) also affect the position of the frame header. In addition, there is a skew (clock offset) between the polarization states, each The position of the frame header of the polarization state is not the same. Therefore, frame positioning requires strict design requirements and good stability. As long as the frame is successfully set, the data is transmitted directly. Therefore, frame positioning is an indispensable key module in the receiver, which directly determines whether the system is normal.
  • DSP digital signal processing
  • the structure of a 100G PM-QPSK optical transmission system is shown in Figure 1.
  • the laser (LD, Laser Diode) emitted by the light emitting end is split into two polarized beams by a PBS (Polarization Beam Splitter).
  • the polarized light is respectively modulated by MZ (Mach-Zehnder) with an electric signal amplified by an electric driver through an electric driver, and two sets of orthogonal signals are obtained through a PBC (Polarization Beam Combiner) to obtain a polarization.
  • MZ Machine-Zehnder
  • PBC Polarization Beam Combiner
  • the beam splitter separates the two polarized light signals and demodulates them with the optical signals emitted by the local oscillator (LO, Local Oscillator), respectively, through 90-degree hybrid (hybrid), photoelectric (O/E, Optical/Electrical) conversion, analog-to-digital converter (ADC, Analog-to-Digital Converter) acquisition, to obtain four digital signals, and digital signal processing.
  • the signal enters the DSP, undergoes dispersion compensation; performs clock recovery processing on the data after the dispersion is eliminated; adaptively equalizes to eliminate residual dispersion and polarization mode dispersion, and polarizes and demultiplexes the two polarization states;
  • the laser itself has linewidth and other factors. It needs to compensate the data for frequency offset and phase offset.
  • After the DSP equalization compensation data can recover the constellation point normally, the data will be compensated after equalization.
  • the frame positioning subsystem is sent for frame
  • a full frame data method or a partial data method is generally used.
  • the method of scanning the entire frame of data requires pre-storing the data of the entire frame, and the amount of data storage is too large, especially for an Application Specific Integrated Circuit (ASIC) system, which occupies a large amount of storage resources; Part of the data method will also add more logical resources.
  • ASIC Application Specific Integrated Circuit
  • the embodiment of the invention provides a method and a device for detecting a frame header.
  • the frame header is detected to implement frame positioning, thereby avoiding buffering large amounts of data and frequent sliding. Search saves related processing resources.
  • An embodiment of the present invention provides a method for detecting a frame header, including:
  • the sliding window is slidably shifted by one bit each time a data stream of one frame length is received, and the sliding window stops sliding after detecting the frame header.
  • the length of the frame data is greater than 2M.
  • the data stream of the received frame data includes: receiving the frame data from the M parallel processing branches, and performing parallel-to-serial conversion on the data received on each branch to obtain a data stream of the frame data.
  • the receiving the data stream of the frame data and buffering the received data according to the length of the M bit includes: receiving the first path branch of the frame data, and buffering according to the length of the M bit;
  • the method further includes: performing frame processing on a second path branch of the data stream of the frame data according to a position of the frame header, the first path branch and the second path A road branch is two branches of the same data stream.
  • the detecting the frame header according to the result of the correlation operation includes:
  • the frame data is frame data of a 100G PM-QPSK optical transmission system.
  • An embodiment of the present invention provides a device for detecting a frame header, including:
  • the receiving module is configured to: receive the data stream of the frame data, and buffer the received data according to the length of the M bits, to obtain a bit sequence of each group of M bits, wherein, when receiving the Nth group of bit sequences, discarding a buffered N-2th bit sequence, the N being greater than or equal to 3, the M being less than a length of the frame data and greater than or equal to a length of a frame header;
  • the operation module is configured to: after each receiving a set of bit sequences, perform a correlation operation on the pre-stored frame header sequence and the corresponding data in the sliding window in the current serial data, wherein the current serial data is a set of bit sequences spliced with the currently received bit sequence;
  • a detecting module configured to: detect the frame header according to a result of the correlation operation, wherein the sliding window is slidingly shifted by one bit after receiving a data stream of one frame length before detecting the frame header The sliding window stops sliding after detecting the frame header.
  • the length of the frame data in the receiving module is greater than 2M.
  • the receiving module is configured to receive the data stream of the frame data by receiving the frame data from the M parallel processing branches, and performing parallel-to-serial conversion on the data received on each branch to obtain the The data stream of the frame data.
  • the receiving module is configured to receive a data stream of frame data in the following manner, and buffer the received data according to the length of the M bit: receiving the first path branch of the frame data, and according to the M bit The length of the cache;
  • the device further includes: a framing module, configured to: after the detecting module detects the frame header, frame the second branch of the data stream of the frame data according to the position of the frame header Processing, wherein the first way branch and the second way branch are two branches of the same data stream.
  • a framing module configured to: after the detecting module detects the frame header, frame the second branch of the data stream of the frame data according to the position of the frame header Processing, wherein the first way branch and the second way branch are two branches of the same data stream.
  • the detection module is set to:
  • the frame data in the receiving module is frame data of a 100G PM-QPSK optical transmission system.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, which are implemented when the computer executable instructions are executed.
  • the method for detecting a frame header caches a data stream of frame data according to a certain length to obtain a fixed length bit sequence, and splicing the previous set of bit sequences with the current bit sequence to obtain current serial data, and discarding the previously cached data.
  • Bit sequence, pre-stored frame header sequence and current serial number The correlation operation is performed according to the corresponding data in the sliding window.
  • 1 is a structural view showing a related art 100G PM-QPSK optical transmission system
  • FIG. 2 is a schematic flowchart diagram of a method for frame header detection according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram showing correlation of a frame header detection position slip in a method for frame header detection according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing a data flow branch of frame data in a method for frame header detection according to an embodiment of the present invention
  • FIG. 5 is a schematic overall flowchart of a method for frame header detection according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram showing an apparatus for frame header detection according to an embodiment of the present invention.
  • the embodiment of the invention provides a method for detecting a frame header. As shown in FIG. 2, the method includes the following steps:
  • Step S100 Receive a data stream of frame data, and buffer the received data according to the length of the M bits, to obtain a bit sequence of each group of M bits, wherein, when receiving the Nth group of bit sequences, discarding the cached N-2 group bit sequence, the N is greater than or equal to 3, the M is smaller than the length of the frame data and greater than or equal to the length of the frame header;
  • Step S200 after each receiving a group of bit sequences, performing a correlation operation on the pre-stored frame header sequence and the corresponding data in the sliding window in the current serial data, wherein the current serial data is from the previous group of bits.
  • the sequence is spliced with the currently received bit sequence, and the length of the data in the sliding window is equal to the length of the frame header;
  • Step S300 detecting the frame header according to the result of the correlation operation, wherein the sliding window is slidingly shifted by one bit after receiving the data stream of one frame length before detecting the frame header, and detecting The sliding window stops sliding after the frame header.
  • the method for detecting the frame header in the embodiment of the present invention can detect the frame header by performing correlation operation on the sliding shifted data and the frame header sequence, thereby realizing system frame positioning, avoiding buffering large amounts of data and frequent sliding search, and saving Related processing resources.
  • the data stream of the received frame data can be buffered by a length of 64 bits to obtain a bit sequence of 64 bits each.
  • the buffered first group of bit sequences may be discarded
  • the buffered second group of bit sequences may be discarded, and the bit sequence length is smaller than the frame. The length of the data.
  • the previous 64-bit bit sequence is spliced with the currently received 64-bit bit sequence to obtain 128-bit current serial data.
  • the 64-bit data in the 128-bit current serial data in the sliding window is correlated with the 64-bit data of the pre-stored Frame Head sequence to perform frame header detection. It should be noted that the length of the data in the sliding window is equal to the length of the frame header. Before the frame header is detected, the position of the sliding window in the current serial data will be shifted by one bit each time a stream of one frame length is received.
  • the current sliding window (identified by the index (Index)) is initially positioned in the first to the 64th bits of the current serial data, and the pre-stored frame header sequence is correlated with the data in the sliding window, if the result of the correlation operation indicates that When the frame header is detected, the correlation operation for the next serial data is continued while the next serial data arrives.
  • the sliding window is moved by one bit, that is, the sliding window is positioned in the 2nd to 65th bits of the current serial data and the correlation operation is performed. And so on.
  • the result of the correlation operation indicates that the frame header is detected within the current sliding window, the sliding of the window is stopped. It can be seen from the analysis that up to 64 frame lengths of data may be received before the frame header is detected. That is to say, the embodiment of the present invention can detect the frame header in the M frame.
  • the previous 64-bit bit sequence is spliced with the currently received 64-bit bit sequence to obtain 128-bit current serial data.
  • the 32-bit data in the 128-bit current serial data in the sliding window is correlated with the 32-bit data of the pre-stored frame header sequence to perform frame header detection.
  • the position of the sliding window in the current serial data will be shifted by one bit each time a stream of one frame length is received. For example, suppose that the current sliding window is initially positioned in the first to 32 bits of the current serial data, and the pre-stored frame header sequence is correlated with the data in the sliding window.
  • the correlation operation for the next serial data continues. Wherein, if the length of the received data reaches the length of one frame when the next serial data arrives, the sliding window is moved by one bit, that is, the sliding window is positioned in the 2nd to 33th bits of the current serial data and the correlation operation is performed. And so on. If the result of the correlation operation indicates that the frame header is detected within the current sliding window, the sliding of the window is stopped. It can be seen from the analysis that up to 64 frame lengths of data may be received before the frame header is detected. That is to say, the embodiment of the present invention can detect the frame header in the M frame.
  • bit sequence of the current group is the first group of bit sequences, since there is no bit sequence before, the current group bit sequence cannot be spliced with the previous group of bit sequences, and the current group bit sequence needs to be performed. Cache, splicing with the next set of bit sequences.
  • the length of the frame data in the step S100 is an integer multiple of M, preferably greater than 2M, and may be selected according to the actual chip and the application scenario.
  • M the smaller the cache resource and the related operation.
  • the processing resource requirements are small, but the time required to detect the frame header (or the length of the received data) is larger; conversely, the larger M is, the greater the processing resource requirements for the cache resource and the related operation, but the detection The less time (or the length of data received) to reach the frame header.
  • the received data stream is a soft data stream in a polarization state.
  • a hard decision is needed on the data stream to obtain a binary bit stream, where each data stream includes two data streams of I and Q respectively.
  • the hard decision is made on the data stream, including:
  • the data in the I channel and the Q channel are respectively determined. When a certain bit data in the I channel and the Q channel data is greater than or equal to 0, the bit value is determined to be 0; when in the I channel and the Q channel data When a bit of data is less than 0, it is determined that the bit value is 1, and two bit streams are obtained.
  • the I and Q bit streams in the data stream after the hard decision are separately decoded differentially, and the obtained data has no frequency offset and phase offset blur.
  • the data stream of the received frame data in step S100 includes: receiving the frame data from the M parallel processing branches, and performing parallel-to-serial conversion on the data received on each branch to obtain a The data stream of the frame data.
  • the M-channel parallel data processing branch may be provided by using a DSP chip, and then the data received on each branch is parallel-converted to obtain a serial data stream, and then the serial data stream may be
  • the above processing procedure of the embodiment of the present invention is performed to perform frame header positioning.
  • step S100 the data stream of the frame data is received, and the received data is buffered according to the length of the M bits: receiving the first branch of the frame data, and according to M The length of the bit is cached;
  • the method further includes: performing frame processing on a second path branch of the data stream of the frame data according to a position of the frame header, the first path branch and the second path A road branch is two branches of the same data stream.
  • the data stream after the DSP equalization compensation is divided into two branches, and the first branch of the data stream of the frame data is first subjected to hard decision and differential decoding. Then, according to the length of the M bits, the buffer is buffered according to the length of the M bits, and then the splicing process and the related detection are performed, and the frame header is detected through the sliding offset position. After the frame header is detected, the second branch of the data stream located in the same frame data as the first way branch is framed.
  • step S200 the pre-stored frame header sequence is correlated with the corresponding data in the current serial data in the sliding window, including:
  • the sliding window is positioned in a certain area of the current serial data, and then the data in the sliding window is compared with the data in the pre-stored frame header sequence, because it is in the sliding window
  • the data is the same as the number of bits of the data in the pre-stored frame header sequence, and the data in the sliding window is compared with the data in the pre-stored frame header sequence to perform correlation operations.
  • step S300 detecting the frame header according to the result of the correlation operation, including:
  • the sliding window when the data in the sliding window is compared with the data in the pre-stored frame header sequence, if the same data bit number in the two is greater than a preset threshold, it indicates that the frame header is detected. If the same number of data bits in the two is less than or equal to the preset threshold, it indicates that the frame header has not been detected and the detection needs to be continued.
  • the sliding window is slid and shifted by one bit to perform a correlation operation.
  • the frame data is frame data of a 100G PM-QPSK optical transmission system.
  • FIG. 5 The overall process of the embodiment of the present invention is shown in FIG. 5:
  • Step S101 Receive a data stream of frame data.
  • Step S102 performing a hard decision on the data stream. Since the received data stream is a soft data stream of a polarization state, it is also necessary to perform a hard decision on the data stream to obtain a binary bit stream. In the hard decision, the I and Q data of each data stream are determined.
  • Step S103 performing differential decoding on the data stream after the hard decision.
  • the data after differential decoding has no frequency offset and phase offset blur.
  • Step S104 Cache the frame data according to the length of the M bits to obtain a plurality of M bit bit sequences.
  • Step S105 splicing the current bit sequence with the previous bit sequence to obtain current serial data.
  • step S106 a correlation operation is performed.
  • the correlation operation is performed, the pre-stored frame header sequence is correlated with the corresponding data in the current serial data that is in the sliding window.
  • the sliding window is slid and shifted by one bit after receiving a data stream of one frame length, and the sliding window stops sliding after detecting the frame header.
  • step S107 it is determined whether the frame header is detected. If the frame header is detected, the next step S108 is performed. If not, the process returns to step S106 to perform a correlation operation.
  • Step S108 Record the position of the frame header.
  • Step S109 data is framed.
  • Step S110 exiting frame positioning, and the process ends.
  • An embodiment of the present invention provides a device for detecting a frame header. As shown in FIG. 6, the device includes:
  • the receiving module 10 is configured to: receive the data stream of the frame data, and buffer the received data according to the length of the M bits, to obtain a bit sequence of each group of M bits, wherein, when receiving the Nth group of bit sequences, discarding a buffered N-2th bit sequence, the N being greater than or equal to 3, the M being less than a length of the frame data and greater than or equal to a length of a frame header;
  • the operation module 20 is configured to: after each receiving a set of bit sequences, perform a correlation operation on the pre-stored frame header sequence and the corresponding data in the current serial data in the sliding window, wherein the current serial data is a set of bit sequences spliced with the currently received bit sequence, the data length in the sliding window being equal to the length of the frame header;
  • the detecting module 30 is configured to: detect the frame header according to a result of the correlation operation, wherein the sliding window is slidingly shifted by one bit after receiving a data stream of one frame length before detecting the frame header The sliding window stops sliding after detecting the frame header.
  • the length of the frame data in the receiving module 10 is greater than 2M.
  • the receiving module 10 is configured to receive a data stream of frame data by receiving the frame data from M parallel processing branches and performing data received on each branch.
  • the parallel stream conversion is performed to obtain a data stream of the frame data.
  • the receiving module 10 is configured to receive a data stream of frame data in the following manner, and buffer the received data stream according to the length of the M bits: the number of the frames The first branch of the data is received and buffered according to the length of the M bits;
  • the apparatus further includes: a framing module 40, configured to: after the detecting module 30 detects the frame header, perform data flow on the frame data according to a position of the frame header
  • the second branch performs framing processing, wherein the first branch and the second branch are two branches of the same data stream.
  • the detecting module 30 is configured to:
  • the frame data in the receiving module 10 is frame data of a 100G PM-QPSK optical transmission system.
  • the method for detecting a frame header caches a data stream of frame data according to a certain length to obtain a fixed length bit sequence, and splicing the previous set of bit sequences with the current bit sequence to obtain current serial data, and discarding the previously cached data.
  • the bit sequence correlates the pre-stored frame header sequence with the corresponding data in the current serial data that is in the sliding window.
  • the device for detecting the frame header provided by the embodiment of the present invention is a device applying the above method, and all the embodiments of the foregoing method are applicable to the device, and all of the same or similar beneficial effects can be achieved.
  • an embodiment of the present invention further provides a computer readable storage medium storing computer executable instructions, the method for implementing the frame header detection when the computer executable instructions are executed.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • This application is not limited to any specific combination of hardware and software.
  • the embodiment of the invention provides a method and a device for detecting a frame header.
  • frame positioning can be implemented, and a large amount of data and frequent sliding are avoided. Search saves related processing resources.

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Abstract

一种帧头检测的方法，包括：接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，所述M小于所述帧数据的长度且大于或等于帧头的长度；在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算；根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。上述方法通过对滑动移位后的接收数据与帧头序列进行相关比较，检测帧头，以实现帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。

Description

一种帧头检测的方法及装置 技术领域
本申请涉及但不限于密集型光波复用(DWDM，Dense Wavelength Division Multiplexing)高速光传输系统，尤其涉及一种帧头检测的方法及装置。
背景技术
通信系统中，由于收发器件的时延、信道的色散、信号处理等，导致接收数据与发送数据不同步。为了实现数据同步，在发送端，数据要以帧为单位发送，帧结构包括帧头、导频序列、数据；在接收端，要进行帧头检测、定帧、删除帧头和导频序列。
对于应用在骨干网承载大容量数据传输的DWDM高速光传输系统，例如100G PM-QPSK(Polarization-Multiplexed Quadrature Phase Shift Keying，偏振复用正交相位调制)系统，相干接收机设计也同样存在帧定位的要求。除了信道、器件的影响外，数字信号处理(DSP，Digital Signal Processing)内的数据缓存、插删值等也影响帧头的位置，另外，偏振态之间存在skew(时钟偏移)，每个偏振态的帧头位置并不相同。因此，帧定位需要严格的设计要求和很好的稳定性，只要定帧成功，数据就直接传送。所以，帧定位是接收机中不可缺少的一个关键模块，直接决定着系统是否正常。
一种100G PM-QPSK光传输系统的结构如图1所示，光发射端的激光器(LD，Laser Diode)发射光经过PBS(Polarization Beam Splitter，分束器)分为两束偏振光，这两束偏振光分别与数字信号经过电驱动器(electrical driver)放大的电信号进行马赫曾德尔(MZ，Mach-Zehnder)调制，得到两组正交信号经过PBC(Polarization Beam Combiner，合束器)，得到偏振复用的光信号，再经过光合波器(OMU，Optical Multiplexing Unit)，通过信道到达光接收端；相干接收机接收到光通道数据单元(ODU，Optical Data Unit)的光信号后，经过光分束器(PBS)将两路偏振光信号分开，并分别与本振激光器(LO，Local Oscillator)发射的光信号进行解调，经90度混频(hybrid)、光电(O/E， Optical/Electrical)转换，模/数转换器(ADC，Analog-to-Digital Converter)采集，得到四路数字信号，并进行数字信号处理。信号进入到DSP中，经过色散补偿；对消除色散后的数据进行时钟恢复处理；通过自适应均衡以便消除残余的色散和偏振模色散，并将两个偏振态进行偏振解复用；由于本振激光器和发端激光器存在频偏，激光器本身存在线宽等因素，需要对数据进行频偏补偿和相偏补偿；经过DSP均衡补偿的数据已经可以正常恢复出星座点，所以将经过均衡补偿后的数据送入帧定位子系统进行帧定位。
对于接收机中的帧定位方法，一般采用扫描整帧数据方法或者扫描部分数据方法。但是，扫描整帧数据方法，需要对整帧的数据进行预先存储，数据存储量太大，尤其是对特定用途集成电路(ASIC，Application Specific Integrated Circuit)系统，会占用大量存储资源；另外，扫描部分数据方法，也会增加更多的逻辑资源。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种帧头检测的方法及装置，通过对滑动移位后的接收数据与帧头序列进行相关比较，检测帧头，以实现帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。
本发明实施例提供一种帧头检测的方法，包括：
接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的；
根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前， 每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
其中，所述帧数据的长度大于2M。
其中，所述接收帧数据的数据流包括：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
其中，所述接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存包括：对所述帧数据的第一路分支进行接收，并按照M位的长度进行缓存；
在检测到所述帧头后，所述方法还包括：根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，所述第一路分支和第二路分支为同一数据流的两个分支。
其中，所述根据所述相关运算的结果检测所述帧头，包括：
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
其中，所述帧数据为100G PM-QPSK光传输系统的帧数据。
本发明实施例提供一种帧头检测的装置，包括：
接收模块，设置为：接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
运算模块，设置为：在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的；
检测模块，设置为：根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
其中，所述接收模块中的所述帧数据的长度大于2M。
其中，所述接收模块是设置为通过以下方式接收帧数据的数据流：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
其中，所述接收模块是设置为通过以下方式接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存：对所述帧数据的第一路分支进行接收，并按照M位的长度进行缓存；
所述装置还包括：定帧模块，设置为：在所述检测模块检测到所述帧头后，根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，其中，所述第一路分支和第二路分支为同一数据流的两个分支。
其中，所述检测模块是设置为：
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
其中，所述接收模块中的所述帧数据为100G PM-QPSK光传输系统的帧数据。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现上述帧头检测的方法。
本发明实施例的上述技术方案至少具有如下有益效果：
本发明实施例的帧头检测的方法，对帧数据的数据流按照一定长度进行缓存，得到固定长度比特序列，将上一组比特序列与当前比特序列拼接得到当前串行数据，丢弃之前缓存的比特序列，将预存的帧头序列与当前串行数 据中处于滑动窗口内的对应数据进行相关运算。通过对滑动移位后的接收数据与帧头序列进行相关比较，检测帧头，可以实现帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1表示相关技术的100G PM-QPSK光传输系统的结构图；
图2表示本发明实施例的帧头检测的方法的流程示意图；
图3表示本发明实施例的帧头检测的方法中帧头检测位置滑动的相关示意图；
图4表示本发明实施例的帧头检测的方法中帧数据的数据流分支示意图；
图5表示本发明实施例的帧头检测的方法的整体流程示意图；
图6表示本发明实施例的帧头检测的装置的示意图。
本发明的实施方式
下面将结合附图及具体实施例对本申请进行详细描述。
本发明实施例提供一种帧头检测的方法，如图2所示，所述方法包括以下步骤：
步骤S100、接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
步骤S200、在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的，所述滑动窗口内的数据长度等于所述帧头的长度；
步骤S300、根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
本发明实施例的帧头检测的方法，可以通过对滑动移位后的数据与帧头序列进行相关运算，检测帧头，可以实现系统帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。
下面将以具体示例对以上方法作更为具体的描述。
例如，假设帧头的长度为64位或32位，本示例中可以将接收到的帧数据的数据流按照64位的长度进行缓存，得到每组长度为64位的比特序列。其中，在接收过程中，在接收第3组比特序列时，可以丢弃缓存的第1组比特序列，在接收第4组比特序列时，可以丢弃缓存的第2组比特序列，比特序列长度小于帧数据的长度。
下面对这两种情况进行分析。
当帧头的长度为64位时：
如图3所示，在接收到一组64位的比特序列后，将上一组64位的比特序列与当前接收到的64位的比特序列进行拼接得到128位的当前串行数据。将128位当前串行数据中处于滑动窗口内的64位数据与预存的帧头(Frame Head)序列的64位数据进行相关运算，进行帧头的检测。需要说明的是，滑动窗口内的数据长度等于帧头的长度。在检测到帧头之前，每接收到一帧长度的数据流后滑动窗口在当前串行数据中的位置将滑动移位一个比特位。例如，假设当前滑动窗口(由索引(Index)标识)初始定位在当前串行数据的第1到64位，将预存帧头序列与滑动窗口内的数据进行相关运算，若相关运算的结果表明未检测到帧头，则在下一个串行数据到来时继续针对下一个串行数据进行相关运算。其中，若下一个串行数据到来时已接收到的数据长度达到一个帧的长度，则将滑动窗口移动一个比特位，即将滑动窗口定位在当前串行数据的第2到65位并进行相关运算，以此类推。若相关运算的结果表明在当前滑动窗口内检测到帧头，则停止窗口的滑动。通过分析可以看出，在检测到帧头前，最多可能接收到64个帧长度的数据。也就是说，本发明实施例可以在M帧内检测到帧头。
当帧头的长度为32位时：
在接收到一组64位的比特序列后，将上一组64位的比特序列与当前接收到的64位的比特序列进行拼接得到128位的当前串行数据。将128位当前串行数据中处于滑动窗口内的32位数据与预存的帧头序列的32位数据进行相关运算，进行帧头的检测。在检测到帧头之前，每接收到一帧长度的数据流后滑动窗口在当前串行数据中的位置将滑动移位一个比特位。例如，假定当前滑动窗口初始定位在当前串行数据的第1到32位，将预存帧头序列与滑动窗口内的数据进行相关运算，若相关运算的结果表明未检测到帧头，则在下一个串行数据到来时继续针对下一个串行数据进行相关运算。其中，若下一个串行数据到来时已接收到的数据长度达到一个帧的长度，则将滑动窗口移动一个比特位，即将滑动窗口定位在当前串行数据的第2到33位并进行相关运算，以此类推。若相关运算的结果表明在当前滑动窗口内检测到帧头，则停止窗口的滑动。通过分析可以看出，在检测到帧头前，最多可能接收到64个帧长度的数据。也就是说，本发明实施例可以在M帧内检测到帧头。
需要说明的是，当当前组的比特序列为第一组比特序列时，因为在此之前没有比特序列，所以无法将当前组比特序列与上一组比特序列进行拼接，需要将当前组比特序列进行缓存，与下一组比特序列进行拼接。
在本发明上述实施例中，步骤S100中所述帧数据的长度为M的整数倍，最好大于2M，可以根据实际芯片和应用场景来进行选择，在M越小时，对缓存资源和相关运算的处理资源的要求较小，但检测到帧头所需时间(或接收到的数据长度)越多；反之，M越大，则对缓存资源和相关运算的处理资源的要求较大，但检测到帧头所需时间(或接收到的数据长度)越少。
在本发明上述实施例中，在接收帧数据的数据流时，获取两个偏振态的软数据流，需要对每个偏振态的软数据流进行帧头检测。由于两个偏振态的数据流检测帧头的方法、相关处理都一致，因此本方案中仅对一个偏振态的软数据流进行相关处理及帧头检测的介绍。
接收到的数据流为偏振态的软数据流，在对数据流进行缓存之前，还需要对数据流进行硬判决，得到二进制的比特流，其中，每个数据流分别包括I和Q两路数据。所述对数据流进行硬判决，包括：
对I路和Q路中的数据分别进行判定，当I路和Q路数据中的某位数据大于或等于0时，则判定比特(bit)值为0；当I路和Q路数据中的某位数据小于0时，则判定bit值为1，得到两路比特流。
对经过硬判决后的数据流中的I和Q两路比特流分别进行差分解码，此时得到的数据不存在频偏和相偏模糊。
在本发明上述实施例中，步骤S100中的接收帧数据的数据流包括：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
可选地，可以利用DSP芯片提供M路并行数据处理支路，然后，将在每个支路上接收到的数据进行并串转换，得到串行的数据流，然后可以对上述串行的数据流进行本发明实施例的上述处理过程，以进行帧头定位。
在本发明上述实施例中，步骤S100中，接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存为：对所述帧数据的第一路分支进行接收，并按照M位的长度进行缓存；
在检测到所述帧头后，所述方法还包括：根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，所述第一路分支和第二路分支为同一数据流的两个分支。
如图4所示，经过DSP均衡补偿后的数据流分为两路分支，首先对帧数据的数据流的第一路分支，进行硬判决和差分解码。然后按照M位的长度进行缓存，将接收到的数据按照M位的长度来进行缓存，然后做拼接处理和相关检测，经过滑动偏移位置检测到帧头。在检测到帧头后，对与第一路分支位于相同帧数据的数据流的第二路分支进行定帧。
在本发明上述实施例中，步骤S200中，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，包括：
将所述预存的帧头序列中的数据与处于所述滑动窗口内的对应数据一一进行比较。
其中，将滑动窗口定位在当前串行数据的某一区域，然后将处于滑动窗口内的数据与预先存储的帧头序列中的数据进行比较，由于处于滑动窗口内 的数据与预先存储的帧头序列中的数据的位数相同，将处于滑动窗口内的数据与预先存储的帧头序列中的数据一一进行比较，进行相关运算。
在本发明上述实施例中，步骤S300中，根据所述相关运算的结果检测所述帧头，包括：
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
其中，将处于滑动窗口内的数据与预先存储的帧头序列中的数据一一进行比较时，如果两者中相同的数据位数大于预先设置的门限值时，则表明检测到帧头，如果两者中相同的数据位数小于或等于预先设置的门限值时，则表明仍未检测到帧头，需要继续检测。当再次接收一帧长度的数据时，滑动窗口滑动移位一个比特位，进行相关运算。
在本发明上述实施例中，所述帧数据为100G PM-QPSK光传输系统的帧数据。
本发明实施例的整体流程如图5所示：
步骤S101、接收帧数据的数据流。
步骤S102、对数据流进行硬判决。由于接收到的数据流为偏振态的软数据流，还需要对数据流进行硬判决，得到二进制的比特流。在硬判决时对每个数据流包括的I和Q两路数据进行判决。
步骤S103、对经过硬判决后的数据流进行差分解码。经过差分解码后的数据不存在频偏和相偏模糊。
步骤S104、按照M位的长度对帧数据进行缓存，得到多个M位的比特序列。
步骤S105、将当前比特序列与上一比特序列进行数据拼接，得到当前串行数据。
步骤S106、进行相关运算。在进行相关运算时，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算。在检测到帧头之前，每接收到一帧长度的数据流后滑动窗口滑动移位一个比特位，在检测到帧头后滑动窗口停止滑动。
步骤S107、判断是否检测到帧头，若检测到帧头，则进行下一步骤S108，若未检测到，则需要回到步骤S106进行相关运算。
步骤S108、记录帧头的位置。
步骤S109、数据定帧。
步骤S110、退出帧定位，流程结束。
本发明实施例提供一种帧头检测的装置，如图6所示，所述装置包括：
接收模块10设置为：接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
运算模块20设置为：在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的，所述滑动窗口内的数据长度等于所述帧头的长度；
检测模块30设置为：根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
在本发明上述实施例中，所述接收模块10中的所述帧数据的长度大于2M。
在本发明上述实施例中，所述接收模块10是设置为通过以下方式接收帧数据的数据流：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
在本发明上述实施例中，所述接收模块10是设置为通过以下方式接收帧数据的数据流，并按照M位的长度对接收到的数据流进行缓存：对所述帧数 据的第一路分支进行接收，并按照M位的长度进行缓存；
如图6所示，所述装置还包括：定帧模块40，设置为：在所述检测模块30检测到所述帧头后，根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，其中，所述第一路分支和第二路分支为同一数据流的两个分支。
在本发明上述实施例中，所述检测模块30是设置为：
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
在本发明上述实施例中，所述接收模块10中的所述帧数据为100G PM-QPSK光传输系统的帧数据。
本发明实施例的帧头检测的方法，对帧数据的数据流按照一定长度进行缓存，得到固定长度比特序列，将上一组比特序列与当前比特序列拼接得到当前串行数据，丢弃之前缓存的比特序列，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算。通过对滑动移位后的接收数据与帧头序列进行相关比较，检测帧头，可以实现帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。
需要说明的是，本发明实施例提供的帧头检测的装置是应用上述方法的装置，则上述方法的所有实施例均适用于该装置，且均能达到相同或相似的有益效果。
此外，本发明实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令被执行时实现所述帧头检测的方法。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分 步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，例如通过集成电路来实现其相应功能，也可以采用软件功能模块的形式实现，例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本申请不限制于任何特定形式的硬件和软件的结合。
以上所述的是本申请的可选实施方式，应当指出对于本技术领域的普通人员来说，在不脱离本申请所述的原理前提下还可以作出若干改进和润饰，这些改进和润饰也在本申请的保护范围内。
工业实用性
本发明实施例提供一种帧头检测的方法及装置，通过对滑动移位后的接收数据与帧头序列进行相关比较，检测帧头，可以实现帧定位，避免了缓存大量数据和频繁的滑动搜索，节省了相关处理资源。

Claims (12)

  1. 一种帧头检测的方法，包括：
    接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
    在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的；
    根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
  2. 如权利要求1所述的帧头检测的方法，其中，所述帧数据的长度大于2M。
  3. 如权利要求1所述的帧头检测的方法，其中，所述接收帧数据的数据流包括：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
  4. 如权利要求1所述的帧头检测的方法，其中，
    所述接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存包括：对所述帧数据的第一路分支进行接收，并按照M位的长度进行缓存；
    在检测到所述帧头后，所述方法还包括：根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，所述第一路分支和第二路分支为同一数据流的两个分支。
  5. 如权利要求1所述的帧头检测的方法，其中，所述根据所述相关运算的结果检测所述帧头，包括：
    当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
    当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
  6. 如权利要求1所述的帧定位的方法，其中，所述帧数据为100G偏振复用正交相位调制PM-QPSK光传输系统的帧数据。
  7. 一种帧头检测的装置，包括：
    接收模块，设置为：接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存，得到每组长度为M位的比特序列，其中，在接收第N组比特序列时，丢弃缓存的第N-2组比特序列，所述N大于或等于3，所述M小于所述帧数据的长度且大于或等于帧头的长度；
    运算模块，设置为：在每接收到一组比特序列后，将预存的帧头序列与当前串行数据中处于滑动窗口内的对应数据进行相关运算，其中，所述当前串行数据是由上一组比特序列与当前接收到的比特序列拼接得到的；
    检测模块，设置为：根据所述相关运算的结果检测所述帧头，其中，在检测到所述帧头之前，每接收到一帧长度的数据流后所述滑动窗口滑动移位一个比特位，在检测到所述帧头后所述滑动窗口停止滑动。
  8. 如权利要求7所述的帧头检测的装置，其中，所述接收模块中的所述帧数据的长度大于2M。
  9. 如权利要求7所述的帧头检测的装置，其中，所述接收模块是设置为通过以下方式接收帧数据的数据流：从M个并行处理支路上接收所述帧数据，并将每个支路上接收到的数据进行并串转换，得到所述帧数据的数据流。
  10. 如权利要求7所述的帧头检测的装置，其中，
    所述接收模块是设置为通过以下方式接收帧数据的数据流，并按照M位的长度对接收到的数据进行缓存：对所述帧数据的第一路分支进行接收，并按照M位的长度进行缓存；
    所述装置还包括：定帧模块，设置为：在所述检测模块检测到所述帧头后，根据所述帧头的位置，对所述帧数据的数据流的第二路分支进行定帧处理，其中，所述第一路分支和第二路分支为同一数据流的两个分支。
  11. 如权利要求7所述的帧头检测的装置，其中，所述检测模块是设置为：
    当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数大于一预设门限值A，则判断在当前滑动窗口内检测到了帧头；
    当所述结果表示所述预存的帧头序列中的数据与所述滑动窗口内的对应数据的数据相同个数小于或等于所述预设门限值A，则判断在当前滑动窗口内未检测到帧头。
  12. 如权利要求7所述的帧定位的装置，其中，所述接收模块中的所述帧数据为100G偏振复用正交相位调制PM-QPSK光传输系统的帧数据。
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