WO2016183883A1 - 一种驱动电路 - Google Patents

一种驱动电路 Download PDF

Info

Publication number
WO2016183883A1
WO2016183883A1 PCT/CN2015/080877 CN2015080877W WO2016183883A1 WO 2016183883 A1 WO2016183883 A1 WO 2016183883A1 CN 2015080877 W CN2015080877 W CN 2015080877W WO 2016183883 A1 WO2016183883 A1 WO 2016183883A1
Authority
WO
WIPO (PCT)
Prior art keywords
scan
output
signal
control signal
driving circuit
Prior art date
Application number
PCT/CN2015/080877
Other languages
English (en)
French (fr)
Inventor
曾玉超
黄泰钧
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/761,409 priority Critical patent/US9621164B2/en
Publication of WO2016183883A1 publication Critical patent/WO2016183883A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a driving circuit applied to an AMOLED.
  • the internal compensation circuit of the existing AMOLED Active-matrix organic light emitting diode usually uses a plurality of scanning signals, and the potentials of the plurality of scanning signals may be opposite, and the relative phases of the plurality of scanning signals Or the width is not the same.
  • the scan driving circuit 101 outputs a set of scan signals E1, . . . , En; the scan drive circuit 102 outputs a set of scan signals F1, . . . , Fn; thereby increasing the cost of the scan drive circuit.
  • the embodiment of the invention provides a driving circuit, which can avoid using multiple sets of independent scanning driving circuits and reduce the cost.
  • a first aspect provides a driving circuit including a scan driving circuit and at least one set of combination logic circuits, the output end of the scan driving circuit outputting a first set of scan signals, an input of at least one set of combinational logic circuits and an output of the scan drive circuit
  • the output of the terminal or the previous set of combinational logic circuits is connected, and the output of the at least one set of combinational logic circuits is configured to output at least one set of the second set of scan signals to enable the drive circuit to output the plurality of sets of scan signals; at least one set of combinational logic
  • the circuit includes a first set of combinational logic circuits and a second set of combinational logic circuits, the inputs of the second set of combinational logic circuits being coupled to the outputs of the first set of combinational logic circuits, the first combinational logic circuit and the second set of combinational logic circuits Including at least one logic circuit, the logic circuit includes a first input terminal, a second input terminal, a third input terminal, a selector, an inverter, a first
  • the signal end of the selector is connected to the first control signal
  • the input end of the inverter is connected to the second control signal
  • the other input end of the second NAND gate is connected to the third control signal.
  • the scan signal satisfies the following logical relationship:
  • Bn is a scan signal, n is an integer greater than 0, Cn is a signal output by the selector; phase is a first control signal; C is a third control signal; D is a second control signal; An-1, An, and An +1 is three consecutive scan signals.
  • the logic circuit controls the phase lag or advance of the scan signal by the high and low levels of the first control signal; and adjusts the phase width of the scan signal by the second control signal and the third control signal.
  • the signal end of the selector is connected to the first control signal, and the input end of the inverter and the other input end of the second NAND gate are both connected to the third control signal.
  • the scan signal satisfies the following logical relationship:
  • Bn is the scan signal, n is an integer greater than 0, Cn is the signal output by the selector; phase is the first control signal; C is the third control signal; An-1, An and An+1 are three consecutive scans signal.
  • the logic circuit controls the phase lag or advance of the scan signal by the high and low levels of the first control signal.
  • a second aspect provides a driving circuit including a scan driving circuit and at least one set of combination logic circuits, wherein an output end of the scan driving circuit outputs a first set of scan signals, an input of at least one set of combinational logic circuits and an output of the scan drive circuit The output of the terminal or the previous set of combinational logic circuits is coupled, and the output of the at least one set of combinational logic circuits is configured to output at least one set of the second set of scan signals to enable the drive circuit to output the plurality of sets of scan signals.
  • At least one set of combinational logic circuits comprises a first set of combinational logic circuits, the first combinational logic circuit comprising at least one logic circuit, a first input end, a second input end of the logic circuit, and
  • the third input terminal respectively obtains three consecutive scan signals from the first group of scan signals output by the scan driving circuit, and the logic circuit generates one scan signal according to the three consecutive scan signals.
  • the logic circuit further includes a selector, an inverter, a first NAND gate, a second NAND gate, and an AND gate, wherein the input end of the selector includes a first input end and a third input end of the logic circuit, the selector The output end is connected to one input end of the first NAND gate, the other input end of the first NAND gate is connected to the output end of the inverter, and one input end of the second NAND gate is the second input end, first The output of the NAND gate and the output of the second NAND gate are connected to the input of the AND gate, and the output of the AND gate outputs a scan signal.
  • the signal end of the selector is connected to the first control signal
  • the input end of the inverter is connected to the second control signal
  • the other input end of the second NAND gate is connected to the third control signal.
  • the scan signal satisfies the following logical relationship:
  • Bn is a scan signal, n is an integer greater than 0, Cn is a signal output by the selector; phase is a first control signal; C is a third control signal; D is a second control signal; An-1, An, and An +1 is three consecutive scan signals.
  • the logic circuit controls the phase lag or advance of the scan signal by the high and low levels of the first control signal; and adjusts the phase width of the scan signal by the second control signal and the third control signal.
  • the signal end of the selector is connected to the first control signal, and the input end of the inverter and the other input end of the second NAND gate are both connected to the third control signal.
  • the scan signal satisfies the following logical relationship:
  • Bn is the scan signal, n is an integer greater than 0, Cn is the signal output by the selector; phase is the first control signal; C is the third control signal; An-1, An and An+1 are three consecutive scans signal.
  • the logic circuit controls the phase lag or advance of the scan signal by the high and low levels of the first control signal.
  • the at least one set of combinational logic circuits further includes a second set of combinational logic circuits, the inputs of the second set of combinational logic circuits being coupled to the outputs of the first set of combinational logic circuits.
  • the driving circuit of the present invention comprises: a scan driving circuit and at least one set of combination logic circuit, the output end of the scan driving circuit outputs a first set of scan signals, and the input ends of at least one set of combination logic circuits Connected to an output of the scan driving circuit or an output of the previous set of combinational logic circuits, the output of the at least one combinational logic circuit is configured to output at least one set of the second set of scan signals, so that the drive circuit can output the plurality of sets of scan signals It can avoid adopting multiple sets of independent scan driving circuits to realize output of multiple sets of scan signals and reduce costs.
  • FIG. 1 is a schematic structural view of two sets of independent scan driving circuits in the prior art
  • FIG. 2 is a schematic structural view of a driving circuit according to a first embodiment of the present invention.
  • Figure 3 is a circuit diagram of the logic circuit shown in Figure 2;
  • FIG. 4 is a timing diagram of the logic circuit of FIG. 3 when the first control signal is at a high level
  • FIG. 5 is a timing diagram of the logic circuit of FIG. 3 when the first control signal is low;
  • Figure 6 is a circuit diagram of a logic circuit of a second embodiment of the present invention.
  • FIG. 7 is a timing diagram of the logic circuit of FIG. 6 when the first control signal is at a high level
  • Figure 8 is a timing diagram of the logic circuit of Figure 6 when the first control signal is low.
  • FIG. 2 is a schematic structural view of a driving circuit according to a first embodiment of the present invention.
  • the driving circuit disclosed in this embodiment is applied to an AMOLED to provide a plurality of sets of scan signals to an internal compensation circuit of an AMOLED, and the driving circuit includes: a scan driving circuit 21 And at least one set of combinational logic circuits 22.
  • the output end of the scan driving circuit 21 outputs a first set of scan signals A1, . . . , An, n is an integer greater than zero.
  • the input of at least one set of combinational logic circuit 22 is coupled to the output of scan drive circuit 21 or the output of previous set of combinational logic circuit 22, and the output of at least one set of combinational logic circuit 22 is used to output at least one set of second set Scanning signals B1, . . . , Bn to enable the drive circuit to output a plurality of sets of scan signals, ie, the drive circuit outputs a first set of scan signals A1, . . . , An and at least one set of second sets Scan signals B1, ..., Bn.
  • At least one set of combinational logic circuits 22 includes a first set of combinational logic circuits 22, the first set of combinational logic circuits 22 including at least one logic circuit 221, the logic circuit 221 comprising a first input terminal 1, a second input terminal 2, and a third input terminal 3. Output terminal 4, selector 222, inverter 223, first NAND gate 224, second NAND gate 225, and AND gate 226, as shown in FIG.
  • the first input terminal 1, the second input terminal 2, and the third input terminal 3 of the logic circuit 221 respectively obtain three consecutive scan signals An-1, An, and An+1 from the first group of scan signals output from the scan driving circuit 21. That is, the first input terminal 1, the second input terminal 2, and the third input terminal 3 are respectively connected to three consecutive output terminals of the scan driving circuit 21.
  • the logic circuit 221 generates a scan signal Bn based on three consecutive scan signals An-1, An, and An+1.
  • the input end of the selector 222 includes a first input end 1 and a third input end 3 of the logic circuit 211.
  • the signal end of the selector 222 is connected to the first control signal phase, and the output end of the selector 222 and the first NAND gate 224.
  • One input terminal is connected, the other input terminal of the first NAND gate 224 is connected to the output terminal of the inverter 223, the input terminal of the inverter 223 is connected to the second control signal D; and one of the second NAND gates 225
  • the input terminal is the second input terminal 2 of the logic circuit 211, and the other input terminal of the second NAND gate 225 is connected to the third control signal C, the output of the first NAND gate 224 and the output of the second NAND gate 225.
  • the terminal is connected to the input of the AND gate 226, and the output of the AND gate 226 outputs the scan signal Bn.
  • the scan signal Bn satisfies the following logical relationship:
  • Cn is the signal output by the selector 222.
  • the logic circuit 221 controls the phase lag or advance of the scan signal Bn by the high and low levels of the first control signal phase; and adjusts the scan signal by the second control signal D and the third control signal C The phase width of Bn.
  • FIG. 4 is a timing diagram of the logic circuit of FIG. 3 when the first control signal is at a high level.
  • FIG. 5 is a timing diagram of the logic circuit of FIG. 3 when the first control signal is low.
  • At least one set of combinational logic circuits 22 further includes a second set of combinational logic circuits 22, the inputs of which are coupled to the outputs of the first set of combinational logic circuits 22, ie, the second set of combinational logic circuits 22 The input is coupled to the output of the previous set of combinational logic circuits 22.
  • the second group combination logic circuit 22 is identical to the first group combination logic circuit 22, and details are not described herein again.
  • At least one set of combinational logic circuits 22 may be integrated on the chip of the scan drive circuit 21, or at least one set of combinational logic circuits 22 may be integrated on the liquid crystal display control panel.
  • At least one set of combinational logic circuits 22 are provided in the drive circuit, and the input ends of the at least one set of combinational logic circuits 22 are connected to the output of the scan drive circuit 21 or the output of the previous set of combinational logic circuits 22, at least one set.
  • the output end of the combinational logic circuit 22 is configured to output at least one set of the second set of scan signals, so that the drive circuit can output multiple sets of scan signals, thereby avoiding using multiple sets of independent scan drive circuits to realize output of multiple sets of scan signals and reducing
  • the scan driving circuit 21 cooperates with the plurality of sets of combinational logic circuits 22 to more easily implement a GOA (Gate Driver on Array) circuit.
  • GOA Gate Driver on Array
  • FIG. 6 is a schematic structural diagram of a logic circuit according to a second embodiment of the present invention.
  • the logic circuit 621 disclosed in this embodiment is different from the logic circuit 221 disclosed in the first embodiment in that the signal end of the selector 622 is connected to the first control signal phase.
  • the input of the inverter 623 and the other input of the second NAND gate 625 are both connected to the third control signal C.
  • the scan signal Bn satisfies the following logical relationship:
  • Cn is the signal output by the selector 622.
  • the logic circuit 621 controls the phase lag or advance of the scan signal Bn by the high and low levels of the first control signal phase; and adjusts the phase width of the scan signal Bn by the third control signal C.
  • FIG. 7 is a timing diagram of the logic circuit of FIG. 6 when the first control signal is at a high level.
  • the scan signal Bn The potential is opposite to the potential of the signal An, the phase of the scanning signal Bn is delayed with respect to the phase of the signal An, and the phase width of the scanning signal Bn is equal to the phase width of the signal An, and is not adjustable.
  • FIG. 8 is a timing diagram of the logic circuit of FIG. 6 when the first control signal is low.
  • the scan signal Bn The potential is opposite to the potential of the signal An, the phase of the scanning signal Bn is advanced with respect to the phase of the signal An, the phase width of the scanning signal Bn is equal to the phase width of the signal An, and is not adjustable.
  • the driving circuit of the present invention comprises a scan driving circuit and at least one set of combination logic circuits, and an output end of the scan driving circuit outputs a first group of scan signals, an input of at least one set of combination logic circuits and an output of the scan drive circuit.
  • the output of the terminal or the previous set of combinational logic circuits is connected, and the output of the at least one combination of the logic circuits is configured to output at least one set of the second set of scan signals, so that the drive circuit can output the plurality of sets of scan signals, thereby avoiding adopting multiple groups
  • the independent scan drive circuit realizes the output of multiple sets of scan signals and reduces the cost.
  • the scan driver circuit cooperates with multiple sets of combinational logic circuits to make it easier to implement the GOA circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

提供了一种驱动电路，该驱动电路包括扫描驱动电路（21）以及至少一组组合逻辑电路（22），扫描驱动电路（21）的输出端输出第一组扫描信号（A1-An），至少一组组合逻辑电路（22）的输入端与扫描驱动电路的输出端或者前一组组合逻辑电路（22）的输出端连接，至少一组组合逻辑电路（22）的输出端用于输出至少一组第二组扫描信号（B1-Bn），以使驱动电路能够输出多组扫描信号。通过以上方式，能够避免采用多组独立的扫描驱动电路，实现多组扫描信号的输出，降低成本。

Description

一种驱动电路 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种应用于AMOLED的驱动电路。
背景技术
现有的AMOLED(Active-matrix organic light emitting diode，主动矩阵有机发光二极体)的内部补偿电路通常会使用多个扫描信号，而多个扫描信号的电位可能相反，多个扫描信号的相对相位或宽度不相同。
为了获取多个扫描信号，现有技术通过使用两组独立的扫描驱动电路，如图1所示。扫描驱动电路101输出一组扫描信号E1，......，En；扫描驱动电路102输出一组扫描信号F1，......，Fn；进而增加了扫描驱动电路的成本。
发明内容
本发明实施例提供了一种驱动电路，能够避免采用多组独立的扫描驱动电路，降低成本。
第一方面提供一种驱动电路，其包括扫描驱动电路以及至少一组组合逻辑电路，扫描驱动电路的输出端输出第一组扫描信号，至少一组组合逻辑电路的输入端与扫描驱动电路的输出端或者前一组组合逻辑电路的输出端连接，至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使驱动电路能够输出多组扫描信号；至少一组组合逻辑电路包括第一组组合逻辑电路和第二组组合逻辑电路，第二组组合逻辑电路的输入端与第一组组合逻辑电路的输出端连接，第一组合逻辑电路和第二组组合逻辑电路均包括至少一个逻辑电路，逻辑电路包括第一输入端、第二输入端、第三输入端、选择器、反相器、第一与非门、第二与非门以及与门，第一输入端、第二输入端以及第三输入端分别从扫描驱动电路输出的第一组扫描信号中获取连续三个扫描信号，逻辑电路根据连续三个扫描信号产生一个扫描信号；选择器的输入端包括逻辑电路的第一输入端和第三输入端，选择器的输出端与第一与非门的一个输入端连接，第一与非门的另一个输 入端与反相器的输出端连接，第二与非门的一个输入端为第二输入端，第一与非门的输出端和第二与非门的输出端与与门的输入端连接，与门的输出端输出扫描信号。
其中，选择器的信号端与第一控制信号连接，反相器的输入端与第二控制信号连接，第二与非门的另一个输入端与第三控制信号连接。
其中，扫描信号满足以下逻辑关系：
Figure PCTCN2015080877-appb-000001
Figure PCTCN2015080877-appb-000002
其中，Bn为扫描信号，n为大于0的整数，Cn为选择器输出的信号；phase为第一控制信号；C为第三控制信号；D为第二控制信号；An-1、An以及An+1为连续三个扫描信号。
其中，逻辑电路通过第一控制信号的高低电平控制扫描信号的相位滞后或提前；并通过第二控制信号和第三控制信号调整扫描信号的相位宽度。
其中，选择器的信号端与第一控制信号连接，反相器的输入端和第二与非门的另一个输入端均与第三控制信号连接。
其中，扫描信号满足以下逻辑关系：
Figure PCTCN2015080877-appb-000003
Figure PCTCN2015080877-appb-000004
其中，Bn为扫描信号，n为大于0的整数，Cn为选择器输出的信号；phase为第一控制信号；C为第三控制信号；An-1、An以及An+1为连续三个扫描信号。
其中，逻辑电路通过第一控制信号的高低电平控制扫描信号的相位滞后或提前。
第二方面提供一种驱动电路，其包括扫描驱动电路以及至少一组组合逻辑电路，扫描驱动电路的输出端输出第一组扫描信号，至少一组组合逻辑电路的输入端与扫描驱动电路的输出端或者前一组组合逻辑电路的输出端连接，至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使驱动电路能够输出多组扫描信号。
其中，至少一组组合逻辑电路包括第一组组合逻辑电路，第一组合逻辑电路包括至少一个逻辑电路，逻辑电路的第一输入端、第二输入端以及 第三输入端分别从扫描驱动电路输出的第一组扫描信号中获取连续三个扫描信号，逻辑电路根据连续三个扫描信号产生一个扫描信号。
其中，逻辑电路还包括选择器、反相器、第一与非门、第二与非门以及与门，选择器的输入端包括逻辑电路的第一输入端和第三输入端，选择器的输出端与第一与非门的一个输入端连接，第一与非门的另一个输入端与反相器的输出端连接，第二与非门的一个输入端为第二输入端，第一与非门的输出端和第二与非门的输出端与与门的输入端连接，与门的输出端输出扫描信号。
其中，选择器的信号端与第一控制信号连接，反相器的输入端与第二控制信号连接，第二与非门的另一个输入端与第三控制信号连接。
其中，扫描信号满足以下逻辑关系：
Figure PCTCN2015080877-appb-000005
Figure PCTCN2015080877-appb-000006
其中，Bn为扫描信号，n为大于0的整数，Cn为选择器输出的信号；phase为第一控制信号；C为第三控制信号；D为第二控制信号；An-1、An以及An+1为连续三个扫描信号。
其中，逻辑电路通过第一控制信号的高低电平控制扫描信号的相位滞后或提前；并通过第二控制信号和第三控制信号调整扫描信号的相位宽度。
其中，选择器的信号端与第一控制信号连接，反相器的输入端和第二与非门的另一个输入端均与第三控制信号连接。
其中，扫描信号满足以下逻辑关系：
Figure PCTCN2015080877-appb-000007
Figure PCTCN2015080877-appb-000008
其中，Bn为扫描信号，n为大于0的整数，Cn为选择器输出的信号；phase为第一控制信号；C为第三控制信号；An-1、An以及An+1为连续三个扫描信号。
其中，逻辑电路通过第一控制信号的高低电平控制扫描信号的相位滞后或提前。
其中，至少一组组合逻辑电路还包括第二组组合逻辑电路，第二组组合逻辑电路的输入端与第一组组合逻辑电路的输出端连接。
通过上述方案，本发明的有益效果是：本发明的驱动电路包括扫描驱动电路以及至少一组组合逻辑电路，扫描驱动电路的输出端输出第一组扫描信号，至少一组组合逻辑电路的输入端与扫描驱动电路的输出端或者前一组组合逻辑电路的输出端连接，至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使驱动电路能够输出多组扫描信号，能够避免采用多组独立的扫描驱动电路，实现多组扫描信号的输出，降低成本。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术中两组独立的扫描驱动电路的结构示意图；
图2是本发明第一实施例的驱动电路的结构示意图；
图3是图2中所示的逻辑电路的电路图；
图4是图3中逻辑电路在第一控制信号为高电平时的时序图；
图5是图3中逻辑电路在第一控制信号为低电平时的时序图；
图6是本发明第二实施例的逻辑电路的电路图；
图7是图6中逻辑电路在第一控制信号为高电平时的时序图；
图8是图6中逻辑电路在第一控制信号为低电平时的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图2所示，图2是本发明第一实施例的驱动电路的结构示意图。如图2所示，本实施例所揭示的驱动电路应用于AMOLED，以向AMOLED的内部补偿电路提供多组扫描信号，该驱动电路包括：扫描驱动电路21以 及至少一组组合逻辑电路22。其中，扫描驱动电路21的输出端输出第一组扫描信号A1，......，An，n为大于0的整数。
至少一组组合逻辑电路22的输入端与扫描驱动电路21的输出端或者前一组组合逻辑电路22的输出端连接，至少一组组合逻辑电路22的输出端用于输出至少一组第二组扫描信号B1，......，Bn，以使驱动电路能够输出多组扫描信号，即驱动电路输出第一组扫描信号A1，......，An和至少一组第二组扫描信号B1，......，Bn。
至少一组组合逻辑电路22包括第一组组合逻辑电路22，第一组组合逻辑电路22包括至少一个逻辑电路221，逻辑电路221包括第一输入端1、第二输入端2、第三输入端3、输出端4、选择器222、反相器223、第一与非门224、第二与非门225以及与门226，如图3所示。逻辑电路221的第一输入端1、第二输入端2以及第三输入端3分别从扫描驱动电路21输出的第一组扫描信号中获取连续三个扫描信号An-1、An以及An+1，即第一输入端1、第二输入端2以及第三输入端3分别与扫描驱动电路21的连续三个输出端连接。逻辑电路221根据连续三个扫描信号An-1、An以及An+1产生一个扫描信号Bn。
选择器222的输入端包括逻辑电路211的第一输入端1和第三输入端3，选择器222的信号端与第一控制信号phase连接，选择器222的输出端与第一与非门224的一个输入端连接，第一与非门224的另一个输入端与反相器223的输出端连接，反相器223的输入端与第二控制信号D连接；第二与非门225的一个输入端为逻辑电路211的第二输入端2，第二与非门225的另一个输入端与第三控制信号C连接，第一与非门224的输出端和第二与非门225的输出端与与门226的输入端连接，与门226的输出端输出扫描信号Bn。
其中，扫描信号Bn满足以下逻辑关系：
Figure PCTCN2015080877-appb-000009
Figure PCTCN2015080877-appb-000010
其中，Cn为选择器222输出的信号。
逻辑电路221通过第一控制信号phase的高低电平控制扫描信号Bn的相位滞后或提前；并通过第二控制信号D和第三控制信号C调整扫描信号 Bn的相位宽度。
请参见图4，图4是图3中逻辑电路在第一控制信号为高电平时的时序图。如图4所示，在第一控制信号phase＝1，即高电平时，选择器222输出的信号Cn＝An-1，第二控制信号D和第三控制信号C的时序图如图4所示，因此扫描信号Bn的电位与信号An的电位相反，扫描信号Bn的相位相对于信号An的相位滞后，并且第二控制信号D和第三控制信号C调整扫描信号Bn的相位宽度。
请参见图5，图5是图3中逻辑电路在第一控制信号为低电平时的时序图。如图5所示，在第一控制信号phase＝0，即低电平时，选择器222输出的信号Cn＝An+1，第二控制信号D和第三控制信号C的时序图如图5所示，因此扫描信号Bn的电位与信号An的电位相反，扫描信号Bn的相位相对于信号An的相位提前，并且第二控制信号D和第三控制信号C调整扫描信号Bn的相位宽度。
此外，至少一组组合逻辑电路22还包括第二组组合逻辑电路22，第二组组合逻辑电路22的输入端与第一组组合逻辑电路22的输出端连接，即第二组组合逻辑电路22的输入端与前一组组合逻辑电路22的输出端连接。第二组组合逻辑电路22与第一组组合逻辑电路22完全相同，在此不再赘述。
值得注意的是，至少一组组合逻辑电路22可以集成在扫描驱动电路21的芯片上，或者至少一组组合逻辑电路22可以集成在液晶显示控制面板上。
本实施例通过在驱动电路设置至少一组组合逻辑电路22，至少一组组合逻辑电路22的输入端与扫描驱动电路21的输出端或者前一组组合逻辑电路22的输出端连接，至少一组组合逻辑电路22的输出端用于输出至少一组第二组扫描信号，以使驱动电路能够输出多组扫描信号，能够避免采用多组独立的扫描驱动电路，实现多组扫描信号的输出，降低成本；此外，扫描驱动电路21配合多组组合逻辑电路22，更容易实现GOA(Gate Driver on Array)电路。
请参见图6所示，图6是本发明第二实施例的逻辑电路的结构示意图。如图6所示，本实施例所揭示的逻辑电路621与第一实施例所揭示的逻辑电路221的不同之处在于：选择器622的信号端与第一控制信号phase连接， 反相器623的输入端和第二与非门625的另一个输入端均与第三控制信号C连接。
其中，扫描信号Bn满足以下逻辑关系：
Figure PCTCN2015080877-appb-000011
Figure PCTCN2015080877-appb-000012
其中，Cn为选择器622输出的信号。
逻辑电路621通过第一控制信号phase的高低电平控制扫描信号Bn的相位滞后或提前；并通过第三控制信号C调整扫描信号Bn的相位宽度。
请参见图7，图7是图6中逻辑电路在第一控制信号为高电平时的时序图。如图6所示，在第一控制信号phase＝1，即高电平时，选择器622输出的信号Cn＝An-1，第三控制信号C的时序图如图7所示，因此扫描信号Bn的电位与信号An的电位相反，扫描信号Bn的相位相对于信号An的相位滞后，扫描信号Bn的相位宽度与信号An的相位宽度相等，并且不可调。
请参见图8，图8是图6中逻辑电路在第一控制信号为低电平时的时序图。如图8所示，在第一控制信号phase＝0，即低电平时，选择器622输出的信号Cn＝An+1，第三控制信号C的时序图如图8所示，因此扫描信号Bn的电位与信号An的电位相反，扫描信号Bn的相位相对于信号An的相位提前，扫描信号Bn的相位宽度与信号An的相位宽度相等，并且不可调。
综上所述，本发明的驱动电路包括扫描驱动电路以及至少一组组合逻辑电路，扫描驱动电路的输出端输出第一组扫描信号，至少一组组合逻辑电路的输入端与扫描驱动电路的输出端或者前一组组合逻辑电路的输出端连接，至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使驱动电路能够输出多组扫描信号，能够避免采用多组独立的扫描驱动电路，实现多组扫描信号的输出，降低成本。此外，扫描驱动电路配合多组组合逻辑电路，更容易实现GOA电路。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种驱动电路，其特征在于，其包括扫描驱动电路以及至少一组组合逻辑电路，所述扫描驱动电路的输出端输出第一组扫描信号，所述至少一组组合逻辑电路的输入端与所述扫描驱动电路的输出端或者前一组所述组合逻辑电路的输出端连接，所述至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使所述驱动电路能够输出多组扫描信号；
    所述至少一组组合逻辑电路包括第一组组合逻辑电路和第二组组合逻辑电路，所述第二组组合逻辑电路的输入端与所述第一组组合逻辑电路的输出端连接，所述第一组合逻辑电路和所述第二组组合逻辑电路均包括至少一个逻辑电路，所述逻辑电路包括第一输入端、第二输入端、第三输入端、选择器、反相器、第一与非门、第二与非门以及与门，所述第一输入端、第二输入端以及第三输入端分别从所述扫描驱动电路输出的第一组扫描信号中获取连续三个扫描信号，所述逻辑电路根据所述连续三个扫描信号产生一个扫描信号；所述选择器的输入端包括所述逻辑电路的第一输入端和第三输入端，所述选择器的输出端与所述第一与非门的一个输入端连接，所述第一与非门的另一个输入端与所述反相器的输出端连接，所述第二与非门的一个输入端为所述第二输入端，所述第一与非门的输出端和第二与非门的输出端与所述与门的输入端连接，所述与门的输出端输出所述扫描信号。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述选择器的信号端与第一控制信号连接，所述反相器的输入端与第二控制信号连接，所述第二与非门的另一个输入端与第三控制信号连接。
  3. 根据权利要求5所述的驱动电路，其特征在于，所述扫描信号满足以下逻辑关系：
    Figure PCTCN2015080877-appb-100001
    Figure PCTCN2015080877-appb-100002
    其中，Bn为所述扫描信号，n为大于0的整数，Cn为所述选择器输出的信号；phase为所述第一控制信号；C为所述第三控制信号；D为所述第二控制信号；An-1、An以及An+1为所述连续三个扫描信号。
  4. 根据权利要求3所述的驱动电路，其特征在于，所述逻辑电路通过所述第一控制信号的高低电平控制所述扫描信号的相位滞后或提前；并通过所述第二控制信号和所述第三控制信号调整所述扫描信号的相位宽度。
  5. 根据权利要求1所述的驱动电路，其特征在于，所述选择器的信号端与第一控制信号连接，所述反相器的输入端和所述第二与非门的另一个输入端均与第三控制信号连接。
  6. 根据权利要求5所述的驱动电路，其特征在于，所述扫描信号满足以下逻辑关系：
    Figure PCTCN2015080877-appb-100003
    Figure PCTCN2015080877-appb-100004
    其中，Bn为所述扫描信号，n为大于0的整数，Cn为所述选择器输出的信号；phase为所述第一控制信号；C为所述第三控制信号；An-1、An以及An+1为所述连续三个扫描信号。
  7. 根据权利要求6所述的驱动电路，其特征在于，所述逻辑电路通过所述第一控制信号的高低电平控制所述扫描信号的相位滞后或提前。
  8. 一种驱动电路，其特征在于，其包括扫描驱动电路以及至少一组组合逻辑电路，所述扫描驱动电路的输出端输出第一组扫描信号，所述至少一组组合逻辑电路的输入端与所述扫描驱动电路的输出端或者前一组所述组合逻辑电路的输出端连接，所述至少一组组合逻辑电路的输出端用于输出至少一组第二组扫描信号，以使所述驱动电路能够输出多组扫描信号。
  9. 根据权利要求8所述的驱动电路，其特征在于，所述至少一组组合逻辑电路包括第一组组合逻辑电路，所述第一组合逻辑电路包括至少一个逻辑电路，所述逻辑电路的第一输入端、第二输入端以及第三输入端分别从所述扫描驱动电路输出的第一组扫描信号中获取连续三个扫描信号，所述逻辑电路根据所述连续三个扫描信号产生一个扫描信号。
  10. 根据权利要求9所述的驱动电路，其特征在于，所述逻辑电路还包括选择器、反相器、第一与非门、第二与非门以及与门，所述选择器的输入端包括所述逻辑电路的第一输入端和第三输入端，所述选择器的输出端与所述第一与非门的一个输入端连接，所述第一与非门的另一个输入端与所述反相器的输出端连接，所述第二与非门的一个输入端为所述第二输 入端，所述第一与非门的输出端和第二与非门的输出端与所述与门的输入端连接，所述与门的输出端输出所述扫描信号。
  11. 根据权利要求10所述的驱动电路，其特征在于，所述选择器的信号端与第一控制信号连接，所述反相器的输入端与第二控制信号连接，所述第二与非门的另一个输入端与第三控制信号连接。
  12. 根据权利要求11所述的驱动电路，其特征在于，所述扫描信号满足以下逻辑关系：
    Figure PCTCN2015080877-appb-100005
    Figure PCTCN2015080877-appb-100006
    其中，Bn为所述扫描信号，n为大于0的整数，Cn为所述选择器输出的信号；phase为所述第一控制信号；C为所述第三控制信号；D为所述第二控制信号；An-1、An以及An+1为所述连续三个扫描信号。
  13. 根据权利要求12所述的驱动电路，其特征在于，所述逻辑电路通过所述第一控制信号的高低电平控制所述扫描信号的相位滞后或提前；并通过所述第二控制信号和所述第三控制信号调整所述扫描信号的相位宽度。
  14. 根据权利要求10所述的驱动电路，其特征在于，所述选择器的信号端与第一控制信号连接，所述反相器的输入端和所述第二与非门的另一个输入端均与第三控制信号连接。
  15. 根据权利要求14所述的驱动电路，其特征在于，所述扫描信号满足以下逻辑关系：
    Figure PCTCN2015080877-appb-100007
    Figure PCTCN2015080877-appb-100008
    其中，Bn为所述扫描信号，n为大于0的整数，Cn为所述选择器输出的信号；phase为所述第一控制信号；C为所述第三控制信号；An-1、An以及An+1为所述连续三个扫描信号。
  16. 根据权利要求15所述的驱动电路，其特征在于，所述逻辑电路通过所述第一控制信号的高低电平控制所述扫描信号的相位滞后或提前。
  17. 根据权利要求9所述的驱动电路，其特征在于，所述至少一组组合逻辑电路还包括第二组组合逻辑电路，所述第二组组合逻辑电路的输入 端与所述第一组组合逻辑电路的输出端连接。
PCT/CN2015/080877 2015-05-20 2015-06-05 一种驱动电路 WO2016183883A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/761,409 US9621164B2 (en) 2015-05-20 2015-06-05 Driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510261214.9 2015-05-20
CN201510261214.9A CN104851391B (zh) 2015-05-20 2015-05-20 一种驱动电路

Publications (1)

Publication Number Publication Date
WO2016183883A1 true WO2016183883A1 (zh) 2016-11-24

Family

ID=53851000

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/080877 WO2016183883A1 (zh) 2015-05-20 2015-06-05 一种驱动电路

Country Status (3)

Country Link
US (1) US9621164B2 (zh)
CN (1) CN104851391B (zh)
WO (1) WO2016183883A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105206225B (zh) * 2015-10-12 2017-09-01 深圳市华星光电技术有限公司 Oled栅极驱动电路架构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794331A (zh) * 2004-12-24 2006-06-28 三星Sdi株式会社 扫描驱动器和有机发光显示器及其驱动方法
CN101592831A (zh) * 2008-05-28 2009-12-02 群康科技(深圳)有限公司 液晶显示器及其驱动方法
CN101630475A (zh) * 2008-07-14 2010-01-20 索尼株式会社 扫描驱动电路和包括该扫描驱动电路的显示设备
CN101950519A (zh) * 2009-07-08 2011-01-19 瑞萨电子株式会社 显示面板驱动器、显示设备、以及显示面板驱动方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19540146B4 (de) * 1994-10-27 2012-06-21 Nec Corp. Flüssigkristallanzeige vom aktiven Matrixtyp mit Treibern für Multimedia-Anwendungen und Ansteuerverfahren dafür
US6437766B1 (en) * 1998-03-30 2002-08-20 Sharp Kabushiki Kaisha LCD driving circuitry with reduced number of control signals
JP3882678B2 (ja) * 2002-05-21 2007-02-21 ソニー株式会社 表示装置
JP4207986B2 (ja) * 2006-06-28 2009-01-14 双葉電子工業株式会社 蛍光表示装置とその駆動方法
US7675498B2 (en) * 2006-07-20 2010-03-09 Tpo Displays Corp. Dot-inversion display devices and driving method thereof with low power consumption
CN101577102B (zh) * 2008-05-08 2011-09-28 联咏科技股份有限公司 扫描驱动器
CN101923833B (zh) * 2009-06-09 2012-08-22 华映视讯（吴江）有限公司 具有输出致能控制电路的栅极驱动器
CN101937655B (zh) * 2009-07-01 2012-10-10 瑞鼎科技股份有限公司 分频器电路及其方法与应用其的栅极驱动器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1794331A (zh) * 2004-12-24 2006-06-28 三星Sdi株式会社 扫描驱动器和有机发光显示器及其驱动方法
CN101592831A (zh) * 2008-05-28 2009-12-02 群康科技(深圳)有限公司 液晶显示器及其驱动方法
CN101630475A (zh) * 2008-07-14 2010-01-20 索尼株式会社 扫描驱动电路和包括该扫描驱动电路的显示设备
CN101950519A (zh) * 2009-07-08 2011-01-19 瑞萨电子株式会社 显示面板驱动器、显示设备、以及显示面板驱动方法

Also Published As

Publication number Publication date
CN104851391A (zh) 2015-08-19
CN104851391B (zh) 2017-10-17
US20160344388A1 (en) 2016-11-24
US9621164B2 (en) 2017-04-11

Similar Documents

Publication Publication Date Title
US9824621B2 (en) Gate drive circuit and display device
US10403222B2 (en) Gate driver on array circuit having clock-controlled inverter and LCD panel
US10204583B2 (en) Gate driver on array driving circuit and LCD device
US9830877B2 (en) Shift register, gate driving circuit, display panel and display apparatus
US10446087B2 (en) GOA driving unit
US10311795B2 (en) Shift register unit, gate driver circuit and display device
US9576677B2 (en) Scan driving circuit
US9805658B2 (en) Shift register, gate driving circuit and display device
US9799296B2 (en) CMOS GOA circuit
US20180033389A1 (en) Goa circuit for ltps-tft
US10152164B2 (en) Touch driving circuit, touch driving method and touch screen
US9922589B2 (en) Emission electrode scanning circuit, array substrate and display apparatus
US9524665B2 (en) Display panel and gate driver
US9881542B2 (en) Gate driver on array (GOA) circuit cell, driver circuit and display panel
US10446094B2 (en) Gate driver on array circuit and LCD panel having GOA protecting circuit
US20170075488A1 (en) Driving unit, driving method, driving circuit, and display panel
US20180218699A1 (en) Driving circuit and display panel
US9224347B2 (en) TFT-LCD driving circuit
US20180277051A1 (en) Driving circuit
US10748501B2 (en) Gate driver, display panel and display using same
US10163414B2 (en) GOA driving circuit
US10255843B2 (en) Scan driving circuit and flat display device thereof
US20190228697A1 (en) Goa circuit and driving method for foldable display panel, and foldable display panel
KR20230019251A (ko) 디스플레이 패널 제어 회로 및 디스플레이 장치
US20170047128A1 (en) Shift register circuit

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14761409

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15892262

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15892262

Country of ref document: EP

Kind code of ref document: A1