WO2016180310A1 - Mems基片的加工方法 - Google Patents

Mems基片的加工方法 Download PDF

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Publication number
WO2016180310A1
WO2016180310A1 PCT/CN2016/081515 CN2016081515W WO2016180310A1 WO 2016180310 A1 WO2016180310 A1 WO 2016180310A1 CN 2016081515 W CN2016081515 W CN 2016081515W WO 2016180310 A1 WO2016180310 A1 WO 2016180310A1
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substrate
mask layer
forming
front side
mems
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French (fr)
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荆二荣
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a method for processing a MEMS substrate.
  • MEMS Micro Electro Mechanical Systems
  • Microelectromechanical systems are micro-integrated systems that use integrated circuit fabrication techniques and micromachining techniques to fabricate microstructures, microsensors, microactuators, control processing circuits, and even interfaces, communications, and power supplies on one or more chips.
  • MEMS Manufacturing technology depends not only on the IC process, but also on the micromachining technology.
  • Micromachining technology includes silicon micromachining technology, surface micromachining technology and special micromachining technology.
  • the bulk micromachining technique refers to a process of etching a silicon substrate along the thickness direction of a silicon substrate, including wet etching and dry etching, and is an important method for realizing a three-dimensional structure.
  • the etching is performed only in a partial region of the silicon wafer, and the non-etched region must be deposited with a mask layer (barrier layer), and the mask layer is first selectively etched to make the etched region
  • the silicon is exposed and then the silicon substrate is etched by wet etching or dry etching.
  • the etching depth can reach several hundred microns, and even the silicon wafer can be etched through.
  • the mask layer is selectively etched, the edge sidewall of the silicon wafer is also etched away because the photoresist cannot be coated, and the mask layer on the sidewall of the edge of the silicon wafer is also etched away.
  • the edge sidewalls of the silicon wafer are also corroded at the same time, resulting in many small corners at the edge of the silicon wafer, and with a small missing corner compared with the smooth silicon wafer.
  • the silicon wafer is easily fragmented, resulting in a decrease in the yield of the product.
  • a method of processing a MEMS substrate comprising the steps of:
  • Providing a substrate comprising a front side, a side surface and a back side;
  • the front side of the exposed portion of the substrate is etched.
  • a second mask layer and a third mask layer are respectively formed on the side and the back surface of the substrate, and the second mask layer is performed on the edge side surface of the substrate. Effective protection can effectively avoid the corrosion of the substrate while etching the edge of the edge of the substrate, resulting in the occurrence of corners on the edge of the substrate. In the subsequent process, the substrate is not easily broken, which improves the yield of the product.
  • 1 is a flow chart of a method of processing a MEMS substrate
  • Figure 2 is a schematic view of a substrate
  • Figure 3 is a schematic view showing the formation of a first mask layer on the front side of the substrate
  • Figure 5 is a schematic view showing the formation of a second mask layer and a third mask layer
  • Figure 6 is a schematic illustration of the exposed portion of the substrate after front side etching.
  • MEMS Micro Electro Mechanical Systems, Microelectromechanical systems
  • MEMS Micro Electro Mechanical Systems, Microelectromechanical systems
  • integrated circuit fabrication techniques and micromachining techniques to fabricate microstructures, microsensors, microactuators, control processing circuits, and even interfaces, communications, and power supplies.
  • Integrated system. along with Development of MEMS technology, using MEMS Technically produced pressure sensors have been widely used in many fields such as the automotive industry, biomedical, industrial control, energy, and semiconductor industries. The following is a method of processing a MEMS substrate.
  • 1 is a flow chart of a method of processing a MEMS substrate.
  • a method of processing a MEMS substrate comprising the steps of:
  • Step S100 Providing a substrate 100 comprising a front side 110, a side surface 120 and a back side 130.
  • the substrate 100 can be a semiconductor material, such as silicon.
  • Figure 2 is a schematic illustration of a substrate.
  • Step S200 forming a first mask layer 210 on the front surface 110 of the substrate 100. It can be deposited by thermal oxidation, such as atmospheric pressure thermal oxidation, low pressure thermal oxidation and high pressure thermal oxidation, etc.; physical deposition such as vacuum evaporation, sputter coating and molecular beam epitaxy can also be used; chemical vapor deposition can also be used. (CVD, Chemical Vapor Deposition), such as atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, and ion enhanced chemical vapor deposition (PECVD, Plasma Enhanced) Chemical Vapor Deposition).
  • thermal oxidation such as atmospheric pressure thermal oxidation, low pressure thermal oxidation and high pressure thermal oxidation, etc.
  • physical deposition such as vacuum evaporation, sputter coating and molecular beam epitaxy can also be used
  • chemical vapor deposition can also be used.
  • CVD Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • FIG. 3 is a schematic illustration of the formation of a first mask layer on the front side of the substrate.
  • the first mask layer 210 on the front side 110 is deposited, the first mask layer 210 can be selectively etched to be patterned.
  • Step S300 patterning the first mask layer 210 and exposing a portion of the front side 112 of the substrate 100.
  • the first mask layer 210 on the front surface 110 of the substrate 100 is coated with a photoresist
  • the first mask layer 210 is selectively etched to form a pattern by exposure and development.
  • the edge sidewall (side surface 120) of the substrate 100 is coated with a photoresist, so that the film on the edge sidewall (side 120) of the substrate 100 is also Etched off.
  • the first mask layer 210 has a thickness of 0.5 micrometers to 2 micrometers, and the material may comprise a semiconductor compound, such as an oxide or nitride of silicon, which may be silicon dioxide.
  • 4 is a schematic view of the first mask layer after being patterned.
  • a side film 120 of the substrate 100 needs to be deposited to protect the edge sidewalls (side 120) of the substrate 100.
  • Step S400 forming a second mask layer 220 on the side surface 120 of the substrate 100, and forming a third mask layer 230 on the back surface 130 of the substrate 100. Due to the characteristics of PECVD deposition, the second mask layer 220 and the third mask layer 230 may be simultaneously formed by PECVD deposition.
  • the back side 130 of the substrate 100 is deposited against the deposition source, and the front side 110 of the substrate 100 is substantially non-deposited with a film attached thereto, while the back side 130 and the side 120 are A film is deposited and a second mask layer 220 and a third mask layer 230 are formed, respectively.
  • the material of the second mask layer 220 and the third mask layer 230 may be the same as that of the first mask layer 210.
  • the material may include a semiconductor compound, such as an oxide or nitride of silicon, which may be silicon dioxide.
  • FIG. 5 is a schematic view after forming a second mask layer and a third mask layer.
  • the subsequent substrate 100 pattern etching can be performed.
  • Step S500 etching a portion of the front surface 112 exposed to the substrate 100 (the front surface of the substrate 100 exposed after the first mask layer 210 is patterned) to obtain a corrosion pattern 140.
  • the portion 112 exposed to the substrate 100 may be wet etched using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), or the partially exposed front portion 112 of the substrate 100 may be subjected to deep reactive ion etching. (DRIE).
  • the material of the first mask layer 210 is related to the etching process of the substrate 100. If the first mask layer 210 is made of silicon dioxide, the substrate 100 is usually etched by the above etching process.
  • Figure 6 is a schematic illustration of the exposed portion of the substrate after front side etching.
  • MEMS substrate processing method describes only some of the main steps and does not represent all the steps of MEMS substrate processing or fabrication.
  • the illustrations in Figures 2-6 are also simple examples of some of the major structures of the device during MEMS substrate processing or fabrication and do not represent the overall structure of the device.
  • a second mask layer and a third mask layer are respectively formed on the side and the back surface of the substrate, and the second mask layer is performed on the edge side surface of the substrate. Effective protection can effectively avoid the corrosion of the substrate while etching the edge of the edge of the substrate, resulting in the occurrence of corners on the edge of the substrate. In the subsequent process, the substrate is not easily broken, which improves the yield of the product.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)

Abstract

一种MEMS基片的加工方法，包括：提供基片(100)，其基片包括正面（110）、侧面（120）和背面（130）；在基片（100）的正面（110）形成第一掩膜层（210）；对第一掩膜层（210）进行图形化并暴露基片（100）的部分正面（110）；在基片（100）的侧面（120）形成第二掩膜层（220），在基片（100）的背面（130）形成第三掩膜层（230）；及对基片（100）暴露的部分正面（110）进行腐蚀。

Description

MEMS基片的加工方法
【技术领域】
本发明涉及半导体器件技术领域，特别涉及一种MEMS基片的加工方法。
【背景技术】
MEMS（Micro Electro Mechanical Systems, 微电子机械系统）是利用集成电路制造技术和微加工技术把微结构、微传感器、微执行器、控制处理电路甚至接口、通信和电源等制造在一块或多块芯片上的微型集成系统。 MEMS 制造技术不仅依赖于IC工艺，更依赖于微加工技术。微加工技术包括硅的体微加工技术、表面微加工技术和特殊微加工技术。体微加工技术是指沿着硅衬底的厚度方向对硅衬底进行刻蚀的工艺，包括湿法腐蚀和干法刻蚀，是实现三维结构的重要方法。为了获得需要的结构，刻蚀只在硅片的局部区域进行，非刻蚀区域必须淀积掩膜层（阻挡层）保护，并首先对掩膜层进行选择性刻蚀，使被刻蚀区域的硅暴露出来，然后采用湿法腐蚀或者干法刻蚀对硅衬底进行腐蚀。与一般的IC工艺不同，腐蚀深度可以达到几百微米，甚至把硅片腐蚀穿通。在对掩膜层进行选择性刻蚀时，硅片的边缘侧壁因为无法涂覆光刻胶，导致硅片边缘侧壁的掩膜层也被刻蚀掉。这样在对硅衬底进行体微加工时，硅片的边缘侧壁也会同时被腐蚀，导致硅片的边缘出现许多小缺角，与边缘光滑的硅片相比较，带有小缺角的硅片在随后的工艺中，很容易碎片，导致产品的成品率下降。
【发明内容】
基于此，有必要提供一种可以有效提高产品的成品率的MEMS基片的加工方法。
一种MEMS基片的加工方法，包括步骤：
提供基片，所述基片包括正面、侧面和背面；
在所述基片的正面形成第一掩膜层；
对所述第一掩膜层进行图形化并暴露所述基片的部分正面；
在所述基片的侧面形成第二掩膜层，在所述基片的背面形成第三掩膜层；及
对所述基片暴露的部分正面进行腐蚀。
上述MEMS基片的加工方法，对基片进行腐蚀前，通过在基片的侧面和背面分别形成第二掩膜层和第三掩膜层，由于第二掩膜层对基片的边缘侧面进行有效保护，可以有效避免在对基片进行腐蚀的同时将基片的边缘侧面腐蚀从而导致基片边缘出现缺角，在随后的工艺中基片不容易碎片，提高产品的成品率。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是MEMS基片的加工方法的流程图；
图2是基片的示意图；
图3是在基片正面形成第一掩膜层的示意图；
图4是第一掩膜层图形化后的示意图；
图5是形成第二掩膜层和第三掩膜层后的示意图；
图6是基片暴露的部分正面刻蚀后的示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
MEMS（Micro Electro Mechanical Systems, 微电子机械系统）是利用集成电路制造技术和微加工技术把微结构、微传感器、微执行器、控制处理电路甚至接口、通信和电源等制造在一块或多块芯片（基片）上的微型集成系统。随着 MEMS 技术的发展，利用MEMS 技术制作的压力传感器已广泛用于汽车工业、生物医学、工业控制、能源、以及半导体工业等众多领域。下面一种MEMS基片的加工方法。
下面结合附图，对本发明的具体实施方式进行详细描述。
图1是MEMS基片的加工方法的流程图。
一种MEMS基片的加工方法，包括步骤：
步骤S100:提供基片100，基片100包括正面110、侧面120和背面130。基片100可以为半导体材料，例如可以为硅材质。图2是基片的示意图。
步骤S200:在基片100的正面110形成第一掩膜层210。可以采用热氧化方法淀积，例如常压热氧化、低压热氧化和高压热氧化等；也可以采用物理淀积，例如真空蒸发、溅射镀膜和分子束外延等；也可以采用化学气相淀积（CVD，Chemical Vapor Deposition），例如常压化学气相淀积、低压化学气相淀积和离子体增强化学气相沉积工艺（PECVD ，Plasma Enhanced Chemical Vapor Deposition）。采用PECVD淀积基片100的正面110时，侧面120也会淀积附上一层薄膜，而背面130则基本不会附上。如采用PECVD淀积形成第一掩膜层210，则由于PECVD淀积的特性使得基片100的侧面120也会附上一层薄膜。图3是在基片正面形成第一掩膜层的示意图。
淀积好正面110上的第一掩膜层210后，可以对第一掩膜层210进行选择性刻蚀以图形化。
步骤S300:对第一掩膜层210进行图形化并暴露基片100的部分正面112。在基片100的正面110上的第一掩膜层210涂上光刻胶后，通过曝光和显影，对第一掩膜层210进行选择性刻蚀形成图形。在对第一掩膜层210进行选择性刻蚀时，基片100的边缘侧壁（侧面120）因为无法涂覆光刻胶，导致基片100边缘侧壁（侧面120）的该薄膜也被刻蚀掉。第一掩膜层210的厚度为0.5微米~2微米，材质可以包含半导体化合物，例如可以是硅的氧化物或氮化物，可以是二氧化硅。图4是第一掩膜层图形化后的示意图。
正面110上的第一掩膜层210图形化后，需要对基片100的侧面120进行淀积薄膜工作以保护基片100的边缘侧壁（侧面120）。
步骤S400:在基片100的侧面120形成第二掩膜层220，在基片100的背面130形成第三掩膜层230。由于PECVD淀积的特性，可以采用PECVD淀积同时形成第二掩膜层220和第三掩膜层230。将基片100的背面130对着淀积源淀积，基片100的正面110基本上不会淀积附上薄膜，而背面130和侧面120 则会淀积附上薄膜并分别形成第二掩膜层220和第三掩膜层230。第二掩膜层220和第三掩膜层230的材质可以和第一掩膜层210一样，材质可以包含半导体化合物，例如可以是硅的氧化物或氮化物，可以是二氧化硅。图5是形成第二掩膜层和第三掩膜层后的示意图。
基片100的边缘侧壁（侧面120）附上第二掩膜层220得到有效保护后，可以进行后续的基片100图形刻蚀。
步骤S500:对基片100暴露的部分正面112（第一掩膜层210图形化后暴露的基片100部分正面）进行腐蚀，得到腐蚀图形140。可以通过对基片100暴露的部分112正面利用氢氧化钾（KOH）或四甲基氢氧化铵（TMAH）进行湿法腐蚀，也可以对基片100暴露的部分正面112进行深反应离子刻蚀（DRIE）。第一掩膜层210的材料关系到基片100刻蚀工艺，如果第一掩膜层210为二氧化硅材质，通常采用上述刻蚀工艺对基片100进行刻蚀。图6是基片暴露的部分正面刻蚀后的示意图。
可以理解，上述MEMS基片的加工方法，仅描述一些主要步骤，并不代表MEMS基片加工或制造的所有步骤。图2~图6中的图示也是对MEMS基片加工或制造过程中器件的一些主要结构的简单示例，并不代表器件的全部结构。
上述MEMS基片的加工方法，对基片进行腐蚀前，通过在基片的侧面和背面分别形成第二掩膜层和第三掩膜层，由于第二掩膜层对基片的边缘侧面进行有效保护，可以有效避免在对基片进行腐蚀的同时将基片的边缘侧面腐蚀从而导致基片边缘出现缺角，在随后的工艺中基片不容易碎片，提高产品的成品率。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (8)

  1. 一种MEMS基片的加工方法，包括：
    提供基片，所述基片包括正面、侧面和背面；
    在所述基片的正面形成第一掩膜层；
    对所述第一掩膜层进行图形化并暴露所述基片的部分正面；
    在所述基片的侧面形成第二掩膜层，在所述基片的背面形成第三掩膜层；及
    对所述基片暴露的部分正面进行腐蚀。
  2. 根据权利要求1 所述的方法，其特征在于，通过等离子体增强化学气相沉积工艺在所述基片的正面形成第一掩膜层。
  3. 根据权利要求1 所述的方法，其特征在于，通过等离子体增强化学气相沉积工艺在所述基片的侧面形成第二掩膜层并在所述基片的背面形成第三掩膜层。
  4. 根据权利要求1 所述的方法，其特征在于，形成所述第一掩膜层、第二掩膜层和第三掩膜层的材料包括二氧化硅。
  5. 根据权利要求1所述的方法，其特征在于，所述第一掩膜层的厚度为0.5微米~2微米。
  6. 根据权利要求1所述的方法，其特征在于，对所述基片暴露的部分正面利用氢氧化钾或四甲基氢氧化铵进行湿法腐蚀。
  7. 根据权利要求1所述的方法，其特征在于，对所述基片暴露的部分正面进行深反应离子刻蚀。
  8. 根据权利要求1所述的方法，其特征在于，所述基片的材料为半导体材料。
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