WO2016180093A1 - Flash芯片读写控制电路和方法、AMOLED应用电路 - Google Patents

Flash芯片读写控制电路和方法、AMOLED应用电路 Download PDF

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Publication number
WO2016180093A1
WO2016180093A1 PCT/CN2016/077223 CN2016077223W WO2016180093A1 WO 2016180093 A1 WO2016180093 A1 WO 2016180093A1 CN 2016077223 W CN2016077223 W CN 2016077223W WO 2016180093 A1 WO2016180093 A1 WO 2016180093A1
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partition
flash chip
read
data
control circuit
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PCT/CN2016/077223
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English (en)
French (fr)
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解红军
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京东方科技集团股份有限公司
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Priority to US15/319,885 priority Critical patent/US10262741B2/en
Publication of WO2016180093A1 publication Critical patent/WO2016180093A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits

Definitions

  • the present disclosure relates to AMOLED module circuit technology, and in particular to a read/write control circuit and method for a Flash chip.
  • the present disclosure further relates to an AMOLED application circuit.
  • the current AMOLED module will be equipped with electrical compensation technology.
  • the electrical compensation technology not only needs to write data to the Flash at the factory, but also needs to read and write the Flash during the use of the product.
  • abnormal events such as a sudden power failure (for example, due to a power outage or a drop of the plug) may occur.
  • the Flash is in the write state, the exception event will cause the Flash write to fail, causing the data in the corresponding partition (Block) to be lost.
  • the Flash needs to erase the corresponding partition before writing each time, for example, after the abnormal event of power failure occurs, the original stored compensation data is erased, and the new compensation data to be written has not yet been written. Go in. In this way, the display of some display areas will be abnormal after power-on.
  • a Flash chip read and write control circuit and method are obtained that are capable of avoiding data loss due to abnormal events such as power down. Also, it is desirable to provide an AMOLED application circuit having such a Flash chip read and write control circuit.
  • a read/write control circuit for a flash chip comprising: a timing control circuit that generates a read/write timing signal for the Flash chip; and a first nonvolatile memory And a plurality of flag bits corresponding to the plurality of partitions in the flash chip, each of the flag bits indicating whether a partition corresponding thereto is normally written; wherein the timing control circuit is Configuring to perform the following operations when writing data to one of the Flash chips: generating the partition to be written Copying data into a non-volatile backup storage area; controlling the first non-volatile memory to set a flag bit corresponding to the partition to be written to a first value indicating an abnormal write Generating a timing signal to erase the partition; generating a timing signal to write data to be written to the partition; and setting the flag bit corresponding to the partition to indicate normal writing after writing is completed a second value; and wherein the timing control circuit is further configured to, when the Flash chip is powered back on, when reading data from
  • a read/write control method for a flash chip comprising: when writing data to a partition in the flash chip: generating data in the partition to be written Copying a timing signal to a non-volatile backup storage area; setting a flag bit corresponding to the partition to be written to a first value indicating an abnormal write; generating a timing signal for erasing the partition; generating Writing a data to be written to the timing signal of the partition; and setting the flag bit corresponding to the partition to a second value indicating normal writing after the writing is completed; and, at the flash chip After re-energizing, when reading data from a partition in the Flash chip: determining whether to read from the partition of the Flash chip or from the non-volatile backup storage area according to the indication of the flag bit data.
  • an AMOLED application circuit comprising a Flash chip and a read/write control circuit according to any of the preceding aspects, wherein the Flash chip is used to store electrical compensation data of the AMOLED, and The read/write control circuit is configured to control writing of the electrical compensation data to the Flash chip and reading the electrical compensation data from the Flash chip.
  • the idea of the present disclosure is to achieve retention of original data before an abnormal event such as a power failure occurs by setting a flag signal and a backup storage space corresponding to respective partitions in the Flash chip. Thereby, the continuity of data processing before and after the abnormal event and the integrity of the data in the flash chip can be guaranteed.
  • FIG. 1 schematically illustrates a read and write control circuit for a flash chip according to an embodiment of the present disclosure
  • FIG. 2 schematically illustrates a Flash chip read and write process in the case of abnormal writes according to an embodiment of the present disclosure
  • FIG. 3 schematically illustrates a Flash chip read and write process in the case where abnormal writes have not occurred, according to an embodiment of the present disclosure
  • FIG. 4 is a flow chart of a method of writing a Flash chip in accordance with an embodiment of the present disclosure.
  • FIG. 1 schematically illustrates a read and write control circuit 100 for a flash chip in accordance with an embodiment of the present disclosure.
  • the read and write control circuit 100 includes a timing control circuit 110 and a first nonvolatile memory 120.
  • a first non-volatile memory 120 is illustrated as an electrically erasable programmable read only memory (EEPROM).
  • EEPROM electrically erasable programmable read only memory
  • the timing control circuit 110 generates read and write timing signals for the Flash chip. These read/write timing signals transmit control, address and data signals to the Flash chip through the I/O interface of the Flash chip, thereby programming (writing), erasing, reading, etc. the Flash. It should be noted that although the interfaces of various products or vendors may vary, whether it is NOR Flash or NAND Flash, the read and write timing signals for the Flash chip are known in the art and therefore will not be described in detail herein.
  • the first non-volatile memory 120 is configured to store a plurality of flag bits (Flags) corresponding to a plurality of partitions in the Flash chip, each of the flag bits indicating whether a partition corresponding thereto is normally written.
  • the first non-volatile memory 120 can be an EEPROM characterized by being able to randomly access and modify any one byte and can write 0 or 1 to each bit.
  • the EEPROM may be advantageous since the modification of the flag bits is for bit operations, although other non-volatile memories are also possible.
  • the timing control circuit 110 When data is written to one partition in the flash chip, the timing control circuit 110 performs the following operations:
  • a timing signal is generated that copies the data in the partition to be written to a non-volatile backup storage area (not shown in Figure 1). Based on the timing signal, the circuit will execute a group The process of combining, first reading data from the corresponding partition of the Flash chip, and then writing the read data to the non-volatile backup storage area.
  • the first nonvolatile memory 120 is controlled to set a flag bit corresponding to the partition to be written to a first value indicating an abnormal write.
  • the flag can usually be set to 1 or 0.
  • the first value can be zero.
  • the flag bit corresponding to the partition is set to a second value indicating normal writing after the writing is completed.
  • the second value can be one.
  • the timing control circuit 110 determines whether to partition from the Flash chip or not based on the indication of the flag bit in the first non-volatile memory 120. Volatile backup storage area reads. Specifically, if the flag bit in the first non-volatile memory 120 is a second value (which indicates normal writing), the timing control circuit 110 generates a timing signal such that data is read from the partition.
  • the timing control circuit 110 If the flag bit in the first non-volatile memory 120 is the first value (which indicates an abnormal write), the timing control circuit 110 generates a timing signal such that the data is read from the non-volatile backup storage area, the data is The data in the partition corresponding to the flag bit that was backed up before the power failure.
  • the timing control circuit 110 can be part of a processor such as a central processing unit (CPU), a digital signal processor (DSP), a microcontroller, or can be a separate circuit component separate from the processor. .
  • the functions of the timing control circuit 110 can be implemented by these processors' read and write operation commands (and possibly storage control circuits) for the memory space (ie, Flash chip, EEPROM, etc.).
  • the timing control circuit 110 can be implemented, for example, as an application specific integrated circuit (ASIC) or a programmable logic circuit (eg, a field programmable gate array FPGA).
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • FIG. 2 schematically illustrates a Flash chip read and write process in the event of an abnormal write occurring in accordance with an embodiment of the present disclosure.
  • the Flash chip has 1024 partitions, which are represented as partition 1, partition 2, ... partition 1023, respectively.
  • Each partition has a corresponding bit flag, which is represented as flag 0, flag 1, ... flag 1023.
  • the flag bit indicates whether the partition has been written normally, 1 indicates normal write, and 0 indicates abnormal write.
  • the solid arrow in Fig. 2 indicates the reading position of the data when the power is turned off after the abnormal event occurs. If no power loss occurs, all partition flags are 1.
  • the timing control circuit 110 first reads the flag bits in the first non-volatile memory 120. Since the flag bits are all 1, the timing control circuit 110 does not read data from the non-volatile backup memory area, but reads data directly from the partition in the flash chip. If a partition (partition 3 in the figure) generates an abnormal event such as a power-down at the time of writing, the flag corresponding to the partition (flag 3 in the figure) is set to 0, and the other flags are 1 .
  • the timing control circuit 110 first reads the flag bit information in the first non-volatile memory 120. If the flag corresponding to the partition is 1, the timing control circuit 110 reads data from the partition; if the flag corresponding to the partition is 0, the timing control circuit 110 reads data from the non-volatile backup storage area, the data That is, the data in the partition that was backed up before the exception occurred. It should also be understood that in the initial default state, the flag bits corresponding to all partitions are set to 1, indicating normal writes.
  • FIG. 3 schematically illustrates a Flash chip read and write process in the event that an abnormal write does not occur, according to an embodiment of the present disclosure.
  • the flag bits of all partitions are 1, so that the timing control circuit 110 does not read data from the non-volatile backup storage area, but directly from the Flash chip.
  • the partition reads the data as indicated by the solid arrows in the figure.
  • the non-volatile backup storage area shown in Figures 2 and 3 may be one partition in the Flash chip. This arrangement makes the data operations in the backup process complete in the Flash chip, which helps to reduce system complexity and processing time. However, as a partition of the Flash chip, the non-volatile backup storage area also faces the risk of data loss due to an abnormal event during the writing process. Alternatively, the non-volatile backup storage area can be mapped into an off-chip non-volatile storage device (eg, EEPROM or other readable and writable non-volatile memory) that is separate from the Flash chip.
  • an off-chip non-volatile storage device eg, EEPROM or other readable and writable non-volatile memory
  • the storage space of the off-chip non-volatile storage device may have a size equal to one partition of the flash chip, which is beneficial to reduce cost, and of course, the storage space of the non-volatile storage device may also be larger than that of the flash chip.
  • the size of a partition may be mapped as previously described The first non-volatile memory 110. This also helps to reduce costs by reducing the number of storage devices used.
  • FIG. 4 is a flow chart of a method of writing a Flash chip in accordance with an embodiment of the present disclosure.
  • a timing signal is generated that copies data in the partition to be written to the non-volatile backup storage area. Based on the timing signal, the circuit will perform a combined process of first reading data from the corresponding partition of the Flash chip and then writing the read data to the non-volatile backup memory area.
  • the flag bit corresponding to the partition to be written is set to a first value indicating an abnormal write.
  • the first value can be zero.
  • a timing signal is generated that erases the partition. Based on the timing signal, the corresponding partition in the Flash chip will be erased.
  • a timing signal is generated that writes data to be written to the partition. Based on the timing signal, data is written to a corresponding partition in the flash chip.
  • the flag bit corresponding to the partition is set to a second value indicating normal writing after the writing is completed.
  • the second value can be one.
  • steps 410-450 are all performed if an abnormal event such as a power down does not occur; if the exception occurs after the partition is erased, steps 440 and 450 will not be performed.
  • the flag bit corresponding to the partition is a second value (which indicates normal writing)
  • a timing signal read from the partition is generated such that data is read from the partition of the flash chip.
  • the flag bit corresponding to the partition is the first value (which indicates abnormal write)
  • generating a timing signal read from the non-volatile backup storage area so that data is read from the non-volatile backup storage area.
  • the data is the data in the partition corresponding to the flag bit that was backed up before the exception event occurred.
  • an AMOLED application circuit using an electrical compensation mechanism includes a Flash chip and a read/write control circuit as described above, wherein the Flash chip can be used to store electrical compensation data, and The read/write control circuit can be used to control writing electrical compensation data to the Flash chip and reading electrical compensation data from the Flash chip.
  • the updated compensation data is stored in the partition that has been written when the abnormal event occurs, and the unupdated compensation data is stored in the partition that has not been written, and the non-volatile backup is performed.
  • the data backed up in the storage area for the partition being written when an abnormal event occurs is also the unupdated compensation data. Since the corresponding flag bit is set for the partition in the Flash chip, when re-energizing, it can be from each partition according to the indication of these flag bits (for the partition that is abnormally written, it is from the non-volatile backup storage area) ) Read the data without waiting for the partition to be written to the exception to be rewritten. This facilitates the continuity of data processing (eg, display). Since the compensation data usually does not have a sudden change, and the compensation data in all the partitions will be updated in a short time (for example, usually several seconds) after being re-energized, there is no significant difference in display.

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Abstract

一种用于Flash芯片的读写控制电路(100)、用于Flash芯片的读写控制方法及具有所述读写控制电路(100)的用于电学补偿机制的AMOLED应用电路；其中，所述读写控制电路(100)包括：时序控制电路(110)，其生成用于Flash芯片的读写时序信号；以及第一非易失性存储器(120)，其用于存储与Flash芯片中的多个分区对应的多个标志位，所述标志位中的每一个指示与其对应的一个分区是否被正常写入。

Description

Flash芯片读写控制电路和方法、AMOLED应用电路 技术领域
本公开涉及AMOLED模组电路技术，特别地涉及一种用于Flash芯片的读写控制电路和方法。本公开进一步涉及一种AMOLED应用电路。
背景技术
在常规的平板显示电路设计中，需要写入Flash芯片的机会很少。一般都是在产品出厂时将数据写入Flash芯片中，使用时只需要读取芯片内的数据，而不需要做写入动作。
现在的AMOLED模组将搭载电学补偿技术。电学补偿技术不仅需要在出厂时向Flash写入数据，而且在产品使用过程中也需要对Flash进行读取和写入动作。然而，在用户的使用过程中，可能发生突然掉电(例如由于停电或插头掉落等原因)等异常事件。此时，若Flash正处于写入状态，则该异常事件将使Flash写入失败，造成对应的分区(Block)内的数据丢失。因为Flash每次写入前需要先将对应的分区进行擦除才能写入，例如掉电的异常事件发生后，原来存储的补偿数据被擦除，将要写入的新的补偿数据还没来得及写进去。这样，重新通电后某些显示区域的显示将是异常的。
因此，需要一种改进的Flash芯片的读写控制电路和方法。
发明内容
有利的是，获得一种能够避免由于例如掉电的异常事件所引起的数据丢失的Flash芯片读写控制电路和方法。同样，合期望的是，提供一种具有这样的Flash芯片读写控制电路的AMOLED应用电路。
根据本公开的第一方面，提供了一种用于Flash芯片的读写控制电路，包括：时序控制电路，其生成用于所述Flash芯片的读写时序信号；以及第一非易失性存储器，其用于存储与所述Flash芯片中的多个分区对应的多个标志位，所述标志位中的每一个指示与其对应的一个分区是否被正常写入；其中，所述时序控制电路被配置成当对所述Flash芯片中的一个分区写入数据时执行以下操作：生成将要写入的所述分区 中的数据复制到一个非易失性备份存储区的时序信号；控制所述第一非易失性存储器将与要写入的所述分区对应的标志位设置为指示异常写入的第一值；生成将所述分区擦除的时序信号；生成将要写入的数据写入到所述分区的时序信号；以及在写入完成后将与所述分区对应的所述标志位设置为指示正常写入的第二值；并且其中，所述时序控制电路被进一步配置成在所述Flash芯片重新通电后，当从所述Flash芯片中的一个分区读取数据时，根据所述第一非易失性存储器中的所述标志位的指示，确定从所述Flash芯片的所述分区还是从所述非易失性备份存储区读取。
根据本公开的第二方面，提供了一种用于Flash芯片的读写控制方法，包括：当对所述Flash芯片中的一个分区写入数据时：生成将要写入的所述分区中的数据复制到一个非易失性备份存储区的时序信号；将与要写入的所述分区对应的标志位设置为指示异常写入的第一值；生成将所述分区擦除的时序信号；生成将要写入的数据写入到所述分区的时序信号；以及在写入完成后将与所述分区对应的所述标志位设置为指示正常写入的第二值；并且，在所述Flash芯片重新通电后，当从所述Flash芯片中的一个分区读取数据时：根据所述标志位的指示，确定从所述Flash芯片的所述分区还是从所述非易失性备份存储区读取数据。
根据本公开的第三方面，提供了一种AMOLED应用电路，包括Flash芯片和如前面任一方面所述的读写控制电路，其中，所述Flash芯片用于存储AMOLED的电学补偿数据，并且所述读写控制电路用于控制向所述Flash芯片写入所述电学补偿数据和从所述Flash芯片读取所述电学补偿数据。
本公开的构思在于通过设置与Flash芯片中的各个分区对应的标志信号和备份存储空间，来实现对于例如掉电的异常事件发生之前的原始数据的保留。由此，可以保证该异常事件前后数据处理的连续性和Flash芯片中的数据的完整性。
根据在下文中所描述的实施例，本公开的这些和其它方面将是显而易见的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1示意性地图示了根据本公开实施例的用于Flash芯片的读写控制电路；
图2示意性地图示了根据本公开实施例的在异常写入的情况下的Flash芯片读写过程；
图3示意性地图示了根据本公开实施例的在未发生异常写入的情况下的Flash芯片读写过程；以及
图4是根据本公开实施例的对Flash芯片进行写入的方法的流程图。
具体实施方式
以下结合附图对本公开的各实施例进行详细描述。
图1示意性地图示了根据本公开实施例的用于Flash芯片的读写控制电路100。读写控制电路100包括时序控制电路110和第一非易失性存储器120。在图1中，第一非易失性存储器120被图示为电可擦除可编程只读存储器(EEPROM)。
时序控制电路110生成用于Flash芯片的读写时序信号。这些读写时序信号通过Flash芯片的I/O接口向Flash芯片传送控制、地址和数据信号，从而对Flash进行编程(烧写)、擦除、读取等操作。需要指出，虽然各个产品或厂商的接口可能各不相同，但是无论是NOR Flash还是NAND Flash，用于Flash芯片的读写时序信号是本领域中已知的，并且因此在本文中不作详细描述。
第一非易失性存储器120用于存储与Flash芯片中的多个分区对应的多个标志位(Flag)，标志位中的每一个指示与其对应的一个分区是否被正常写入。如所图示的，第一非易失性存储器120可以为EEPROM，其特点是可以随机访问和修改任何一个字节，并且可以往每个bit中写入0或者1。在本实施例的应用中，由于标志位的修改是针对bit的操作，所以EEPROM可以是有利的，尽管其他的非易失性存储器也是可能的。
当对Flash芯片中的一个分区写入数据时，时序控制电路110执行以下操作：
生成将要写入的分区中的数据复制到一个非易失性备份存储区(图1中未示出)的时序信号。基于该时序信号，电路将执行一个组 合的过程，即先从Flash芯片的对应分区中读取数据，然后将所读取的数据写入非易失性备份存储区。
控制第一非易失性存储器120将与要写入的分区对应的标志位设置为指示异常写入的第一值。标志位通常可以被置为1或0。作为示例，第一值可以为0。
生成将分区擦除的时序信号。基于该时序信号，Flash芯片中的对应分区将被擦除。
生成将要写入的数据写入到分区的时序信号。基于该时序信号，向Flash芯片中的对应分区写入数据。
在写入完成后将与分区对应的标志位设置为指示正常写入的第二值。作为示例，第二值可以为1。
相应地，在重新通电后，当从Flash芯片中的一个分区读取数据时，时序控制电路110根据第一非易失性存储器120中的标志位的指示，确定从Flash芯片的分区还是从非易失性备份存储区读取。具体地，如果第一非易失性存储器120中的标志位为第二值(其指示正常写入)，则时序控制电路110生成时序信号，使得从分区读取数据。如果第一非易失性存储器120中的标志位为第一值(其指示异常写入)，则时序控制电路110生成时序信号，使得从非易失性备份存储区读取数据，该数据即掉电前备份的与该标志位对应的分区中的数据。
应当理解，时序控制电路110可以作为诸如中央处理单元(CPU)、数字信号处理器(DSP)、微控制器之类的处理器的一部分，或者可以作为一个与处理器相分离的单独的电路元件。在前者的情况下，时序控制电路110的功能可以通过这些处理器对于存储空间(即，Flash芯片、EEPROM等)的读写操作命令(和可能地存储控制电路)来实现。在后者的情况下，时序控制电路110可以例如被实现为专用集成电路(ASIC)或可编程逻辑电路(例如，现场可编程门阵列FPGA)。
图2示意性地图示了根据本公开实施例的在发生异常写入的情况下的Flash芯片读写过程。假定Flash芯片具有1024个分区，分别表示为分区1、分区2、......分区1023。每个分区具有对应的一个bit的标志位，分别表示为标志位0、标志位1、......标志位1023。如前所述，标志位表示该分区是否已经正常写入，1表示正常写入，0表示异常写入。针对任一分区写入时，先将该分区的原始数据复制到非易失性备 份存储区，然后将该分区对应的标志位置为0，然后将该分区进行擦除，将新的数据写入到该分区，写入完毕后将该分区对应的标志位置为1。此时，对该分区的写入完成，可以进入下一分区的写入阶段。所有分区都以这样的步骤进行写入操作。
图2中的实线箭头表示异常事件发生后重新通电时数据的读取位置。若不发生掉电，则所有的分区标志位都是1。下次通电时，时序控制电路110首先读取第一非易失性存储器120中的标志位。由于标志位都是1，所以时序控制电路110不从非易失性备份存储区读取数据，而是直接从Flash芯片中的分区读取数据。若某分区(在图中为分区3)在写入时发生例如掉电的异常事件，则该分区对应的标志位(在图中为标志位3)被置为0，其他标志位都是1。下次通电时，时序控制电路110首先读取第一非易失性存储器120中的标志位信息。如果分区对应的标志位是1，则时序控制电路110将从分区读取数据；如果分区对应的标志位为0，则时序控制电路110将从非易失性备份存储区读取数据，该数据即异常事件发生之前备份的分区中的数据。还应当理解，在最初的缺省状态下，与所有分区对应的标志位被置为1，即指示正常写入。
图3示意性地图示了根据本公开实施例的在未发生异常写入的情况下的Flash芯片读写过程。如图所示，由于未发生例如掉电的异常事件，所以所有分区的标志位都是1，使得时序控制电路110不从非易失性备份存储区读取数据，而是直接从Flash芯片中的分区读取数据，如图中的实线箭头所示。
可选地，图2和3中所示的非易失性备份存储区可以是Flash芯片中的一个分区。这种布置使得备份过程中的数据操作都在Flash芯片内完成，有利于降低系统复杂度和处理时间。然而，作为Flash芯片的一个分区，非易失性备份存储区同样面临在写入过程中由于异常事件而导致数据丢失的风险。替换地，非易失性备份存储区可以被映射到与Flash芯片相分离的一个片外非易失性存储设备(例如，EEPROM或其他可读写的非易失性存储器)中。可选地，该片外非易失性存储设备的存储空间可以具有等于Flash芯片的一个分区的大小，这有利于降低成本，当然该非易失性存储设备的存储空间也可以大于Flash芯片的一个分区的大小。替换地，非易失性备份存储区可以被映射到如前所述 的第一非易失性存储器110。由于减少了使用的存储设备的数量，这同样有利于降低成本。
图4是根据本公开实施例的对Flash芯片进行写入的方法的流程图。当对Flash芯片中的一个分区写入数据时，可以执行以下操作：
在步骤410处，生成将要写入的分区中的数据复制到非易失性备份存储区的时序信号。基于该时序信号，电路将执行一个组合的过程，即先从Flash芯片的对应分区中读取数据，然后将所读取的数据写入非易失性备份存储区。
在步骤420处，将与要写入的分区对应的标志位设置为指示异常写入的第一值。如前所述，作为示例，第一值可以为0。
在步骤430处，生成将分区擦除的时序信号。基于该时序信号，Flash芯片中的对应分区将被擦除。
在步骤440处，生成将要写入的数据写入到分区的时序信号。基于该时序信号，向Flash芯片中的对应分区写入数据。
在步骤450处，在写入完成后将与分区对应的标志位设置为指示正常写入的第二值。如前所述，作为示例，第二值可以为1。
需要指出，如果不发生例如掉电的异常事件，则步骤410-450全部被执行；如果分区被擦除后发生该异常事件，则步骤440和450将不会被执行。
对该分区的写入完成后，可以进入下一分区的写入阶段。所有分区都以这样的步骤进行写入操作。
相应地，在重新通电后，当从Flash芯片中的一个分区读取数据时，根据标志位的指示，确定从Flash芯片的分区还是从非易失性备份存储区读取数据。具体地，如果与该分区对应的标志位为第二值(其指示正常写入)，则生成从分区读取的时序信号，使得从Flash芯片的该分区读取数据。如果与该分区对应的标志位为第一值(其指示异常写入)，则生成从非易失性备份存储区读取的时序信号，使得从非易失性备份存储区读取数据，该数据即异常事件发生之前备份的与该标志位对应的分区中的数据。
根据本公开的另一实施例，还提供了一种使用电学补偿机制的AMOLED应用电路。该AMOLED应用电路包括Flash芯片和如前所述的读写控制电路，其中，Flash芯片可以用于存储电学补偿数据，并且 读写控制电路可以用于控制向Flash芯片写入电学补偿数据和从Flash芯片读取电学补偿数据。
由前面的分析可知，发生异常事件时已经完成写入的分区中存储的是已更新的补偿数据，而尚未被写入的分区中存储的是未更新的补偿数据，并且在非易失性备份存储区中为发生异常事件时正被写入的分区所备份的数据也是未更新的补偿数据。由于为Flash芯片中的分区设置了对应的标志位，在重新通电时，可以根据这些标志位的指示从每个分区中(对于异常写入的分区，则是从非易失性备份存储区中)读取数据，而不必等待对该异常写入的分区重新进行写入。这有利于保证数据处理(例如，显示)的连续性。由于补偿数据通常不存在突变，并且重新通电后在短时间(例如，通常几秒钟)内所有分区中的补偿数据将会得以更新，所以不会造成显示上的明显差异。
虽然前面的讨论包含若干特定的实现细节，但是这些不应解释为对任何发明或者可能要求保护的范围的限制，而应解释为对可能仅限于特定发明的特定实施例的特征的描述。在本说明书中不同的实施例中描述的特定特征也可以在单个实施例中以组合形式实现。与此相反，在单个实施例中描述的不同特征也可以在多个实施例中分别地或者以任何适当的子组合形式实现。此外，尽管前面可能将特征描述为以特定组合起作用，甚至最初也被如此要求保护，但是来自所要求保护的组合中的一个或多个特征在某些情况下也可以从该组合中排除，并且该要求保护的组合可以被导向子组合或子组合的变型。
类似地，虽然各个操作在附图中被描绘为按照特定的顺序，但是这不应理解为要求这些操作必须以所示的特定顺序或者按顺行次序执行，也不应理解为要求必须执行所有示出的操作以获得期望的结果。
鉴于前面的描述并结合阅读附图，对前述本公开的示例性实施例的各种修改和改动对于相关领域的技术人员可以变得显而易见。任何和所有修改仍将落入本公开的非限制性和示例性实施例的范围内。此外，属于本公开的这些实施例所属领域的技术人员，在得益于前面的描述和相关附图所给出的教导后，将会想到在此描述的本公开的其他实施例。
因此，应当理解，本公开的实施例并不限于所公开的特定实施例，并且修改和其他的实施例也意图被包含在所附权利要求书的范围内。 尽管此处使用了特定术语，但是它们仅在通用和描述性意义上使用，而非为了限制的目的。

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  1. 一种用于Flash芯片的读写控制电路，包括：
    时序控制电路，其生成用于所述Flash芯片的读写时序信号；以及
    第一非易失性存储器，其用于存储与所述Flash芯片中的多个分区对应的多个标志位，所述标志位中的每一个指示与其对应的一个分区是否被正常写入；
    其中，所述时序控制电路被配置成当对所述Flash芯片中的一个分区写入数据时执行以下操作：
    生成将要写入的所述分区中的原有数据复制到一个非易失性备份存储区的时序信号；
    控制所述第一非易失性存储器将与要写入的所述分区对应的标志位设置为指示异常写入的第一值；
    生成将要写入的所述分区擦除的时序信号；
    生成将要写入的数据写入到所述分区的时序信号；以及
    在写入完成后将与所述分区对应的所述标志位设置为指示正常写入的第二值；并且
    其中，所述时序控制电路被进一步配置成在所述Flash芯片重新通电后，当从所述Flash芯片中的一个分区读取数据时，根据所述第一非易失性存储器中的所述标志位的指示，确定数据是从所述Flash芯片的所述分区还是从所述非易失性备份存储区读取。
  2. 根据权利要求1所述的读写控制电路，其中，所述时序控制电路被进一步配置成：
    当从所述Flash芯片中的一个分区读取数据时，如果所述第一非易失性存储器中的所述标志位为所述第二值，则生成从所述分区读取数据的时序信号，或者，如果所述第一非易失性存储器中的所述标志位为所述第一值，则生成从所述非易失性备份存储区读取数据的时序信号。
  3. 根据权利要求1所述的读写控制电路，其中，所述非易失性备份存储区为所述Flash芯片中的一个分区。
  4. 根据权利要求1所述的读写控制电路，其中，所述非易失性备份存储区被映射到与所述Flash芯片相分离的非易失性存储设备中。
  5. 根据权利要求4所述的读写控制电路，其中，所述非易失性存储设备的存储空间具有大于或等于所述Flash芯片的一个分区的大小。
  6. 根据权利要求1所述的读写控制电路，其中，所述非易失性备份存储区被映射到所述第一非易失性存储器。
  7. 根据权利要求1所述的读写控制电路，其中，所述第一非易失性存储器为电可擦除可编程只读存储器。
  8. 一种用于Flash芯片的读写控制方法，包括：
    当对所述Flash芯片中的一个分区写入数据时：
    生成将要写入的所述分区中的数据复制到一个非易失性备份存储区的时序信号；
    将与要写入的所述分区对应的标志位设置为指示异常写入的第一值；
    生成将所述分区擦除的时序信号；
    生成将要写入的数据写入到所述分区的时序信号；以及
    在写入完成后将与所述分区对应的所述标志位设置为指示正常写入的第二值；并且，
    在所述Flash芯片重新通电后，当从所述Flash芯片中的一个分区读取数据时：
    根据所述标志位的指示，确定是从所述Flash芯片的所述分区还是从所述非易失性备份存储区读取数据。
  9. 根据权利要求7所述的读写控制方法，其中，当从所述Flash芯片中的一个分区读取时，如果所述标志位为所述第二值，则生成从所述分区读取的时序信号，或者，如果所述标志位为所述第一值，则生成从所述非易失性备份存储区读取的时序信号。
  10. 一种AMOLED应用电路，包括Flash芯片和如权利要求1-7中任一项所述的读写控制电路，其中，所述Flash芯片用于存储AMOLED的电学补偿数据，并且所述读写控制电路用于控制向所述Flash芯片写入所述电学补偿数据和从所述Flash芯片读取所述电学补偿数据。
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