WO2016175137A1 - Laser oscillator - Google Patents

Abstract

A correction unit (98) receives a control signal from a control circuit (14), corrects the timing at which the control signal rises and falls, and outputs the corrected control signal to a gate driving unit (97). The gate driving unit (97) receives the control signal from the correction unit (98), and generates a gate driving signal for switching a switching element on or off on the basis of the timing at which the control signal rises or falls. The correction unit (98) includes one or more stages of a delay circuit having a variable delay amount, and the delay amount can be adjusted so that the timings at which a plurality of the switching elements are turned on or off can be brought close enough to each other to prevent any effect on the machining characteristics of a laser machining device connected to a laser oscillator.

Description

Laser oscillator

The present invention relates to a laser oscillator.

As a method of driving the discharge tube that is the load of the laser oscillator power supply with a desired current, the output current of the inverter that constitutes the laser oscillator and the discharge current by the transformer in the subsequent stage are detected, the detection result is fed back, and the inverter drive signal A method for controlling the pulse width is used (for example, Patent Document 1). Further, as a means for increasing energy, a method is used in which inverters are paralleled via a transformer to increase the output current to the discharge load.

In the circuit that controls inverter switching, various signal timing adjustments are made. For example, in Patent Document 2, a one-stage phase delay circuit in which an integrating circuit is connected between two inverters is used as both an output side inverter of the phase delay circuit and an input side inverter of the next phase delay circuit. And a pulse delay circuit including at least one phase delay cascade circuit in which even stages are cascaded.

JP 2009-194554 A JP-A-5-243926

In a laser oscillator composed of multiple inverters connected in parallel, if the output voltage or output current rises at the start of rising or falling timing between the multiple inverters, the output current waveform to the discharge tube Distortion occurs. As a result, the output characteristics of the laser in the discharge tube change, and when the laser oscillator is connected to the laser processing machine, the processing characteristics of the laser processing machine may be affected.

In the output voltage or output current of each inverter constituting the laser oscillator, the output voltage or output current of each inverter is set as in the circuit configuration shown in Patent Document 1 in order to align the timing at the start of rise and the start of fall. This is fed back to a control circuit that generates a control signal that determines the drive timing of the inverter so that each detected output voltage or each output current is equal, and each inverter starts and rises at the start of control signal rise. The timing at the start of descent can be adjusted. However, this requires complicated detection and control for each inverter. As a result, problems such as an increase in the size of the control circuit, an increase in wiring, and an increase in cost arise.

Therefore, an object of the present invention is to provide a laser oscillator capable of aligning the output voltage or output current rising start timing or falling start timing among a plurality of inverters with a simple configuration.

The laser oscillator according to the present invention includes a rectifier circuit that rectifies an AC voltage input from an AC power source and converts the AC voltage into a DC voltage, and a plurality of switching elements that are alternately turned on / off. An inverter unit for converting into an AC voltage, a transformer unit for boosting an AC voltage output from the inverter unit, a plurality of gate drive circuits each connected to one of a plurality of switching elements, and a plurality of gate drive circuits A control circuit that outputs a control signal for controlling the gate driving circuit, and a plurality of correction circuits each connected to one of the plurality of gate driving circuits in a one-to-one relationship. The correction circuit receives a control signal from the control circuit, corrects the rising timing and the falling timing of the control signal, and outputs the correction timing to the gate driving circuit. The gate drive circuit receives the control signal from the correction circuit and generates a gate drive signal for switching on / off of the switching element based on the rising timing and falling timing of the control signal. The correction circuit includes one or more stages of delay circuits having variable delay amounts, and the ON / OFF timings of the plurality of switching elements are brought close to a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. Thus, the delay amount can be adjusted.

According to the present invention, the correction circuit includes one or more stages of delay circuits having variable delay amounts, and a plurality of switching elements are turned on within a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. / The delay amount can be adjusted so that the OFF timing approaches. Thus, with a simple configuration, the difference in timing at the start of rising or the start of falling of the output voltage or output current among a plurality of inverters can be set within a range that does not affect the processing characteristics of the laser processing machine.

FIG. 3 is a circuit configuration diagram showing a laser oscillator and a discharge tube that outputs a laser as a load of the laser oscillator in the first embodiment. It is a figure which shows an example of a structure of a semiconductor switch. It is a figure which shows another example of a structure of a semiconductor switch. It is a figure which shows the relationship between the drive signal and output signal of a full bridge inverter. (A) is a figure which shows an example of a waveform when a shift | offset | difference does not arise in the timing at the time of the rise start of output current and the fall start of the inverter 9A. (B) is a figure which shows an example of a waveform when the shift | offset | difference arises in the rise or fall timing of output voltage or output current between the inverter 9A and the inverter 9B. 3 is a diagram illustrating an example of a correction circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a voltage input to the correction circuit according to the first embodiment, a voltage generated inside the correction circuit, and a voltage output from the correction circuit. FIG. It is a figure showing the structure of the trans | transformer part of a modification. It is a figure showing the example of the voltage with a narrow pulse width with respect to the period input into the correction circuit of Embodiment 1, the voltage produced | generated inside a correction circuit, and the voltage output from a correction circuit. It is a figure showing another example of the voltage with a narrow pulse width with respect to the period input into the correction circuit of Embodiment 1, the voltage produced | generated inside a correction circuit, and the voltage output from a correction circuit. 6 is a diagram illustrating a configuration of a correction circuit according to a second embodiment. FIG. It is a figure showing the example of the voltage input into the correction circuit of Embodiment 2, the voltage produced | generated inside a correction circuit, and the voltage output from a correction circuit. It is a figure showing the example of the voltage with a large pulse width with respect to the period input into the correction circuit of Embodiment 1, the voltage produced | generated inside a correction circuit, and the voltage output from a correction circuit. It is a figure showing another example of the voltage with a large pulse width with respect to the period input into the correction circuit of Embodiment 1, the voltage produced | generated inside a correction circuit, and the voltage output from a correction circuit. FIG. 10 is a diagram illustrating a configuration of a correction circuit according to a third embodiment. FIG. 10 is a diagram illustrating an example of a voltage input to the correction circuit according to the third embodiment, a voltage generated inside the correction circuit, and a voltage output from the correction circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
FIG. 1 is a circuit configuration diagram showing a laser oscillator 1 and a discharge tube 2 that outputs a laser as a load of the laser oscillator 1 in the first embodiment.

Referring to FIG. 1, a load discharge tube 2 is constituted by a dielectric capacitor 3 and a discharge resistor 4.

The laser oscillator 1 includes an AC power source 5, a rectifier circuit 6, a smoothing capacitor 7, an inverter unit 8, a transformer unit 10, an output current detection device 12, an output current monitoring unit 13, a control circuit 14, and a correction. Parts 98A1 to 98A4, 98B1 to 98B4, and gate driving parts 97A1 to 97A4 and 97B1 to 97B4.

The AC voltage input from the AC power supply 5 is rectified by the rectifier circuit 6 and converted into a DC voltage, smoothed by the smoothing capacitor 7, and then sent to the inverter unit 8.

The inverter unit 8 converts the sent DC voltage into an AC voltage. The inverter unit 8 includes a plurality of switching elements (semiconductor elements) that are alternately turned on / off.

The inverter unit 8 includes at least two or more inverters. In FIG. 1, the inverter unit includes an inverter 9A and an inverter 9B. Inverter 9A and inverter 9B are connected to common input nodes N1P and N1N.

The output nodes N2P and N2N of the inverter 9A and the output nodes N3P and N3N of the inverter 9B are connected to the transformer unit 10.

The transformer unit 10 boosts the AC voltage output from the inverter unit 8. The transformer unit 10 includes a plurality of transformers each having one primary winding and one secondary winding. In FIG. 1, the transformer unit 10 includes a transformer 50A and a transformer 50B. The primary side of transformer 50A is connected to output nodes N2P and N2N of inverter 9A. The primary side of transformer 50B is connected to output nodes N3P and N3N of inverter 9B. The secondary side of transformer 50A and the secondary side of transformer 50B are connected to common output nodes N4P and N4N.

The output current generated by synthesizing the secondary currents of the transformer 50A and the transformer 50B flows to the discharge tube 2 via the output reactor 11.

The output current detection device 12 detects the peak value of the output current.
The output current monitoring unit 13 calculates the difference between the peak value of the output current detected by the output current detection device 12 and the current command value input from the outside, and feeds it back to the control circuit 14.

The control circuit 14 generates a control signal that determines the switching timing of the inverter 9A and the inverter 9B. The control circuit 14 receives feedback of the difference between the peak value of the output current to the discharge tube 2 detected by the output current detection device 12 and the current command value input from the outside, which is calculated by the output current monitoring unit 13. The pulse width of the control signal is adjusted so as to eliminate the difference between the peak value of the output current and the current command value input from the outside.

The inverter 9A is a full bridge inverter constituted by arms A1 to A4. The inverter 9B is a full bridge inverter constituted by arms B1 to B4.

Each of the arms A1 to A4 and B1 to B4 includes semiconductor switches 15A1 to 15A4 and 15B1 to 15B4. The semiconductor switches 15A1 to 15A4 and 15B1 to 15B4 include at least one semiconductor element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor).

Depending on the rated current or rated voltage of the semiconductor switches 15A1 to 15A4 and 15B1 to 15B4, the semiconductor switches 15A1 to 15A4 and 15B1 to 15B4 include a single semiconductor device or a plurality of semiconductor elements connected in series or in parallel.

FIG. 2 is a diagram illustrating an example of the configuration of the semiconductor switch 15X. However, X = A1 to A4 and B1 to B4. The same applies to the following description.

As shown in FIG. 2, the semiconductor switch 15X includes a plurality of semiconductor elements 16Xa to 16Xd connected in series.

FIG. 3 is a diagram illustrating another example of the configuration of the semiconductor switch 15X.
As shown in FIG. 3, the semiconductor switch 15X includes a plurality of semiconductor elements 16Xa to 16Xd connected in parallel.

As shown in FIG. 2 or FIG. 3, when the semiconductor switch 15X is configured by a plurality of semiconductor elements 16Xa to 16Xd, the gate drive circuits 17Xa to 17Xd are connected to the semiconductor elements 16Xa to 16Xd at a one-to-one ratio. The The gate drive circuit 97X of FIG. 1 is configured by the gate drive circuits 17Xa to 17Xd. Correction circuits 18Xa to 18Xd are connected to gate driving circuits 17Xa to 17Xd at a one-to-one ratio. The correction circuit 18Xa to 18Xd constitutes the correction unit 98X in FIG.

The gate drive circuit 17Y converts the signal output from the correction circuit 18Y into a gate signal having a voltage or current sufficient to switch on / off the semiconductor element 16Y. The gate drive circuit 17Y raises the gate signal and turns on the semiconductor element 16Y at the timing when the signal output from the correction circuit 18Y rises. The gate drive circuit 17Y turns off the semiconductor element 16Y by lowering the gate signal at the timing when the signal output from the correction circuit 18Y falls. Y is A1a to A1d, A2a to A2d, A3a to A3d, A4a to A4d, B1a to B1d, B2a to B2d, B3a to B3d, B4a to B4d. The same applies to the following description.

Suppose that the semiconductor element 16Y is an ideal switch that switches on / off in an instant. In the arms A1 to A4 and B1 to B4 constituting the inverter unit 8, when the on / off of a certain arm X is switched, all the semiconductor elements 16Xa to 16Xd constituting the arm X are simultaneously switched on / off.

For example, when the arm A1 is turned on, all the semiconductor elements 16A1a to 16A1d constituting the arm A1 are simultaneously switched on. When the arm A1 is turned off, all the semiconductor elements 16A1a to 16A1d constituting the arm A1 are switched on. Switches off at the same time.

FIG. 4 is a diagram showing the relationship between the drive signal and the output signal of the full bridge inverter.
As the arms A1 to A4 are alternately turned on / off, the DC voltage input from the rectifier circuit 6 to the inverter 9A is converted into an AC voltage, and the converted AC voltage is input to the primary side of the transformer 50A. Is done. Similarly, by alternately switching on / off the arms B1 to B4, a DC voltage input from the rectifier circuit 6 to the inverter 9B is converted into an AC voltage, and the converted AC voltage is converted into the primary side of the transformer 50B. Is input.

For example, as shown in FIG. 4, arms A1, A3, B1, and B3 are simultaneously turned on / off, and arms A2, A4, B2, and B4 are at a timing that is 180 degrees out of phase with arms A1, A3, B1, and B3. Are simultaneously turned on / off, the DC voltage input from the rectifier circuit 6 to the inverters 9A and 9B can be converted into an AC voltage.

The input part of the correction circuit 18Y is connected to the output part of the control circuit 14. The correction circuit 18Y delays the timing of the rising start and the falling start of the control signal input from the control circuit 14, and sends the control signal corrected for the timing of the rising start and the falling start to the gate drive circuit 17Y. Output.

In the inverters 9A and 9B, the timing at which the output voltage or output current starts to rise and when it starts to fall depends on the switching characteristics of the semiconductor element 16Y used in the semiconductor switch 15X constituting the inverters 9A and 9B, or the semiconductor element 16Y. It changes in accordance with the input / output characteristics of the gate drive circuit 17Y to be driven or the switching characteristic difference or input / output characteristic difference caused by manufacturing variations in the semiconductor element 16Y or the gate drive circuit 17Y.

FIG. 5 (a) is a diagram showing an example of a waveform when there is no difference between the timing of the output current rising start and the falling start timing of the inverter 9A and the inverter 9B.

FIG. 5B is a diagram illustrating an example of a waveform when a shift occurs in the rise or fall timing of the output voltage or output current between the inverter 9A and the inverter 9B.

In FIG. 5B, the output current of the inverter 9A is delayed from the output current of the inverter 9B at the start of the rise and the start of the fall.

If the output voltage or output current starts to rise or starts to fall between the inverter 9A and the inverter 9B, a difference occurs between the transformer 50A connected to the inverter 9A and the transformer 50B connected to the inverter 9B. The secondary side current timing is shifted. Since the two secondary currents with different timings are combined and flow to the discharge tube 2, the waveform of the output current to the discharge tube 2 is distorted, and the peak value of the output current increases or decreases.

When distortion occurs in the waveform of the output current flowing into the discharge tube 2, the output characteristics of the laser in the discharge tube 2 change. If the output characteristics of the laser in the discharge tube 2 change, when the laser oscillator 1 is connected to the laser processing machine, the processing characteristics of the laser processing machine may be adversely affected.

Assuming that the values of the dielectric capacitor 3 and the discharge resistor 4 constituting the discharge tube 2 as the load of the laser oscillator 1 are constant and the current flowing into the semiconductor switch 15X constituting the inverters 9A and 9B is constant, the laser When a timing shift occurs between the inverter 9A and the inverter 9B constituting the oscillator 1 when the output voltage or the output current starts to rise or when the output starts falling, the timing is shifted to the discharge tube 2 as compared with the case where no timing shift occurs. The peak value of the output current that flows in decreases.

A decrease in the peak value of the output current flowing into the discharge tube 2 caused by the timing shift is detected by the output current detection device 12, and the detected result is fed back to the control circuit 14 via the output current monitoring unit 13. . The control circuit 14 adjusts the pulse width of the control signal so that a large output current flows through the discharge tube 2. At this time, a current larger than expected flows through the semiconductor element 16Y included in the semiconductor switch 15X constituting the inverters 9A and 9B, the semiconductor switch 15X generates heat suddenly, and in the worst case, it may be damaged. In order to prevent such a situation, it is necessary to reduce the timing difference at the start of rising or at the start of falling in the output voltages or output currents of the inverters 9A and 9B. For example, the timings may be aligned.

For example, in the circuit configuration shown in Patent Document 1, the following method is used to align the timings of the start of rise and the start of fall in the output voltage or output current of the inverter 9A and the inverter 9B. The output voltage or output current of the inverters 9A and 9B is detected by a detection device, and fed back to the control circuit 14 that generates a control signal that determines the drive timing of the inverters 9A and 9B. The control circuit 14 adjusts the timings of the control signal rising start and falling start. However, this method requires a detection device for the inverter 9A and a detection device for the inverter 9B. Further, since the control system becomes complicated, problems such as an increase in the size of the control circuit 14, an increase in wiring, and an increase in cost arise.

Therefore, in the present embodiment, a control for determining the drive timing of the inverter 9A and the inverter 9B by measuring in advance the timing difference between the start of the rise and the start of the fall in the output voltage or output current of the inverter 9A and the inverter 9B. The correction circuit 18Y corrects the signal at the start of signal rise and at the start of fall according to the measured timing difference. As a result, the timings of the rising start and the falling start in the output voltage or output current of the inverter 9A and the inverter 9B included in the laser oscillator 1 are made uniform.

In the present embodiment, the correction circuit 18Y individually corrects the drive timing of the gate drive circuit 17Y.

In the following description, the correction circuit 18Y is represented as a correction circuit 18 as a representative.
The correction circuit 18 includes at least one delay circuit in which a one-stage delay circuit in which an integrating circuit composed of a resistor and a capacitor is connected between two logic inverters is connected in an even number of stages.

FIG. 6 is a diagram illustrating an example of the correction circuit 18 according to the first embodiment.
As shown in FIG. 6, the correction circuit 18 includes logic inverters 19, 20, 23, and 26 and integration circuits 101 and 102. The integration circuit 101 includes a resistor 21 and a capacitor 22. The integration circuit 102 includes a resistor 24 and a capacitor 25.

Integrating circuit 101 is arranged between logic inverter 20 and logic inverter 23. An integration circuit 102 is disposed between the logic inverter 23 and the logic inverter 26. The logic inverter 19 is for matching the input and output logic.

In this embodiment, the logic inverters 19, 20, 23, and 26 are treated as ideal elements, and signal delays due to these elements are not considered. The same applies to other embodiments.

The logic inverter 20, the integration circuit 101, and the logic inverter 23 constitute a first-stage delay circuit DL1. The logic inverter 23, the integrating circuit 102, and the logic inverter 26 constitute a second stage delay circuit DL2.

The resistors 21 and 24 are variable resistors, and the resistance values Ra and Rb are variable. The capacitors 22 and 25 are variable capacitors, and the capacitance values Ca and Cb are variable.

FIG. 7 is a diagram illustrating an example of a voltage input to the correction circuit 18 according to the first embodiment, a voltage generated inside the correction circuit 18, and a voltage output from the correction circuit 18.

In FIG. 7, the voltage V <b> 1 represents the input voltage to the logic inverter 19. Voltage V2 represents a voltage input to logic inverter 23 included in delay circuit DL1 and delay circuit DL2. Voltage V3 represents a voltage output from logic inverter 23 and input to integrating circuit 102. Voltage V4 represents an input voltage to logic inverter 26 included in delay circuit DL2. Voltage V5 represents a voltage output from logic inverter 26. Vcc represents the power supply voltage of the logic inverters 19, 20, 23 and 26. Vth represents the threshold voltage of the logic inverters 19, 20, 23 and 26. It is assumed that the logic inverters 19, 20, 23 and 26 use elements having the same characteristics.

The time t1 represents a delay time of the rising timing of the voltage V2 with respect to the rising timing of the voltage V1. Time t2 represents a delay time of the falling timing of the voltage V2 with respect to the falling timing of the voltage V1. Time t3 represents a delay time of the rising timing of the voltage V4 with respect to the rising timing of the voltage V3. Time t4 represents a delay time of the falling timing of the voltage V4 with respect to the falling timing of the voltage V3.

When the voltage V1 is input to the logic inverter 19, the capacitor 22 is charged through the resistor 21 when the voltage V1 rises. Therefore, the rise of the voltage V2 is delayed by a delay time t1 from the rise of the voltage V1. When the voltage V1 falls, the charge stored in the capacitor 22 is discharged through the resistor 21, so that the fall of the voltage V2 is delayed by a delay time t2 from the fall of the voltage V1.

When the voltage V1 is a pulse signal that varies between 0 V and the power supply voltage Vcc of the logic inverters 19, 20, 23, and 26, the change V2_U at the rise of the voltage V2 with respect to time t is expressed by the following equation: .

V2_U = Vcc {1-EXP (−t / (Ra × Ca))} (1)
However, t = 0 represents the rising time of the voltage V1 and the rising start time of the voltage V2.

A change V2_D when the voltage V2 falls with respect to time t is expressed by the following equation.
V2_D = Vcc {EXP (-t / (Ra × Ca))} (2)
However, t = 0 represents the falling time of the voltage V1 and the falling start time of the voltage V2.

The delay time t1 is expressed as follows from the equation (1).
t1 = −Ra × Ca × ln (1-Vth / Vcc) (3)
The delay time t2 is expressed as follows from the equation (2).

t2 = −Ra × Ca × ln (Vth / Vcc) (4)
When a CMOS logic inverter is used as the logic inverter, assuming that the threshold voltage Vth of the logic inverter is Vth = Vcc / 2, the delay time t1 and the delay time t2 are expressed as follows from equations (3) and (4). The

t1 = t2≈0.693 × Ra × Ca (5)
When the voltage V2 is input to the logic inverter 23, a voltage V3 obtained by logically inverting the voltage V2 is output from the logic inverter 23 with the threshold voltage Vth as a boundary.

When the voltage V3 is input to the integration circuit 102, the capacitor 25 is charged through the resistor 24 when the voltage V3 rises, so that the rise of the voltage V4 is delayed by a delay time t3 from the rise of the voltage V3. When the voltage V3 falls, the charge stored in the capacitor 25 is discharged via the resistor 24, so that the fall of the voltage V4 is delayed by a delay time t4 from the fall of the voltage V3.

When the voltage V3 is a pulse signal that varies between 0 V and the power supply voltage Vcc of the logic inverters 19, 20, 23, and 26, the change V4_U at the rise of the voltage V4 with respect to time t is expressed by the following equation: .

V4_U = Vcc {1-EXP (−t / (Rb × Cb))} (6)
However, t = 0 represents the rise time of the voltage V3 and the rise start time of the voltage V4.

A change V4_D at the fall of the voltage V4 with respect to time t is expressed by the following equation.
V4_D = Vcc {EXP (-t / (Rb × Cb))} (7)
However, t = 0 represents the falling time of the voltage V3 and the falling start time of the voltage V4.

The delay time t3 is expressed as follows from the equation (6).
t3 = −Rb × Cb × ln (1-Vth / Vcc) (8)
The delay time t4 is expressed as follows from the equation (7).

t4 = −Rb × Cb × ln (Vth / Vcc) (9)
When a CMOS logic inverter is used as the logic inverter, assuming that the threshold voltage Vth of the logic inverter is Vth = Vcc / 2, the delay time t3 and the delay time t4 can be expressed as follows from equations (8) and (9). Is done.

t3 = t4≈0.693 × Rb × Cb (10)
When the voltage V4 is input to the logic inverter 26, a voltage V5 obtained by logically inverting the input voltage V4 with the threshold voltage Vth as a boundary is output.

As shown in the waveform diagram of FIG. 7, the delay time of the rise timing of the signal output from the correction circuit 18 is t1 + t4 with respect to the rise timing of the signal input to the correction circuit 18. The delay time of the falling timing of the signal output from the correction circuit 18 with respect to the falling timing of the signal input to the correction circuit 18 is t2 + t3.

When a CMOS logic inverter is used as the logic inverter, assuming that the threshold voltage Vth = Vcc / 2 of the logic inverter, t1 = t2 and t3 = t4. Therefore, the delay time t1 + t4 is equal to the delay time t2 + t3.

The resistors 21 and 24 included in any one or more of the correction circuits 18Y are set so that the timing difference Δt between the start of rising and the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B becomes zero. The resistance values Ra and Rb and the capacitance values Ca and Cb of the capacitors 22 and 25 are adjusted. As a result, the timings of the rising start and the falling start in the output voltage or output current of the inverter 9A and the inverter 9B included in the laser oscillator 1 are made uniform.

Or, measure the timing when arm X switches on / off. The latest timing among the measured timings is specified as the reference timing, and the difference ΔtX between the on / off switching timing of the arm X and the reference timing is calculated. The correction circuits 18Xa to 18Xd delay the rising of the control signal to the gate drive circuits 17Xa to 17Xd corresponding to the semiconductor elements 16Xa to 16Xd by ΔtX. The delay of ΔtX is obtained by adjusting the resistance values Ra and Rb of the resistors 21 and 24 and the capacitance values Ca and Cb of the capacitors 22 and 25 included in the correction circuits 18Xa to 18Xd.

Alternatively, the timing at which the semiconductor element 16Y is switched on / off is measured. The latest timing among the measured timings is specified as the reference timing, and a difference ΔtY between the on / off switching timing of the semiconductor switch 16Y and the reference timing is calculated. The correction circuit 18Y delays the rise of the control signal to the gate drive circuit 17Y corresponding to the semiconductor element 16Y by ΔtY. The delay of ΔtY is obtained by adjusting the resistance values Ra and Rb of the resistors 21 and 24 and the capacitance values Ca and Cb of the capacitors 22 and 25 included in the correction circuit 18Y.

By the above correction, it is possible to align the timings at the start of rising or the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B.

Further, since the correction circuit 18 of the present embodiment is composed of small and inexpensive general-purpose parts such as a resistor, a capacitor, and a logic inverter IC, the cost can be reduced.

[Modification of Embodiment 1]
In the first embodiment, a plurality of transformers each having one primary winding and one secondary winding are used as the transformer unit 10, and the primary side of each transformer is connected to each output unit of the inverters 9A and 9B on a one-to-one basis. The case where the transformer secondary side is connected in parallel has been described.

FIG. 8 is a diagram illustrating a configuration of a transformer unit 501 according to a modification.
In the present modification, the transformer unit 501 uses one transformer having a plurality of primary windings 31 and 32 and one secondary winding 33, and each connection end on the transformer primary side is each output of the inverters 9A and 9B. Needless to say, the same effects as those of the first embodiment can be obtained even when the transformer secondary side is a common winding, which is connected one-to-one with each other.

[Embodiment 2]
The correction circuit 28 according to the second embodiment is different from the correction circuit 18 according to the first embodiment. Other components of the second embodiment are the same as those of the first embodiment.

In the correction circuit 18 according to the first embodiment, the delay time (t1 + t4) of the rise timing of the control signal output from the correction circuit 18 with respect to the rise timing of the control signal input to the correction circuit 18, and the correction circuit 18 The delay time (t2 + t3) of the falling timing of the control signal output from the correction circuit 18 is equal to the falling timing of the control signal input to. Therefore, the difference between the rise of the output voltage or output current of the inverter 9A and the rise of the output voltage or output current of the inverter 9B, the fall of the output voltage or output current of the inverter 9A, and the output voltage or output current of the inverter 9B. When the difference in falling timing is different, both cannot be corrected simultaneously (Problem 1).

Next, problem 2 will be described.
FIG. 9 is a diagram illustrating an example of a voltage having a narrow pulse width with respect to a period input to the correction circuit 18 according to the first embodiment, a voltage generated inside the correction circuit 18, and a voltage output from the correction circuit 18. It is.

When the pulse width Ti of the control signal is as narrow as 0 <Ti << Ts / 2 with respect to the cycle Ts of the control signal input to the correction circuit 18 as in the example of the waveform diagram shown in FIG. 9, the delay circuit DL1 When the discharge starts before the voltage between the terminals of the capacitor 22 rises to the power supply voltage Vcc of the logic inverters 20 and 23, the delay time t2 provided with respect to the timing at the start of the fall of the voltage V1 is the set delay. There is a problem that it becomes shorter than time.

In order to prevent the delay time t2 from being shortened, it is necessary to set the delay time tx so as to start discharging from a sufficiently charged state until the voltage between the terminals of the capacitor 22 reaches the power supply voltage Vcc of the logic inverters 20 and 23. .

For example, the state in which the voltage between the terminals of the capacitor 22 is charged until it reaches 99% of the power supply voltage Vcc of the logic inverters 20 and 23 is sufficiently charged until the voltage between the terminals of the capacitor 22 reaches the power supply voltage Vcc of the logic inverter. Assuming that the voltage between the terminals of the capacitor 22 is sufficiently discharged and almost zero, the time required for charging until reaching 99% of the power supply voltage Vcc of the logic inverters 20 and 23 is assumed. tx (99%) is expressed by the following equation.

tx (99%) = − Ra × Ca × ln (1−0.99 × Vcc / Vcc) (11)
In order to prevent the delay time t2 from being shortened as shown in FIG. 9, the following conditions must be satisfied.

tx (99%) <Ti (12)
From the equation (3), the delay time t1 is expressed by the following equation.

t1 = −Ra × Ca × ln (1-Vth / Vcc) (13)
From Equations (11), (12), and (13), in order to prevent the provided delay time t2 from becoming shorter than the set delay time in the correction circuit 18 of the first embodiment, the delay circuit DL1 is referred to. The delay time t1 provided with respect to the timing at which the input voltage V1 starts to rise needs to satisfy the following conditions.

t1 <ln (1-Vth / Vcc) / ln (1-0.99 × Vcc / Vcc) × Ti (14)
Further, as in the example of the waveform diagram shown in FIG. 9, when charging is started before discharging until the voltage across the terminals of the capacitor 25 in the delay circuit DL1 becomes almost zero, the timing at the start of rising of the voltage V3 There is a problem that the delay time t <b> 3 provided is shorter than the set delay time.

In order to prevent the delay time t3 from being shortened, it is necessary to start charging from a state where the capacitor 25 is completely discharged until the voltage between the terminals of the capacitor 25 becomes almost zero.

For example, it is assumed that the state in which the inter-terminal voltage of the capacitor 25 is 1% of the power supply voltage Vcc of the logic inverters 23 and 26 is equivalent to the state in which the capacitor 25 is sufficiently discharged until the inter-terminal voltage of the capacitor 25 becomes almost zero. Then, the time ty (1%) required to discharge the capacitor 25 from the fully charged state until it reaches the power supply voltage Vcc of the logic inverters 23 and 26 until it becomes almost zero is expressed by the following equation: It is represented by

ty (1%) = − Rb × Cb × ln (0.01 × Vcc / Vcc) (15)
In order to prevent the delay time t3 from being shortened as shown in FIG. 9, the following conditions must be satisfied.

ty (1%) <Ti−t1 + t2 (16)
From the equation (9), the delay time t4 is expressed by the following equation.

t4 = −Rb × Cb × ln (Vth / Vcc) (17)
From Equations (15), (16), and (17), in order to prevent the delay time t3 provided in the correction circuit 18 of the first embodiment from becoming shorter than the set delay time, the delay circuit DL2 is entered. The delay time t4 provided with respect to the timing when the input voltage V3 starts to fall needs to satisfy the following conditions.

t4 <ln (Vth / Vcc) / ln (0.01 × Vcc / Vcc) × (Ti−t1 + t2) (18)
As described above, in the first embodiment, when a voltage having a narrow pulse width with respect to the period is input to the correction circuit 18, if it is not designed to satisfy the expressions (14) and (18), it is actually The provided delay amount becomes shorter than the set delay amount, and the timing shift of the inverters 9A and 9B cannot be accurately corrected. Theoretically, a plurality of delay circuits may be connected in cascade so that a delay amount satisfying Expressions (14) and (18) is generated, but problems such as an increase in the number of elements arise (Problem 2). .

Next, problem 3 will be described.
In the first embodiment, when the pulse width of the control signal input to the correction circuit 18 is narrow, for example, the pulse width Ti of the input signal is 0 <Ti << Ts with respect to the cycle Ts of the input signal to the delay circuit. When the delay time t1 set with respect to the timing at the start of rising of the voltage V1 input to the correction circuit 18 is longer than the pulse width Ti in the control signal input to the correction circuit 18, When t1> Ti, the following problem occurs.

FIG. 10 shows another example of a voltage having a narrow pulse width with respect to the period input to the correction circuit 18 of the first embodiment, a voltage generated inside the correction circuit 18, and a voltage output from the correction circuit 18. FIG.

When the voltage V1 input to the correction circuit 18 rises, the capacitor 22 starts discharging before the voltage across the capacitor 22 in the delay circuit DL1 reaches the threshold voltage Vth of the logic inverter. Thus, the pulse disappears at the output voltage V3 of the delay circuit DL1, and always becomes a constant voltage, and the inverters 9A and 9B cannot be driven (Problem 3).

In the second embodiment, in order to solve the problems 1 to 3 in the delay circuit in the first embodiment, a correction circuit 28 using a delay circuit having the same number of stages as the correction circuit in the first embodiment is used.

FIG. 11 is a diagram illustrating the configuration of the correction circuit 28 according to the second embodiment.
The correction circuit 28 includes a first-stage delay circuit DL1 and a second-stage delay circuit DL2 connected in series.

The delay circuit DL1 includes an integration circuit 201 including a resistor 37 and a capacitor 29, a diode 27, and a logic inverter 30. The diode 27 is connected in parallel with the resistor 37. The logic inverter 30 receives the output of the integration circuit 201. The diode 27 is connected in a direction in which a charging current flows from the input unit of the integration circuit 201 to the capacitor 29 of the integration circuit 201.

The delay circuit DL2 includes an integration circuit 202 composed of a resistor 32 and a capacitor 33, a diode 31, and a logic inverter 34. The diode 31 is connected in parallel with the resistor 32. Logic inverter 34 receives the output of integration circuit 202. The diode 31 is connected in a direction in which a charging current flows from the input unit of the integration circuit 202 to the capacitor 33 of the integration circuit 202.

The resistors 37 and 32 are variable resistors, and the resistance values Ra and Rb are variable. The capacitors 29 and 33 are variable capacitors, and the capacitance values Ca and Cb are variable.

In the correction circuit 28, since the capacitors 29 and 33 are required to be charged and discharged at high speed, it is desirable to use a film capacitor or a ceramic capacitor. Further, in order to realize high-speed charging / discharging in the capacitors 29 and 33, a fast recovery diode (FRD) or a Schottky barrier diode (SBD) capable of high-speed switching is used for the diodes 27 and 31. desirable.

FIG. 12 is a diagram illustrating an example of a voltage input to the correction circuit 28, a voltage generated inside the correction circuit 28, and a voltage output from the correction circuit 28 according to the second embodiment.

In FIG. 12, a voltage e1 is an input voltage to the delay circuit DL1, a voltage e2 is a voltage input to the logic inverter 30, a voltage e3 is output from the logic inverter 30 and is input to the delay circuit DL2, and a voltage e4 is The voltage input to the logic inverter 34, the voltage e5 is the voltage output from the logic inverter 34, Vcc represents the power supply voltage of the logic inverter, and Vth represents the threshold voltage of the logic inverter. It is assumed that the logic inverters 30 and 34 use elements having the same characteristics, and that the diodes 27 and 31 operate as ideal switches and switch instantaneously.

Time td1 is the delay time of the fall of the voltage generated in the delay circuit DL1, time td2 is the delay time of the fall of the voltage generated in the delay circuit DL2, Ts is the period of the signal input to the correction circuit 28, and Ti is The pulse width To of the signal input to the correction circuit 28 and To represent the pulse width of the signal output from the correction circuit 28.

When the voltage e1 is input to the delay circuit DL1, the capacitor 29 is charged rapidly through the diode 27 when the voltage e1 rises. Therefore, the rise of the voltage e2 does not cause a delay time with respect to the rise of the voltage e1. When the voltage e1 falls, the charge stored in the capacitor 29 is discharged through the resistor 37. Therefore, the fall of the voltage e2 is delayed by the delay time td1 with respect to the fall of the voltage e1.

The voltage e1 is a pulse signal that varies between 0V and the power supply voltage Vcc of the logic inverters 30 and 34.

A change e2_D when the voltage e2 falls with respect to time t is expressed by the following equation.
e2_D = Vcc {EXP (−t / (Ra × Ca))} (19)
However, t = 0 represents the falling time of voltage e1 and the start time of falling of voltage e2.

From the equation (19), the delay time td1 is expressed by the following equation.
td1 = −Ra × Ca × ln (Vth / Vcc) (20)
When a CMOS logic inverter is used as the logic inverters 30 and 34, assuming that the threshold voltage Vth of the logic inverters 30 and 34 is Vcc / 2, the delay time td1 is expressed as follows from the equation (20).

td1≈0.693 × Ra × Ca (21)
When the voltage e2 is input to the logic inverter 30, a voltage e3 obtained by logically inverting the input voltage e2 with the threshold voltage Vth as a boundary is output.

When the voltage e3 is input to the delay circuit DL2, the capacitor 33 is charged rapidly through the diode 31 when the voltage e3 rises. Therefore, the rise of the voltage e4 does not cause a delay time with respect to the rise of the voltage e3. When the voltage e4 falls, the charge stored in the capacitor 33 is discharged via the resistor 32. Therefore, the fall of the voltage e4 is delayed by the delay time td2 with respect to the fall of the voltage e3.

When the voltage e3 is a pulse signal that fluctuates between 0 V and the power supply voltage Vcc of the logic inverters 30 and 34, the change e4_D at the time of falling of the voltage e4 with respect to time t is expressed by the following equation.

e4_D = Vcc {EXP (−t / (Rb × Cb))} (22)
However, t = 0 represents the falling time of the voltage e3 and the starting time of the falling of the voltage e4.

From the equation (22), the delay time td2 is expressed by the following equation.
td2 = −Rb × Cb × ln (Vth / Vcc) (23)
When a CMOS logic inverter is used as the logic inverters 30 and 34, assuming that the threshold voltage Vth of the logic inverters 30 and 34 is Vcc / 2, the delay time td2 is expressed as follows from the equation (23).

td2≈0.693 × Rb × Cb (24)
When the voltage e4 is input to the logic inverter 34, a voltage e5 obtained by logically inverting the input voltage e4 with the threshold voltage Vth as a boundary is output.

As shown in the waveform diagram of FIG. 12, the delay time of the rising timing of the signal output from the correction circuit 28 with respect to the rising timing of the signal input to the correction circuit 28 is td2. The delay time of the falling timing of the signal output from the correction circuit 28 with respect to the falling timing of the signal input to the correction circuit 28 is td1.

When a CMOS logic inverter having a threshold voltage Vth = Vcc / 2 is used for the logic inverter, the delay time td1 and the delay time td2 can be set to different values as shown in the equations (21) and (24). Therefore, the correction circuit 28 of the present embodiment can solve the problem 1.

Further, in the correction circuit 28 of the present embodiment, the capacitors 29 and 33 are rapidly charged via the diodes 27 and 31 as in the example of the waveform diagram shown in FIG. The power supply voltage Vcc of the logic inverter rises instantly. Thus, unlike the first embodiment, even when the pulse width Ti of the input signal to the correction circuit 28 is as narrow as 0 <Ti << Ts / 2 with respect to the cycle Ts of the input signal, the input to the correction circuit 28 is performed. The delay time td1 generated with respect to the timing at which the voltage e1 starts falling does not become shorter than the set delay time. Therefore, the correction circuit 28 of the present embodiment can solve the problem 2.

Further, when the pulse width of the signal input to the correction circuit 28 of the present embodiment is narrow, for example, when the pulse width Ti of the input signal is 0 <Ti << Ts / 2 with respect to the signal period Ts, When the correction circuit 28 is used, in the delay circuit DL1, when the voltage e1 rises, the voltage between the terminals of the capacitor 29 rises instantaneously to the power supply voltage Vcc of the logic inverter, so that a pulse is generated at the output voltage e3 of the delay circuit DL1. Does not disappear. However, in the delay circuit DL2, when charging starts before the voltage across the capacitor 33 decreases to the threshold voltage Vth of the logic inverter, the pulse disappears at the output voltage e5 in the delay circuit DL2 of the correction circuit 28, and always. The voltage becomes constant and the inverters 9A and 9B cannot be driven.

In order to avoid this problem, referring to the waveform diagram of FIG. 12, in the delay circuit DL2 of the correction circuit 28, the delay time td2 is set in the following range.

td2 <Ti + td1 (25)
Accordingly, the timing at the start of the fall of the voltage e3 can be delayed without the pulse disappearing in the output voltage e5 of the delay circuit DL2 in the correction circuit 28. Therefore, the correction circuit 28 of the present embodiment can solve the problem 3.

Therefore, even in the case where the output voltage waveform or output current waveform of the inverters 9A and 9B constituting the laser oscillator 1 is a narrow pulse with the circuit configuration of FIG. 1, the delay time of the correction circuit 28 is within the range shown in the equation (25). By setting and using the output voltage or output current of the inverters 9A and 9B, the timing at the start of rising or the start of falling can be made uniform.

The resistance value Rb of the resistor 32 included in any one or more of the correction circuits 28Y and the capacitance of the capacitor 33 so that the timing difference Δt1 at the start of rising in the output voltage or output current of the inverter 9A and the inverter 9B becomes zero. The capacitance value Cb is adjusted. In addition, the resistance value Ra of the resistor 37 included in any one or the plurality of correction circuits 28Y is set so that the timing shift Δt2 at the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B becomes zero. The capacitance value Ca of the capacitor 29 is adjusted. As a result, the timings of the rising start and the falling start in the output voltage or output current of the inverter 9A and the inverter 9B included in the laser oscillator 1 are made uniform. However, it shall satisfy | fill the conditions of Formula (25).

Or, measure the timing when arm X switches on. The latest timing among the measured timings is specified as the reference timing, and a difference Δt1X between the arm X ON switching timing and the reference timing is calculated. The correction circuits 28Xa to 28Xd delay the rise of the control signal to the gate drive circuits 17Xa to 17Xd corresponding to the semiconductor elements 16Xa to 16Xd by Δt1X. The delay of Δt1X is obtained by adjusting the resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in the correction circuits 28Xa to 28Xd. Also, the timing at which the arm X switches off is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt2X between the arm X OFF switching timing and the reference timing is calculated. The correction circuits 28Xa to 28Xd delay the fall of the control signal to the gate drive circuits 17Xa to 17Xd corresponding to the semiconductor elements 16Xa to 16Xd by Δt2X. The delay of Δt2X is obtained by adjusting the resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in the correction circuits 28Xa to 28Xd. However, td2 = Δt1X, td1 = Δt2X, and the condition of Expression (25) is satisfied.

Alternatively, the timing at which the semiconductor element 16Y is turned on is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt1Y between the ON switching timing of the semiconductor switch 16Y and the reference timing is calculated. The correction circuit 28Y delays the rise of the control signal to the gate drive circuit 17Y corresponding to the semiconductor element 16Y by Δt1Y. The delay of Δt1Y is obtained by adjusting the resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in the correction circuit 28Y. In addition, the timing at which the semiconductor element 16Y is switched off is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt2Y between the switching timing of turning off the semiconductor switch 16Y and the reference timing is calculated. The correction circuit 28Y delays the fall of the control signal to the gate drive circuit 17Y corresponding to the semiconductor element 16Y by Δt2Y. The delay of Δt2Y is obtained by adjusting the resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in the correction circuit 28Y. However, it is assumed that td2 = Δt1Y, td1 = Δt2Y, and the condition of Expression (25) is satisfied.

By the above correction, it is possible to align the timings at the start of rising or the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B.

(Comparison with the width of delay amount in the first embodiment)
From the equations (14) and (18), in the correction circuit 18 of the first embodiment, the delay time is not shortened in the process of providing the delay time, and the pulse is not lost by the output signal of the delay circuit. The delay time t1 set with respect to the timing at the start of rising of the voltage V1 input to the delay circuit DL1, and the delay time t4 set with respect to the timing at the start of falling of the voltage V3 input to the delay circuit DL2. Must be set within the following range.

t1 <ln (1-Vth / Vcc) / ln (1-0.99 × Vcc / Vcc) × Ti (26)
t4 <ln (Vth / Vcc) / ln (0.01 × Vcc / Vcc) × (Ti−t1 + t2) (27)
For example, in the correction circuit 18 of the first embodiment, when a CMOS logic inverter is used as the logic inverter, assuming that Vth = Vcc / 2, it is input to the delay circuit DL1 from the equations (3) and (4). The delay time t1 set with respect to the timing when the voltage V1 starts to rise and the delay time t2 set with respect to the timing when the voltage V1 input to the delay circuit DL1 starts to fall are expressed as t1 = t2. Therefore, from the equations (26) and (27), the conditional expression can be expressed as follows.

t1 = t4 <0.15 × Ti (28)
In the above equation, calculation was performed using ln (0.5) / ln (0.01) = 0.15.

From equation (28), the correction circuit 18 according to the first embodiment can be operated so that the delay time is not shortened in the process of providing the delay time and the pulse is not lost by the output signal of the delay circuit. What is necessary is just to set delay time t1 + t4 provided with respect to the timing at the time of the start of the rise of the signal input to the correction circuit 18 of the form 1 in the following range.

t1 + t4 <0.3 × Ti (29)
However, equation (28) must be satisfied at the same time.

On the other hand, in the correction circuit 28 of the present embodiment, in order to operate the pulses so as not to disappear with the output signal of the correction circuit 28, each delay time is set as follows from the waveform diagram shown in FIG. There is a need to.

td1 <Ts-Ti (30)
td2 <Ti + td1 (31)
In order to compare the setting range of the delay time of the correction circuit 28 with the setting range of the delay time of the correction circuit 18, dividing the right side of the equation (31) by the right side of the equation (29) yields the following equation.

[Correction based on Rule 91 10.08.2016]
(Ti + td1) / (0.3) × Ti = 3.3 × (1 + td1 / Ti) (32)
From the equation (32), when the delay time td1> 0, the setting range of the delay time td2 in the correction circuit 28 of the present embodiment is three times or more wider than the setting range of the delay time t1 + t4 of the first embodiment.

From the above, in the circuit configuration shown in FIG. 1, when a signal with a narrow pulse width is input to the correction circuit, the delay time is not shortened in the process of providing the delay time in the correction circuit, and the pulse is not generated at the output of the delay circuit. When operating so as not to disappear, the correction circuit 28 of the second embodiment can be provided with a delay time that is three or more times larger than that of the correction circuit 18 of the first embodiment.

Needless to say, in the circuit configuration shown in FIG. 1, even when the correction circuit 28 of the second embodiment is used, the same effect as that of the first embodiment can be obtained.

[Embodiment 3]
The correction circuit 38 according to the third embodiment is different from the correction circuit 18 according to the first embodiment. Other components of the third embodiment are the same as those of the first embodiment.

First, the problem of the correction circuit 18 according to the first embodiment will be described in detail.
FIG. 13 is a diagram illustrating an example of a voltage having a large pulse width with respect to a cycle input to the correction circuit 18 according to the first embodiment, a voltage generated inside the correction circuit 18, and a voltage output from the correction circuit 18. It is.

When the pulse width Ti of the input signal is as thick as Ts / 2 << Ti <Ts with respect to the period Ts of the input signal to the correction circuit 18 as in the example of the waveform diagram shown in FIG. 13, the capacitor in the delay circuit DL1 The delay time t1 provided for the timing at the start of the rise of the voltage V1 is shorter than the set delay time when charging is started before the terminal 22 has been discharged until the voltage between the terminals becomes almost zero. There's a problem.

In the correction circuit 18, in order to prevent the delay time t1 from being shortened, it is necessary to set the delay time t2 so that charging is started from a sufficiently discharged state until the voltage between the terminals of the capacitor 22 becomes almost zero.

For example, assuming that the state in which the inter-terminal voltage of the capacitor 22 is 1% of the power supply voltage Vcc of the logic inverter is equivalent to the state in which the capacitor 22 is sufficiently discharged until the inter-terminal voltage of the capacitor 22 becomes almost zero. The time ty (1%) required to discharge from the fully charged state until the terminal voltage of 22 reaches the power supply voltage Vcc of the logic inverter to almost zero is expressed by the following equation.

ty (1%) = − Ra × Ca × ln (0.01 × Vcc / Vcc) (33)
In the correction circuit 18, in order to prevent the delay time t1 from being shortened as shown in FIG.

ty (1%) <Ts-Ti (34)
From the equation (4), the delay time t2 provided with respect to the timing at the start of the fall of the voltage V1 is expressed by the following equation.

t2 = −Ra × Ca × ln (Vth / Vcc) (35)
From Equations (33), (34), and (35), in order to prevent the delay time t1 provided in the correction circuit 18 of the first embodiment from being shorter than the set delay time, the delay circuit DL1 is entered. The delay time t2 provided with respect to the falling timing of the input voltage V1 needs to satisfy the following expression.

t2 <ln (Vth / Vcc) / ln (0.01 × Vcc / Vcc) × (Ts−Ti) (36)
When the correction circuit 18 starts discharging before the voltage across the capacitor 25 in the delay circuit DL2 reaches the power supply voltage Vcc of the logic inverter as shown in the example of the waveform diagram of FIG. There is a problem that the delay time t4 provided for the timing at the start of falling is shorter than the set delay time.

In the correction circuit 18, in order to prevent the delay time t4 from being shortened, it is necessary to set the delay time t3 so as to start discharging from a sufficiently charged state until the voltage between the terminals of the capacitor 25 reaches the power supply voltage Vcc of the logic inverter. There is.

For example, in the correction circuit 18, the state in which the voltage between the terminals of the capacitor 25 is charged until it reaches 99% of the power supply voltage Vcc of the logic inverter is sufficiently charged until the voltage between the terminals of the capacitor 25 reaches the power supply voltage Vcc of the logic inverter. Assuming that the voltage between the terminals of the capacitor 25 is sufficiently discharged and almost zero, the time tx () required for charging until reaching 99% of the power supply voltage Vcc of the logic inverter is assumed. 99%) is represented by the following formula.

tx (99%) = − Rb × Cb × ln (1−0.99 × Vcc / Vcc) (37)
In the correction circuit 18, in order to prevent the delay time t4 from being shortened as shown in FIG.

tx (99%) <Ts−Ti + t1−t2 (38)
In the correction circuit 18, in order to prevent the provided delay time t4 from becoming shorter than the set delay time, the delay time t3 provided with respect to the timing at which the voltage V3 input to the delay circuit DL2 starts to rise. However, it is necessary to satisfy the following formula.

t3 <ln (1-Vth / Vcc) / ln (1-0.99 × Vcc / Vcc) × (Ts−Ti + t1−t2) (39)
As described above, in the first embodiment, when a voltage having a large pulse width with respect to the period is input to the correction circuit 18, it is actually not designed so as to satisfy the expressions (36) and (39). The provided delay amount becomes shorter than the set delay amount, and the timing shift of the inverters 9A and 9B cannot be accurately corrected. Theoretically, the delay circuits may be cascaded in a plurality of stages so that a delay amount satisfying Expressions (36) and (39) is generated, but problems such as an increase in the number of elements arise (Problem 4). .

Next, problem 5 will be described.
FIG. 14 shows another example of a voltage having a large pulse width with respect to the period input to the correction circuit 18 of the first embodiment, a voltage generated inside the correction circuit 18, and a voltage output from the correction circuit 18. FIG.

When the pulse width of the input signal to the correction circuit 18 of the first embodiment is large, for example, the pulse width Ti of the control signal is Ts / 2 << Ti << with respect to the cycle Ts of the control signal input to the correction circuit 18. When Ts, the delay time t2 set with respect to the timing at which the control signal input to the correction circuit 18 starts to fall is the difference Ts− between the signal period Ts and the pulse width Ti in the control signal to the correction circuit 18. When longer than Ti, that is, when t2> Ts-Ti, there are the following problems.

When the signal input to the correction circuit 18 falls, charging starts before the voltage across the terminals of the capacitor 22 in the delay circuit DL1 drops to the threshold voltage Vth of the logic inverter. As a result, as shown in FIG. 14, the pulse disappears at the output voltage V3 of the delay circuit DL1, always becomes a constant voltage, and the inverters 9A and 9B cannot be driven (problem 5).

FIG. 15 is a diagram illustrating the configuration of the correction circuit 38 according to the third embodiment.
The correction circuit 38 includes a first-stage delay circuit DL1 and a second-stage delay circuit DL2 connected in series.

The delay circuit DL1 includes an integration circuit 201 including a resistor 37 and a capacitor 29, a diode 27, and a logic inverter 30. The diode 27 is connected in parallel with the resistor 37. The logic inverter 30 receives the output of the integration circuit 201. The diode 27 is connected in a direction in which a discharge current flows from the capacitor 29 of the integration circuit 201 to the input unit of the integration circuit 201.

The delay circuit DL2 includes an integration circuit 202 composed of a resistor 32 and a capacitor 33, a diode 31, and a logic inverter 34. The diode 31 is connected in parallel with the resistor 32. Logic inverter 34 receives the output of integration circuit 202. The diode 31 is connected in a direction in which a discharge current flows from the capacitor 33 of the integration circuit 202 to the input unit of the integration circuit 202.

The resistors 37 and 32 are variable resistors, and the resistance values Ra and Rb are variable. The capacitors 29 and 33 are variable capacitors, and the capacitance values Ca and Cb are variable.

In the correction circuit 38, since the capacitors 29 and 33 are required to be charged and discharged at high speed, it is desirable to use a film capacitor or a ceramic capacitor. Further, in order to realize high-speed charging / discharging in the capacitors 29 and 33, it is desirable to use fast recovery diodes (FRD) or Schottky barrier diodes (SBD) capable of high-speed switching for the diodes 27 and 31. .

FIG. 16 is a diagram illustrating an example of a voltage input to the correction circuit 38, a voltage generated inside the correction circuit 38, and a voltage output from the correction circuit 38 according to the third embodiment.

In FIG. 16, a voltage e6 represents an input voltage to the delay circuit DL1. Voltage e7 represents a voltage input to logic inverter 30. Voltage e8 represents a voltage output from logic inverter 30 and input to delay circuit DL2. Voltage e9 represents a voltage input to logic inverter 34. Voltage e10 represents a voltage output from logic inverter 34. Vcc represents the power supply voltage of the logic inverter. Vth represents the threshold voltage of the logic inverters 30 and 34. It is assumed that the logic inverters 30 and 34 use elements having the same characteristics, and that the diodes 27 and 31 operate as ideal switches and switch instantaneously.

The time td3 represents the delay time of the voltage rise generated in the delay circuit DL1. Time td4 represents the delay time of the rise of the voltage generated in the delay circuit DL2. Ts is the period of the signal input to the correction circuit 38, Ti is the pulse width of the signal input to the correction circuit 38, and To is the pulse width of the signal output from the correction circuit 38.

When the voltage e6 is input to the delay circuit DL1, when the voltage e6 falls, the charge stored in the capacitor 29 is rapidly discharged through the diode 27, so that no delay time occurs. Therefore, the fall of the voltage e7 does not cause a delay time with respect to the fall of the voltage e6. When the voltage e6 rises, the capacitor 29 is charged through the resistor 37. Therefore, the rise of the voltage e7 is delayed by the delay time td3 with respect to the rise of the voltage e6.

When the voltage e6 is a pulse signal that varies between 0V and the power supply voltage Vcc of the logic inverter, the change e7_U at the rise of the voltage e7 with respect to time t is expressed by the following equation.

e7_U = Vcc {1-EXP (−t / (Ra × Ca))} (40)
However, t = 0 represents the rise time of the voltage e6 and the start time of the fall of the voltage e7.

From the equation (40), the delay time td3 is expressed by the following equation.
td3 = −Ra × Ca × ln (1-Vth / Vcc) (41)
In the correction circuit 38, when a CMOS logic inverter is used as the logic inverter, assuming that the threshold voltage Vth of the logic inverter is Vth = Vcc / 2, the delay time td3 is expressed as follows from the equation (41).

td3≈0.693 × Ra × Ca (42)
When the voltage e7 is input to the logic inverter 30, a voltage e8 obtained by logically inverting the input voltage e7 with the threshold voltage Vth as a boundary is output.

[Correction based on Rule 91 10.08.2016]
When the voltage e8 is input to the delay circuit DL2, the charge stored in the capacitor 33 is rapidly discharged through the diode 31 when the voltage e8 falls, so that no delay time occurs. Therefore, the fall of the voltage e9 does not cause a delay time with respect to the fall of the voltage e8. When the voltage e8 rises, the capacitor 33 is charged through the resistor 32. Therefore, the rise of the voltage e9 is delayed by the delay time td4 with respect to the rise of the voltage e8.

When the voltage e8 is a pulse signal that varies between 0V and the power supply voltage Vcc of the logic inverter, the change e9_U at the rise of the voltage e9 with respect to time t is expressed by the following equation.

e9_U = Vcc {1-EXP (−t / (Rb × Cb))} (43)
However, t = 0 represents the rise time of the voltage e8 and the start time of the rise of the voltage e9.

From the equation (43), the delay time td4 is expressed by the following equation.
td4 = −Rb × Cb × ln (1-Vth / Vcc) (44)
In the correction circuit 38, when a CMOS logic inverter is used as the logic inverter, assuming that the threshold voltage Vth of the logic inverter is Vth = Vcc / 2, the delay time td4 is expressed by the following equation from the equation (44).

td4≈0.693 × Rb × Cb (45)
When the voltage e9 is input to the logic inverter 34, a voltage e10 obtained by logically inverting the input voltage e9 with the threshold voltage Vth as a boundary is output.

As shown in the waveform diagram of FIG. 16, the delay time of the rise timing of the signal output from the correction circuit 38 is td3 with respect to the rise timing of the signal input to the correction circuit 38. The delay time of the falling timing of the signal output from the correction circuit 38 is td4 with respect to the falling timing of the signal input to the correction circuit 38.

When a CMOS logic inverter having a threshold voltage Vth = Vcc / 2 is used for the logic inverter, the delay time td3 and the delay time td4 can be set to different values as shown in the equations (42) and (45). Therefore, the correction circuit 38 of the present embodiment can solve the problem 1.

In the correction circuit 38, as in the example of the waveform diagram shown in FIG. 16, the capacitors 29 and 33 are rapidly discharged through the diodes 27 and 31, and the voltage between the terminals of the capacitors 29 and 33 is instantaneously reduced to almost zero. descend. Therefore, unlike the case where the correction circuit 18 of the first embodiment is used, when the pulse width Ti of the input signal to the correction circuit 38 is as thick as Ts / 2 << Ti <Ts with respect to the cycle Ts of the input signal. However, the delay time td4 provided with respect to the timing at the start of falling of the voltage e6 input to the correction circuit 38 does not become shorter than the set delay time. Therefore, the correction circuit 38 according to the third embodiment can solve the problem 4.

Further, when the pulse width of the signal input to the correction circuit 38 of the present embodiment is large, for example, when the pulse width Ti of the input signal is Ts / 2 << Ti <Ts with respect to the signal period Ts. When the correction circuit 38 according to the present embodiment is used, the voltage between the terminals of the capacitor 29 drops to almost zero instantaneously when the voltage e6 falls in the delay circuit DL1, and therefore the output voltage e8 of the delay circuit DL1. In this case, the pulse does not disappear. However, if the delay circuit DL2 of the correction circuit 38 starts discharging before the voltage across the capacitor 33 rises to the threshold voltage Vth of the logic inverter, the pulse disappears in the output voltage e10 of the delay circuit DL2 of the correction circuit 38. However, the voltage is always constant and the inverters 9A and 9B cannot be driven.

In order to avoid this problem, referring to the waveform diagram of FIG. 16, in the delay circuit DL2 of the correction circuit 38, the delay time td4 is set to the following range.

td4 <Ts−Ti + td3 (46)
Therefore, even in the case where the output voltage waveform or output current waveform of the inverters 9A and 9B constituting the laser oscillator 1 is a pulse having the circuit configuration of FIG. 1, the delay time of the correction circuit 38 is within the range shown in the equation (46). By setting and using the output voltage or output current of the inverters 9A and 9B, the timing at the start of rising or the start of falling can be made uniform.

The resistance value Ra of the resistor 37 included in any one or a plurality of correction circuits 38Y and the capacitance of the capacitor 29 so that the timing difference Δt1 at the start of rising in the output voltage or output current of the inverter 9A and the inverter 9B becomes zero. The capacitance value Ca is adjusted. In addition, the resistance value Rb of the resistor 32 included in any one or more of the correction circuits 38Y so that the timing shift Δt2 at the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B becomes zero. The capacitance value Cb of the capacitor 33 is adjusted. As a result, the timings of the rising start and the falling start in the output voltage or output current of the inverter 9A and the inverter 9B included in the laser oscillator 1 are made uniform. However, it shall satisfy | fill the conditions of Formula (46).

Or, measure the timing when arm X switches on. The latest timing among the measured timings is specified as the reference timing, and a difference Δt1X between the arm X ON switching timing and the reference timing is calculated. The correction circuits 38Xa to 38Xd delay the rise of the control signal to the gate drive circuits 17Xa to 17Xd corresponding to the semiconductor elements 16Xa to 16Xd by Δt1X. The delay of Δt1X is obtained by adjusting the resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in the correction circuits 38Xa to 38Xd. Also, the timing at which the arm X switches off is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt2X between the arm X OFF switching timing and the reference timing is calculated. The correction circuits 38Xa to 38Xd delay the fall of the control signal to the gate drive circuits 17Xa to 17Xd corresponding to the semiconductor elements 16Xa to 16Xd by Δt2X. The delay of Δt2X is obtained by adjusting the resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in the correction circuits 38Xa to 38Xd. However, td3 = Δt1X, td4 = Δt2X, and the condition of Expression (46) is satisfied.

Alternatively, the timing at which the semiconductor element 16Y is turned on is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt1Y between the ON switching timing of the semiconductor switch 16Y and the reference timing is calculated. The correction circuit 38Y delays the rise of the control signal to the gate drive circuit 17Y corresponding to the semiconductor element 16Y by Δt1Y. The delay of Δt1Y is obtained by adjusting the resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in the correction circuit 38Y. In addition, the timing at which the semiconductor element 16Y is switched off is measured. The latest timing among the measured timings is specified as the reference timing, and a difference Δt2Y between the switching timing of turning off the semiconductor switch 16Y and the reference timing is calculated. The correction circuit 38Y delays the fall of the control signal to the gate drive circuit 17Y corresponding to the semiconductor element 16Y by Δt2Y. The delay of Δt2Y is obtained by adjusting the resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in the correction circuit 38Y. However, it is assumed that td3 = Δt1Y, td4 = Δt2Y, and the condition of Expression (46) is satisfied.

(Comparison with the width of delay amount in the first embodiment)
From Equations (36) and (39), in the correction circuit 18 of the first embodiment, the delay time is not shortened in the process of providing the delay time, and the pulse is not lost by the output signal of the delay circuit. The delay time t2 set with respect to the timing at the start of falling of the voltage V1 input to the delay circuit DL1, and the delay time t3 set with respect to the timing at the start of rising of the voltage V3 input to the delay circuit DL2. Must be set within the following range.

t2 <ln (Vth / Vcc) / ln (0.01 × Vcc / Vcc) × (Ts−Ti) (47)
t3 <ln (1-Vth / Vcc) / ln (1-0.99 × Vcc / Vcc) × (Ts−Ti + t1−t2) (48)
For example, in the correction circuit 18 of the first embodiment, when a CMOS logic inverter is used as the logic inverter, assuming that Vth = Vcc / 2, it is input to the delay circuit DL1 from the equations (3) and (4). The delay time t1 set with respect to the timing at the start of rising of the voltage V1 and the delay time t2 set with respect to the timing at the start of falling of the voltage V1 input to the delay circuit DL1 are represented by t1 = t2. Therefore, the conditional expression can be expressed as follows from the expressions (47) and (48).

t2 = t3 <0.15 × (Ts−Ti) (49)
From the equation (49), the correction circuit 18 according to the first embodiment can be operated so that the delay time is not shortened in the process of providing the delay time and the pulse is not lost by the output signal of the delay circuit. What is necessary is just to set delay time t2 + t3 provided with respect to the timing at the time of the fall start of the signal input into the 1 correction circuit 18 in the following ranges.

t2 + t3 <0.3 × (Ts−Ti) (50)
However, it is also necessary to satisfy equation (49).

On the other hand, in the correction circuit 38 of the present embodiment, in order to operate the pulses of the output signal of the correction circuit 38 so as not to disappear, each delay time is determined as follows from the waveform diagram and the equation (46) shown in FIG. Must be set.

td3 <Ti (51)
td4 <Ts−Ti + td3 (52)
In order to compare the setting range of the delay time of the correction circuit 18 and the setting range of the delay time of the correction circuit 38, the following equation is established by dividing the right side of the equation (52) by the right side of the equation (50).

[Correction based on Rule 91 10.08.2016]
(Ts−Ti + td3) / (0.3 × (Ts−Ti)) = 3.3 × (1 + td3 / (Ts−Ti)) (53)
From the equation (53), when the delay time td3> 0, the setting range of the delay time td4 in the correction circuit 38 of this embodiment is 3 compared to the setting range of the delay time t2 + t3 in the correction circuit 18 of the first embodiment. More than twice as wide.

From the above, in the circuit configuration shown in FIG. 1, when a signal having a large pulse width is input to the correction circuit, the delay time is not shortened in the process of providing the delay time in the correction circuit, and the pulse is generated at the output of the delay circuit. When operating so as not to disappear, the correction circuit 38 of the third embodiment can be provided with a delay time that is three or more times larger than that of the correction circuit 18 of the first embodiment.

(Comparison with the width of delay amount in the second embodiment)
In order for the correction circuit 28 of the second embodiment to operate so that the pulse is not lost by the output signal of the correction circuit 28, the falling edge of the signal input to the correction circuit 28 as in the example of the waveform diagram shown in FIG. It is necessary to set the delay time td1 provided for the start timing and the delay time td2 provided for the start timing of the signal input to the correction circuit 28 as follows.

td1 <Ts-Ti (54)
td2 <Ti + td1 (55)
In the correction circuit 38 of the third embodiment, in order to prevent the pulse from being lost by the output signal of the correction circuit 28, the falling edge of the signal input to the correction circuit 38 as in the example of the waveform diagram shown in FIG. It is necessary to set the delay time td4 provided for the start timing and the delay time td3 provided for the start timing of the signal input to the correction circuit 38 as follows.

td4 <Ts−Ti + td3 (56)
td3 <Ti (57)
When the pulse width of the signal input to the correction circuit 28 of the second embodiment is large, for example, when Ts / 2 << Ti <Ts, the following expression is established from the expression (54).

td1 << Ts / 2 (58)
From the expressions (55) and (58), the following expression is established.

td2 <Ti + td1≈Ts (59)
On the other hand, when the pulse width of the signal input to the correction circuit 38 of the third embodiment is large, for example, when Ts / 2 << Ti <Ts, the following expression is established from Expression (57).

td3 <Ti≈Ts (60)
From the expressions (56) and (60), the following expression is established.

td4 <Ts−Ti + td3≈Ts (61)
Comparing equations (58) and (60), in the circuit configuration shown in FIG. 1, when the pulse width Ti of the signal input to the correction circuit is large, for example, when Ts / 2 << Ti <Ts, The correction circuit 38 of the third embodiment can set the delay time in a wider range than the correction circuit 28 of the second embodiment.

When the pulse width of the signal input to the correction circuit 28 of the second embodiment is narrow, for example, when 0 <Ti << Ts / 2, the following equation is established from the equation (54).

td1 <Ts−Ti≈Ts (62)
From the expressions (55) and (62), the following expression is established.

td2 <Ti + td1≈Ts (63)
On the other hand, when the pulse width of the signal input to the correction circuit 38 of the third embodiment is narrow, for example, when 0 <Ti << Ts / 2, the following equation is established from the equation (57).

td3 << Ts / 2 (64)
From the expressions (56) and (64), the following expression is established.

td4 <Ts−Ti + td3≈Ts (65)
Comparing Expressions (62) and (64), in the circuit configuration shown in FIG. 1, when the pulse width Ti of the signal input to the correction circuit is narrow, for example, when 0 <Ti << Ts / 2, The correction circuit 28 according to the second embodiment can set the delay time in a wider range than the correction circuit 38 according to the third embodiment.

Needless to say, in the circuit configuration shown in FIG. 1, even when the correction circuit 38 of the third embodiment is used, the same effect as that of the first embodiment can be obtained.

In addition, it is not necessary to adjust the delay amount of the correction circuit so that the on / off timings of the plurality of switching elements coincide with each other, as long as the processing characteristics of the laser machine connected to the laser oscillator are not affected. The delay amount of the correction circuit may be adjusted so that the on / off timings of the plurality of switching elements are close to each other.

For example, the timing difference Δt between the start of rising and the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B is in a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. Alternatively, the resistance values Ra and Rb of the resistors 21 and 24 and the capacitance values Ca and Cb of the capacitors 22 and 25 included in any one or a plurality of correction circuits 18Y may be adjusted.

In the circuit of FIG. 11, the timing shift Δt1 at the start of rising in the output voltage or output current of the inverter 9A and the inverter 9B is in a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. As described above, the resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in any one or a plurality of correction circuits 28Y may be adjusted. Similarly, the timing difference Δt2 at the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B is set so that it does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. The resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in the correction circuit 28Y or the correction circuit 28Y may be adjusted.

In the circuit of FIG. 15, the timing difference Δt1 at the start of rising in the output voltage or output current of the inverter 9A and the inverter 9B is in a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. As described above, the resistance value Ra of the resistor 37 and the capacitance value Ca of the capacitor 29 included in any one or a plurality of correction circuits 38Y may be adjusted. Similarly, the timing difference Δt2 at the start of falling in the output voltage or output current of the inverter 9A and the inverter 9B is set so that it does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. The resistance value Rb of the resistor 32 and the capacitance value Cb of the capacitor 33 included in the correction circuit 38Y or the correction circuit 38Y may be adjusted.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 laser oscillator, 2 discharge tube, 3 dielectric capacitor, 4 discharge resistance, 5 AC power supply, 6 rectifier circuit, 7 smoothing capacitor, 8 inverter unit, 9A, 9B inverter, 10,501 transformer unit, 11 output reactor, 12 output Current detection device, 13 output current monitoring unit, 14 control circuit, 15 semiconductor switch, 16 semiconductor element, 17 gate drive circuit, 18, 28, 38 correction circuit, 19, 20, 23, 26, 30, 34 logic inverter, 21 24, 32, 37 resistance, 22, 25, 29, 33 capacitor, 27, 31 diode, 97 gate drive unit, 98 correction unit, 101, 102, 201, 202 integration circuit, 50A, 50B transformer.

Claims (9)

1. A laser oscillator,
   A rectifier circuit that rectifies an alternating voltage input from an alternating current power source and converts it into a direct current voltage;
   An inverter unit that includes a plurality of switching elements that are alternately turned on / off, and that converts a DC voltage output from the rectifier circuit into an AC voltage;
   A transformer unit that boosts the AC voltage output from the inverter unit;
   A plurality of gate drive circuits each connected one-to-one with one of the plurality of switching elements;
   A control circuit for outputting a control signal for controlling the plurality of gate driving circuits;
   Each comprising a plurality of correction circuits connected one-to-one with one of the plurality of gate drive circuits;
   The correction circuit receives the control signal from the control circuit, corrects the rising timing and the falling timing of the control signal, and outputs to the gate driving circuit,
   The gate drive circuit receives the control signal from the correction circuit and generates a gate drive signal for switching on / off of the switching element based on the rising timing and falling timing of the control signal. ,
   The correction circuit includes one or more stages of delay circuits having variable delay amounts, and the plurality of switching elements are turned on / off within a range that does not affect the processing characteristics of the laser processing machine connected to the laser oscillator. A laser oscillator in which the delay amount can be adjusted so that the timing approaches.
2. An output current detection device for detecting an output current from the transformer unit;
   An output current monitoring unit that calculates a difference between an output current detected by the output current detection device and a current command value input from the outside and outputs it as a feedback result;
   The laser oscillator according to claim 1, wherein the control circuit outputs a control signal for controlling the plurality of gate drive circuits based on the feedback result.
3. The delay circuit is
   An integration circuit composed of a resistor and a capacitor;
   A diode connected in parallel with the resistor;
   A logic inverter connected to the integrating circuit,
   The laser oscillator according to claim 1, wherein the diode is connected in a direction in which a charging current flows from an input portion of the integration circuit to a capacitor included in the integration circuit.
4. The correction circuit includes a first delay circuit in the first stage and a second delay circuit in the second stage,
   td1 is the delay time of the fall of the voltage generated in the first delay circuit, td2 is the delay time of the fall of the voltage generated in the second delay circuit, and Ti is the pulse of the control signal input to the correction circuit. When the width is set, the following conditions are satisfied:
   td2 <Ti + td1 (A1)
   The laser oscillator according to claim 3.
5. The delay circuit is
   An integration circuit composed of a resistor and a capacitor;
   A diode connected in parallel with the resistor;
   A logic inverter connected to the integrating circuit,
   The laser oscillator according to claim 1, wherein the diode is connected in a direction in which a discharge current flows from a capacitor included in the integration circuit to an input unit of the integration circuit.
6. The correction circuit includes a first delay circuit in the first stage and a second delay circuit in the second stage,
   td3 is the delay time of the rise of the voltage generated in the second delay circuit, td4 is the delay time of the rise of the voltage generated in the second delay circuit, Ts is the period of the control signal input to the correction circuit, Ti Is the pulse width of the control signal input to the correction circuit, the following condition is satisfied:
   td4 <Ts−Ti + td3 (A2)
   The laser oscillator according to claim 5.
7. The laser oscillator according to any one of claims 3 to 6, wherein the resistor included in the integrating circuit is a variable resistor, and the capacitor is a variable capacitor.
8. The laser oscillator according to any one of claims 3 to 6, wherein the capacitor included in the integrating circuit is a film capacitor or a ceramic capacitor.
9. The laser oscillator according to any one of claims 3 to 6, wherein the diode is a fast recovery diode or a Schottky barrier diode.

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