JPH01235415A - Method for driving field effect type transistor - Google Patents

Abstract

PURPOSE:To set an action delay which an FET itself has to a dead time and to improve control precision and responsibility by generating a turn-on-signal with making that the inverse bias detection element of a transistor in one arm which is serial to the other arm to non-action as a prohibition condition. CONSTITUTION:The detection elements X11, X12, X21 and X22 which operate when respective transistors 3 and 4 are inversely biased are provided, and the turn-on-signal is generated with the non-action of the detection elements X11, X12, X21 and X22 of the transistor 4 or 3 in one arm to which a gate circuit 20A or 20B that generates the turn-on/turn-off signal of the transistor 3 or 4 in the other arm is connected in serial to the other arm as the prohibition condition. Since the gate circuit 20A or 20B of the transistor 3 or 4 in one arm does not generate the turn-on signal until the inverse bias is secured between the gate sources of the transistor 3 or 4 in the other transistor, the positive and negative arms are prevented from being shortened. Furthermore, the dead time can automatically be secured by the characteristics of the transistors 3 and 4, whereby it can be shortened to the shortest possible time on circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for driving field effect transistors in a PWM inverter using them as switching elements.

[Conventional technology]

In a voltage source inverter with bridge-connected semiconductor switching elements, in order to prevent short circuits between the positive and negative arms,
The drive circuit is configured so that there is a period (dead time) in which the switching elements of both arms are both off.

A conventional example of this type of drive circuit will be described below with reference to FIG. The figure shows one phase of a PWM type voltage source inverter, and 1 and 2 are DC power supplies (voltage value = E/2
), 3 and 4 are switching elements (MO3 field effect transistor FET) of the inverter main circuit INV, 5 is an inductive load, VL is the inverter output voltage applied to the load 5, and iL is the load current flowing through the load 5. It shows. 6 is a triangular wave generator, which generates a triangular wave signal (period T) Vc serving as a carrier wave. 7 is a comparator, which compares the voltage command signal V" and the triangular wave signal Vc, and creates PWM signals Va and Vb. 8A is a timer circuit (on-delay/off-instant timer circuit, delay time ta); As shown in FIG. 4, the PWM signal Va is guided, and as shown in FIG. is waveform-shaped by the waveform shaping circuit 9A as shown in FIG. 4. IOA is a gate circuit, and the waveform shaping circuit 9
A gate signal (on/off signal) VGA for the FET 3 is generated in response to the output of the FET 3, and is supplied to the gate of the FET 3. The PWM signal vb is supplied to the gate circuit 10B through a timer circuit (on-delay/off-instant timer circuit, delay time ta) 8B and a waveform shaping circuit 9B, and the gate circuit 10B receives the gate signal (on/off signal) VGB of FET4. is prepared and supplied to the gate of the FET4.

Incidentally, waveforms of each part of this drive circuit are shown in FIG.

As is clear from this waveform diagram, the on/off signal VGA of FET3 and the on/off signal VGB of FET4 are always generated with a time interval t, and during time 1, the on/off signal VGA of FET3 is generated.
and 4 are both turned off, so the positive and negative arms of the inverter main circuit INV will not be short-circuited.

(Problem to be Solved by the Invention) However, the above time 1d is a dead time in which voltage control is not performed, so the inverter output voltage
is smaller than the voltage command value ■4 when the negative current iL is of positive polarity, as shown in FIG. 5(f), and conversely, when the load current iL is of negative polarity, As shown in Figure Fg), the output voltage vL becomes larger than the voltage command value V'', and the output voltage vL deviates from the voltage command value ■'' by a dead time of 14 minutes. This deviation (error) increases as the dead time [,] increases, and the carrier frequency (carrier frequency) increases.
The dead time t4 increases as the value increases, so it is desirable to make the dead time t4 as small as possible. However, in the conventional system described above, this is set using timer circuits 8A and 8B, so safety and reliability are ensured. Therefore, gate circuit 1
It is necessary to take into account the variations in the operation of the components of 0A, IOB, FET3, FET4, etc., and allow for a margin of dead time. There was a problem that it was not possible to set it too short.

The present invention has been made to solve the above problems, and provides a method for driving a field effect transistor that can shorten the dead time and improve control accuracy and responsiveness compared to the conventional method. The purpose is to

[Means to solve the problem]

In order to achieve the above object, the present invention provides a detection element that operates when each transistor is reverse biased, and
A gate circuit that receives a signal and creates an on/off signal for a transistor in one arm is configured to create an on signal when the above-mentioned detection element of a transistor in the other arm connected in series with the one arm is prohibited from operating. It is.

[Effect]

In the present invention, the gate circuit of the transistor in one arm is turned on regardless of the state of the PWM signal until an off signal is supplied to the transistor in the other arm and a reverse bias is established between the gate and source of the transistor. Since no signal is generated, the positive and negative arms will not be short-circuited, and the dead time is automatically secured due to the characteristics of the transistor, so the dead time is compared to the case where the setting circuit (timer circuit) is used. , the circuit configuration can be shortened to the shortest possible time.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In Figure 1, 2OA is the gate circuit of FET3, 20
B is a gate circuit of FET4. Gate circuit 20A
is an inverting amplifier PCI and a power supply 21a connected in parallel to a series circuit of electric currents 21a and 22a (both voltage Ea/2).
It has a series circuit of an on-signal transistor Tll and an off-signal transistor TI2 connected in parallel to the series circuit of 22a and 22a, and has an insulated gate (in this example, a photocoupler and an inverting element that inverts the polarity of its output). )The output of PCI is connected to the base of transistor Tll by photocoupler TX2.
(phototransistor) X22 and directly to the base of the transistor T12. Xll is the primary side (light emitting diode) of the photocoupler TXI, and is inserted between the gate and source of FET3 in the direction shown (in the forward direction on the gate side) via the reverse blocking diode D and the resistor r. There is. R is resistance.

The gate circuit 20B also has power supplies 21b and 22b (both voltage E).
a / 2 ) insulated gate (in this example, consisting of a photocoupler and an inverting element that inverts the polarity of its output) connected in parallel to the series circuit of the power supplies 21b and 22b, PO2, for the on signal connected in parallel to the series circuit of the power supplies 21b and 22b Transistor T21
, has a series circuit of off-signal transistor T22, and the output of insulated gate PC2 is connected to the base of transistor T21 on the secondary side of photocoupler TXI (phototransistor).
X12 and directly to the base of transistor T22.

X21 is the primary side (light emitting diode) of the photocoupler TX2, and is connected to F via a backflow blocking diode D and a resistor r.
It is inserted between the gate and source of ET3. R is resistance. The insulated gates PCI and PO2 each have P
WM signals Va and vb are guided. Since the other configuration is the same as the conventional configuration shown in FIG. 3, the same components are denoted by the same reference numerals.

Next, the operation of this embodiment will be explained with reference to the waveform time chart of FIG. In Figure 2, VGI and VG2
represent the voltages at the gates of FETs 3 and 4, respectively.

In this configuration, the light emitting diode
While it is turned on in response to GB and positive gate voltage VG2 is applied between the gate and source, the transistor X22 of the photocoupler TX2 is off, and the on-signal transistor Tll of the gate circuit 20A is in the off state. Te, P
The ON signal VGA is not supplied to the FET 3 regardless of the state of the WM signal Va. When the PWM signal vb turns off, the off signal transistor T2 of the gate circuit 20B
2 is turned on and an off signal is created, and after a certain minute time determined by the characteristics of FET 4 (input capacitance, equivalent series resistance, etc.), Δt
After b (< ta ), a reverse bias starts to be applied between the gate and source of FET4, and phototransistor X22 of photocoupler TX2 is turned on. At this time, since the PWM signal Va is on, the transistor Tll is immediately turned on, and after a certain time Δtm (<td), the FET
The voltage VGI applied between the gate and source of FET 3 becomes a positive voltage, turning on FET 3. At the same time as FET3 turns on,
The phototransistor X12 of the photocoupler TXI is turned off, and the transistor T21 of the gate circuit 20B is turned off regardless of the state of the PWM signal vb.

As described above, in this embodiment, the ON transistor Tll in the gate circuit 20A of the FET3 in the positive arm is connected to the PWM mode via the photodiode X22 of the photocoupler TX2.
In response to the signal Va, the light emitting diode ), FET3 always turns on 611 hours after FET4 turns off, and similarly, FET4 always turns on 611 hours after FET3 turns off.

In this embodiment, the dead times Δt1 and Δt are FET3
, is automatically given when FET4 is determined, and there is no need to provide a setting circuit (timer circuit) as described above.
There is no need to provide a margin in consideration of operation delays of the gate circuit 10A and IOB and variations in elements, and the dead time can be shortened compared to the conventional method.

〔Effect of the invention〕

As explained above, in the present invention, since the operation delay of the FET itself becomes the dead time, the influence of the dead time on the inverter operation can be minimized, and the control accuracy and responsiveness can be improved compared to the conventional method. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform time chart of each part of the above embodiment, Fig. 3 is a circuit diagram showing a conventional inverter drive circuit, and Fig. 4 is the above conventional example. FIG. 5 is a waveform time chart for the above-mentioned conventional example. 3.4-Field-effect transistor, 6-Triangular wave generator, 7-Comparator, 20A, 20B-Gate circuit, TI
L T12, T21, T22-) - transistor, TX
I, T X 2-7 Otocoupler, PCI, PC2 - insulated gate.

Claims (2)

[Claims] (1) In a PWM voltage source inverter that uses field effect transistors as switching elements in the main circuit, each transistor is provided with a detection element that operates when the transistor is reverse biased, and one arm A field effect type, characterized in that a gate circuit that creates an on/off signal for a transistor creates an on signal with the prohibition condition that the detection element of the transistor in the other arm connected in series with the one arm is inoperable. How to drive a transistor. (2) A claim characterized in that the detection element is a photocoupler, the primary side of which is inserted between the gate and source of a transistor in the other arm, and the primary side incorporated in the gate circuit of the transistor in one arm. 2. A method for driving a field effect transistor according to item 1.