JP2000324842A - Controller for power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce distortion of an AC output or input waveform caused by low order harmonies of a power converter. SOLUTION: The controller 7 for a power converter comprises a correction signal generator 38 outputting a correction signal S becoming an symmetric wave for the AC output or input frequency. Saw-tooth carrier h of a carrier generator 9 is corrected by the correction signal S into a correction carrier h1 symmetric for the AC output or input frequency and a PWM signal U being outputted from a comparator 10 is corrected by the correction carrier h1, Since the PWM signal U is corrected into a symmetric wave for the AC output or input frequency and a low even order harmonic is not contained in the corrected PWM signal U1, distortion of an AC output or input waveform caused by low order harmonics can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a power conversion device including an inverter device for converting DC power to AC power or a converter device for converting AC power to DC power, and in particular, to an AC output by low-order harmonics. It belongs to the control device of the power conversion device which can reduce the distortion of the waveform of the AC input.

[0002]

2. Description of the Related Art A power converter for converting DC power into AC power by controlling on / off of a plurality of switching elements for power conversion by PWM (pulse width modulation) control has conventionally been an inverter for driving an induction motor, an uninterruptible power supply. It is used for power supply devices and the like. In particular, recently, a resonance DC link type power conversion device that uses a resonant commutation circuit to reduce switching loss of a power conversion switching element has attracted attention.

FIG. 19 shows a carrier comparison type inverter device as a conventional power conversion device. The inverter device shown in FIG. 19 includes a pair of power conversion IGBTs (insulated gate bipolar transistors) as a plurality of switching elements connected in series to a DC power supply (1).
(2) (3) and a diode (4) connected between the collector and emitter terminals of the pair of power conversion IGBTs (2) and (3), respectively.
(5), a load (6) connected to a connection point of the pair of power conversion IGBTs (2) and (3), and a pair of power conversion IGBTs (2) and (3).
The first and second control pulse signals V _G1 ,
And a control circuit (7) as a control device for applying _VG2 and controlling on / off of the pair of power conversion IGBTs (2) and (3). A switching circuit composed of a pair of power conversion IGBTs (2) and (3) has a series circuit shown in FIG.
Other than the type, there is a half-bridge type configured by bridge-connecting a pair of power conversion IGBTs and a pair of capacitors, or a full-bridge type configured by two pairs of power conversion IGBTs. In the inverter device shown in FIG.
First and second control pulse signal V _G1, V pair of power conversion IGBT in _G2 output from (7) (2) on and (3)
By performing the off control, the DC power from the DC power supply (1) is converted into AC power and supplied to the load (6).

The control circuit (7) includes a reference voltage generator (8) as reference voltage generation means, a carrier wave generator (9) as carrier wave generation means, a comparator (10) as comparison means, and a code. Detector (11), inverter (12), dead time former (13)
(14) and gate drive circuits (15) and (16).
The reference voltage generator (8) is connected to the + input terminal of the comparator (10), and the carrier generator (9) is connected to the-input terminal of the comparator (10). The output terminal of the comparator (10) is connected to the code detector (11). The output terminal of the code detector (11) is connected to the dead time former (13) and to the other dead time former (14) via the inverter (12). The dead time former (13) is connected to the gate terminal of the power conversion IGBT (2) via a gate drive circuit (15), and the other dead time former (14) is connected to the other gate drive circuit (16). ) Is connected to the gate terminal of the other power conversion IGBT (3).

[0005] The reference voltage generator (8) outputs the reference voltage V _R of the AC output supplied to the load (6). Carrier generator (9)
Outputs a sawtooth carrier h sufficiently higher in frequency (20 to 150 kHz) than the frequency of the AC output (50 to 60 Hz).
The saw-tooth carrier h rises linearly from the minimum value to the maximum value, then drops sharply from the maximum value to the minimum value and is reset. Comparator (10) compares the voltage level of the level and sawtooth carrier wave h of the reference voltage V _R, if the level of the reference voltage V _R is higher than the voltage level of the sawtooth carrier wave h outputs a signal of positive value, If the level of the reference voltage V _R is lower than the voltage level of the sawtooth carrier wave h outputs a signal of a negative value. The sign detector (11) outputs a PWM signal U that is "+1" when the output signal of the comparator (10) is positive and "-1" when the output signal is negative. The inverter (12) is the PWM of the code detector (11).
When the signal U is "+1", "-1" is output, and otherwise, "+1" is output. Dead time former (13)
(14) when the PWM signal U is changed from "-1" to "+1", a predetermined period t _D outputs "-1", otherwise, to output the same signal as the PWM signal U. The gate drive circuits (15) and (16) output signals of the dead time formers (13) and (14) to each of the power conversion IGBTs (2) and (3) by “+”.
1 "turned on when the outputs of the first and second control pulse signal V _G1, V _G2 to the OFF state other than that.

FIG. 20A shows the output waveforms of the reference voltage V _R of the reference voltage generator 8 and the sawtooth carrier h of the carrier generator 9, and the output of the PWM signal U of the sign detector 11. Figure 2 shows the waveform
0 (B). Also, a pair of power conversion IGBTs (2) (3)
Operation delay or the like occurs in one of the power conversion I
When the GBTs (2) and (3) are simultaneously turned on, the DC power supply (1) is short-circuited.
Delaying the rise of the WM signal U by a certain period t _D ,
The turn-on of the pair of power conversion IGBTs (2) and (3) is delayed. Thus, showing the gate drive circuit (15) first and second from (16) are output of the control pulse signal V _G1, V _G2 of the waveform in FIGS 21 (A) and (B). In the following description, the dead time t _D of the first and second control pulse signals V _G1 and V _G2 shown in FIGS. 21A and 21B is omitted.

Next, a conventional resonant DC link type PWM inverter device is shown in FIG. The inverter device of FIG. 22 shows a three-phase AC type, in which a resonant commutation circuit (17) connected to a DC power supply (1), and a bridge connection between the resonant commutation circuit (17) and the load (6). 3 pairs of power conversion IGBTs (2) (3), (18)
(19), (20) (21) and three pairs of power conversion IGBTs (2) (3),
Diodes (4) (5), (22) (23), (24) (25) connected between the collector and emitter terminals of (18) (19), (20) (21)
And three pairs of power conversion IGBTs (2) (3), (18) (19), (20)
And a control circuit (7) for controlling on / off of (21). The control circuit (7) shown in FIG. 22 controls the reference voltage generator (8) shown in FIG. 19 to have U, V, and W-phase reference voltages V _UR , having a phase difference of (（) π [rad] from each other. V _VR, U for generating a V _WR, V, W-phase reference voltage generator (26), (27), was changed to (28), a comparator (10), code detectors (11), inverter (12 ), Dead time former (13) (14) and gate drive circuit (15) (16)
19 is substantially the same as the control circuit (7) shown in FIG.

The resonance commutation circuit (17) includes a resonance capacitor (2
9), resonance reactor (30), and three commutation IGBTs
(31), (32), (33) and three commutation diodes (34), (3
5) and (36). The collector terminal of the commutation IGBT (31) is connected to the positive terminal of the DC power supply (1). A commutation diode (34) is connected between the collector and emitter terminals of the commutation IGBT (31). IGBT for commutation (31)
Between the negative terminal of the DC power supply (1) and the
A commutation IGBT (32) and a commutation diode (35) are connected in series. A commutation diode (36) and a commutation IGBT (33) are connected in series between the collector terminal of the commutation IGBT (32) and the anode terminal of the commutation diode (35). A resonance reactor (30) is connected between a connection point of the commutation IGBT (32) and the commutation diode (35) and a connection point of the commutation diode (36) and the commutation IGBT (33).
A resonance capacitor (29) is connected between the commutation diode (36) and the commutation IGBT (33) and the power conversion IGBTs (2) and (3). In addition, three commutation IGBTs (31), (32),
(33) is turned on and off by the commutation control circuit (37),
Each time the pair of power conversion IGBTs (2) (3), (18) (19), (20) (21) is turned on and off, the resonance commutation circuit (17) operates and the resonance capacitor (29) The voltage at both ends, that is, the DC link voltage _VDL becomes approximately 0V.

The outline of the operation of the resonant commutation circuit (17) is as follows. When the IGBTs for commutation (31) are in the ON state and the IGBTs for commutation (32) and (33) are simultaneously turned from the OFF state to the ON state, the DC power supply (1) passes through the IGBTs (32) and (33) for commutation. As a result, a current flows through the resonance reactor (30), and energy is stored. At this time, the resonance capacitor (29) is charged to the voltage E of the DC power supply (1) with the polarity shown. When the IGBT for commutation (31) is turned off from the on state in the above state, the energy stored in the reactor for resonance (30) is reversed through the IGBTs for commutation (32) and (33) with the polarity opposite to that shown in the drawing. It is supplied to the resonance capacitor (29) and discharged until the charge of the resonance capacitor (29) becomes substantially zero. Resonant capacitor (2
When the electric charge of 9) becomes substantially zero, the voltage across the resonance capacitor (29), that is, the DC link voltage V _DL becomes substantially 0 V.
Within this period, each power conversion IGBT (2) (3), (18) (19),
(20) Perform the switching of (21). Thereby, the zero voltage switching (ZV) at the time of turning on or turning off each of the power conversion IGBTs (2) (3), (18) (19), (20) (21).
S). Thereafter, when the IGBTs (32) and (33) for commutation are simultaneously turned off from the on state, the resonance reactor (3
The energy of (0) is supplied to the resonance capacitor (29) via the commutation diodes (35) and (36), and the resonance capacitor (29)
Is charged with the polarity shown. When the DC link voltage _VDL exceeds the voltage E of the DC power supply (1), the commutation diode (34) becomes conductive and the accumulated charge of the resonance capacitor (29) is fed back to the DC power supply (1). IG for commutation within this period
The BT (31) is turned on from the off state. This allows
Zero voltage switching is performed when the commutation IGBT (31) is turned on. The resonance commutation circuit (1) shown in FIG.
The details of the operation 7) are described in, for example, “Anjo, Nakaoka: Resonant DC for New Generation Three-phase Voltage Type ZVS-PWM Inverter / Converter”
Link Circuit Topology and Characteristic Evaluation, Power Electronics Research Society Transactions Vol.21, No.2 (1996) ".

FIG. 23A shows the waveforms of the U, V, and W phase reference voltages V _UR , V _VR , V _WR and the sawtooth carrier h in the control circuit (7).
The waveforms of the U, V, and W phase PWM signals U _U , U _V , and U _W are shown in FIGS. 23 (B), (C), and (D), respectively. FIG. _23E shows the waveforms of the U, V, and W phase currents I _LU , I _LV , and I _LW flowing through the load (6), and shows the waveform of the DC link voltage V _DL of the resonant commutation circuit (17). Is shown in FIG. Further, the switching current I _T1 flowing between the collector-emitter terminals of the power conversion IGBTs (2), (3), (18), (19), (20), (21),
_{I T2, I T3, I T4} , I T5, the waveform of I _T6 respectively Figure 24
(A), (B), (C), (D), (E) and (F) are shown. In FIGS. 23 and 24, t ₀ ~t ₁₈ shows the reset timing of the sawtooth carrier wave h the voltage of the sawtooth carrier wave h abruptly changes from the maximum value to the minimum value.

In the resonance DC link type PWM inverter device shown in FIG. 22, each commutation IGBT of the resonance commutation circuit (17) is provided.
(31), (32), and (33) are switched to set the DC link voltage _VDL to approximately 0 V, and within that period, each power conversion IG
By performing switching of BT (2) (3), (18) (19), (20) (21), each power conversion IGBT (2) (3), (18) (19),
(20) Since zero voltage switching is performed at the time of turn-on or turn-off of (21), each power conversion IGBT (2)
(3) The surge voltage, surge current, and switching loss during the switching operation of (18), (19), (20), and (21) can be suppressed.

[0012]

By the way, in the carrier comparison type inverter device shown in FIG. 19, the reference voltage V _R
Since the waveform of the sawtooth carrier wave h does not become a positive-negative symmetric waveform as shown in FIG.
PW output from the comparator (10) via the code detector (11)
Reference waveform M signal U is as shown in FIG. 20 (B) Voltage V _R
Are not mutually inverted during the positive and negative half periods of. That is, when the function representing the PWM signal U and U (ψ) (ψ denotes the phase [rad] of the reference voltage V _R), U (ψ)
Since the relationship of = −U (ψ + π) does not hold, the PWM signal U becomes asymmetric with respect to the frequency of the AC output, and such a PWM signal contains many even-order low-order harmonic components. Therefore, when a function indicating the AC output voltage V _O supplied to the load (6) is V (θ) (θ indicates the phase [rad] of the AC output voltage V _O ), V (θ) = − V Since the relationship of (θ + π) is not established and a positive / negative symmetric sine waveform is not obtained, distortion of the AC output waveform due to even-order lower harmonics occurs. Further, in the resonant DC link type PWM inverter device shown in FIG. 22, as shown in FIGS. 23 (B), (C), (D) and (F), each IGBT for power conversion (2) (3), ( IGBTs (31) for each commutation of the resonant commutation circuit (17) for each switching of (18) (19), (20) and (21),
(32) and (33) are switched to make the DC link voltage V
_In order to make _DL approximately 0 V, each power conversion IGBT (2) (3),
(18) (19), (20) (21) Surge voltage, surge current and switching loss during switching operation can be reduced.
The power loss in the resonant commutation circuit (17) increases. The number of operations of the resonant commutation circuit (17) increases as the number of phases of the AC power supplied to the load (6) increases. Furthermore, the resonant commutation circuit (17)
The operating time of the resonance capacitor (2
9) and the switching frequency of the power conversion IGBT other than the power conversion IGBT during the switching operation during the operation of the resonance commutation circuit (17) because it depends on the resonance frequency determined by the constant of the resonance reactor (30). Can not. Therefore,
As the number of times of operation of the resonant commutation circuit (17) increases, the operation timing of the resonant commutation circuit (17) overlaps, whereby the power conversion IGBTs (2) (3), (18) (19) , (20) and (21), there is a problem in that there is a period during which switching cannot be performed, and there are many restrictions on switching timing.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control device for a power conversion device which can reduce the distortion of the waveform of an AC output or an AC input due to low-order harmonics. Another object of the present invention is to provide a control device for a power converter that can reduce power loss in a resonance commutation circuit when the device has a resonance commutation circuit. Still another object of the present invention is to provide a control device for a power converter in which the switching timing is less restricted due to the overlapping of the operation timings of the resonant commutation circuit.

[0014]

According to a first aspect of the present invention, a control device (7) for a power conversion device controls on / off of a plurality of switching elements (2) and (3) by a control signal to control a direct current (DC). AC or AC - converting power between direct current output and the reference voltage the reference voltage generating means for outputting (V _R) (8), a high enough frequency than the frequency of the AC output or AC input sawtooth carrier wave (h) And a PWM signal for controlling on / off of a plurality of switching elements (2) and (3) by comparing the level of the reference voltage (V _R ) with the voltage level of the sawtooth carrier (h). (U)
And a correction signal generating means (38) for outputting a correction signal (S) that becomes a symmetric wave with respect to the frequency of the AC output or AC input. Corrected carrier wave with the sawtooth carrier (h) or reference voltage (V _R ) corrected by the correction signal (S)
(h ₁ ) or the correction reference voltage (V _R1 ) corrects the PWM signal (U) to a symmetrical wave with respect to the frequency of the AC output or AC input.
As a result, even-order low-order harmonic components included in the PWM signal (U) asymmetric with respect to the frequency of the AC output or AC input are canceled out, so that the corrected PWM signal (U ₁ ) has even-order harmonic components. Does not include low-order harmonic components of Therefore, the waveform of the AC output or AC input is corrected to be symmetrical in the positive and negative directions, and the distortion of the waveform of the AC output or AC input due to low-order harmonics can be reduced.

According to a second aspect of the present invention, the control device (7) for the power converter includes a multiplication means (39) for outputting a corrected carrier (h ₁ ) representing a product of the saw-tooth carrier (h) and the correction signal (S). ) Is compared with the level of the reference voltage (V _R ) of the reference voltage generating means (8) and the voltage level of the corrected carrier (h ₁ ) of the multiplying means (39).
(U ₁ ). A product signal of the sawtooth carrier (h) and the correction signal (S) is formed by the multiplication means (39), and the correction carrier (h ₁ ) is output. The voltage level of the corrected carrier (h ₁ ) output from the multiplying means (39) is compared with the reference voltage generating means (8) by the comparing means (10).
Is compared to the level of the reference voltage (V _R), is output as correction PWM signal corrected symmetrically wave with respect to the frequency of the AC output or AC input a PWM signal (U) (U _1). Since the corrected PWM signal (U ₁ ) does not include even-order low-order harmonic components,
The waveform of the AC output or the AC input is corrected to be symmetrical in the positive and negative directions, and the distortion of the waveform of the AC output or the AC input due to the lower harmonics can be reduced.

According to a third aspect of the present invention, a control device (7) for a power conversion device outputs a first reference voltage (V _R1 ) representing a product of a reference voltage (V _R ) and a correction signal (S). Multiplying means (40), and comparing means (10) for comparing the level of the correction reference voltage (V _R1 ) with the voltage level of the sawtooth carrier (h) and outputting a PWM signal (U)
And a correction PW representing a product of the PWM signal (U) and the correction signal (S)
A second multiplying means (41) for outputting an M signal (U ₁ ). A product signal of the reference voltage (V _R ) and the correction signal (S) is formed by the first multiplication means (40), and is output as a correction reference voltage (V _R1 ). The level of the corrected reference voltage (V _R1 ) output from the first multiplying means (40) is compared with the voltage level of the sawtooth carrier (h) of the carrier generating means (9) by the comparing means (10), and PW
It is output as an M signal (U). The PWM signal (U) output from the comparing means (10) and the correction signal of the correction signal generating means (38)
(S) is formed by the second multiplication means (41),
The PWM signal (U) is output as a corrected PWM signal (U ₁ ) obtained by correcting the PWM signal (U) into a symmetric wave with respect to the frequency of the AC output or AC input. Since the corrected PWM signal (U ₁ ) does not include even-order low-order harmonic components, the waveform of the AC output or AC input is corrected to be positive / negative symmetric, and the waveform of the AC output or AC input due to the low-order harmonics is corrected. Distortion can be reduced. Further, in the case of the control device (7) of the power converter having three or more phase outputs or phase inputs, the sawtooth carrier (h) can be commonly used for all phases, so that three or more phase outputs are provided. Alternatively, when the present invention is applied to a power conversion device having a phase input, there is an advantage that the circuit configuration can be simplified as compared with the control device (7) of the power conversion device according to claim 2.

According to a fourth aspect of the present invention, there is provided a control device for a power converter, wherein a multiplying means for outputting a corrected reference voltage (V _R1 ) representing a product of the reference voltage (V _R ) and the correction signal (S). (39), comparing means (10) for comparing the level of the correction reference voltage (V _R1 ) with the voltage level of the sawtooth carrier (h) and outputting a PWM signal (U);
Drive signal generating means for generating signals (V _G1 ) and (V _G2 ) for driving on / off the plurality of switching elements (2) and (3) from the M signal (U) and the value of the correction signal (S) Signal switching means (42) for switching the output signals (V _G1 ) and (V _G2 ) of the drive signal generation means. Depending on the value of the correction signal (S), a signal (V _G1 ) for driving the plurality of switching elements (2) and (3) on and off,
Since (V _G2 ) is replaced by the signal switching means (42), the currents (I _T1 ), (I _T2 ) flowing through the plurality of switching elements (2) and (3)
Is corrected to a symmetric wave with respect to the frequency of the AC output or AC input. With this, a plurality of switching elements (2), (3)
Since the even-order lower harmonics are not superimposed on the currents (I _T1 ) and (I _T2 ) flowing through the AC, the waveform of the AC output or AC input is corrected to be symmetrical, and the AC output or AC Input waveform distortion can be reduced.

According to a fifth aspect of the present invention, the control device (7) for a power conversion device includes a current detection means (43) for detecting an AC output or AC input current (I _L ), and a correction signal generation means (38). ) Generates a correction signal (S) based on the direction of the detection current (I) of the current detection means (43). The reset timing of the sawtooth carrier (h) is always synchronized with the turn-on or turn-off timing of the plurality of switching elements (2) and (3), and each current ( _IT1 ) flowing through the plurality of switching elements (2) and (3) ) And (I _T2 ) have positive and negative symmetry, so AC output or AC input current (I _L )
Can be reduced by low-order harmonics of the waveform.

The control unit (7) of the power converter of the invention according to claim 6, the correction signal generating means (38) generates a correction signal (S) based on the polarity of the reference voltage (V _R). When the phase of the reference voltage (V _R ) and the phase of the AC output or AC input current (I _L ) match, the timing of resetting the saw-tooth carrier (h) is always a plurality of times, as in the case of claim 5. Switching element
Synchronous with the turn-on or turn-off timing of (2) and (3). Therefore, in this case, substantially the same effect as that of the fifth aspect can be obtained. Furthermore, since the current detecting means (43) is not required as compared with the case of claim 5, there is an advantage that the number of detectors can be reduced.

According to a seventh aspect of the present invention, the control device (7) for the power converter has a resonance commutation circuit (17) connected to the DC input side or the DC output side of the plurality of switching elements (2) and (3). The resonant commutation circuit (17) is driven in synchronization with the reset of the sawtooth carrier wave (h) of the carrier wave generation means (9) and outputs a DC link voltage (V
_DL ) to approximately 0V. Sawtooth carrier wave of carrier wave generation means (9)
Since the DC link voltage (V _DL ) output from the resonant commutation circuit (17) in synchronization with the reset of (h) becomes approximately 0 V, when the plurality of switching elements (2) and (3) are turned off, zero. Voltage switching is performed. Thereby, the surge voltage, surge current, and switching loss at the time of turning off the plurality of switching elements (2) and (3) are reduced. Also, when the sawtooth carrier (h) of the carrier generator (9) is reset, the resonant commutation circuit (1
Only the driving of (7) can reduce the switching loss and the like of the plurality of switching elements (2) and (3).
7) The number of operations can be reduced. Therefore, the resonant commutation circuit
The power loss in (17) can be reduced and the resonant commutation circuit (1
Since the operation timing of 7) does not overlap, the restriction on the switching timing of the plurality of switching elements (2) and (3) can be reduced.

The control device (7) of the power conversion device according to the invention of claim 8 connects the snubber capacitors (44) and (45) between both main terminals of the plurality of switching elements (2) and (3). Then, when the plurality of switching elements (2) and (3) are turned on, the sawtooth carrier (h) of the carrier generator (9) is reset. Carrier generation means when multiple switching elements (2) and (3) are turned on
The sawtooth carrier (h) of (9) is reset, and the resonant commutation circuit (17)
Since the DC link voltage (V _{D L} ) output from the switch becomes approximately 0 V, zero voltage switching is performed when the plurality of switching elements (2) and (3) are turned on. As a result, the surge voltage at the time of turning on the switching elements (2) and (3),
Surge current and switching loss are reduced. Also,
When the plurality of switching elements (2) and (3) are turned off, zero voltage switching is performed by the snubber action of the snubber capacitors (44) and (45), and the surge voltage, surge current and switching loss are reduced. Therefore, zero voltage switching is performed during all switching operations of the plurality of switching elements (2) and (3), so that the surge voltage, surge current and switching loss can be further reduced as compared with the case of claim 7. is there.

According to a ninth aspect of the present invention, the control device (7) for a power converter includes a current detecting means (43) for detecting an AC output or AC input current (I _L ). A plurality of switching elements (2) based on the direction of the detected current (I),
A gate switching means (50) for suspending any one of the switching operations of (3) is provided. By the gate switching means (50)
Based on the direction of the detection current (I) of the current detection means (43), the switching operation of the switching element (2), (3) where no current flows is paused. Therefore, since the plurality of switching elements (2) and (3) do not perform a switching operation at the same time, there is no need to provide a dead time, that is, a period in which the plurality of switching elements (2) and (3) are simultaneously turned off. This has the advantage that the circuit configuration of the control device (7) can be simplified.

According to a tenth aspect of the present invention, there is provided a control device for a power conversion device, comprising: a voltage correction value calculating means for calculating a voltage correction value (ΔV) from the reference voltage (V _R ) of the reference voltage generating means (8). (53)
And a correction reference that outputs a correction reference voltage (V _R2 ) by adding a voltage correction value (ΔV) to the reference voltage (V _R ) during an arbitrary period including when the voltage level of the correction signal (S) is switched. Voltage generation means. The correction signal is generated by the correction reference voltage generation means.
The reference voltage can be set during any period, including when the voltage level of (S) is switched.
(V _R ) to the voltage correction value (Δ
V) and outputs a corrected reference voltage ( _VR2 ). Thereby, the corrected PWM signal generated when the corrected carrier (h ₁ ) is switched
Since the spread of the pulse width of (U ₁ ) is suppressed, the distortion of the waveform of the AC output or AC input is corrected. Accordingly, there is an advantage that the distortion of the waveform of the AC output or the AC input generated when the corrected carrier (h ₁ ) is switched can be minimized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a control device of a power conversion device according to the present invention is applied to an inverter device of a carrier comparison type will be described below with reference to FIGS. However, in these drawings, substantially the same portions as those shown in FIGS. 19 and 20 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 1 shows an inverter device according to the present embodiment.
That is, the control circuit (7) as a control device of the inverter device shown in FIG. 1 is a binary signal of "+1" or "-1" which becomes a symmetric wave with respect to the frequency of the AC output supplied to the load (6). And a correction signal generator (38) as a correction signal generating means for outputting the correction signal S, and a correction representing the product of the sawtooth carrier h of the carrier generator 9 and the correction signal S of the correction signal generator 38. Carrier h ₁
This is characterized in that a multiplier (39) as a multiplying means for outputting a signal is provided in the control circuit (7) of the inverter device shown in FIG. The control circuit shown in FIG. 1 (7) of the comparator (10), compares the reference voltage generator and the level of the reference voltage V _R (8) and the voltage level of the correction carriers h ₁ of the multiplier (39) And the code detector (1
1) via the output correction PWM signal U _1. Other circuit configurations are substantially the same as those of the conventional inverter device shown in FIG.

In the configuration shown in FIG. 1, the configuration shown in FIG.
The sawtooth carrier h of the carrier generator (9) and the correction shown in FIG.
The product signal of the signal generator (38) and the correction signal S is sent to the multiplier (39).
Formed. The product signal output from the multiplier (39) is
As shown in FIG. 2B, the sawtooth carrier wave h is supplied to the load (6).
Correction corrected to a symmetric wave with respect to the frequency of the AC output
Carrier h₁Becomes Corrected transport output from multiplier (39)
Wave h₁2 (B) is shown by the comparator (10).
Reference voltage generator (8) reference voltage V_RCompared to the level of
As shown in FIG. 2C, the PWM signal U is supplied to the load (6).
Compensated to be symmetrical with respect to the frequency of the supplied AC output
Positive PWM signal U₁Output through the code detector (11) as
It is. Output from the comparator (10) through the code detector (11)
Corrected PWM signal U₁Directly to the dead time former (13)
The other input is input via the inverter (12).
It is input to the dead time generator (14). Dead time former
(13) Dead time t due to (14)_DCorrected PW in which
M signal U₁And its inverted signal -U ₁Is the gate drive circuit
(15) (16) is input to the gate drive circuit (15) (16).
First and second control pulse signals V_G1, V_G2As each
Output to the gate terminal of each power conversion IGBT (2) (3)
You. The operation of the main circuit of the inverter device of the present embodiment
The operation is based on the operation of the main circuit of the conventional inverter device shown in FIG.
Since the operation is substantially the same as that of the operation, the description is omitted.

[0026] In the embodiment shown in FIG. 1, a multiplier for correcting carrier h ₁ output from (39) are symmetrical wave with respect to the frequency of the AC output supplied to the load (6), a comparator ( 10) via the code detector (11), the corrected PWM signal U
₁ also becomes a symmetric wave with respect to the frequency of the AC output supplied to the load (6). Therefore, even-order low-order harmonic components included in the PWM signal U that are asymmetric with respect to the frequency of the AC output are canceled out, so that the corrected PWM signal U ₁ does not include even-order low-order harmonic components. . As a result, the waveform of the AC output supplied to the load (6) is corrected to be symmetrical in the positive / negative direction, and the AC output with less waveform distortion due to low-order harmonics can be supplied to the load (6).

The present invention is capable of various modifications. For example, in the embodiment shown in FIG. 3, a correction signal that outputs a binary correction signal S of “+1” or “−1” that becomes a symmetric wave with respect to the frequency of the AC output supplied to the load (6). Generator
And (38), a reference voltage generator as a first multiplying means for outputting a corrected reference voltage V _{R 1} representing a product of the correction signal S of the reference voltage V _R and the correction signal generator (38) (8) A first multiplier (40);
The output signal of the comparator (10) and the correction signal generator (38) of the correction signal a second multiplier as a second multiplication means for outputting a corrected PWM signal U ₁ representing the product of the S and (41) This is provided in the control circuit (7) shown in FIG. Further, the comparator (10) of the control circuit (7) shown in FIG. 3 is configured to control the level of the correction reference voltage V _R1 of the first multiplier (40) and the voltage level of the sawtooth carrier h of the carrier generator (9). And outputs a PWM signal U as a comparison output. Other circuit configurations are substantially the same as those of the conventional inverter device shown in FIG.

In the configuration shown in FIG. 3, a reference voltage generator
Product signal with the correction signal S of the reference voltage V _R and the correction signal generator (8) (38) is formed by a first multiplier (40), is output as the correction reference voltage V _R1. The level of the corrected reference voltage V _R1 output from the first multiplier (40) is compared with the voltage level of the sawtooth carrier h of the carrier generator (9) by the comparator (10), and the comparison output is a PWM signal. Code detector as U (11)
Is output to the second multiplier (41). Second multiplier
In (41), the PWM signal U output from the comparator (10) via the code detector (11) and the correction signal S of the correction signal generator (38) are output.
Product signal is formed with, the product signal is output as a corrected PWM signal U ₁ corrected symmetrically wave with respect to the frequency of the AC output supplied to the PWM signal U to the load (6). The subsequent operation is substantially the same as the operation of the control circuit (7) shown in FIG.

[0029] In the embodiment shown in FIG. 3, the waveform of the corrected PWM signal U ₁ is substantially the same as the waveform of the corrected PWM signal U ₁ in the case of the embodiment shown in FIG. Therefore,
An effect similar to that of the embodiment of FIG. 1 can be obtained. Also, 3
In the case of an inverter device having one or more phase outputs, the sawtooth carrier wave h can be used in common for all phases, so that only one carrier wave generator (9) is required, and the inverter of the embodiment shown in FIG. There is an advantage that the circuit configuration can be simplified as compared with the control circuit (7) of the device.

Further, in the embodiment shown in FIG.
A correction signal generator (38) that outputs a binary correction signal S of “+1” or “−1” that becomes a symmetrical wave with respect to the frequency of the AC output supplied to (6), and a reference voltage generator ( reference voltage V _R and the correction signal generator 8) and (38) of the correction signal S a multiplier for outputting a corrected reference voltage V _R1 representing the product of (39), the correction signal S of the correction signal generator (38) A pair of power conversion IGBs
Control pulse signals V _G1 and V _{G for} driving T (2) (3) on / off
A signal switch (42) as a signal switching means for switching _G2 is provided in the control circuit (7) shown in FIG. FIG.
The comparator (10) of the control circuit (7) compares the level of the correction reference voltage V _R1 of the multiplier (39) with the voltage level of the sawtooth carrier h of the carrier generator (9), and outputs the comparison output. As a PWM signal U. Other circuit configurations are substantially the same as those of the conventional inverter device shown in FIG.

In the configuration shown in FIG. 4, a reference voltage generator
A product signal of the reference voltage VR of (8) and the correction signal S of the correction signal generator (38) is formed by the multiplier (39), and the corrected reference voltage V _R
Output as _R1 . The level of the corrected reference voltage V _R1 output from the multiplier (39) is determined by the comparator (10).
It is compared with the voltage level of the sawtooth carrier h of (9), and the comparison output is output as the PWM signal U via the code detector (11). The PWM signal U output from the comparator (10) via the code detector (11) is directly input to the dead time forming unit (13) and also forms the other dead time via the inverter (12). Input to the vessel (14). Dead time former (1
3), PWM signal U and the inverted signal -U dead time t _D is formed by (14) is input to the signal switching device (42). In the signal switch (42), when the value of the correction signal S of the correction signal generator (38) is "+1", the dead time former (13)
PW with dead time t _D input from (14)
The M signal U and its inverted signal -U are output to the gate drive circuits (15) and (16), respectively, and the value of the correction signal S is "-1".
In this case, the signals input from the dead time generators (13) and (14) are interchanged and output to the gate drive circuits (16) and (15), respectively. Therefore, the signal switch (4
Signal output from 2) is equal to the correction PWM signal U ₁ and its inverted signal -U ₁ corrected symmetrically wave with respect to the frequency of the AC output supplied to the PWM signal U to the load (6). The subsequent operation is substantially the same as the operation of the control circuit (7) shown in FIG.

In the embodiment shown in FIG. 4, the signal switch (4
The waveforms of the signals input from 2) to the gate drive circuits (15) and (16) are substantially the same as those of the embodiment shown in FIGS. Therefore, substantially the same effects as in the embodiment of FIGS. 1 and 3 can be obtained. In addition, some microcomputers having a PWM function, such as SH7032 manufactured by Hitachi, Ltd., can output PWM signals for a plurality of phase outputs and can form a dead time. When the control circuit (7) is configured, there is an advantage that the circuit configuration can be simplified as compared with the inverter device of the embodiment shown in FIGS.

In the embodiment shown in FIG.
Current detector (43) a pair of power conversion IGBT as a current detecting means for detecting an AC output current I _L supplied to (6)
(2) Provided on an output line between (3) and the load (6), and when the sign of the detection signal I of the current detector (43) is positive, “+1”, and when negative, “−1” A correction signal generator (38) for outputting a correction signal S, and a correction carrier h ₁ representing the product of the sawtooth carrier h of the carrier generator (9) and the correction signal S of the correction signal generator (38).
Is provided in the control circuit (7) shown in FIG. The comparator (1) of the control circuit (7) shown in FIG.
0) compares the voltage level of the correction carriers h ₁ of the reference voltage generator (8) level and a multiplier of the reference voltage V _R (39), through a sign detector (11) corrected PWM signal U Outputs ₁ . Other circuit configurations are substantially the same as those of the conventional inverter device shown in FIG.

[0034] In the configuration shown in FIG. 5, the load (6) AC output current shown in FIG. 6 (E) to be supplied to the I _L is the current detector (4
3), the correction signal S shown in FIG. 6 (D) is "+1" when the sign of the detection signal I is positive and "-1" when the sign of the detection signal I is negative, from the correction signal generator (38). Is output. FIG.
The correction signal S of the correction signal generator (38) shown in FIG.
9A, and a product signal with the sawtooth carrier h of the carrier generator 9 shown in FIG. 6A is formed. Product signal output from the multiplier (39) is corrected symmetrically wave with respect to the frequency of the current I _L of the AC output supplied to the load (6) a sawtooth carrier wave h as shown in FIG. 6 (B) It was the correction carrier h _1. Multiplier (3
The voltage level of the correction carrier h ₁ outputted from 9) is compared to the level of the reference voltage V _R of the comparator (10) by the reference voltage generator shown in FIG. 6 (B) (8), FIG. 6 (C )
Code detector as correction PWM signal U ₁ corrected symmetrically wave with respect to the frequency of the current I _L of the AC output supplied to WM signal U to the load (6) (11) via the output. The corrected PWM signal U output from the comparator (10) via the code detector (11)
₁ is directly input to the dead time former (13) and the other dead time former (14) via the inverter (12).
Is input to Dead time former (13), the correction PWM signal U ₁ and its inverted signal -U ₁ dead time t _D is formed by (14) is a gate drive circuit (15), is input to the (16), the gate drive circuit First and second from (15) and (16)
Are output to the gate terminals of the power conversion IGBTs (2) and (3), respectively, as control pulse signals V _G1 and V _G2 . The first and second control pulse signals V _G1 and V _G2 output from the gate drive circuits (15) and (16) allow a pair of power conversion I
The GBTs (2) and (3) are turned on and off, and each power conversion IG
The switching currents I _T1 and I _T1 shown in FIGS. 6F and 6G are respectively applied between the collector and emitter terminals of the BTs (2) and (3).
_T2 flows. Also, FIG. 6 (F) and as shown in (G), each of the power conversion IGBT (2), (3) the switching current I _T1 flowing in, the timing of turn-on when I _T2 is positive direction in FIG. 6 ( It is synchronized with the timing of the reset (falling portion) of the sawtooth carrier wave h shown in A).

[0035] In the embodiment shown in FIG. 5, the correction since PWM signal U ₁ is symmetrical wave in synchronization with the direction of the switching current I _L of the AC output supplied to the load (6), shown in FIG. 1 Almost the same effects as in the embodiment can be obtained. Further, an inverted signal of the correction signal S shown in FIG.
The same effect as described above can be obtained by using a sawtooth carrier wave whose rising portion is reset instead of the sawtooth carrier wave h whose falling portion is reset as shown in FIG. In this case, the turn-off timing when the switching currents I _T1 and I _T2 flowing through the power conversion IGBTs (2) and (3) are in the positive direction is synchronized with the timing of the rising sawtooth carrier wave reset (rising portion). Further, as shown in FIG. 7, even when the embodiment shown in FIG. 5 is applied to a three-phase inverter device, the operational effects obtained are substantially the same as those shown in FIG.

In the embodiment shown in FIG. 8, when the reference voltage V _R of the reference voltage generator (8) has a positive half cycle, “+”
1), a correction signal generator (38) for outputting a correction signal S which becomes "-1" in the negative half cycle, a sawtooth carrier h of the carrier generator (9) and a correction signal generator (38). multiplier for outputting the corrected carrier wave h ₁ representing the product of the correction signal S and (39) are provided in the control circuit (7) shown in FIG. 19. The control circuit shown in FIG. 8 (7) of the comparator (10), compares the reference voltage generator and the level of the reference voltage V _R (8) and the voltage level of the correction carriers h ₁ of the multiplier (39) And a corrected PWM signal U via a code detector (11).
Outputs ₁ . Other circuit configurations are substantially the same as those of the conventional inverter device shown in FIG.

In the configuration shown in FIG. 8, a reference voltage generator
(8) reference voltage V_RIs "+1" when positive half cycle, negative
When the correction signal S becomes "-1" in the half cycle, the correction signal is generated.
It is output from the creature (38). The correction signal of the correction signal generator (38)
The signal S is input to the multiplier (39), and the sawtooth of the carrier generator (9)
A product signal with the carrier h is formed. Output from multiplier (39)
The resulting product signal is a sawtooth carrier h that is applied to the reference voltage generator (8).
Reference voltage V_RCorrected to a symmetrical wave with respect to the frequency of
Carrier h₁Becomes Corrected transport output from multiplier (39)
Wave h₁The reference voltage is generated by the comparator (10).
Reference voltage V _ROf the PWM signal U
Is the reference voltage V of the reference voltage generator (8)._RVs. frequency
Corrected PWM signal U corrected to the nominal wave₁As sign detector
Output via (11). The subsequent operation is shown in FIG.
Since the operation is substantially the same as that of the control circuit (7), the description is omitted.
You.

[0038] In the embodiment shown in FIG. 8, the reference voltage the reference voltage V correction in synchronization with the switching of the polarity of the _R PW generator (8)
Since M signal U ₁ is symmetrical wave, it is substantially the same effect as in the embodiment shown in FIG. 1 is obtained. Further, the AC phase and the inverter device of the reference voltage V _R in this case, the reference voltage generator (8) for applying an inverter device having a control circuit (7) of the embodiment shown in FIG. 8 to the power factor control converter Output current I _L
And the phases of the switching currents I _T1 and I _T2 flowing through the power conversion IGBTs (2) and (3) are in the positive direction, similarly to the embodiment shown in FIG. Are synchronized with the reset timing of the sawtooth carrier wave h of the carrier wave generator (9). In this case, there is an advantage that the number of detectors can be reduced because the current detector (43) is not required as compared with the embodiment shown in FIG.

Next, FIG. 9 shows an embodiment in which the control device of the power converter according to the present invention is applied to the resonance DC link type PWM inverter device shown in FIG. The inverter device according to the embodiment shown in FIG. 9 includes a current detector (43) for detecting U-phase, V-phase, and W-phase AC output currents I _LU , I _LV , and I _LW shown in FIG. A correction signal which is provided on each of the output lines of the phase and W phases and outputs a correction signal S which becomes "+1" when the sign of the detection signal I of the current detector (43) is positive and "-1" when the sign is negative. generator (38), a saw-tooth carrier h and the correction signal generator (38) of the correction signal S a multiplier for outputting the corrected carrier wave h ₁ representing the product of (39) and the phase of the carrier generator (9) Figure 2 for each
It is characterized in that it is provided in the control circuit (7) shown in FIG. Also,
The comparator (1) provided for each phase of the control circuit (7) shown in FIG.
0) is the U, V, W phase reference voltage V _UR , V _VR , V _WR level of the U, V, W phase reference voltage generators (26), (27), (28) and the multiplication of each phase. The voltage levels of the corrected carriers h _U1 , h _V1 and h _W1 of the detector (39) are compared with each other.
It outputs corrected PWM signals U _U1 , U _V1 and U _W1 of the V and W phases. The commutation control circuit (37) synchronizes with the reset timing of the sawtooth carrier wave h of the carrier wave generator (9) in synchronization with the resonance commutation circuit (1).
The on / off control of each IGBT (31), (32), (33) for commutation in 7) is performed. Other circuit configurations are substantially the same as those of the conventional resonant DC link type PWM inverter device shown in FIG.

In the configuration shown in FIG. 9, the power is supplied to the load (6).
AC output of U-phase, V-phase and W-phase shown in FIG.
Current I_LU, I_LV, I_LWIs detected by the current detector (43).
And the detection signal I_U, I_V, I_WWhen the sign of
FIG. 10 (H), which is “+1” and “−1” when negative.
U-phase, V-phase and W-phase correction signals S shown in (I) and (J)._U,
S_V, S _WAre output from the correction signal generator (38) for each phase.
10 (H), (I), and (J) show the correction signal generators (3
8) Correction signal S_U, S_V, S_WIs input to the multiplier (39) of each phase.
And the product signal with the sawtooth carrier h of the carrier generator (9) is formed.
Is done. The product signal output from the multiplier (39) of each phase is
As shown in FIGS. 10A, 10B, and 10C, the sawtooth carrier h
Phase AC output current I_LU, I_LV, I_LWVs. frequency
U-phase, V-phase, and W-phase corrected carriers corrected to nominal waves
h_U1, H_V1, H_W1Becomes Correction transfer of U-phase, V-phase and W-phase
Transmission h_U1, H_V1, H_W1Voltage level of each phase comparator (1
0), the U, V and W phase bases shown in FIGS. 10 (A), (B) and (C).
Reference voltage V of reference voltage generators (26), (27), (28)_UR, V_VR,
V_WR10D, and the comparison output is shown in FIG.
(E), (F), U, V, W phase AC output current I
_LU, I_LV, I_LWCorrected to a symmetric wave with respect to the frequency of
U, V, W phase corrected PWM signal U_U1, U_V1, U_W1As
It is output via the code detector (11) of each phase. U, V, W
Phase corrected PWM signal U_U1, U_V1, U_W1Is the inversion of each phase
Unit (12), dead time forming units (13) (14) and gate dry
The first through sixth control pulse signals V
_G1~ V_G6IGBTs for power conversion (2) (3),
Output to the gate terminals of (18), (19), (20) and (21). First to first
Sixth control pulse signal V_G1~ V_G63 power conversion
Replacement IGBT (2) (3), (18) (19), (20) (21) on / off
IGBTs for power conversion (2), (3), (18), (1
9), (20), and (21)
The switching current I as shown in FIGS._T1,
I_T2, I_T3, I_T4, I_T5, I_T6Flows. FIG.
As shown in (A) to (F), each power conversion IGBT (2),
Switching current flowing through (3), (18), (19), (20), and (21)
Style I_T1, I_T2, I_T3, I_T4, I_T5, I_T6Is positive
Turn-off timing is the sawtooth transfer of the carrier generator (9)
Reset timing t of transmission h₀~ T₁₈Sync to.
Timing of reset of sawtooth carrier h of carrier generator (9)
Good₀~ T₁₈For each commutation of the resonant commutation circuit (17)
IGBTs (31), (32) and (33) are turned off by the commutation control circuit (37).
On and off, and the DC voltage across the resonance capacitor (29)
Link voltage V_DLBecomes approximately 0 V as shown in FIG.
You. The operation of the resonant commutation circuit (17) is as shown in FIG.
The description is omitted because it is substantially the same as. Therefore, each
Turn of IGBT (2) (3), (18) (19), (20) (21) for force conversion
When turned off, the resonant commutation circuit (17) operates to convert each power conversion
Collectors of IGBTs (2) (3), (18) (19), (20) (21)
Since the voltage between the transmitter terminals is approximately 0V,
When the IGBTs (2) (3), (18) (19), (20) (21) turn off
Zero voltage switching (ZVS).

In the embodiment shown in FIG. 9, the load (6) is
U, V, W phase AC output current I_LU, I_LV, I_LW
U, V, W phase corrected PWM signals
No. U _U1, U_V1, U_W1Is a symmetrical wave,
U-, V-, and W-phase corrected PWM signals in substantially the same manner as in the embodiment.
U_U1, U_V1, U_W1Contains even-order lower harmonic components.
Absent. As a result, the three-phase AC output supplied to the load (6)
Waveform is corrected to be positive / negative symmetric,
The three-phase AC output with low distortion can be supplied to the load (6).
it can. Also, only once for one cycle of the sawtooth carrier wave h
IGBT (2) for each power conversion by the operation of the resonant commutation circuit (17)
(3), (18) (19), (20) (21)
Therefore, as shown in FIG. 22, one cycle of the sawtooth carrier wave h
On the other hand, the number of times corresponding to the number of phases, that is, up to four times, the resonance commutation circuit
Operation of the resonant commutation circuit (17) compared to when (17) operates
The number of times can be reduced. Therefore, as shown in FIG.
Power loss in the resonant commutation circuit (17)
be able to. Also, the number of operations of the resonant commutation circuit (17) is small.
Therefore, as shown in the inverter device shown in FIG.
The operation timing of the flow circuit (17) does not overlap. But
Therefore, each IGBT for power conversion (2) (3), (18) (19), (20) (2
There is almost no period during which 1) cannot be switched,
The restriction on the timing can be reduced. Note that FIG. 9 shows
In the embodiment, the resonance commutation circuit (17) shown in FIG. 22 is used.
Inverter device is shown, but other types of resonance
It is possible to obtain substantially the same effect by using a flow circuit.
You.

The inverter device according to the embodiment shown in FIG. 12 is different from the inverter device shown in FIG. 9 in that each of the IGBTs (2), (3), (18), (19), (20), and (21) for power conversion. Collector
Snubber capacitors (44) (45), (46) (4
7), (48) and (49) are connected, and an inverter (12) is connected between a correction signal generator (38) and a multiplier (39) provided for each phase. Other circuit configurations are substantially the same as those of the inverter device shown in FIG.

In the configuration shown in FIG.
The AC output of the U-phase, V-phase and W-phase shown in FIG.
Force current I_LU, I_LV, I_LWIs detected by the current detector (43).
And the detection signal I_U, I_V, I_WWhen the sign of
FIG. 13 (H), which becomes “+1” and “−1” when negative.
U-phase, V-phase and W-phase correction signals S shown in (I) and (J)._U,
S_V, S_WAre output from the correction signal generator (38) for each phase.
13 (H), (I) and (J) show the correction signal generators (3
8) Correction signal S_U, S_V, S_WMultiplies through the inverter (12)
And the sawtooth carrier h of the carrier generator (9).
Is formed. Output from the multiplier (39) for each phase.
The product signal is a sawtooth as shown in FIGS. 13 (A), (B) and (C).
The carrier h is converted to the AC output current I of each phase._LU, I_LV, I_LWFrequency
Complementation of U-phase, V-phase and W-phase corrected to symmetrical waves with respect to numbers
Positive carrier h_U1, H_V1, H_W1Becomes U phase, V phase and W phase
Corrected carrier h_U1, H_V1, H_W1Voltage level of each phase
13 (A), (B) and (C) shown in FIG.
V, W phase reference voltage generator (26), (27), (28) reference voltage V
_UR, V_VR, V_WRIs compared with the level of
13 (D), (E), (F), U, V, W phase alternating current
Output current I_LU, I_LV, I_LWComplementary to a symmetrical wave
Corrected U, V, W phase corrected PWM signal U_U1, U_V1, U
_W1Is output via the code detector (11) of each phase.
U, V, W phase corrected PWM signal U_U1, U_V1, U_W1Is each
Inverters (12), dead time formers (13) (14), and
The first to sixth control packets are controlled by the port drive circuits (15) and (16).
Loose signal V_G1~ V _G6IGB for each power conversion as
Output to the gate terminals of T (2) (3), (18) (19), (20) (21)
You. First to sixth control pulse signals V_G1~ V_G6Thereby 3
The pair of power conversion IGBTs (2) (3), (18) (19), (20) (21)
Driven on / off, each power conversion IGBT (2), (3),
(18), (19), (20), (21)
Switching voltages as shown in FIGS.
Style I_T1, I_T2, I_T3, I_T4, I_T5, I_T6Flows. Ma
As shown in FIGS. 14A to 14F, each power conversion IG
BT (2), (3), (18), (19), (20), (21)
Ching current I_T1, I_T2, I_T3, I_T4, I_T5, I_T6Is square
Turn-on timing when the carrier wave generator (9)
Reset timing t of sawtooth carrier wave h₀~ T₁₈Same as
Expect Reset of sawtooth carrier wave h of carrier generator (9)
Timing t₀~ T₁₈In synchronization with the resonance commutation circuit (17).
Each IGBT for commutation (31), (32), (33) is a commutation control circuit (37)
ON / OFF control by the resonance capacitor (29)
End DC link voltage V_DLIs substantially zero as shown in FIG.
V. The operation of the resonant commutation circuit (17) is described in FIG.
The description is omitted because it is almost the same as in the case of FIG. Accordingly
IGBTs for power conversion (2) (3), (18) (19), (20) (21)
When the device is turned on, the resonant commutation circuit (17)
IGBT for power conversion (2) (3), (18) (19), (20) (21)
Since the voltage between the emitter and emitter terminals is approximately 0 V,
Turn of IGBT (2) (3), (18) (19), (20) (21) for force conversion
Zero voltage switching (ZVS) at ON
You. In addition, each power conversion IGBT (2) (3), (18) (19), (2
When turning off (0) and (21), the snubber capacitors (44) and (4)
5), (46) (47), (48) (49) act as snubbers and
Collector of IGBT (2) (3), (18) (19), (20) (21) for conversion
-The voltage between the emitter terminals gradually rises from approximately 0V
Therefore, each IGBT for power conversion (2) (3), (18) (19), (20) (2
Zero voltage switching occurs even at turn-off in 1).
You.

In the embodiment shown in FIG. 12, the U, V, and W phase AC output currents I _LU , I _LV , I
Correction PWM of U, V, W phases in synchronization with switching of _LW direction
Since the signals U _U1 , U _V1 and U _W1 become symmetrical waves and the corrected PWM signals U _U1 , U _V1 and U _W1 of the U, V and W phases do not include even-order low-order harmonic components, the load ( The waveform of the three-phase AC output supplied to 6) is corrected to be positive / negative symmetric. Therefore, similarly to the embodiment shown in FIG. 9, a three-phase AC output with less waveform distortion due to lower harmonics can be supplied to the load (6). Further, since the resonance commutation circuit (17) operates only once for one cycle of the sawtooth carrier wave h, the number of operations of the resonance commutation circuit (17) can be reduced as in the embodiment shown in FIG. Power loss in the resonant commutation circuit (17) can be reduced. Further, since the number of times of operation of the resonant commutation circuit (17) is small, the limitation on the switching timing can be reduced similarly to the embodiment shown in FIG. Furthermore, each power conversion IGBT (2) (3),
(18) Since all the switching operations of (19), (20), and (21) perform zero voltage switching, the surge voltage, surge current, and switching loss are lower than those of the inverter device of the embodiment shown in FIG. There is an advantage that it can be further reduced.

The inverter device of the embodiment shown in FIG. 15 is different from the control circuit (7) shown in FIG. 5 in place of the dead time generators (13) and (14) and the gate drive circuits (15) and (16). A gate switching means (50) for suspending the switching operation of one of the pair of power conversion IGBTs (2) and (3) in accordance with the correction signal S of the correction signal generator (38). The gate switching means (50) includes a code detector (11) and a power conversion I
A gate drive circuit (51) connected between the gate terminal of the GBT (2) and the correction signal generator (38);
8) an inverter (12) connected to the code detector (11) and the gate terminal and inverter of the other power conversion IGBT (3);
(12) Another gate drive circuit (52) connected between
It is composed of When the correction signal S of the correction signal generator (38) is "+1", the gate drive circuit (51) uses the PWM signal U input from the code detector (11) as a first control pulse signal _VG1 to generate power. The correction signal S is given to the gate terminal of the conversion IGBT (2).
A low (L) level constant off signal is applied to the gate terminal of BT (2). When the correction signal S of the correction signal generator (38) is "-1", the other gate drive circuit (52) outputs the inverted PWM input from the code detector (11) via the inverter (12).
The signal -U imparted to the gate terminal of the other power conversion IGBT as a second control pulse signal V _G2 (3), the other power conversion IGBT when the correction signal S is "+1"
A low (L) level constant off signal is applied to the gate terminal of (3). Other circuit configurations are substantially the same as those of the inverter device of the embodiment shown in FIG.

[0046] In the configuration shown in FIG. 15, the load current I _L of the AC output flowing through (6) is detected by a current detector (43), "+1" when the sign of the detection signal I is positive, negative The correction signal S which is sometimes "-1" is output from the correction signal generator (38).
Output from When the correction signal S of the correction signal generator (38) is "+1", the first control pulse signal is supplied from the gate drive circuit (51) of the gate switching means (50) to the gate terminal of the power conversion IGBT (2). While _VG1 is output, the other gate drive circuit (52) outputs a constant low (L) level off signal to the gate terminal of the other power conversion IGBT (3). Thus, when the current I _L of the AC output flowing through the load (6) is a positive half cycle, power conversion IGB
The switching operation of T (2) is performed, and the other power conversion IGBT (3) is held in the off state. When the correction signal S of the correction signal generator (38) is "-1", a low (L) signal is sent from the gate drive circuit (51) of the gate switching means (50) to the gate terminal of the power conversion IGBT (2). ) with the level constant oFF signal is output, the second control pulse signal V _G2 is output to the gate terminal of the other power conversion IGBT from the other of the gate drive circuit (52) (3). Thus, when the load (6) of the AC output flowing through the current I _L is a negative half cycle, the other power conversion IGBT (3) together with the power conversion IGBT (2) is held in the OFF state Switching operation is performed.

[0047] In the embodiment shown in FIG. 15, who does not carry current of the load pair of power conversion IGBT according to the direction of the current I _L of the AC output supplied to (6) (2) (3) Is stopped by the gate switching means (50). Therefore, since the pair of power conversion IGBTs (2) and (3) do not perform switching operations at the same time, the dead time formers (13) and (14) can be omitted as compared with the embodiment shown in FIG. There is an advantage that the circuit configuration of the circuit (7) can be simplified.

Further, the invar of the embodiment shown in FIG.
The reference voltage V of the reference voltage generator (8)_RFrom the voltage
Voltage as voltage correction value calculation means for calculating correction value ΔV
A correction value calculation circuit (53) and a correction signal for the sawtooth carrier wave h
The reference voltage V during any period including when the value of S is switched_RAgainst
To add the voltage correction value ΔV of the voltage correction value calculation circuit (53).
Correction reference voltage V_R2And a correction reference voltage generating means for outputting
It is provided in the control circuit (7) of the inverter device shown in FIG.
You. The voltage correction value calculation circuit (53) is provided for the reference voltage generator (8).
Reference voltage V_RΔV = (1−V_R ^Two) / 8
The indicated voltage correction value ΔV is output. Correction reference voltage generation
The means includes first and second delay circuits (54) and (55);
And a second subtractor (56), (57) and a multiplier (58).
It is. The first delay circuit (54) is provided from the correction signal generator (38).
Output correction signal S₀For one period of the sawtooth carrier wave h
The correction signal S for the sawtooth carrier h is output
Power. The second delay circuit (55) is different from the first delay circuit (54).
The correction signal S output from the counter is further added for one cycle of the sawtooth carrier h.
Correction signal S delayed by the time₁Is output. First
The subtractor (56) corrects the correction output from the second delay circuit (55).
Signal S₁And the correction signal output from the correction signal generator (38)
S₀Difference signal S_TwoIs output. The multiplier (58) performs voltage correction
The voltage correction value ΔV of the value calculating circuit (53) and the voltage correction value ΔV of the first subtractor (56)
Difference signal S_TwoCorrection signal ΔV representing the product of₁Is output.
The second subtracter (57) is provided with a reference voltage V of the reference voltage generator (8)._R
And the voltage correction signal ΔV of the multiplier (58)₁Correction base that represents the difference from
Reference voltage V _R2Is output. The control circuit shown in FIG.
The comparator (10) of (7) is output from the second subtractor (57).
Correction reference voltage V_R2Level and output from multiplier (39)
Corrected carrier h₁And the sign detector (1
1) via the corrected PWM signal U₁Is output. Other structures
The configuration is substantially the same as that of the control circuit (7) shown in FIG.

[0049] In the configuration shown in FIG. 16, the correction signal S ₀ output from the correction signal generator (38) a first delay circuit (5
4) is delayed by one period of the sawtooth carrier h,
It is output as a correction signal S for the saw-tooth carrier h shown in FIG. The correction signal S of the first delay circuit (54) shown in FIG. 17 (B) is input to the multiplier (39) together with the sawtooth carrier h of the carrier generator (9), and the correction carrier S shown in FIG. h
₁ is formed. At the same time, the correction signal S of the first delay circuit (54) is input to the second delay circuit (55), further from the correction signal S correction delayed by one period of time of sawtooth carrier h signal S ₁ Is output. Second delay circuit (55) of the correction signals S ₁ the correction signal generator (38) of the correction signal S ₀ with the first
Is input to the subtractor (56), the difference signal S ₂ between the correction signals S ₁ and the correction signal S ₀ is outputted. Therefore, the first subtractor (56)
The difference signal S ₂ output from the sawtooth carrier wave h as the center voltage level of the switching of the correction signal S for sawtooth carrier wave h
Is a rectangular pulse signal having a pulse width of two periods. The difference signal S ₂ of the first subtractor (56) is input to a multiplier (58) together with the voltage correction value ^{_{ΔV = (1-V R 2}} ) / 8 of the voltage correction value calculating circuit (53), the voltage correction A signal ΔV ₁ is formed. The voltage correction signal ΔV ₁ of the multiplier (58) is a reference voltage generator
Is input with the reference voltage V _R (8) to a second subtractor (57),
The difference signal between the reference voltage V _R and the voltage correction signal ΔV ₁ is shown in FIG.
It is output as the correction reference voltage V _R2 shown in FIG. Level correction reference voltage V _R2 of the second subtracter (57) is compared with the voltage level of the correction carriers h ₁ of the multiplier (39) by the comparator (10), their comparison output code detector (11 17) via FIG.
Is output as the correction PWM signal U ₁ shown in (D). The subsequent operation is substantially the same as the operation of the control circuit (7) shown in FIG.

[0050] In the embodiment shown in FIG. 16, to correct the reference voltage V _R by adding the voltage correction value ΔV to the reference voltage V _R before and after the switching of the voltage level of the correction signal S for sawtooth carrier wave h it, the correction is carrier h ₁ of generated switching correction PWM signal spread of the pulse width of U ₁ is suppressed, the distortion of the AC output of the waveform supplied to the load (6) is corrected. Therefore, the distortion of the AC output of the waveform generated in the switching correction carrier h ₁ can be minimized. 17 and 18 show simulation waveforms with and without the correction of the reference voltage V _R, respectively. Figure If is If no correction is distorted waveform of FIG. 18 (E) and the voltage of the AC output to the switching correction carriers h _1, as shown in (F) V _O and the AC output current I _L, which was corrected 1
It is possible to suppress the distortion of the 7 (E) and the voltage of the AC output as shown in (F) V _O and AC output current I _L of the waveform.
In this embodiment, the voltage correction value ΔV is a function of the reference voltage V _R , but a similar effect can be obtained with a fixed value or another arithmetic expression.

The embodiments of the present invention are not limited to the above embodiments, and various changes can be made. For example, in each of the above-described embodiments, an embodiment in which an IGBT (insulated gate bipolar transistor) is used as a power conversion switching element and a commutation switching element has been described, but a MOS-FET (MOS field effect transistor), a junction A bipolar transistor, a J-FET (junction field effect transistor) or a thyristor can also be used. Further, in each of the above embodiments, the embodiment in which the present invention is applied to a single-phase or three-phase inverter device has been described. However, the present invention is also applicable to a multi-phase inverter device having four or more phase outputs. Is possible. Furthermore, the present invention is not limited to an inverter device that converts DC power into AC power, but is also applicable to a converter device that converts AC power into DC power. In particular, when the present invention is applied to a power factor correction type converter device, the waveform of the AC input becomes a symmetrical wave, and the waveform distortion is improved, so that the AC input current can accurately follow the AC input voltage, and the input power The effect of improving the rate can be further improved.

[0052]

According to the present invention, since the distortion of the waveform of the AC output or AC input due to the lower harmonics can be reduced, a power converter with a low loss and a high power factor can be realized. In addition, when a resonance commutation circuit is provided, power loss in the resonance commutation circuit can be reduced and switching timing is less restricted, so that a highly efficient power conversion device can be realized.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing an embodiment in which a control device of a power conversion device according to the present invention is applied to a carrier comparison type inverter device.

FIG. 2 is a waveform chart showing signals and voltages of respective parts of the circuit shown in FIG.

FIG. 3 is an electric circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an electric circuit diagram showing a third embodiment of the present invention.

FIG. 5 is an electric circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a waveform chart showing signals, voltages, and currents of respective parts of the circuit shown in FIG.

FIG. 7 is an electric circuit diagram showing an embodiment in which the control device of the power converter according to the embodiment shown in FIG. 5 is applied to a three-phase inverter device.

FIG. 8 is an electric circuit diagram showing a fifth embodiment of the present invention.

9 is an electric circuit diagram showing an embodiment in which the present invention is applied to the resonant DC link type PWM inverter device shown in FIG.

FIG. 10 is a waveform chart showing signals, voltages, and currents of respective parts of the circuit shown in FIG. 9;

11 is a waveform chart showing a switching current of each IGBT for power conversion shown in FIG.

FIG. 12 is an electric circuit diagram showing a modified embodiment of the inverter device shown in FIG. 9;

FIG. 13 is a waveform chart showing signals, voltages, and currents of respective parts of the circuit shown in FIG.

FIG. 14 is a waveform chart showing a switching current of each IGBT for power conversion shown in FIG.

FIG. 15 is an electric circuit diagram showing a sixth embodiment of the present invention.

FIG. 16 is an electric circuit diagram showing a seventh embodiment of the present invention.

17 is a simulation waveform chart when the reference voltage of the circuit shown in FIG. 16 is corrected.

18 is a simulation waveform chart when the reference voltage of the circuit shown in FIG. 16 is not corrected.

FIG. 19 is an electric circuit diagram showing a conventional carrier comparison type inverter device.

20 is a waveform chart showing signals of respective parts of the circuit shown in FIG.

21 is an enlarged waveform diagram showing a control pulse signal of the circuit shown in FIG.

FIG. 22 is an electric circuit diagram showing a conventional resonant DC link type PWM inverter device.

23 is a waveform chart showing signals, voltages, and currents of respective parts of the circuit shown in FIG.

FIG. 24 is a waveform chart showing a switching current of each IGBT for power conversion shown in FIG.

[Explanation of symbols]

(1) DC power supply, (2), (3) IGBT for power conversion
(Switching element), (4), (5)
(6) ··· Load, (7) ··· Control circuit (control device), (8)
..Reference voltage generator (reference voltage generation means), (9)
Carrier generator (carrier generation means), (10) ··· comparator (comparison means), (11) ··· code detector, (12) · · · inverter, (13), (14) · · · dead time formation Vessel, (15), (1
6) ・ ・ Gate drive circuit, (17) ・ ・ Resonant commutation circuit,
(18), (19), (20), (21) IGBT for power conversion,
(22), (23), (24), (25) · · diode, (26) · · · U
Phase reference voltage generator, (27) V-phase reference voltage generator,
(28) W phase reference voltage generator, (29) Resonance capacitor, (30) Resonance reactor, (31), (32), (33)
..Commutation IGBT, (34), (35), (36) .. commutation diode, (37) .commutation control circuit, (38) .. compensation signal generator (compensation signal generation means), ( 39) ··· Multiplier (multiplication means), (40) ··· first multiplier (first multiplication means), (41) ···· second multiplier (second multiplication means),
(42) ··· Signal switch (signal switching means), (43) ·· Current detector (current detection means), (44), (45), (46), (47),
(48), (49) ······················································································································
3) ..voltage correction value calculation circuit (voltage correction value calculation means)
(54) ··· First delay circuit; (55) ···· Second delay circuit
(56) ··· First subtractor, (57) ··· Second subtractor, (5
8) Multiplier

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (10)

[Claims] 1. A control device for a power conversion device for converting power between DC-AC or AC-DC by controlling on / off of a plurality of switching elements by a control signal, wherein a reference voltage generating means for outputting a reference voltage is provided. A carrier generating means for outputting a sawtooth carrier having a frequency sufficiently higher than the frequency of an AC output or an AC input, and comparing the level of the reference voltage with the voltage level of the sawtooth carrier to turn on / off the plurality of switching elements. Comparing means for outputting a PWM signal to be controlled, and correction signal generating means for outputting a correction signal that becomes a symmetrical wave with respect to the frequency of the AC output or AC input; The PWM is corrected by a corrected carrier or a corrected reference voltage.
A control device for a power converter, wherein a signal is corrected to a symmetric wave with respect to the frequency of the AC output or the AC input. 2. A multiplying means for outputting a corrected carrier representing a product of the sawtooth carrier and the correction signal, and comparing a level of a reference voltage of the reference voltage generating means with a voltage level of the corrected carrier of the multiplying means. 2. The control device for a power conversion device according to claim 1, further comprising a comparison unit that outputs a corrected PWM signal. 3. A first multiplying means for outputting a correction reference voltage representing a product of the reference voltage and the correction signal, and comparing a level of the correction reference voltage with a voltage level of the sawtooth carrier to generate a PWM signal. 2. The control device for the power conversion device according to claim 1, further comprising: a comparison unit that outputs a PWM signal; and a second multiplication unit that outputs a corrected PWM signal representing a product of the PWM signal and the correction signal. 4. A multiplying means for outputting a correction reference voltage representing a product of the reference voltage and the correction signal, and outputting a PWM signal by comparing a level of the correction reference voltage with a voltage level of the sawtooth carrier. A comparing means, a driving signal generating means for generating a signal for turning on and off the plurality of switching elements from the PWM signal, and a signal switching means for replacing an output signal of the driving signal generating means with the value of the correction signal. The control device for a power conversion device according to claim 1, further comprising: 5. The apparatus according to claim 1, further comprising current detection means for detecting the AC output or AC input current, wherein the correction signal generation means generates the correction signal based on a direction of a current detected by the current detection means. ~ 4
The control device for a power conversion device according to any one of claims 1 to 4. 6. The correction signal generator according to claim 1, wherein the correction signal generator generates the correction signal based on a polarity of the reference voltage.
The control device for a power conversion device according to any one of claims 1 to 4. 7. A resonance commutation circuit is connected to a DC input side or a DC output side of the plurality of switching elements, and the resonance commutation circuit is driven and output synchronously when a sawtooth carrier of the carrier generation means is reset. The control device for a power conversion device according to claim 5, wherein the DC link voltage to be applied is set to approximately 0V. 8. The power converter according to claim 7, wherein a snubber capacitor is connected between both main terminals of the plurality of switching elements, and the sawtooth carrier of the carrier generating means is reset when the plurality of switching elements are turned on. Equipment control device. 9. A gate switching device comprising: current detection means for detecting the current of the AC output or AC input; and stopping a switching operation of any of the plurality of switching elements based on a direction of a detection current of the current detection means. The control device for a power conversion device according to any one of claims 1 to 8, further comprising means. 10. A voltage correction value calculating means for calculating a voltage correction value from a reference voltage of the reference voltage generating means, and a voltage correction means for calculating the voltage with respect to the reference voltage during an arbitrary period including a time when a voltage level of the correction signal is switched. 10. A correction reference voltage generating means for adding a correction value and outputting a correction reference voltage.
The control device for a power conversion device according to any one of claims 1 to 4.