WO2016171436A1 - Organic memory device and method for preparing same using high-temperature heat treatment - Google Patents

Organic memory device and method for preparing same using high-temperature heat treatment Download PDF

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WO2016171436A1
WO2016171436A1 PCT/KR2016/003977 KR2016003977W WO2016171436A1 WO 2016171436 A1 WO2016171436 A1 WO 2016171436A1 KR 2016003977 W KR2016003977 W KR 2016003977W WO 2016171436 A1 WO2016171436 A1 WO 2016171436A1
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organic
memory device
heat treatment
high temperature
insulating layer
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PCT/KR2016/003977
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Korean (ko)
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김영규
김화정
정재훈
서주역
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경북대학교산학협력단
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80Constructional details

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  • the present invention relates to an organic memory device using a high temperature heat treatment and a method of manufacturing the same, and more particularly, by forming a polymer memory insulating layer by heat treatment at a high temperature of 80 °C or more can exhibit excellent memory characteristics even at low voltage while ensuring thermal stability.
  • Organic memory device using high temperature heat treatment that uses sulfonic acid-based organic material as memory storage layer, which can improve stability of charge transport layer due to low acidity and high glass transition temperature. And a method for producing the same.
  • nonvolatile memory devices are mainly made of flash memory based on silicon materials.
  • conventional flash memories have a limited number of write / erase times, have a slow writing speed, are highly integrated, and are difficult to miniaturize.
  • researches on various types of next generation nonvolatile memory devices have been conducted.
  • an organic memory device As such an organic memory device, a technology of an organic memory device having an insulating layer made of polyvinyl alcohol (PVA) having a memory function and having a proper dielectric constant in Korean Patent Nos. 1190570 and Korean Patent No. 1234225 is disclosed. have.
  • PVA polyvinyl alcohol
  • the organic memory device includes a polymethyl methacrylate (PMMA), a polyvinyl phenol (PVP), and a polyvinyl alcohol (PVA) between the gate electrode layer and the source and drain electrode layers. It has a structure including a tunneling organic insulating layer consisting of at least one selected from the group consisting of.
  • PMMA polymethyl methacrylate
  • PVP polyvinyl phenol
  • PVA polyvinyl alcohol
  • the organic memory device having an insulating layer made of such a polyvinyl alcohol (PVA) material has an advantage of increasing charge mobility due to high dielectric constant, but has a disadvantage in that a lot of leakage current is generated. Due to the low glass transition temperature of the high temperature is difficult to drive and has the disadvantage that can be driven only at low temperatures.
  • PVA polyvinyl alcohol
  • the charge transport layer formed adjacent to the organic insulating layer in the organic memory device is generally a weak acid, it is also important to select an appropriate type of organic material to lower the acidity of the organic insulating layer itself. It is essential to securing.
  • the present invention has been made to solve the above problems, the object of the present invention is to heat treatment at a high temperature of 80 °C or more to form a polymer memory insulating layer to ensure thermal stability high temperature heat treatment that can exhibit excellent memory characteristics even at low voltage An organic memory device using and a method of manufacturing the same are provided.
  • Another object of the present invention is to improve the stability of the charge transport layer due to the low acidity and high glass transition temperature of the high temperature heat treatment applied to the organic storage material of sulfonic acid (sulfonic acid) series that can be heat treated at a high temperature up to 300 °C as a memory storage layer
  • sulfonic acid sulfonic acid
  • An organic memory device for achieving the above object, in an organic memory device comprising a gate electrode and a source and a drain electrode formed on a substrate, between the gate electrode and the source and drain electrode It is an organic memory device using a high temperature heat treatment, characterized in that the electrically polarizable polymer memory insulating layer formed of a heat-treated organic material exhibits hysteresis.
  • the organic material may be a sulfonic acid-based material, in particular, the organic material may be a compound represented by Chemical Formula 1 below, or may be a compound represented by Chemical Formula 2 below.
  • n is an integer of 2 or more.
  • n is an integer of 2 or more.
  • An organic memory device a substrate; A gate electrode formed on the substrate; An electrically polarizable polymer memory insulating layer formed on the gate electrode and exhibiting hysteresis made of a heat-treated organic material; A charge transport layer formed on the polymer memory insulating layer; And source and drain electrodes formed on the charge transport layer to be spaced apart from each other by a predetermined distance.
  • the polymer memory insulating layer is characterized in that the heat treatment is performed for 0.4 ⁇ 0.6 hours at a temperature of 80 ⁇ 230 °C after spin coating the solution of the organic material, the organic material is sulfonic acid (sulfonic acid) It may be a substance, in particular, a compound represented by Chemical Formula 1 or a compound represented by Chemical Formula 2 above.
  • the charge transport layer is characterized in that the hole transport layer.
  • a method of manufacturing an organic memory device includes forming a gate electrode on a substrate; Forming an electrically polarizable polymer memory insulating layer formed on the gate electrode and made of an organic material to exhibit hysteresis; Heat treating the polymer memory insulation layer; Forming a charge transport layer on the polymer memory insulating layer; The method may include forming a source electrode and a drain electrode spaced apart from each other by a predetermined distance on the charge transport layer.
  • the forming of the polymer memory insulating layer may include spin coating a solution of a sulfonic acid-based organic material to form a polymer memory insulating layer having a thickness of 300 to 800 nm.
  • the formed polymer memory insulation layer may be heat treated at a temperature of 80 ° C. to 230 ° C. for 0.4 to 0.6 hours on a hot plate.
  • the organic material may be a compound represented by Chemical Formula 1 or a compound represented by Chemical Formula 2, and a hole transport layer may be formed as the charge transport layer.
  • the low acidity improves the stability of the charge transport layer and the glass transition temperature is so high that the sulfonic acid-based organic material, which can be heat-treated even at high temperatures up to 300 ° C, is applied to the memory storage layer for durability and safety. Can increase.
  • FIG. 1 is a cross-sectional view of an organic memory device according to an exemplary embodiment of the present invention.
  • FIG. 2 is a cross-sectional view illustrating an operating principle of an organic memory device according to an exemplary embodiment of the present invention.
  • FIG. 3 is a graph illustrating retention test results of a sulfonic acid based organic memory device according to an exemplary embodiment of the present invention.
  • FIG. 4 is a gate voltage graph of an organic memory device using a high temperature heat treatment according to an exemplary embodiment of the present invention.
  • FIG. 5 is a graph of hysteresis characteristics of an organic memory device subjected to 170 ° C. heat treatment according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a method of manufacturing an organic memory device using high temperature heat treatment according to an embodiment of the present invention.
  • 7A to 7D are cross-sectional views sequentially illustrating a method of manufacturing an organic memory device using high temperature heat treatment according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of an organic memory device according to an exemplary embodiment of the present invention
  • FIG. 2 is a cross-sectional view illustrating an operating principle of an organic memory device according to an exemplary embodiment of the present invention.
  • the organic memory device using the high temperature heat treatment according to the present invention may include a substrate 100, a gate electrode 110 formed on the substrate, and a polymer memory insulating layer 120 formed on the gate electrode 110. ), The charge transport layer 130, the source electrode 140, and the drain electrode 150.
  • the present invention utilizes the fact that the insulating layer 130 located between the gate electrode 110 and the charge transport layer 130 can function as a memory when the insulating layer 130 is made of an electrically polarizable organic material exhibiting hysteresis.
  • the memory device using the hysteresis characteristic stores each quadrant of the hysteresis curve using a hysteresis curve having a different current change curve when the voltage is increased and a current change curve when the voltage is decreased (00,01,10,11). ) Is a technology used for.
  • the substrate 100 may be a silicon substrate, a glass substrate, a plastic substrate, or the like.
  • the gate electrode 110 may be formed of a conductive material such as gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, or a polymer.
  • the polymer memory insulating layer 120 is made of an organic material and is in a heat-treated state. After spin coating the organic material solution, the polymer memory insulating layer 120 is preferably heat-treated at a temperature of 80 to 230 ° C. for 0.4 to 0.6 hours. Particularly, according to the experiment of the applicant, when the heat treatment was performed at about 170 ° C., the most excellent thermal stability and memory characteristics were obtained. This will be described in detail with reference to FIG. 5.
  • the organic material may be a sulfonic acid-based material that does not damage the material even at high temperature heat treatment, and among the sulfonic acid-based materials, a compound represented by the following Chemical Formula 1 or a compound represented by the following Chemical Formula 2 may be used. It is preferable to use.
  • n is an integer of 2 or more.
  • the two sulfonic acid-based organic materials have a glass transition temperature of about 300 ° C., so that when the polymer memory insulating layer 120 is formed and heat-treated with these materials, heat treatment is possible up to 300 ° C.
  • Applicants' experiment according to this was found to be most preferable to heat treatment for 0.4 ⁇ 0.6 hours at a temperature of 80 ⁇ 230 °C.
  • the charge transport layer 130 is formed on the polymer memory insulating layer 120, and may be formed as a hole transport layer to increase charge transport efficiency.
  • the charge transport layer 130 may be formed of poly (3-hexylthiophene) (P3HT). have.
  • the charge transport layer 130 is generally an acid weak material, it is important to appropriately select a type of organic material so as to lower the acidity of the adjacent polymer memory insulating layer 120, which is represented by Chemical Formulas 1 and 2 above.
  • the sulfonic acid-based organic material is a material having a pH of about 1.5 or more, and in this respect, it can be seen that it is a suitable material for the organic memory device.
  • the source electrode 140 and the drain electrode 150 are formed to be spaced apart from each other on the charge transport layer 130 by a predetermined distance, and include gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, and polymers. It may be formed of a conductive material such as.
  • the polymer memory insulating layer 120 is electrically polarized to generate a hysteresis phenomenon, thereby causing a charge transport layer. Hole hysteresis is also induced at 130.
  • the hysteresis characteristic is generated in the hole movement of the charge transport layer 130 as described above, the charge mobility from the source electrode 140 to the drain electrode 150 is increased, so that the drain current has the hysteresis characteristic. It will be able to function as a volatile memory.
  • FIG. 3 is a graph illustrating retention test results of a sulfonic acid based organic memory device according to an exemplary embodiment of the present invention.
  • the organic memory device using the high temperature heat treatment according to the exemplary embodiment of the present invention shows stable results even after retention tests of about 10,000 times.
  • the charge transport layer formed on the polymer memory insulating layer is generally weak in acidity, it is important to lower the acidity of the adjacent polymer memory insulating layer.
  • the organic material of sulfonic acid type represented by Chemical Formulas 1 and 2 is used. As a result, a test was conducted on an organic memory device in which a polymer memory insulating layer was formed, thereby achieving the purpose.
  • the graph shows that the current value is kept uniform over time, especially because it is stable in each of the write-read (read1, read2) -erase items of each memory device. You can expect quality memory features.
  • FIG. 4 is a gate voltage graph of an organic memory device using a high temperature heat treatment according to an embodiment of the present invention
  • FIG. 5 is a graph of hysteresis characteristics of an organic memory device subjected to 170 ° C. heat treatment according to an embodiment of the present invention.
  • the organic memory device using the high temperature heat treatment according to the embodiment of the present invention shows high thermal stability after heat treatment at high temperature.
  • the smooth operation of the organic transistor device is performed, and it is shown that it is operated without problems even at a low voltage.
  • FIG. 5 a graph of hysteresis characteristics of an organic memory device heat-treated at 170 ° C. according to the applicant's experiment can be seen.
  • the heat-treated polymer memory insulating layer is electrically polarized to generate a hysteresis phenomenon.
  • a hole hysteresis phenomenon is induced in the charge transport layer, and the charge mobility from the source electrode to the drain electrode is increased, so that the drain current has hysteresis characteristics, thereby enabling a nonvolatile memory function having a transistor structure.
  • the hysteresis characteristic of the drain current is clearly indicated, it means that the voltage difference due to hysteresis is large. Therefore, when the 170 ° C. heat-treated polymer memory insulating layer having the large voltage difference due to hysteresis is used, the threshold voltage difference of the memory device increases. Therefore, driving at low voltage becomes possible.
  • FIGS. 7A to 7D are process cross-sectional views sequentially illustrating a method of manufacturing an organic memory device using a high temperature heat treatment according to an embodiment of the present invention. to be.
  • the method of manufacturing an organic memory device using a high temperature heat treatment includes forming a gate electrode on a substrate (S10), and formed on the gate electrode and made of an organic material. Forming an electrically polarizable polymer memory insulation layer exhibiting hysteresis (S20), heat treating the polymer memory insulation layer (S30), forming a charge transport layer on the polymer memory insulation layer (S40) and on the hole transport layer Forming a source electrode and a drain electrode spaced apart from each other by a predetermined distance (S50).
  • the gate electrode 110 is formed on the substrate 100 as shown in FIG. 7A.
  • the gate electrode 110 is formed by thermal evaporation of a conductive material and then patterned.
  • the conductive material may include, for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, Polymers and the like can be used.
  • the polymer memory insulating layer 120 is formed to have a thickness of 300 to 800 nm on the substrate 100 on which the gate electrode 110 is formed as shown in FIG. 7B.
  • the polymer memory insulating layer 120 is formed of an electrically polarizable material that exhibits hysteresis.
  • a sulfonic acid-based organic material solution is used. Specifically, it is preferable to use the compound represented by the following general formula (1) or the compound represented by the following general formula (2) among sulfonic acid series materials.
  • n is an integer of 2 or more.
  • the coating of the organic material solution may be carried out by a spin coating method, and in the step (S30) of heat treating the polymer memory insulating layer after the coating is completed, the polymer memory insulating layer formed is 0.4 at a temperature of 80 ° C. to 230 ° C. on a hot plate. Heat treatment for ⁇ 0.6 hours.
  • the charge transport layer 130 is formed on the polymer memory insulation layer 120, but the hole transport layer P3HT is used to increase the charge transport efficiency. (poly (3-hexylthiophene)) is coated using a spin coating method or the like.
  • the charge transport layer 130 may include a polymer active layer as an organic semiconductor layer.
  • conductive materials on the charge transport layer 130 are illustrated as gold (Au), silver (Ag), copper (Cu), and nickel (Ni) as shown in FIG. 7D.
  • a source electrode 140 and a drain electrode 150 spaced by a predetermined distance are formed through a patterning process.

Abstract

The present invention relates to an organic memory device and a method for preparing same using high-temperature heat treatment and, more specifically, to an organic memory device which enables obtaining of thermal stability as well as excellent memory properties even at a low voltage by means of forming a polymer memory insulating layer by means of heat treatment at a high temperature of 80°C or higher. And the present invention enables enhanced stability of a charge transport layer due to low acidity and has applied, to a memory storage layer, a sulfonic acid-based organic material of which the glass transition temperature is very high and thus can be heat treated at a high temperature up to 300°C. In order to attain the purpose, an organic memory device in a transistor that comprises source and drain electrodes and a gate electrode formed on a substrate, according to an embodiment of the present invention, has formed thereon an electrically polarizable polymer memory insulating layer that is formed from a heat treated organic material between the gate electrode and the source and drain electrodes and shows hysteresis.

Description

고온 열처리를 이용한 유기 메모리 소자 및 그 제조 방법Organic memory device using high temperature heat treatment and manufacturing method thereof
본 발명은 고온 열처리를 이용한 유기 메모리 소자 및 그 제조 방법에 관한 것으로서, 보다 상세하게는 80℃ 이상의 고온에서 열처리하여 고분자 메모리 절연층을 형성시킴으로써 열적 안정성을 확보하면서도 저전압에서도 우수한 메모리 특성을 보일 수 있으며, 산성도가 적어 전하 수송층의 안정성을 높일 수 있고 유리전이온도가 매우 높아 300℃까지의 고온에서도 열처리가 가능한 술폰산(sulfonic acid) 계열의 유기물질을 메모리 저장층으로 적용시킨 고온 열처리를 이용한 유기 메모리 소자 및 그 제조 방법에 관한 것이다.The present invention relates to an organic memory device using a high temperature heat treatment and a method of manufacturing the same, and more particularly, by forming a polymer memory insulating layer by heat treatment at a high temperature of 80 ℃ or more can exhibit excellent memory characteristics even at low voltage while ensuring thermal stability. Organic memory device using high temperature heat treatment that uses sulfonic acid-based organic material as memory storage layer, which can improve stability of charge transport layer due to low acidity and high glass transition temperature. And a method for producing the same.
정보통신 산업과 휴대용 정보 기기의 비약적인 발전에 따라 대용량 비휘발성 메모리 소자에 대한 요구가 증가하고 있다. 현재 이러한 비휘발성 메모리 소자는 실리콘 재료에 기반을 둔 플래시 메모리 (flash memory)가 주류를 이루고 있으나, 기존의 플래시 메모리는 기록/소거 횟수가 제한되고, 기록 속도가 느리며, 고집적, 소형화가 곤란한 등의 기술적 한계가 드러남에 따라서 다양한 형태의 차세대 비 휘발성 메모리 소자에 대한 연구가 진행되고 있다.With the rapid development of the information and communication industry and portable information devices, the demand for large capacity nonvolatile memory devices is increasing. Currently, such nonvolatile memory devices are mainly made of flash memory based on silicon materials. However, conventional flash memories have a limited number of write / erase times, have a slow writing speed, are highly integrated, and are difficult to miniaturize. As the technical limitations are revealed, researches on various types of next generation nonvolatile memory devices have been conducted.
일례로 메모리 소자의 메모리층 재료로 유기물을 사용하여, 기존의 실리콘 메모리 소자의 물리적인 한계를 극복하고, 초고속, 고용량, 저소비전력, 저가격 특성을 갖는 차세대 비휘발성 메모리 소자를 구현하기 위한 기술의 개발이 활발하게 진행되고 있다.For example, by using organic materials as a memory layer material of memory devices, technology for overcoming physical limitations of existing silicon memory devices and for implementing next-generation nonvolatile memory devices having ultra-high speed, high capacity, low power consumption, and low cost characteristics This is actively going on.
이러한 유기 메모리 소자로서 한국등록특허 1190570호 및 한국등록특허 1234225호에 적당한 유전율을 가지면서 메모리 기능을 갖는 폴리비닐알코올(polyvinyl alcohol; PVA)로 이루어지는 절연층을 갖는 유기 메모리 소자에 대한 기술이 개시되어 있다.As such an organic memory device, a technology of an organic memory device having an insulating layer made of polyvinyl alcohol (PVA) having a memory function and having a proper dielectric constant in Korean Patent Nos. 1190570 and Korean Patent No. 1234225 is disclosed. have.
상기 선행문헌에 따르면 유기 메모리 소자는 게이트 전극층과 소스 및 드레인 전극 층 사이에 폴리메틸메타크릴레이트(polymethyl methacrylate; PMMA), 폴리비닐페놀(polyvinyl phenol; PVP) 및 폴리비닐알코올(polyvinyl alcohol; PVA)로 이루어진 군에서 선택된 적어도 하나로 이루어진 터널링 유기 절연층을 포함하는 구조를 갖는다.According to the preceding document, the organic memory device includes a polymethyl methacrylate (PMMA), a polyvinyl phenol (PVP), and a polyvinyl alcohol (PVA) between the gate electrode layer and the source and drain electrode layers. It has a structure including a tunneling organic insulating layer consisting of at least one selected from the group consisting of.
이러한 폴리비닐알코올(polyvinyl alcohol; PVA) 류의 물질로 이루어지는 절연층을 갖는 유기 메모리 소자의 경우 유전율이 높아 전하 이동도가 높아지는 장점이 있지만 그만큼 누설 전류를 많이 발생하게 되는 단점이 있으며, 80℃ 이하의 낮은 유리전이온도로 인하여 고온 구동이 어렵고 저온에서만 구동이 가능하다는 단점이 있다.The organic memory device having an insulating layer made of such a polyvinyl alcohol (PVA) material has an advantage of increasing charge mobility due to high dielectric constant, but has a disadvantage in that a lot of leakage current is generated. Due to the low glass transition temperature of the high temperature is difficult to drive and has the disadvantage that can be driven only at low temperatures.
그리고 초고집적화되어 가는 메모리 소자에 있어서 종래의 저온으로 열처리된 메모리 소자의 경우 발열 문제가 발생할 수 있다. 발열 현상은 소자의 변형 및 구동 능력 저하 등의 악영향을 미치게 되는 것으로, 이에 따라 메모리 소자의 열적 안정성을 확보할 수 있는 제조기술에 대한 필요성이 높아지고 있다.In the memory device, which is becoming highly integrated, a heat generation problem may occur in the case of a conventional low temperature heat treated memory device. The heat generation phenomenon adversely affects the deformation of the device and the deterioration of the driving ability. Accordingly, the necessity for a manufacturing technology capable of securing thermal stability of the memory device is increasing.
또한 유기 메모리 소자에서 유기 절연층과 인접하여 형성되는 전하 수송층이 일반적으로 산성에 약한 물질이기 때문에 유기 절연층 자체의 산도를 낮출 수 있도록 유기물질의 종류를 적절하게 선택하는 것도 유기 메모리 소자의 내구성을 확보하는 데에 필수적이라 할 수 있다.In addition, since the charge transport layer formed adjacent to the organic insulating layer in the organic memory device is generally a weak acid, it is also important to select an appropriate type of organic material to lower the acidity of the organic insulating layer itself. It is essential to securing.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 80℃ 이상의 고온에서 열처리하여 고분자 메모리 절연층을 형성시킴으로써 열적 안정성을 확보하면서도 저전압에서도 우수한 메모리 특성을 보일 수 있는 고온 열처리를 이용한 유기 메모리 소자 및 그 제조 방법을 제공함에 있다.The present invention has been made to solve the above problems, the object of the present invention is to heat treatment at a high temperature of 80 ℃ or more to form a polymer memory insulating layer to ensure thermal stability high temperature heat treatment that can exhibit excellent memory characteristics even at low voltage An organic memory device using and a method of manufacturing the same are provided.
본 발명의 다른 목적은 산성도가 적어 전하 수송층의 안정성을 높일 수 있고 유리전이온도가 매우 높아 300℃까지의 고온에서도 열처리가 가능한 술폰산(sulfonic acid) 계열의 유기물질을 메모리 저장층으로 적용시킨 고온 열처리를 이용한 유기 메모리 소자 및 그 제조 방법을 제공함에 있다.Another object of the present invention is to improve the stability of the charge transport layer due to the low acidity and high glass transition temperature of the high temperature heat treatment applied to the organic storage material of sulfonic acid (sulfonic acid) series that can be heat treated at a high temperature up to 300 ℃ as a memory storage layer An organic memory device using and a method of manufacturing the same are provided.
상기와 같은 목적을 달성하기 위한 본 발명의 일측면에 따른 유기 메모리 소자는, 기판 상에 형성된 게이트 전극과 소스 및 드레인 전극을 포함하는 유기 메모리 소자에 있어서, 상기 게이트 전극과 소스 및 드레인 전극 사이에 열처리된 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층이 형성된 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자이다.An organic memory device according to an aspect of the present invention for achieving the above object, in an organic memory device comprising a gate electrode and a source and a drain electrode formed on a substrate, between the gate electrode and the source and drain electrode It is an organic memory device using a high temperature heat treatment, characterized in that the electrically polarizable polymer memory insulating layer formed of a heat-treated organic material exhibits hysteresis.
그리고 상기 유기물질은 술폰산(sulfonic acid) 계열의 물질, 특히 상기 유기물질은 하기의 화학식 1로 표현되는 화합물일 수도 있으며, 하기의 화학식 2로 표현되는 화합물일 수도 있는 것이 특징이다.The organic material may be a sulfonic acid-based material, in particular, the organic material may be a compound represented by Chemical Formula 1 below, or may be a compound represented by Chemical Formula 2 below.
[화학식 1][Formula 1]
Figure PCTKR2016003977-appb-I000001
Figure PCTKR2016003977-appb-I000001
(상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
[화학식 2][Formula 2]
Figure PCTKR2016003977-appb-I000002
Figure PCTKR2016003977-appb-I000002
(상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
본 발명의 다른 측면에 따른 유기 메모리 소자는, 기판; 상기 기판 상에 형성된 게이트 전극; 상기 게이트 전극 상에 형성되며 열처리된 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층; 상기 고분자 메모리 절연층 상에 형성된 전하 수송층; 및 상기 전하 수송층 상에 일정 거리 이격되게 각각 형성된 소스 및 드레인 전극을 포함할 수 있다.An organic memory device according to another aspect of the present invention, a substrate; A gate electrode formed on the substrate; An electrically polarizable polymer memory insulating layer formed on the gate electrode and exhibiting hysteresis made of a heat-treated organic material; A charge transport layer formed on the polymer memory insulating layer; And source and drain electrodes formed on the charge transport layer to be spaced apart from each other by a predetermined distance.
여기에 상기 고분자 메모리 절연층은, 상기 유기물질의 용액을 스핀 코팅한 후 80 ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리가 이루어진 것을 특징으로 하고, 상기 유기물질은 술폰산(sulfonic acid) 계열의 물질, 특히 상기의 화학식 1로 표현되는 화합물 또는 상기의 화학식 2로 표현되는 화합물일 수 있다.Here, the polymer memory insulating layer is characterized in that the heat treatment is performed for 0.4 ~ 0.6 hours at a temperature of 80 ~ 230 ℃ after spin coating the solution of the organic material, the organic material is sulfonic acid (sulfonic acid) It may be a substance, in particular, a compound represented by Chemical Formula 1 or a compound represented by Chemical Formula 2 above.
또한 상기 전하 수송층은 정공 수송층인 것을 특징으로 한다.In addition, the charge transport layer is characterized in that the hole transport layer.
본 발명의 또 다른 측면에 따른 유기 메모리 소자의 제조 방법은, 기판 상에 게이트 전극을 형성하는 단계; 상기 게이트 전극 상에 형성되며 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층을 형성하는 단계; 상기 고분자 메모리 절연층을 열처리하는 단계; 상기 고분자 메모리 절연층 상에 전하 수송층을 형성하는 단계; 상기 전하 수송층 상에 일정 거리 이격되는 소스 전극과 드레인 전극을 형성하는 단계를 포함할 수 있다.In another aspect, a method of manufacturing an organic memory device includes forming a gate electrode on a substrate; Forming an electrically polarizable polymer memory insulating layer formed on the gate electrode and made of an organic material to exhibit hysteresis; Heat treating the polymer memory insulation layer; Forming a charge transport layer on the polymer memory insulating layer; The method may include forming a source electrode and a drain electrode spaced apart from each other by a predetermined distance on the charge transport layer.
여기서 상기 고분자 메모리 절연층을 형성하는 단계는, 술폰산(sulfonic acid) 계열의 유기물질 용액을 스핀 코팅하여 300 ~ 800nm 두께의 고분자 메모리 절연층을 형성할 수 있다. 그리고 상기 고분자 메모리 절연층을 열처리하는 단계는, 상기 형성된 고분자 메모리 절연층을 핫플레이트에서 80℃ ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리할 수 있다.The forming of the polymer memory insulating layer may include spin coating a solution of a sulfonic acid-based organic material to form a polymer memory insulating layer having a thickness of 300 to 800 nm. In the heat treatment of the polymer memory insulation layer, the formed polymer memory insulation layer may be heat treated at a temperature of 80 ° C. to 230 ° C. for 0.4 to 0.6 hours on a hot plate.
또한 상기 유기물질은 상기의 화학식 1로 표현되는 화합물 또는 상기의 화학식 2로 표현되는 화합물일 수 있으며, 상기 전하 수송층으로서 정공 수송층을 형성하는 것이 가능하다.The organic material may be a compound represented by Chemical Formula 1 or a compound represented by Chemical Formula 2, and a hole transport layer may be formed as the charge transport layer.
상기와 같은 본 발명에 따르면, 유기 메모리 소자를 80℃ 이상의 고온에서 열처리하여 고분자 메모리 절연층을 형성시킴으로써 열적 안정성을 확보할 수 있어 저전압에서도 우수한 쓰기-읽기-소거 기능을 보일 수 있는 고품질의 메모리 소자를 제조할 수 있는 효과가 있다.According to the present invention as described above, by heat-treating the organic memory device at a high temperature of 80 ℃ or more to form a polymer memory insulating layer to ensure thermal stability high quality memory device that can exhibit excellent write-read-erase function even at low voltage There is an effect that can be prepared.
그리고 산성도가 적어 전하 수송층의 안정성을 높일 수 있고 유리전이온도가 매우 높아 300℃까지의 고온에서도 열처리가 가능한 술폰산(sulfonic acid) 계열의 유기물질을 메모리 저장층으로 적용시킴으로써 유기 메모리 소자의 내구성 및 안전성을 높일 수 있다.The low acidity improves the stability of the charge transport layer and the glass transition temperature is so high that the sulfonic acid-based organic material, which can be heat-treated even at high temperatures up to 300 ° C, is applied to the memory storage layer for durability and safety. Can increase.
도 1은 본 발명의 실시예에 따른 유기 메모리 소자의 단면도이다. 1 is a cross-sectional view of an organic memory device according to an exemplary embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 유기 메모리 소자의 동작 원리를 나타낸 단면도이다.2 is a cross-sectional view illustrating an operating principle of an organic memory device according to an exemplary embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 술폰산 계열 유기 메모리 소자의 리텐션(retention) 테스트 결과 그래프이다.3 is a graph illustrating retention test results of a sulfonic acid based organic memory device according to an exemplary embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자의 게이트 전압 그래프이다.4 is a gate voltage graph of an organic memory device using a high temperature heat treatment according to an exemplary embodiment of the present invention.
도 5는 본 발명의 실시예에 따라 170℃ 열처리를 한 유기 메모리 소자의 히스테리시스 특성 그래프이다.5 is a graph of hysteresis characteristics of an organic memory device subjected to 170 ° C. heat treatment according to an embodiment of the present invention.
도 6은 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자 제조 방법의 순서도이다.6 is a flowchart of a method of manufacturing an organic memory device using high temperature heat treatment according to an embodiment of the present invention.
도 7a 내지 도 7d는 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자 제조 방법을 순차로 나타낸 공정 단면도이다.7A to 7D are cross-sectional views sequentially illustrating a method of manufacturing an organic memory device using high temperature heat treatment according to an embodiment of the present invention.
이하에서는 첨부된 도면을 참조하여 본 발명을 보다 상세하게 설명한다. 도면들 중 동일한 구성요소들은 가능한 한 어느 곳에서든지 동일한 부호로 나타내고 있음을 유의해야 한다. 한편, 이에 앞서 본 명세서 및 특허청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니 되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다. 따라서 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일 실시예에 불과할 뿐이고, 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. It should be noted that the same elements in the figures are denoted by the same reference signs wherever possible. On the other hand, the terms or words used in the present specification and claims are not to be construed as limiting the ordinary or dictionary meanings, the inventors should use the concept of the term in order to explain the invention in the best way. It should be interpreted as meanings and concepts corresponding to the technical idea of the present invention based on the principle that it can be properly defined. Therefore, the embodiments described in the present specification and the configuration shown in the drawings are only the most preferred embodiments of the present invention, and do not represent all of the technical ideas of the present invention, and various alternatives may be substituted at the time of the present application. It should be understood that there may be equivalents and variations.
도 1은 본 발명의 실시예에 따른 유기 메모리 소자의 단면도, 도 2는 본 발명의 실시예에 따른 유기 메모리 소자의 동작 원리를 나타낸 단면도이다.1 is a cross-sectional view of an organic memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating an operating principle of an organic memory device according to an exemplary embodiment of the present invention.
도 1 및 도 2를 참조하면, 본 발명의 고온 열처리를 이용한 유기 메모리 소자는 기판(100), 기판 상에 형성된 게이트 전극(110), 게이트 전극(110) 상에 형성되는 고분자 메모리 절연층(120), 전하 수송층(130), 소스 전극(140) 및 드레인 전극(150)을 포함하여 이루어진다. 1 and 2, the organic memory device using the high temperature heat treatment according to the present invention may include a substrate 100, a gate electrode 110 formed on the substrate, and a polymer memory insulating layer 120 formed on the gate electrode 110. ), The charge transport layer 130, the source electrode 140, and the drain electrode 150.
본 발명은 게이트 전극(110)과 전하 수송층(130) 사이에 위치하는 절연층(130)이 히스테리시스(hysteresis)를 나타내는 전기적으로 분극 가능한 유기물질로 이루어질 경우 메모리의 기능을 할 수 있다는 점을 이용하는 것으로서, 히스테리시스 특성을 이용한 메모리 소자는 전압을 증가시킬 때의 전류 변화 곡선과 전압을 감소시킬 때의 전류 변화 곡선이 상이한 히스테리시스 곡선을 이용하여 히스테리시스 곡선의 각 사분면을 저장 수단(00,01,10,11)으로 이용하는 기술이다.The present invention utilizes the fact that the insulating layer 130 located between the gate electrode 110 and the charge transport layer 130 can function as a memory when the insulating layer 130 is made of an electrically polarizable organic material exhibiting hysteresis. The memory device using the hysteresis characteristic stores each quadrant of the hysteresis curve using a hysteresis curve having a different current change curve when the voltage is increased and a current change curve when the voltage is decreased (00,01,10,11). ) Is a technology used for.
우선, 기판(100)은 실리콘(silicon) 기판, 유리 기판 또는 플라스틱(plastic) 기판 등이 이용될 수 있다.First, the substrate 100 may be a silicon substrate, a glass substrate, a plastic substrate, or the like.
게이트 전극(110)은 예시적으로, 금(Au), 은(Ag), 구리(Cu), 니켈(Ni)/알루미늄, 폴리머 등의 도전성 물질로 형성될 수 있다.For example, the gate electrode 110 may be formed of a conductive material such as gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, or a polymer.
고분자 메모리 절연층(120)은 유기물질로 이루어지고 열처리된 상태이며, 유기물질 용액을 스핀 코팅한 후 80 ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리하는 것이 바람직하다. 특히 출원인의 실험에 따르면 약 170℃의 열처리를 하였을 경우 가장 열적 안정성이 뛰어나고 메모리 특성도 우수한 결과를 얻을 수 있었는데, 이는 도 5에서 자세히 살펴보기로 한다.The polymer memory insulating layer 120 is made of an organic material and is in a heat-treated state. After spin coating the organic material solution, the polymer memory insulating layer 120 is preferably heat-treated at a temperature of 80 to 230 ° C. for 0.4 to 0.6 hours. Particularly, according to the experiment of the applicant, when the heat treatment was performed at about 170 ° C., the most excellent thermal stability and memory characteristics were obtained. This will be described in detail with reference to FIG. 5.
유기물질로는 고온의 열처리에도 소재가 손상되지 않는 술폰산(sulfonic acid) 계열의 물질을 이용할 수 있으며, 술폰산 계열의 물질 중에서도 특히 하기의 화학식 1로 표현되는 화합물 또는 하기의 화학식 2로 표현되는 화합물을 이용하는 것이 바람직하다.The organic material may be a sulfonic acid-based material that does not damage the material even at high temperature heat treatment, and among the sulfonic acid-based materials, a compound represented by the following Chemical Formula 1 or a compound represented by the following Chemical Formula 2 may be used. It is preferable to use.
[화학식 1][Formula 1]
Figure PCTKR2016003977-appb-I000003
Figure PCTKR2016003977-appb-I000003
[화학식 2][Formula 2]
Figure PCTKR2016003977-appb-I000004
Figure PCTKR2016003977-appb-I000004
(상기 식들에서, n은 2 이상의 정수이다.)(In the above formulas, n is an integer of 2 or more.)
상기의 두 술폰산 계열의 유기물질은 유리전이온도가 300℃ 가까이 되기 때문에 이 물질들로 고분자 메모리 절연층(120)을 형성시켜 열처리할 경우, 최대 300℃까지도 열처리가 가능해지는 것이다. 이에 대한 출원인의 실험에 따르면 80 ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리하는 것이 가장 바람직한 것으로 나타났다.The two sulfonic acid-based organic materials have a glass transition temperature of about 300 ° C., so that when the polymer memory insulating layer 120 is formed and heat-treated with these materials, heat treatment is possible up to 300 ° C. Applicants' experiment according to this was found to be most preferable to heat treatment for 0.4 ~ 0.6 hours at a temperature of 80 ~ 230 ℃.
한편 전하 수송층(130)은 고분자 메모리 절연층(120) 상에 형성된 것으로서, 전하의 수송 효율을 높이기 위하여 정공 수송층으로 형성할 수 있고, 예시적으로 P3HT(poly(3-hexylthiophene))로 형성할 수 있다.Meanwhile, the charge transport layer 130 is formed on the polymer memory insulating layer 120, and may be formed as a hole transport layer to increase charge transport efficiency. For example, the charge transport layer 130 may be formed of poly (3-hexylthiophene) (P3HT). have.
이러한 전하 수송층(130)이 일반적으로 산성에 약한 물질이기 때문에 인접한 고분자 메모리 절연층(120)의 산도를 낮출 수 있도록 유기물질의 종류를 적절하게 선택하는 것이 중요한데, 상기 화학식 1 및 화학식 2로 표현되는 술폰산 계열의 유기물질은 pH가 약 1.5 이상이 되는 물질들로써 이러한 측면에서도 유기 메모리 소자의 소재로 적절한 것을 알 수 있다.Since the charge transport layer 130 is generally an acid weak material, it is important to appropriately select a type of organic material so as to lower the acidity of the adjacent polymer memory insulating layer 120, which is represented by Chemical Formulas 1 and 2 above. The sulfonic acid-based organic material is a material having a pH of about 1.5 or more, and in this respect, it can be seen that it is a suitable material for the organic memory device.
소스 전극(140)과 드레인 전극(150)은 전하 수송층(130) 상에 일정 거리 이격되게 형성되는 것으로서, 금(Au), 은(Ag), 구리(Cu), 니켈(Ni)/알루미늄, 폴리머 등의 도전성 물질로 형성될 수 있다.The source electrode 140 and the drain electrode 150 are formed to be spaced apart from each other on the charge transport layer 130 by a predetermined distance, and include gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, and polymers. It may be formed of a conductive material such as.
이렇게 형성된 본 발명의 유기 메모리 소자에서 게이트 전극(110)에 전압을 인가하면, 도 2에 도시한 바와 같이 고분자 메모리 절연층(120)이 전기적으로 분극되어 히스테리시스 현상이 발생하게 되고, 이로 인하여 전하 수송층(130)에도 정공 히스테리시스 현상이 유도된다. When a voltage is applied to the gate electrode 110 in the organic memory device of the present invention formed as described above, as shown in FIG. 2, the polymer memory insulating layer 120 is electrically polarized to generate a hysteresis phenomenon, thereby causing a charge transport layer. Hole hysteresis is also induced at 130.
이와 같이 전하 수송층(130)의 정공 이동에 히스테리시스 특성이 발생함에 따라 소스 전극(140)에서 드레인 전극(150)으로의 전하 이동도가 높아져, 드레인 전류가 히스테리시스 특성을 가지게 되므로 트랜지스터 구조를 가지면서도 비휘발성의 메모리 기능을 할 수 있게 되는 것이다. As the hysteresis characteristic is generated in the hole movement of the charge transport layer 130 as described above, the charge mobility from the source electrode 140 to the drain electrode 150 is increased, so that the drain current has the hysteresis characteristic. It will be able to function as a volatile memory.
도 3은 본 발명의 실시예에 따른 술폰산 계열 유기 메모리 소자의 리텐션(retention) 테스트 결과 그래프이다.3 is a graph illustrating retention test results of a sulfonic acid based organic memory device according to an exemplary embodiment of the present invention.
도 3을 참조하면, 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자는 실제 출원인이 테스트한 결과 약 일만회 이상의 리텐션 테스트에서도 안정적인 결과를 보이고 있음을 알 수 있다. Referring to FIG. 3, it can be seen that the organic memory device using the high temperature heat treatment according to the exemplary embodiment of the present invention shows stable results even after retention tests of about 10,000 times.
전술한 바와 같이 고분자 메모리 절연층 상에 형성된 전하 수송층이 일반적으로 산성에 약한 물질이기 때문에 인접한 고분자 메모리 절연층의 산도를 낮추는 것이 중요한데, 상기 화학식 1 및 화학식 2로 표현되는 술폰산 계열의 유기물질을 사용하여 고분자 메모리 절연층을 형성시킨 유기 메모리 소자를 대상으로 테스트해본 결과 목적을 달성할 수 있게 된 것이다.As described above, since the charge transport layer formed on the polymer memory insulating layer is generally weak in acidity, it is important to lower the acidity of the adjacent polymer memory insulating layer. The organic material of sulfonic acid type represented by Chemical Formulas 1 and 2 is used. As a result, a test was conducted on an organic memory device in which a polymer memory insulating layer was formed, thereby achieving the purpose.
그래프는 시간의 흐름에 따른 전류값이 균일하게 유지되고 있음을 보여주며, 특히 메모리 소자의 각 특성인 쓰기(write)-읽기(read1, read2)-소거(erase)의 항목에서 모두 안정적이기 때문에 우수한 품질의 메모리 기능을 기대할 수 있을 것이다.The graph shows that the current value is kept uniform over time, especially because it is stable in each of the write-read (read1, read2) -erase items of each memory device. You can expect quality memory features.
도 4는 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자의 게이트 전압 그래프, 도 5는 본 발명의 실시예에 따라 170℃ 열처리를 한 유기 메모리 소자의 히스테리시스 특성 그래프이다.4 is a gate voltage graph of an organic memory device using a high temperature heat treatment according to an embodiment of the present invention, and FIG. 5 is a graph of hysteresis characteristics of an organic memory device subjected to 170 ° C. heat treatment according to an embodiment of the present invention.
도 4 및 도 5를 참조하면, 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자는 고온에서 열처리를 가한 후 높은 열적 안정성을 보이고 있음을 알 수 있다. 특히 도 4에 도시된 바와 같이 유기 트랜지스터 소자로 원할한 작동이 이루어지고 있으며, 저전압에서도 문제없이 구동되고 있음을 보여 준다.4 and 5, it can be seen that the organic memory device using the high temperature heat treatment according to the embodiment of the present invention shows high thermal stability after heat treatment at high temperature. In particular, as shown in FIG. 4, the smooth operation of the organic transistor device is performed, and it is shown that it is operated without problems even at a low voltage.
도 5에서는 출원인의 실험에 따라 170℃ 고온으로 열처리를 한 유기 메모리 소자의 히스테리시스 특성 그래프를 살펴볼 수 있는데, 게이트 전극에 전압을 인가하면, 열처리한 고분자 메모리 절연층이 전기적으로 분극되어 히스테리시스 현상이 발생하게 되고, 이로 인하여 전하 수송층에도 정공 히스테리시스 현상이 유도되고 소스 전극에서 드레인 전극으로의 전하 이동도가 높아져, 드레인 전류가 히스테리시스 특성을 가지게 되므로 트랜지스터 구조를 가지면서도 비휘발성의 메모리 기능을 할 수 있게 되는 것이다. In FIG. 5, a graph of hysteresis characteristics of an organic memory device heat-treated at 170 ° C. according to the applicant's experiment can be seen. When voltage is applied to the gate electrode, the heat-treated polymer memory insulating layer is electrically polarized to generate a hysteresis phenomenon. As a result, a hole hysteresis phenomenon is induced in the charge transport layer, and the charge mobility from the source electrode to the drain electrode is increased, so that the drain current has hysteresis characteristics, thereby enabling a nonvolatile memory function having a transistor structure. will be.
즉, 드레인 전류의 히스테리시스 특성이 명확히 나타난다는 것은 히스테리시스에 의한 전압차가 크다는 것을 의미하므로, 히스테리시스에 의한 전압차가 큰 본 발명의 170℃ 열처리된 고분자 메모리 절연층이 사용되면, 메모리 소자의 문턱전압차가 증가되므로 저전압에서도 구동이 가능해지게 된다. That is, since the hysteresis characteristic of the drain current is clearly indicated, it means that the voltage difference due to hysteresis is large. Therefore, when the 170 ° C. heat-treated polymer memory insulating layer having the large voltage difference due to hysteresis is used, the threshold voltage difference of the memory device increases. Therefore, driving at low voltage becomes possible.
도 6은 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자 제조 방법의 순서도, 도 7a 내지 도 7d는 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자 제조 방법을 순차로 나타낸 공정 단면도이다.6 is a flowchart illustrating a method of manufacturing an organic memory device using a high temperature heat treatment according to an embodiment of the present invention, and FIGS. 7A to 7D are process cross-sectional views sequentially illustrating a method of manufacturing an organic memory device using a high temperature heat treatment according to an embodiment of the present invention. to be.
도 6 및 도 7을 참조하면, 본 발명의 실시예에 따른 고온 열처리를 이용한 유기 메모리 소자 제조 방법은, 기판 상에 게이트 전극을 형성하는 단계(S10), 게이트 전극 상에 형성되며 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층을 형성하는 단계(S20), 고분자 메모리 절연층을 열처리하는 단계(S30), 고분자 메모리 절연층 상에 전하 수송층을 형성하는 단계(S40) 및 정공 수송층 상에 일정 거리 이격되는 소스 전극과 드레인 전극을 형성하는 단계(S50)를 포함하여 이루어진다.6 and 7, the method of manufacturing an organic memory device using a high temperature heat treatment according to an embodiment of the present invention includes forming a gate electrode on a substrate (S10), and formed on the gate electrode and made of an organic material. Forming an electrically polarizable polymer memory insulation layer exhibiting hysteresis (S20), heat treating the polymer memory insulation layer (S30), forming a charge transport layer on the polymer memory insulation layer (S40) and on the hole transport layer Forming a source electrode and a drain electrode spaced apart from each other by a predetermined distance (S50).
기판 상에 게이트 전극을 형성하는 단계(S10)에는 도 7a와 같이 기판(100)에 게이트 전극(110)을 형성한다. 게이트 전극(110)은 도전성 물질을 열 증착(thermal evaporation)한 후 패터닝 함으로써 형성되며, 도전성 물질은 예시적으로 금(Au), 은(Ag), 구리(Cu), 니켈(Ni)/알루미늄, 폴리머 등이 이용될 수 있다.In the step S10 of forming the gate electrode on the substrate, the gate electrode 110 is formed on the substrate 100 as shown in FIG. 7A. The gate electrode 110 is formed by thermal evaporation of a conductive material and then patterned. The conductive material may include, for example, gold (Au), silver (Ag), copper (Cu), nickel (Ni) / aluminum, Polymers and the like can be used.
고분자 메모리 절연층을 형성하는 단계(S20)에는 도 7b와 같이 게이트 전극(110)이 형성된 기판(100) 상에 고분자 메모리 절연층(120)을 300 ~ 800nm 두께로 형성한다. In the forming of the polymer memory insulating layer (S20), the polymer memory insulating layer 120 is formed to have a thickness of 300 to 800 nm on the substrate 100 on which the gate electrode 110 is formed as shown in FIG. 7B.
고분자 메모리 절연층(120)을 히스테리시스(hysteresis)를 나타내는 전기적으로 분극 가능한 물질로 형성하는 것으로서, 본 발명에서는 술폰산(sulfonic acid) 계열의 유기물질 용액을 이용한다. 구체적으로는, 술폰산 계열의 물질 중에서도 특히 하기의 화학식 1로 표현되는 화합물 또는 하기의 화학식 2로 표현되는 화합물을 이용하는 것이 바람직하다.The polymer memory insulating layer 120 is formed of an electrically polarizable material that exhibits hysteresis. In the present invention, a sulfonic acid-based organic material solution is used. Specifically, it is preferable to use the compound represented by the following general formula (1) or the compound represented by the following general formula (2) among sulfonic acid series materials.
[화학식 1][Formula 1]
Figure PCTKR2016003977-appb-I000005
Figure PCTKR2016003977-appb-I000005
[화학식 2][Formula 2]
Figure PCTKR2016003977-appb-I000006
Figure PCTKR2016003977-appb-I000006
(상기 식들에서, n은 2 이상의 정수이다.)(In the above formulas, n is an integer of 2 or more.)
위의 술폰산 계열의 유기물질 용액을 준비한 후 게이트 전극(110)이 형성된 기판(100) 상에 코팅한다. 이때, 유기물질 용액 코팅은 스핀 코팅 방식으로 진행 할 수 있으며, 코팅이 완료된 후에 고분자 메모리 절연층을 열처리하는 단계(S30)에서는 형성된 고분자 메모리 절연층을 핫플레이트에서 80℃ ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리한다.After preparing the sulfonic acid-based organic material solution is coated on the substrate 100 on which the gate electrode 110 is formed. At this time, the coating of the organic material solution may be carried out by a spin coating method, and in the step (S30) of heat treating the polymer memory insulating layer after the coating is completed, the polymer memory insulating layer formed is 0.4 at a temperature of 80 ° C. to 230 ° C. on a hot plate. Heat treatment for ~ 0.6 hours.
고분자 메모리 절연층 상에 전하 수송층을 형성하는 단계(S40)에는 도 7c와 같이 고분자 메모리 절연층(120) 상에 전하 수송층(130)을 형성하되, 전하 수송 효율을 높이기 위하여 정공 수송층 예시적으로 P3HT(poly(3-hexylthiophene))을 스핀 코팅 방식 등을 이용하여 코팅한다.In the step S40 of forming the charge transport layer on the polymer memory insulation layer, as shown in FIG. 7C, the charge transport layer 130 is formed on the polymer memory insulation layer 120, but the hole transport layer P3HT is used to increase the charge transport efficiency. (poly (3-hexylthiophene)) is coated using a spin coating method or the like.
이때, 전하 수송층(130)은 유기 반도체층으로서 폴리머 활성층을 포함할 수 있다.In this case, the charge transport layer 130 may include a polymer active layer as an organic semiconductor layer.
끝으로 소스 전극과 드레인 전극을 형성하는 단계(S50)에는 도 7d와 같이 전하 수송층(130) 상에 도전성 물질 예시적으로 금(Au), 은(Ag), 구리(Cu), 니켈(Ni)/알루미늄, 폴리머 등의 도전성 물질을 형성한 후에 패터닝 공정을 통하여 일정 거리 이격되는 소스 전극(140)과 드레인 전극(150)을 형성한다.Finally, in the step S50 of forming the source electrode and the drain electrode, conductive materials on the charge transport layer 130 are illustrated as gold (Au), silver (Ag), copper (Cu), and nickel (Ni) as shown in FIG. 7D. After forming a conductive material such as aluminum and a polymer, a source electrode 140 and a drain electrode 150 spaced by a predetermined distance are formed through a patterning process.
비록 본 발명이 상기 언급된 바람직한 실시예와 관련하여 설명되어 졌지만, 발명의 요지와 범위로부터 벗어남이 없이 다양한 수정이나 변형을 하는 것이 가능하다. 따라서 첨부된 특허등록청구의 범위는 본 발명의 요지에서 속하는 이러한 수정이나 변형을 포함할 것이다.Although the present invention has been described in connection with the above-mentioned preferred embodiments, it is possible to make various modifications or variations without departing from the spirit and scope of the invention. Therefore, the scope of the appended claims will include such modifications and variations that fall within the spirit of the invention.

Claims (16)

  1. 기판 상에 형성된 게이트 전극과 소스 및 드레인 전극을 포함하는 유기 메모리 소자에 있어서, An organic memory device comprising a gate electrode and a source and a drain electrode formed on a substrate,
    상기 게이트 전극과 소스 및 드레인 전극 사이에 열처리된 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층이 형성된 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.And an electrically polarizable polymer memory insulating layer formed of an organic material heat-treated between the gate electrode and the source and drain electrodes to exhibit hysteresis.
  2. 제 1항에 있어서,The method of claim 1,
    상기 유기물질은 술폰산(sulfonic acid) 계열의 물질인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the sulfonic acid-based material.
  3. 제 2항에 있어서,The method of claim 2,
    상기 유기물질은 하기의 화학식 1로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (1).
    [화학식 1][Formula 1]
    Figure PCTKR2016003977-appb-I000007
    Figure PCTKR2016003977-appb-I000007
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  4. 제 2항에 있어서,The method of claim 2,
    상기 유기물질은 하기의 화학식 2로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (2).
    [화학식 2][Formula 2]
    Figure PCTKR2016003977-appb-I000008
    Figure PCTKR2016003977-appb-I000008
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  5. 기판;Board;
    상기 기판 상에 형성된 게이트 전극;A gate electrode formed on the substrate;
    상기 게이트 전극 상에 형성되며 열처리된 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층;An electrically polarizable polymer memory insulating layer formed on the gate electrode and exhibiting hysteresis made of a heat-treated organic material;
    상기 고분자 메모리 절연층 상에 형성된 전하 수송층; 및A charge transport layer formed on the polymer memory insulating layer; And
    상기 전하 수송층 상에 일정 거리 이격되게 각각 형성된 소스 및 드레인 전극을 포함하는 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.And a source and a drain electrode each formed on the charge transport layer at a predetermined distance apart from each other.
  6. 제 5항에 있어서,The method of claim 5,
    상기 고분자 메모리 절연층은, 상기 유기물질의 용액을 스핀 코팅한 후 80 ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리가 이루어진 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The polymer memory insulating layer is an organic memory device using a high temperature heat treatment, characterized in that the heat treatment for 0.4 ~ 0.6 hours at a temperature of 80 ~ 230 ℃ after spin coating the solution of the organic material.
  7. 제 5항에 있어서,The method of claim 5,
    상기 유기물질은 술폰산(sulfonic acid) 계열의 물질인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the sulfonic acid-based material.
  8. 제 7항에 있어서,The method of claim 7, wherein
    상기 유기물질은 하기의 화학식 1로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (1).
    [화학식 1][Formula 1]
    Figure PCTKR2016003977-appb-I000009
    Figure PCTKR2016003977-appb-I000009
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  9. 제 7항에 있어서,The method of claim 7, wherein
    상기 유기물질은 하기의 화학식 2로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The organic material is an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (2).
    [화학식 2][Formula 2]
    Figure PCTKR2016003977-appb-I000010
    Figure PCTKR2016003977-appb-I000010
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  10. 제 5항에 있어서,The method of claim 5,
    상기 전하 수송층은 정공 수송층인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자.The charge transport layer is an organic memory device using a high temperature heat treatment, characterized in that the hole transport layer.
  11. 기판 상에 게이트 전극을 형성하는 단계;Forming a gate electrode on the substrate;
    상기 게이트 전극 상에 형성되며 유기물질로 이루어져 히스테리시스를 나타내는 전기적으로 분극 가능한 고분자 메모리 절연층을 형성하는 단계;Forming an electrically polarizable polymer memory insulating layer formed on the gate electrode and made of an organic material to exhibit hysteresis;
    상기 고분자 메모리 절연층을 열처리하는 단계;Heat treating the polymer memory insulation layer;
    상기 고분자 메모리 절연층 상에 전하 수송층을 형성하는 단계;Forming a charge transport layer on the polymer memory insulating layer;
    상기 전하 수송층 상에 일정 거리 이격되는 소스 전극과 드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.Forming a source electrode and a drain electrode spaced apart from each other by a predetermined distance on the charge transport layer.
  12. 제 11항에 있어서,The method of claim 11,
    상기 고분자 메모리 절연층을 형성하는 단계는,Forming the polymer memory insulating layer,
    술폰산(sulfonic acid) 계열의 유기물질 용액을 스핀 코팅하여 300 ~ 800nm 두께의 고분자 메모리 절연층을 형성하는 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.A method of manufacturing an organic memory device using a high temperature heat treatment, comprising: spin coating a sulfonic acid-based organic material solution to form a polymer memory insulating layer having a thickness of 300 to 800 nm.
  13. 제 11항에 있어서,The method of claim 11,
    상기 고분자 메모리 절연층을 열처리하는 단계는,The heat treatment of the polymer memory insulating layer,
    상기 형성된 고분자 메모리 절연층을 핫플레이트에서 80℃ ~ 230℃의 온도로 0.4 ~ 0.6시간동안 열처리하는 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.A method of manufacturing an organic memory device using high temperature heat treatment, wherein the formed polymer memory insulation layer is heat-treated at a temperature of 80 ° C. to 230 ° C. for 0.4 to 0.6 hours.
  14. 제 12항에 있어서,The method of claim 12,
    상기 유기물질은 하기의 화학식 1로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.The organic material is a method of manufacturing an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (1).
    [화학식 1][Formula 1]
    Figure PCTKR2016003977-appb-I000011
    Figure PCTKR2016003977-appb-I000011
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  15. 제 12항에 있어서,The method of claim 12,
    상기 유기물질은 하기의 화학식 2로 표현되는 화합물인 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.The organic material is a method of manufacturing an organic memory device using a high temperature heat treatment, characterized in that the compound represented by the formula (2).
    [화학식 2][Formula 2]
    Figure PCTKR2016003977-appb-I000012
    Figure PCTKR2016003977-appb-I000012
    (상기 식에서, n은 2 이상의 정수이다.)(Wherein n is an integer of 2 or more).
  16. 제 11항에 있어서,The method of claim 11,
    상기 전하 수송층으로서 정공 수송층을 형성하는 것을 특징으로 하는 고온 열처리를 이용한 유기 메모리 소자의 제조 방법.A hole transport layer is formed as the charge transport layer. A method of manufacturing an organic memory device using high temperature heat treatment.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260205A (en) * 2004-02-13 2005-09-22 Matsushita Electric Ind Co Ltd Method for forming organic/inorganic hybrid insulation film
KR20080109196A (en) * 2007-06-12 2008-12-17 삼성전자주식회사 Composition for preparing organic insulator and organic insulator prepared using the same
KR20100049853A (en) * 2008-11-04 2010-05-13 한국화학연구원 A method for preparing photo-crosslinkable organic gate insulator and organic thin film transistor device using the same
KR20100126407A (en) * 2008-03-18 2010-12-01 도레이 카부시키가이샤 Gate insulating material, gate insulating film, and organic field effect transistor
KR20120033722A (en) * 2010-09-30 2012-04-09 한국전자통신연구원 Graphene oxide memory devices and fabrication methods thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012950B1 (en) * 2003-10-15 2011-02-08 삼성전자주식회사 Composition for Preparing Organic Insulator and the Organic Insulator
KR101190570B1 (en) 2010-12-01 2012-10-16 국민대학교산학협력단 flexible organic memory device and method of fabricating the same
KR101234225B1 (en) 2011-04-26 2013-02-18 국민대학교산학협력단 flexible organic memory device and method of fabricating the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260205A (en) * 2004-02-13 2005-09-22 Matsushita Electric Ind Co Ltd Method for forming organic/inorganic hybrid insulation film
KR20080109196A (en) * 2007-06-12 2008-12-17 삼성전자주식회사 Composition for preparing organic insulator and organic insulator prepared using the same
KR20100126407A (en) * 2008-03-18 2010-12-01 도레이 카부시키가이샤 Gate insulating material, gate insulating film, and organic field effect transistor
KR20100049853A (en) * 2008-11-04 2010-05-13 한국화학연구원 A method for preparing photo-crosslinkable organic gate insulator and organic thin film transistor device using the same
KR20120033722A (en) * 2010-09-30 2012-04-09 한국전자통신연구원 Graphene oxide memory devices and fabrication methods thereof

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