WO2016170894A1 - Wiring board and laminated chip capacitor - Google Patents

Wiring board and laminated chip capacitor Download PDF

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Publication number
WO2016170894A1
WO2016170894A1 PCT/JP2016/059099 JP2016059099W WO2016170894A1 WO 2016170894 A1 WO2016170894 A1 WO 2016170894A1 JP 2016059099 W JP2016059099 W JP 2016059099W WO 2016170894 A1 WO2016170894 A1 WO 2016170894A1
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Prior art keywords
terminal
main body
chip capacitor
multilayer chip
vias
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PCT/JP2016/059099
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French (fr)
Japanese (ja)
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田中　大介
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株式会社村田製作所
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Publication of WO2016170894A1 publication Critical patent/WO2016170894A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a wiring board in which a multilayer chip capacitor is embedded, and a multilayer chip capacitor.
  • Patent Document 1 discloses a wiring board in which a multilayer chip capacitor unit for decoupling is embedded.
  • the multilayer chip capacitor unit is formed by connecting and integrating the external electrodes of the multilayer chip capacitor.
  • the wiring of the wiring board and the external electrode of the multilayer chip capacitor unit are electrically connected by vias.
  • the multilayer chip capacitor has a substantially rectangular parallelepiped outer shape.
  • the pair of external electrodes are provided on the end faces at both ends in the longitudinal direction of the multilayer chip capacitor, and are provided in a part of the upper surface, the lower surface, and the side surfaces that are continuous with the end faces.
  • a pair of external electrodes are electrically connected to the ground pattern and the power supply pattern of the wiring board, respectively, by contact of the vias with the external electrodes provided in part of the upper and lower surfaces.
  • the current path connecting one external electrode of the multilayer chip capacitor and the ground pattern, and the other external electrode and the power supply pattern are connected. It is desired to reduce the impedance of the current path.
  • a wiring board provides: A substrate having an upper surface and a lower surface; A multilayer chip capacitor including a first terminal and a second terminal and embedded in the substrate; A first pad and a second pad provided on the lower surface of the substrate; A third pad and a fourth pad provided on the upper surface of the substrate; A first current path connecting the first pad and the first terminal; A second current path connecting the third pad and the first terminal; A third current path connecting the second pad and the second terminal; A fourth current path connecting the fourth pad and the second terminal;
  • the multilayer chip capacitor includes a main body having an upper surface and a lower surface, The first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body, The second terminal is provided in a partial region of each of the upper surface and the lower surface of the main body, Of the first terminal, the portion provided on the upper surface of the main body occupies a larger area than the portion provided on the lower surface of the main body, Of the second terminal, a portion provided on the lower surface of the main body
  • the second current path can be made substantially thicker.
  • the portion provided on the lower surface of the main body occupies a larger area than the portion provided on the upper surface of the main body, so that the third current path can be made substantially thicker. . Thereby, the equivalent series inductance of the second current path and the third current path can be reduced.
  • the first current path includes at least one first via that contacts a portion of the first terminal provided on a lower surface of the main body;
  • the second current path includes a plurality of second vias in contact with a portion of the first terminal provided on an upper surface of the main body;
  • the number of second vias is greater than the number of first vias;
  • the third current path includes a plurality of third vias in contact with a portion of the second terminal provided on the lower surface of the main body;
  • the fourth current path includes at least one fourth via that contacts a portion of the second terminal provided on the upper surface of the main body;
  • the number of third vias is greater than the number of fourth vias.
  • the current path can be made substantially thicker.
  • the first via, the second via, the third via, and the fourth via have the same thickness.
  • Aligning the thickness of the via can simplify the processing of the via hole as compared with the case where a plurality of via holes having different thicknesses are formed.
  • the multilayer chip capacitor according to the fourth aspect of the present invention is: A first electrode layer; a second electrode layer; and a dielectric layer disposed between the first electrode layer and the second electrode layer, wherein upper and lower surfaces from which the dielectric is exposed are defined.
  • the body A first terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the first electrode layer; A second terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the second electrode layer; Of the first terminal, the portion provided on the upper surface occupies a larger area than the portion provided on the lower surface, Of the second terminal, the portion provided on the lower surface occupies a larger area than the portion provided on the upper surface.
  • more vias can be connected to the portion provided on the upper surface than the portion provided on the lower surface.
  • more vias than the portion provided on the upper surface can be connected to the portion provided on the lower surface of the second terminal.
  • the main body has an outer shape whose dimension in the longitudinal direction is longer than that in the width direction
  • the first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body that is continuous with one end surface in the longitudinal direction of the main body
  • the second terminal is provided in a partial region of each of the upper surface and the lower surface of the main body that is continuous with the other end surface in the longitudinal direction of the main body,
  • the dimension in the longitudinal direction of the portion provided on the upper surface of the main body is longer than the dimension in the longitudinal direction of the portion provided on the lower surface of the main body
  • the dimension in the longitudinal direction of the portion provided on the lower surface of the main body is longer than the dimension in the longitudinal direction of the portion provided on the upper surface of the main body.
  • the second current path can be made substantially thicker.
  • the portion provided on the lower surface of the main body occupies a larger area than the portion provided on the upper surface of the main body, so that the third current path can be made substantially thicker. . Thereby, the equivalent series inductance of the second current path and the third current path can be reduced.
  • FIGS. 2B and 2C are plan views of the multilayer chip capacitor and the via, respectively. It is a bottom view.
  • FIG. 3 is a cross-sectional view of the multilayer chip capacitor and the via in a state where the multilayer chip capacitor according to the first embodiment is embedded in the wiring board.
  • FIG. 4 is an equivalent circuit diagram of the multilayer chip capacitor, the first via, the second via, the third via, and the fourth via.
  • FIG. 5A is a perspective view of a multilayer chip capacitor, a first via, a second via, a third via, and a fourth via according to a comparative example
  • FIG. 5B is an equivalent circuit diagram thereof.
  • 6A to 6D are cross-sectional views in the middle of manufacturing a wiring board according to the second embodiment.
  • 6E is a cross-sectional view in the middle of manufacturing the wiring board according to the second embodiment, and
  • FIG. 6F is a cross-sectional view of the wiring board according to the second embodiment.
  • FIG. 7 is a schematic cross-sectional view of the wiring board, the mother board, and the integrated circuit element according to the second embodiment.
  • 8A and 8B are schematic cross-sectional views of the multilayer chip capacitor unit according to the third embodiment.
  • FIG. 1 A multilayer chip capacitor according to Example 1 will be described with reference to FIGS. 1A to 4.
  • FIG. 1A A multilayer chip capacitor according to Example 1 will be described with reference to FIGS. 1A to 4.
  • the multilayer chip capacitor 30 includes a main body 10, a first terminal 11, and a second terminal 12.
  • the main body 10 has a substantially rectangular parallelepiped outer shape, and the dimension in the longitudinal direction is longer than the dimension in the width direction and the height direction.
  • the main body 10 has six surfaces including end surfaces 104 and 105 at both ends in the longitudinal direction, an upper surface 101, a lower surface 102, and a pair of side surfaces 103.
  • the first terminal 11 is provided over the entire area of the one end face 104, and is provided in a partial region of the upper face 101, the lower face 102, and the side face 103 that is continuous with the end face 104.
  • the second terminal 12 is provided in the entire region of the other end surface 105, and is provided in a part of the upper surface 101, the lower surface 102, and the side surface 103 that is continuous with the end surface 105.
  • portions provided on the upper surface 101 and the lower surface 102 have a substantially rectangular or square planar shape (FIGS. 1B and 1C).
  • the planar shape of the portion provided on the side surface 103 is a trapezoid whose two inner angles are right angles.
  • the portion of the first terminal 11 provided on the upper surface 101 occupies a larger area than the portion provided on the lower surface 102.
  • a portion of the second terminal 12 provided on the lower surface 102 occupies a larger area than a portion provided on the upper surface 101.
  • the dimension L1 (FIG. 1B) in the longitudinal direction of the portion provided on the upper surface 101 of the first terminal 11 is the dimension L2 in the longitudinal direction of the portion provided in the lower surface 102 (FIG. 1B). Longer than FIG. 1C).
  • the dimension L4 (FIG. 1C) in the longitudinal direction of the portion provided on the lower surface 102 of the second terminal 12 is longer than the dimension L3 (FIG. 1B) in the longitudinal direction of the portion provided on the upper surface 101.
  • FIG. 2A shows a perspective view of the multilayer chip capacitor 30 and vias in a state where the multilayer chip capacitor 30 according to the first embodiment is embedded in a wiring board.
  • 2B and 2C are a plan view and a bottom view of the multilayer chip capacitor 30 and the via, respectively.
  • At least one first via 15 is in contact with a portion provided on the lower surface 102 of the main body 10, and a plurality of first vias 15 are provided on a portion provided on the upper surface 101 of the main body 10.
  • Two vias 16 come into contact.
  • the number of second vias 16 is greater than the number of first vias 15.
  • a plurality of third vias 17 are in contact with a portion provided on the lower surface 102 of the main body 10, and at least one first terminal is provided on a portion provided on the upper surface 101 of the main body 10.
  • Four vias 18 come into contact.
  • the number of third vias 17 is greater than the number of fourth vias 18.
  • two first vias 15, four second vias 16, four third vias 17, and two fourth vias 18 are provided. Yes.
  • the two first vias 15 are arranged side by side in the width direction of the main body 10.
  • the two fourth vias 18 are also arranged side by side in the width direction of the main body 10.
  • the four second vias 16 are arranged in a matrix of 2 rows and 2 columns in which the longitudinal direction and the width direction of the main body 10 are the row direction and the column direction.
  • the four third vias 17 are also arranged in a matrix of 2 rows and 2 columns.
  • a structure suitable for making the second via 16 larger than the first via 15 and making the third via 17 larger than the fourth via 18 is adopted. That is, the area of the portion provided on the upper surface 101 of the first terminal 11 is larger than the area of the portion provided on the lower surface 102 and the portion provided on the lower surface 102 of the second terminal 12. Is larger than the area of the portion provided on the upper surface 101.
  • the dimension L1 is 1.5 times or more the dimension L2, It is preferable that the dimension L4 is 1.5 times or more the dimension L3.
  • FIG. 3 shows a cross-sectional view of the multilayer chip capacitor 30 and vias in a state where the multilayer chip capacitor 30 according to the first embodiment is embedded in the wiring board.
  • a plurality of first electrode layers 21 and a plurality of second electrode layers 22 are alternately stacked in the main body 10 of the multilayer chip capacitor 30.
  • a dielectric layer 23 is disposed between the first electrode layer 21 and the second electrode layer 22.
  • a dielectric is exposed on the upper surface 101 and the lower surface 102 of the main body 10.
  • a dielectric ceramic such as barium titanate is used as the dielectric exposed on the inner dielectric layer 23, the upper surface 101, and the lower surface 102, for example.
  • a metal whose main component is Ag, Cu, Ni, or the like is used.
  • the end of the first electrode layer 21 is exposed on one end face 104, and the end of the second electrode layer 22 is exposed on the other end face 105.
  • the first electrode layer 21 is connected to the first terminal 11 at the end exposed at the end face 104.
  • the second electrode layer 22 is connected to the second electrode layer 22 at the end exposed at the end face 105.
  • At least one first via 15 is in contact with a portion provided on the lower surface 102 of the main body 10, and a plurality of second vias are provided on a portion provided on the upper surface 101. Vias 16 are in contact.
  • a plurality of third vias 17 are in contact with a portion provided on the lower surface 102 of the main body 10, and at least one fourth terminal is provided on a portion provided on the upper surface 101. Vias 18 are in contact.
  • first via 15 and the third via 17 are connected to the ground pattern and the power supply pattern of the motherboard, respectively.
  • the second via 16 and the fourth via 18 are connected to the ground terminal GND and the power supply terminal VDD of the integrated circuit element, respectively.
  • FIG. 4 shows an equivalent circuit diagram of the multilayer chip capacitor 30, the first via 15, the second via 16, the third via 17, and the fourth via 18.
  • Each of the first via 15, the second via 16, the third via 17, and the fourth via 18 has an equivalent series inductance L.
  • the multilayer chip capacitor 30 is represented by a series circuit of a capacitance and an equivalent series inductance.
  • the first via 15 and the fourth via 18 are each represented by a parallel circuit of two equivalent series inductances L.
  • the second via 16 and the third via 17 are each represented by a parallel circuit of four equivalent series inductances L.
  • FIG. 5A is a perspective view of the multilayer chip capacitor 30, the first via 15, the second via 16, the third via 17, and the fourth via 18 according to the comparative example.
  • the portion provided on the upper surface 101 of the main body 10 and the portion provided on the lower surface 102 of the first terminal 11 are included in the first terminal 11 of the multilayer chip capacitor 30 according to the first embodiment.
  • the portion provided on the lower surface 102 of the main body 10 and the portion provided on the upper surface 101 of the second terminal 12 are the upper surfaces of the second terminals 12 of the multilayer chip capacitor 30 according to the first embodiment.
  • 101 has the same dimensions as the portion provided in 101 (FIG. 2B).
  • FIG. 5B shows an equivalent circuit diagram of the multilayer chip capacitor and the via.
  • the first via 15, the second via 16, the third via 17, and the fourth via 18 are each represented by two equivalent series inductances L.
  • Example 1 as shown in FIG. 4, the second via 16 and the third via 17 are each represented by a parallel circuit of four equivalent series inductances L.
  • the equivalent series inductance of the current path connecting the ground pattern of the motherboard and the ground terminal GND of the integrated circuit element can be reduced.
  • more stable power supply from the mother board to the integrated circuit element can be achieved.
  • the minimum distance (FIG. 2B) between the second via 16 and the fourth via 18 is the minimum distance (FIG. 5A) between the second via 16 and the fourth via 18 in the comparative example. Narrower.
  • the minimum distance (FIG. 2C) between the third via 17 and the first via 15 is narrower than the minimum distance (FIG. 5A) between the third via 17 and the first via 15 in the comparative example.
  • the configuration of the first embodiment adopts the configuration of the first via 15 and the third via 17. It is possible to reduce the minimum interval and the minimum interval between the second via 16 and the fourth via 18.
  • the magnetic flux due to the electrical signal flowing through the first via 15 and the magnetic flux due to the electrical signal flowing in the reverse direction through the third via 17 efficiently cancel each other.
  • the magnetic flux due to the electrical signal flowing through the second via 16 and the magnetic flux due to the electrical signal flowing in the reverse direction through the fourth via 18 effectively cancel each other.
  • Example 1 when the portions of the first terminal 11 and the second terminal 12 provided on the upper surface 101 are compared, the second terminal 12 is smaller than the first terminal 11. On the contrary, when the portion provided on the lower surface 102 is compared, the first terminal 11 is smaller than the second terminal 12. Thus, by making one of the first terminal 11 and the second terminal 12 smaller than the other, it is possible to prevent the distance between them from becoming excessively narrow. As a result, occurrence of a short circuit failure can be suppressed.
  • FIGS. 6A to 6F and FIG. 6A to 6E are cross-sectional views of the wiring board in the middle of manufacturing, and FIG. 6F is a cross-sectional view of the wiring board according to the second embodiment.
  • a core substrate 40 provided with a cavity 41 is prepared.
  • the cavity 41 penetrates the core substrate 40 in the thickness direction.
  • An adhesive sheet 42 is attached to one surface of the core substrate 40.
  • the adhesive sheet 42 closes one opening of the cavity 41 and constitutes the bottom surface of the cavity 41.
  • the multilayer chip capacitor 30 according to the first embodiment is accommodated in the cavity 41 with the lower surface 102 facing the adhesive sheet 42.
  • a portion provided on the lower surface 102 is bonded to the adhesive sheet 42.
  • the upper surface of the portion provided on the upper surface 101 is located at substantially the same height as the upper surface of the core substrate 40.
  • FIG. 6B shows a cross-sectional view of the core substrate 40 and the multilayer chip capacitor 30 after the adhesive sheet 42 is peeled off.
  • the multilayer chip capacitor 30 is supported on the core substrate 40 by the filler 43.
  • a build-up resin layer 45 is formed on both surfaces of the core substrate 40, the multilayer chip capacitor 30, and the filler 43.
  • a plurality of via holes and a plurality of through holes are formed in the core substrate 40 and the resin layer 45.
  • Laser processing can be used to form via holes and through holes.
  • the first via 15, the second via 16, the third via 17, the fourth via 18, and the through via 19 are formed.
  • the through via 19 penetrates three layers of the one resin layer 45, the core substrate 40, and the other resin layer 45.
  • the first via 15 is connected to a portion of the first terminal 11 provided on the lower surface 102.
  • the second via 16 is connected to a portion of the first terminal 11 provided on the upper surface 101.
  • the third via 17 is connected to a portion provided on the lower surface 102 of the second terminal 12.
  • the fourth via 18 is connected to a portion of the second terminal 12 provided on the upper surface 101.
  • the thicknesses of the first via 15, the second via 16, the third via 17, and the fourth via 18 are the same. By aligning the thickness of the via, laser processing for forming the via hole can be simplified.
  • the resin layer 45 is further stacked on the already formed resin layer 45 to form a multilayer wiring layer. Thereafter, a first pad 46, a second pad 47, and a plurality of other pads are formed on the lower surface of the lower resin layer 45. A third pad 48, a fourth pad 49, and a plurality of other pads are formed on the upper surface of the upper resin layer 45.
  • the first current path 51 including the first via 15 in the lower resin layer 45 connects the first pad 46 and the first terminal 11 of the multilayer chip capacitor 30.
  • a second current path 52 including the second via 16 in the upper resin layer 45 connects the third pad 48 and the first terminal 11 of the multilayer chip capacitor 30.
  • a third current path 53 including the third via 17 in the lower resin layer 45 connects the second pad 47 and the second terminal 12 of the multilayer chip capacitor 30.
  • a fourth current path 54 including the fourth via 18 in the upper resin layer 45 connects the fourth pad 49 and the second terminal 12 of the multilayer chip capacitor 30.
  • the wiring board according to the second embodiment is used as, for example, an interposer interposed between a mother board and an integrated circuit element.
  • FIG. 7 shows a schematic cross-sectional view of the wiring board, the mother board, and the integrated circuit element according to the second embodiment.
  • An integrated circuit element 70 is mounted on the mother board 60 via the wiring board 50.
  • a plurality of pads 61 are formed on the mounting surface of the mother board 60.
  • a plurality of pads 71 are formed on the lower surface of the integrated circuit element 70.
  • the first pad 46, the second pad 47, and other pads on the lower surface of the wiring board 50 are connected to the pads 61 of the mother board 60 through solder balls.
  • the third pad 48, the fourth pad 49, and other pads on the upper surface of the wiring substrate 50 are connected to the pads 71 of the integrated circuit element 70 through solder balls.
  • the first terminal 11 of the multilayer chip capacitor 30 is connected to the ground pad 61 of the motherboard via the first current path 51 and the first pad 46, and the second current path 52 and the third
  • the pad 48 is connected to the ground pad 71 of the integrated circuit element 70 through the pad 48.
  • the second terminal 12 of the multilayer chip capacitor 30 is connected to the power supply pad 61 of the mother board 60 through the third current path 53 and the second pad 47, and the fourth current path 54 and the 4 is connected to the power supply pad 71 of the integrated circuit element 70 via the pad 49.
  • the first via 15, the second via 16, the third via 17, and the fourth via 18 shown in FIG. 6F are the same as the first via 15 and the second via 16 shown in FIGS. 2A to 2C.
  • the third via 17 and the fourth via 18 have the same configuration. For this reason, stable power supply from the mother board 60 to the integrated circuit element 70 becomes possible.
  • the multilayer chip capacitor unit according to the third embodiment includes a plurality of multilayer chip capacitors according to the first embodiment shown in FIGS. 1A to 4.
  • FIG. 8A shows a schematic cross-sectional view of the multilayer chip capacitor unit according to the third embodiment.
  • the multilayer chip capacitor unit according to the third embodiment includes three multilayer chip capacitors 30 stacked in the height direction.
  • the first terminals 11 of the three multilayer chip capacitors 30 are connected to each other, and the second terminals 12 are connected to each other.
  • the upper and lower multilayer chip capacitors 30 are stacked such that the upper surfaces 101 or the lower surfaces 102 face each other. That is, relatively wide portions of the first terminals 11 are connected to face each other, and narrow portions are connected to face each other.
  • the second terminal 12 relatively wide portions are connected to face each other, and relatively narrow portions are connected to face each other.
  • the three multilayer chip capacitors 30 are electrically connected in parallel.
  • the end surfaces of the first terminals 11 may be connected by arranging the multilayer chip capacitor units shown in FIG. 8A in the horizontal direction. At this time, a relatively wide portion of the first terminal 11 and a relatively narrow portion of the second terminal 12 appear on the uppermost surface of the multilayer chip capacitor unit. On the bottom surface, a relatively narrow portion of the first terminal 11 and a relatively wide portion of the second terminal 12 appear. Furthermore, since the number of multilayer chip capacitors 30 connected in parallel increases, a larger capacitance is realized. This makes it possible to supply more stable power.

Abstract

Disclosed is a laminated chip capacitor wherein a main body includes a first electrode layer, a second electrode layer, and a dielectric layer that is disposed between the first electrode layer and the second electrode layer. In a region of an upper surface of the main body, and in a region of a lower surface of the main body, a first terminal electrically connected to the first electrode layer is provided. In a region of the upper surface of the main body, and in a region of the lower surface of the main body, a second terminal electrically connected to the second electrode layer is provided. A first terminal portion that is provided on the upper surface occupies a larger area than a first terminal portion that is provided on the lower surface, and a second terminal portion that is provided on the lower surface occupies a larger area than a second terminal portion that is provided on the upper surface.

Description

配線基板及び積層チップコンデンサWiring board and multilayer chip capacitor
　本発明は、積層チップコンデンサが埋め込まれた配線基板、及び積層チップコンデンサに関する。 The present invention relates to a wiring board in which a multilayer chip capacitor is embedded, and a multilayer chip capacitor.
　下記の特許文献１に、デカップリング用の積層チップコンデンサユニットが埋め込まれた配線基板が開示されている。積層チップコンデンサユニットは、積層チップコンデンサの外部電極同士を接続して一体化したものである。配線基板の配線と、積層チップコンデンサユニットの外部電極とがビアで電気的に接続される。 The following Patent Document 1 discloses a wiring board in which a multilayer chip capacitor unit for decoupling is embedded. The multilayer chip capacitor unit is formed by connecting and integrating the external electrodes of the multilayer chip capacitor. The wiring of the wiring board and the external electrode of the multilayer chip capacitor unit are electrically connected by vias.
特開２００９－８１１８３号公報JP 2009-81183 A
　積層チップコンデンサは、ほぼ直方体状の外形を有する。一対の外部電極は、積層チップコンデンサの長手方向の両端の端面に設けられるとともに、上面、下面、及び側面の、端面に連続する一部の領域に設けられている。上面及び下面の一部の領域に設けられている外部電極にビアが接触することにより、一対の外部電極が、それぞれ配線基板のグランドパターン及び電源パターンに電気的に接続される。 The multilayer chip capacitor has a substantially rectangular parallelepiped outer shape. The pair of external electrodes are provided on the end faces at both ends in the longitudinal direction of the multilayer chip capacitor, and are provided in a part of the upper surface, the lower surface, and the side surfaces that are continuous with the end faces. A pair of external electrodes are electrically connected to the ground pattern and the power supply pattern of the wiring board, respectively, by contact of the vias with the external electrodes provided in part of the upper and lower surfaces.
　配線基板に実装される集積回路素子に安定的に電源を供給するために、積層チップコンデンサの一方の外部電極とグランドパターンとを接続する電流経路、及び他方の外部電極と電源パターンとを接続する電流経路のインピーダンスを低減することが望まれている。 In order to stably supply power to the integrated circuit element mounted on the wiring board, the current path connecting one external electrode of the multilayer chip capacitor and the ground pattern, and the other external electrode and the power supply pattern are connected. It is desired to reduce the impedance of the current path.
　本発明の第１の観点による配線基板は、
　上面及び下面を有する基板と、
　第１の端子及び第２の端子を含み、前記基板に埋め込まれた積層チップコンデンサと、
　前記基板の下面に設けられている第１のパッド及び第２のパッドと、
　前記基板の上面に設けられている第３のパッド及び第４のパッドと、
　前記第１のパッドと前記第１の端子とを接続する第１の電流経路と、
　前記第３のパッドと前記第１の端子とを接続する第２の電流経路と、
　前記第２のパッドと前記第２の端子とを接続する第３の電流経路と、
　前記第４のパッドと前記第２の端子とを接続する第４の電流経路と
を有し、
　前記積層チップコンデンサは、上面及び下面を有する本体を含み、
　前記第１の端子は、前記本体の上面及び下面の各々の一部の領域に設けられており、
　前記第２の端子は、前記本体の上面及び下面の各々の一部の領域に設けられており、
　前記第１の端子のうち、前記本体の上面に設けられている部分が、前記本体の下面に設けられている部分より広い面積を占め、
　前記第２の端子のうち、前記本体の下面に設けられている部分が、前記本体の上面に設けられている部分より広い面積を占める。 A wiring board according to a first aspect of the present invention provides:
A substrate having an upper surface and a lower surface;
A multilayer chip capacitor including a first terminal and a second terminal and embedded in the substrate;
A first pad and a second pad provided on the lower surface of the substrate;
A third pad and a fourth pad provided on the upper surface of the substrate;
A first current path connecting the first pad and the first terminal;
A second current path connecting the third pad and the first terminal;
A third current path connecting the second pad and the second terminal;
A fourth current path connecting the fourth pad and the second terminal;
The multilayer chip capacitor includes a main body having an upper surface and a lower surface,
The first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body,
The second terminal is provided in a partial region of each of the upper surface and the lower surface of the main body,
Of the first terminal, the portion provided on the upper surface of the main body occupies a larger area than the portion provided on the lower surface of the main body,
Of the second terminal, a portion provided on the lower surface of the main body occupies a larger area than a portion provided on the upper surface of the main body.
　第１の端子のうち、本体の上面に設けられている部分が、本体の下面に設けられている部分より広い面積を占めるため、第２の電流経路を実質的に太くすることが可能である。第２の端子のうち、本体の下面に設けられている部分が、本体の上面に設けられている部分より広い面積を占めるため、第３の電流経路を実質的に太くすることが可能である。これにより、第２の電流経路、及び第３の電流経路の等価直列インダクタンスを小さくすることができる。 Since the portion provided on the upper surface of the main body of the first terminal occupies a larger area than the portion provided on the lower surface of the main body, the second current path can be made substantially thicker. . Of the second terminal, the portion provided on the lower surface of the main body occupies a larger area than the portion provided on the upper surface of the main body, so that the third current path can be made substantially thicker. . Thereby, the equivalent series inductance of the second current path and the third current path can be reduced.
　本発明の第２の観点による配線基板においては、第１の観点による配線基板の構成に加えて、
　前記第１の電流経路が、前記第１の端子のうち、前記本体の下面に設けられている部分に接触する少なくとも１本の第１のビアを含み、
　前記第２の電流経路が、前記第１の端子のうち、前記本体の上面に設けられている部分に接触する複数の第２のビアを含み、
　前記第２のビアの本数が、前記第１のビアの本数より多く、
　前記第３の電流経路が、前記第２の端子のうち、前記本体の下面に設けられている部分に接触する複数の第３のビアを含み、
　前記第４の電流経路が、前記第２の端子のうち、前記本体の上面に設けられている部分に接触する少なくとも１本の第４のビアを含み、
　前記第３のビアの本数が、前記第４のビアの本数より多い。 In the wiring board according to the second aspect of the present invention, in addition to the configuration of the wiring board according to the first aspect,
The first current path includes at least one first via that contacts a portion of the first terminal provided on a lower surface of the main body;
The second current path includes a plurality of second vias in contact with a portion of the first terminal provided on an upper surface of the main body;
The number of second vias is greater than the number of first vias;
The third current path includes a plurality of third vias in contact with a portion of the second terminal provided on the lower surface of the main body;
The fourth current path includes at least one fourth via that contacts a portion of the second terminal provided on the upper surface of the main body;
The number of third vias is greater than the number of fourth vias.
　ビアの本数を増やすことにより、電流経路を実質的に太くすることができる。 • By increasing the number of vias, the current path can be made substantially thicker.
　本発明の第３の観点による配線基板においては、第２の観点による配線基板の構成に加えて、
　前記第１のビア、前記第２のビア、前記第３のビア、及び前記第４のビアが、同一の太さを有する。 In the wiring board according to the third aspect of the present invention, in addition to the configuration of the wiring board according to the second aspect,
The first via, the second via, the third via, and the fourth via have the same thickness.
　ビアの太さを揃えることにより、異なる太さの複数のビアホールを形成する場合に比べて、ビアホール加工を簡素化することができる。 Aligning the thickness of the via can simplify the processing of the via hole as compared with the case where a plurality of via holes having different thicknesses are formed.
　本発明の第４の観点による積層チップコンデンサは、
　第１の電極層、第２の電極層、前記第１の電極層と前記第２の電極層との間に配置された誘電体層を含み、誘電体が露出した上面及び下面が画定された本体と、
　前記上面の一部の領域及び前記下面の一部の領域に設けられ、前記第１の電極層に電気的に接続された第１の端子と、
　前記上面の一部の領域及び前記下面の一部の領域に設けられ、前記第２の電極層に電気的に接続された第２の端子と
を有し、
　前記第１の端子のうち、前記上面に設けられている部分が、前記下面に設けられている部分より広い面積を占め、
　前記第２の端子のうち、前記下面に設けられている部分が、前記上面に設けられている部分より広い面積を占める。 The multilayer chip capacitor according to the fourth aspect of the present invention is:
A first electrode layer; a second electrode layer; and a dielectric layer disposed between the first electrode layer and the second electrode layer, wherein upper and lower surfaces from which the dielectric is exposed are defined. The body,
A first terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the first electrode layer;
A second terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the second electrode layer;
Of the first terminal, the portion provided on the upper surface occupies a larger area than the portion provided on the lower surface,
Of the second terminal, the portion provided on the lower surface occupies a larger area than the portion provided on the upper surface.
　第１の端子のうち、上面に設けられている部分に、下面に設けられている部分より多くのビアを接続することができる。同様に、第２の端子のうち、下面に設けられている部分に、上面に設けられている部分より多くのビアを接続することができる。ビアの本数を多くすることにより、ビアを流れる電気信号に作用する等価直列インダクタンスを小さくすることができる。 Of the first terminal, more vias can be connected to the portion provided on the upper surface than the portion provided on the lower surface. Similarly, more vias than the portion provided on the upper surface can be connected to the portion provided on the lower surface of the second terminal. By increasing the number of vias, the equivalent series inductance acting on the electrical signal flowing through the vias can be reduced.
　本発明の第５の観点による積層チップコンデンサにおいては、第４の観点による積層チップコンデンサの構成に加えて、
　前記本体が、幅方向の寸法より長手方向の寸法の方が長い外形を有し、
　前記第１の端子が、前記本体の上面及び下面の各々の、前記本体の前記長手方向の一方の端面に連続する一部の領域に設けられており、
　前記第２の端子が、前記本体の上面及び下面の各々の、前記本体の前記長手方向の他方の端面に連続する一部の領域に設けられており、
　前記第１の端子のうち、前記本体の上面に設けられている部分の、前記長手方向に関する寸法が、前記本体の下面に設けられている部分の、前記長手方向に関する寸法より長く、
　前記第２の端子のうち、前記本体の下面に設けられている部分の、前記長手方向に関する寸法が、前記本体の上面に設けられている部分の、前記長手方向に関する寸法より長い。 In the multilayer chip capacitor according to the fifth aspect of the present invention, in addition to the structure of the multilayer chip capacitor according to the fourth aspect,
The main body has an outer shape whose dimension in the longitudinal direction is longer than that in the width direction,
The first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body that is continuous with one end surface in the longitudinal direction of the main body,
The second terminal is provided in a partial region of each of the upper surface and the lower surface of the main body that is continuous with the other end surface in the longitudinal direction of the main body,
Of the first terminal, the dimension in the longitudinal direction of the portion provided on the upper surface of the main body is longer than the dimension in the longitudinal direction of the portion provided on the lower surface of the main body,
Of the second terminal, the dimension in the longitudinal direction of the portion provided on the lower surface of the main body is longer than the dimension in the longitudinal direction of the portion provided on the upper surface of the main body.
　長手方向に関する寸法を長くすることにより、長手方向に沿って、より多くのビアを配置することが可能になる。 長 く By increasing the dimension in the longitudinal direction, more vias can be arranged along the longitudinal direction.
　第１の端子のうち、本体の上面に設けられている部分が、本体の下面に設けられている部分より広い面積を占めるため、第２の電流経路を実質的に太くすることが可能である。第２の端子のうち、本体の下面に設けられている部分が、本体の上面に設けられている部分より広い面積を占めるため、第３の電流経路を実質的に太くすることが可能である。これにより、第２の電流経路、及び第３の電流経路の等価直列インダクタンスを小さくすることができる。 Since the portion provided on the upper surface of the main body of the first terminal occupies a larger area than the portion provided on the lower surface of the main body, the second current path can be made substantially thicker. . Of the second terminal, the portion provided on the lower surface of the main body occupies a larger area than the portion provided on the upper surface of the main body, so that the third current path can be made substantially thicker. . Thereby, the equivalent series inductance of the second current path and the third current path can be reduced.
図１Ａ、図１Ｂ、及び図１Ｃは、それぞれ実施例１による積層チップコンデンサの斜視図、平面図、及び底面図である。1A, 1B, and 1C are a perspective view, a plan view, and a bottom view, respectively, of the multilayer chip capacitor according to the first embodiment. 図２Ａは、実施例１による積層チップコンデンサが配線基板に埋め込まれた状態における積層チップコンデンサとビアとの斜視図であり、図２Ｂ及び図２Ｃは、それぞれ積層チップコンデンサとビアとの平面図及び底面図である。2A is a perspective view of the multilayer chip capacitor and the via in a state where the multilayer chip capacitor according to the first embodiment is embedded in the wiring board. FIGS. 2B and 2C are plan views of the multilayer chip capacitor and the via, respectively. It is a bottom view. 図３は、実施例１による積層チップコンデンサが配線基板に埋め込まれた状態の積層チップコンデンサとビアとの断面図である。FIG. 3 is a cross-sectional view of the multilayer chip capacitor and the via in a state where the multilayer chip capacitor according to the first embodiment is embedded in the wiring board. 図４は、積層チップコンデンサ、第１のビア、第２のビア、第３のビア、及び第４のビアの等価回路図である。FIG. 4 is an equivalent circuit diagram of the multilayer chip capacitor, the first via, the second via, the third via, and the fourth via. 図５Ａは、比較例による積層チップコンデンサ、第１のビア、第２のビア、第３のビア、及び第４のビアの斜視図であり、図５Ｂは、その等価回路図である。FIG. 5A is a perspective view of a multilayer chip capacitor, a first via, a second via, a third via, and a fourth via according to a comparative example, and FIG. 5B is an equivalent circuit diagram thereof. 図６Ａ～図６Ｄは、実施例２による配線基板の製造途中段階における断面図である。6A to 6D are cross-sectional views in the middle of manufacturing a wiring board according to the second embodiment. 図６Ｅは、実施例２による配線基板の製造途中段階における断面図であり、図６Ｆは、実施例２による配線基板の断面図である。6E is a cross-sectional view in the middle of manufacturing the wiring board according to the second embodiment, and FIG. 6F is a cross-sectional view of the wiring board according to the second embodiment. 図７は、実施例２による配線基板と、マザーボード及び集積回路素子の概略断面図である。FIG. 7 is a schematic cross-sectional view of the wiring board, the mother board, and the integrated circuit element according to the second embodiment. 図８Ａ及び図８Ｂは、実施例３による積層チップコンデンサユニットの概略断面図である。8A and 8B are schematic cross-sectional views of the multilayer chip capacitor unit according to the third embodiment.
　図１Ａ～図４を参照して、実施例１による積層チップコンデンサについて説明する。 A multilayer chip capacitor according to Example 1 will be described with reference to FIGS. 1A to 4. FIG.
　図１Ａ、図１Ｂ、及び図１Ｃに、それぞれ実施例１による積層チップコンデンサ３０の斜視図、平面図、及び底面図を示す。積層チップコンデンサ３０は、本体１０、第１の端子１１、及び第２の端子１２を含む。本体１０は、ほぼ直方体の外形を有し、幅方向及び高さ方向の寸法より長手方向の寸法の方が長い。本体１０は、長手方向の両端の端面１０４、１０５、上面１０１、下面１０２、及び一対の側面１０３の六面を有する。 1A, 1B, and 1C are a perspective view, a plan view, and a bottom view of the multilayer chip capacitor 30 according to the first embodiment, respectively. The multilayer chip capacitor 30 includes a main body 10, a first terminal 11, and a second terminal 12. The main body 10 has a substantially rectangular parallelepiped outer shape, and the dimension in the longitudinal direction is longer than the dimension in the width direction and the height direction. The main body 10 has six surfaces including end surfaces 104 and 105 at both ends in the longitudinal direction, an upper surface 101, a lower surface 102, and a pair of side surfaces 103.
　第１の端子１１は、一方の端面１０４の全域に設けられているとともに、上面１０１、下面１０２、及び側面１０３の各々の、端面１０４に連続する一部の領域に設けられている。第２の端子１２は、他方の端面１０５の全域に設けられているとともに、上面１０１、下面１０２、及び側面１０３の各々の、端面１０５に連続する一部の領域に設けられている。第１の端子１１及び第２の端子１２のうち、上面１０１及び下面１０２に設けられている部分は、ほぼ長方形または正方形の平面形状を有する（図１Ｂ、図１Ｃ）。第１の端子１１及び第２の端子１２のうち、側面１０３に設けられている部分の平面形状は、２つの内角が直角の台形である。 The first terminal 11 is provided over the entire area of the one end face 104, and is provided in a partial region of the upper face 101, the lower face 102, and the side face 103 that is continuous with the end face 104. The second terminal 12 is provided in the entire region of the other end surface 105, and is provided in a part of the upper surface 101, the lower surface 102, and the side surface 103 that is continuous with the end surface 105. Of the first terminal 11 and the second terminal 12, portions provided on the upper surface 101 and the lower surface 102 have a substantially rectangular or square planar shape (FIGS. 1B and 1C). Of the first terminal 11 and the second terminal 12, the planar shape of the portion provided on the side surface 103 is a trapezoid whose two inner angles are right angles.
　第１の端子１１のうち上面１０１に設けられている部分は、下面１０２に設けられている部分より広い面積を占める。第２の端子１２のうち下面１０２に設けられている部分は、上面１０１に設けられている部分より広い面積を占める。より具体的には、第１の端子１１のうち上面１０１に設けられている部分の、長手方向に関する寸法Ｌ１（図１Ｂ）が、下面１０２に設けられている部分の、長手方向に関する寸法Ｌ２（図１Ｃ）より長い。第２の端子１２のうち下面１０２に設けられている部分の、長手方向に関する寸法Ｌ４（図１Ｃ）は、上面１０１に設けられている部分の、長手方向に関する寸法Ｌ３（図１Ｂ）より長い。 The portion of the first terminal 11 provided on the upper surface 101 occupies a larger area than the portion provided on the lower surface 102. A portion of the second terminal 12 provided on the lower surface 102 occupies a larger area than a portion provided on the upper surface 101. More specifically, the dimension L1 (FIG. 1B) in the longitudinal direction of the portion provided on the upper surface 101 of the first terminal 11 is the dimension L2 in the longitudinal direction of the portion provided in the lower surface 102 (FIG. 1B). Longer than FIG. 1C). The dimension L4 (FIG. 1C) in the longitudinal direction of the portion provided on the lower surface 102 of the second terminal 12 is longer than the dimension L3 (FIG. 1B) in the longitudinal direction of the portion provided on the upper surface 101.
　図２Ａに、実施例１による積層チップコンデンサ３０が配線基板に埋め込まれた状態における積層チップコンデンサ３０とビアとの斜視図を示す。図２Ｂ及び図２Ｃに、それぞれ積層チップコンデンサ３０とビアの平面図及び底面図を示す。 FIG. 2A shows a perspective view of the multilayer chip capacitor 30 and vias in a state where the multilayer chip capacitor 30 according to the first embodiment is embedded in a wiring board. 2B and 2C are a plan view and a bottom view of the multilayer chip capacitor 30 and the via, respectively.
　第１の端子１１のうち、本体１０の下面１０２に設けられている部分に、少なくとも１本の第１のビア１５が接触し、本体１０の上面１０１に設けられている部分に、複数の第２のビア１６が接触する。第２のビア１６の本数は、第１のビア１５の本数より多い。第２の端子１２のうち、本体１０の下面１０２に設けられている部分に、複数の第３のビア１７が接触し、本体１０の上面１０１に設けられている部分に、少なくとも１本の第４のビア１８が接触する。第３のビア１７の本数は、第４のビア１８の本数より多い。図２Ａ～図２Ｃに示した例では、第１のビア１５が２本、第２のビア１６が４本、第３のビア１７が４本、及び第４のビア１８が２本設けられている。 In the first terminal 11, at least one first via 15 is in contact with a portion provided on the lower surface 102 of the main body 10, and a plurality of first vias 15 are provided on a portion provided on the upper surface 101 of the main body 10. Two vias 16 come into contact. The number of second vias 16 is greater than the number of first vias 15. Among the second terminals 12, a plurality of third vias 17 are in contact with a portion provided on the lower surface 102 of the main body 10, and at least one first terminal is provided on a portion provided on the upper surface 101 of the main body 10. Four vias 18 come into contact. The number of third vias 17 is greater than the number of fourth vias 18. In the example shown in FIGS. 2A to 2C, two first vias 15, four second vias 16, four third vias 17, and two fourth vias 18 are provided. Yes.
　２本の第１のビア１５は、本体１０の幅方向に並んで配置されている。同様に、２本の第４のビア１８も、本体１０の幅方向に並んで配置されている。４本の第２のビア１６は、本体１０の長手方向及び幅方向を行方向及び列方向とする２行２列の行列状に配置されている。同様に、４本の第３のビア１７も２行２列の行列状に配置されている。 The two first vias 15 are arranged side by side in the width direction of the main body 10. Similarly, the two fourth vias 18 are also arranged side by side in the width direction of the main body 10. The four second vias 16 are arranged in a matrix of 2 rows and 2 columns in which the longitudinal direction and the width direction of the main body 10 are the row direction and the column direction. Similarly, the four third vias 17 are also arranged in a matrix of 2 rows and 2 columns.
　実施例１では、第２のビア１６を第１のビア１５より多くし、第３のビア１７を第４のビア１８より多くするのに適した構造が採用されている。すなわち、第１の端子１１のうち上面１０１に設けられている部分の面積が、下面１０２に設けられている部分の面積より広く、かつ第２の端子１２のうち下面１０２に設けられている部分の面積が、上面１０１に設けられている部分の面積より広い。 In the first embodiment, a structure suitable for making the second via 16 larger than the first via 15 and making the third via 17 larger than the fourth via 18 is adopted. That is, the area of the portion provided on the upper surface 101 of the first terminal 11 is larger than the area of the portion provided on the lower surface 102 and the portion provided on the lower surface 102 of the second terminal 12. Is larger than the area of the portion provided on the upper surface 101.
　第１の端子１１のうち上面１０１に設けられている部分に、本体１０の長手方向に複数の第２のビア１６を並べて配置するために、寸法Ｌ１を寸法Ｌ２の１．５倍以上とし、寸法Ｌ４を寸法Ｌ３の１．５倍以上とすることが好ましい。 In order to arrange a plurality of second vias 16 side by side in the longitudinal direction of the main body 10 in a portion provided on the upper surface 101 of the first terminal 11, the dimension L1 is 1.5 times or more the dimension L2, It is preferable that the dimension L4 is 1.5 times or more the dimension L3.
　図３に、実施例１による積層チップコンデンサ３０が配線基板に埋め込まれた状態の積層チップコンデンサ３０とビアとの断面図を示す。 FIG. 3 shows a cross-sectional view of the multilayer chip capacitor 30 and vias in a state where the multilayer chip capacitor 30 according to the first embodiment is embedded in the wiring board.
　積層チップコンデンサ３０の本体１０内に、複数の第１の電極層２１と、複数の第２の電極層２２とが、交互に積み重ねられている。第１の電極層２１と第２の電極層２２との間に、誘電体層２３が配置されている。本体１０の上面１０１及び下面１０２には、誘電体が露出している。内部の誘電体層２３、上面１０１及び下面１０２に露出する誘電体には、例えばチタン酸バリウム等の誘電体セラミックが用いられる。第１の電極層２１及び第２の電極層２２には、例えばＡｇ、Ｃｕ、Ｎｉ等を主成分とする金属が用いられる。 A plurality of first electrode layers 21 and a plurality of second electrode layers 22 are alternately stacked in the main body 10 of the multilayer chip capacitor 30. A dielectric layer 23 is disposed between the first electrode layer 21 and the second electrode layer 22. A dielectric is exposed on the upper surface 101 and the lower surface 102 of the main body 10. A dielectric ceramic such as barium titanate is used as the dielectric exposed on the inner dielectric layer 23, the upper surface 101, and the lower surface 102, for example. For the first electrode layer 21 and the second electrode layer 22, for example, a metal whose main component is Ag, Cu, Ni, or the like is used.
　第１の電極層２１の端部が、一方の端面１０４に露出しており、第２の電極層２２の端部が、他方の端面１０５に露出している。第１の電極層２１が、端面１０４に露出した端部において、第１の端子１１に接続されている。第２の電極層２２が、端面１０５に露出した端部において、第２の電極層２２に接続されている。 The end of the first electrode layer 21 is exposed on one end face 104, and the end of the second electrode layer 22 is exposed on the other end face 105. The first electrode layer 21 is connected to the first terminal 11 at the end exposed at the end face 104. The second electrode layer 22 is connected to the second electrode layer 22 at the end exposed at the end face 105.
　第１の端子１１のうち、本体１０の下面１０２に設けられている部分に、少なくとも１本の第１のビア１５が接触しており、上面１０１に設けられている部分に、複数の第２のビア１６が接触している。第２の端子１２のうち、本体１０の下面１０２に設けられている部分に、複数の第３のビア１７が接触しており、上面１０１に設けられている部分に、少なくとも１本の第４のビア１８が接触している。 In the first terminal 11, at least one first via 15 is in contact with a portion provided on the lower surface 102 of the main body 10, and a plurality of second vias are provided on a portion provided on the upper surface 101. Vias 16 are in contact. In the second terminal 12, a plurality of third vias 17 are in contact with a portion provided on the lower surface 102 of the main body 10, and at least one fourth terminal is provided on a portion provided on the upper surface 101. Vias 18 are in contact.
　一例として、第１のビア１５及び第３のビア１７が、それぞれマザーボードのグランドパターン及び電源パターンに接続される。第２のビア１６及び第４のビア１８が、それぞれ集積回路素子のグランド端子ＧＮＤ及び電源端子ＶＤＤに接続される。 As an example, the first via 15 and the third via 17 are connected to the ground pattern and the power supply pattern of the motherboard, respectively. The second via 16 and the fourth via 18 are connected to the ground terminal GND and the power supply terminal VDD of the integrated circuit element, respectively.
　図４に、積層チップコンデンサ３０、第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８の等価回路図を示す。第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８の各々が、等価直列インダクタンスＬを有する。積層チップコンデンサ３０が、キャパシタンスと等価直列インダクタンスとの直列回路で表される。第１のビア１５及び第４のビア１８は、それぞれ２つの等価直列インダクタンスＬの並列回路で表される。第２のビア１６及び第３のビア１７は、それぞれ４つの等価直列インダクタンスＬの並列回路で表される。 FIG. 4 shows an equivalent circuit diagram of the multilayer chip capacitor 30, the first via 15, the second via 16, the third via 17, and the fourth via 18. Each of the first via 15, the second via 16, the third via 17, and the fourth via 18 has an equivalent series inductance L. The multilayer chip capacitor 30 is represented by a series circuit of a capacitance and an equivalent series inductance. The first via 15 and the fourth via 18 are each represented by a parallel circuit of two equivalent series inductances L. The second via 16 and the third via 17 are each represented by a parallel circuit of four equivalent series inductances L.
　図５Ａに、比較例による積層チップコンデンサ３０、第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８の斜視図を示す。比較例においては、第１の端子１１のうち、本体１０の上面１０１に設けられた部分、及び下面１０２に設けられた部分が、実施例１による積層チップコンデンサ３０の第１の端子１１のうち、下面１０２に設けられた部分（図２Ｃ）と同一の寸法を有する。同様に、第２の端子１２のうち、本体１０の下面１０２に設けられた部分、及び上面１０１に設けられた部分が、実施例１による積層チップコンデンサ３０の第２の端子１２のうち、上面１０１に設けられた部分（図２Ｂ）と同一の寸法を有する。このため、第１の端子１１のうち、本体１０の上面１０１に設けられた部分に接触する第２のビア１６の本数を、第１のビア１５の本数より多くすることが困難である。同様に、第３のビア１７の本数を第４のビア１８の本数より多くすることが困難である。その結果、比較例においては、第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８が、それぞれ２本ずつ配置されている。 FIG. 5A is a perspective view of the multilayer chip capacitor 30, the first via 15, the second via 16, the third via 17, and the fourth via 18 according to the comparative example. In the comparative example, the portion provided on the upper surface 101 of the main body 10 and the portion provided on the lower surface 102 of the first terminal 11 are included in the first terminal 11 of the multilayer chip capacitor 30 according to the first embodiment. , Having the same dimensions as the portion (FIG. 2C) provided on the lower surface 102. Similarly, the portion provided on the lower surface 102 of the main body 10 and the portion provided on the upper surface 101 of the second terminal 12 are the upper surfaces of the second terminals 12 of the multilayer chip capacitor 30 according to the first embodiment. 101 has the same dimensions as the portion provided in 101 (FIG. 2B). For this reason, it is difficult to increase the number of the second vias 16 that are in contact with the portion of the first terminal 11 provided on the upper surface 101 of the main body 10 more than the number of the first vias 15. Similarly, it is difficult to increase the number of third vias 17 than the number of fourth vias 18. As a result, in the comparative example, two each of the first via 15, the second via 16, the third via 17, and the fourth via 18 are arranged.
　図５Ｂに、積層チップコンデンサ及びビアの等価回路図を示す。第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８が、それぞれ２本の等価直列インダクタンスＬで表される。 FIG. 5B shows an equivalent circuit diagram of the multilayer chip capacitor and the via. The first via 15, the second via 16, the third via 17, and the fourth via 18 are each represented by two equivalent series inductances L.
　実施例１では、図４に示すように、第２のビア１６及び第３のビア１７が、それぞれ４本の等価直列インダクタンスＬの並列回路で表される。このため、実施例１の構成を採用することにより、マザーボードのグランドパターンと、集積回路素子のグランド端子ＧＮＤとを接続する電流経路の等価直列インダクタンスを低減することができる。同様に、マザーボードの電源パターンと集積回路素子の電源端子ＶＤＤとを接続する電流経路の等価直列インダクタンスを低減することができる。その結果、マザーボードから集積回路素子への、より安定した電源の供給が可能になる。 In Example 1, as shown in FIG. 4, the second via 16 and the third via 17 are each represented by a parallel circuit of four equivalent series inductances L. For this reason, by adopting the configuration of the first embodiment, it is possible to reduce the equivalent series inductance of the current path connecting the ground pattern of the motherboard and the ground terminal GND of the integrated circuit element. Similarly, the equivalent series inductance of the current path connecting the power supply pattern of the motherboard and the power supply terminal VDD of the integrated circuit element can be reduced. As a result, more stable power supply from the mother board to the integrated circuit element can be achieved.
　さらに、実施例１においては、第２のビア１６と第４のビア１８との最小間隔（図２Ｂ）が、比較例における第２のビア１６と第４のビア１８との最小間隔（図５Ａ）より狭い。同様に、第３のビア１７と第１のビア１５との最小間隔（図２Ｃ）が、比較例における第３のビア１７と第１のビア１５との最小間隔（図５Ａ）より狭い。言い換えると、実施例１の構成（図２Ａ）と比較例の構成（図５Ａ）とを比較すると、実施例１の構成を採用することにより、第１のビア１５と第３のビア１７との最小間隔、及び第２のビア１６と第４のビア１８との最小間隔を狭くすることが可能である。 Furthermore, in Example 1, the minimum distance (FIG. 2B) between the second via 16 and the fourth via 18 is the minimum distance (FIG. 5A) between the second via 16 and the fourth via 18 in the comparative example. Narrower. Similarly, the minimum distance (FIG. 2C) between the third via 17 and the first via 15 is narrower than the minimum distance (FIG. 5A) between the third via 17 and the first via 15 in the comparative example. In other words, when the configuration of the first embodiment (FIG. 2A) is compared with the configuration of the comparative example (FIG. 5A), the configuration of the first embodiment adopts the configuration of the first via 15 and the third via 17. It is possible to reduce the minimum interval and the minimum interval between the second via 16 and the fourth via 18.
　このため、第１のビア１５を流れる電気信号による磁束と、第３のビア１７を逆方向に流れる電気信号による磁束とが、効率的に打ち消し合う。同様に、第２のビア１６を流れる電気信号による磁束と、第４のビア１８を逆方向に流れる電気信号による磁束とが、効率的に打ち消し合う。磁束が打ち消し合うことにより、グランド側の電流経路及び電源側の電流経路に発生する合成の等価直列インダクタンスが低減される。その結果、マザーボードから集積回路素子への、より安定した電源の供給が可能になる。 For this reason, the magnetic flux due to the electrical signal flowing through the first via 15 and the magnetic flux due to the electrical signal flowing in the reverse direction through the third via 17 efficiently cancel each other. Similarly, the magnetic flux due to the electrical signal flowing through the second via 16 and the magnetic flux due to the electrical signal flowing in the reverse direction through the fourth via 18 effectively cancel each other. By canceling out the magnetic flux, the combined equivalent series inductance generated in the current path on the ground side and the current path on the power supply side is reduced. As a result, more stable power supply from the mother board to the integrated circuit element can be achieved.
　実施例１においては、第１の端子１１及び第２の端子１２の、上面１０１に設けられた部分を比較すると、第２の端子１２が第１の端子１１より小さい。その反対に、下面１０２に設けられた部分を比較すると、第１の端子１１が第２の端子１２より小さい。このように、第１の端子１１及び第２の端子１２の一方を他方より小さくすることにより、両者の間隔が過度に狭くなることを防止できる。その結果、短絡故障の発生を抑制することができる。 In Example 1, when the portions of the first terminal 11 and the second terminal 12 provided on the upper surface 101 are compared, the second terminal 12 is smaller than the first terminal 11. On the contrary, when the portion provided on the lower surface 102 is compared, the first terminal 11 is smaller than the second terminal 12. Thus, by making one of the first terminal 11 and the second terminal 12 smaller than the other, it is possible to prevent the distance between them from becoming excessively narrow. As a result, occurrence of a short circuit failure can be suppressed.
　次に、図６Ａ～図６Ｆ及び図７を参照して、実施例２による配線基板について説明する。図６Ａ～図６Ｅは、製造途中段階における配線基板の断面図を示し、図６Ｆは、実施例２による配線基板の断面図を示す。 Next, a wiring board according to the second embodiment will be described with reference to FIGS. 6A to 6F and FIG. 6A to 6E are cross-sectional views of the wiring board in the middle of manufacturing, and FIG. 6F is a cross-sectional view of the wiring board according to the second embodiment.
　図６Ａに示すように、キャビティ４１が設けられたコア基板４０を準備する。キャビティ４１は、コア基板４０を厚さ方向に貫通している。コア基板４０の一方の面に粘着シート４２が貼付されている。粘着シート４２は、キャビティ４１の一方の開口部を塞ぎ、キャビティ４１の底面を構成する。キャビティ４１内に、実施例１による積層チップコンデンサ３０を、下面１０２が粘着シート４２と対向する姿勢で収容する。第１の端子１１及び第２の端子１２のうち下面１０２に設けられている部分が、粘着シート４２に接着される。上面１０１に設けられている部分の上面は、コア基板４０の上面とほぼ同一の高さに位置する。 As shown in FIG. 6A, a core substrate 40 provided with a cavity 41 is prepared. The cavity 41 penetrates the core substrate 40 in the thickness direction. An adhesive sheet 42 is attached to one surface of the core substrate 40. The adhesive sheet 42 closes one opening of the cavity 41 and constitutes the bottom surface of the cavity 41. The multilayer chip capacitor 30 according to the first embodiment is accommodated in the cavity 41 with the lower surface 102 facing the adhesive sheet 42. Of the first terminal 11 and the second terminal 12, a portion provided on the lower surface 102 is bonded to the adhesive sheet 42. The upper surface of the portion provided on the upper surface 101 is located at substantially the same height as the upper surface of the core substrate 40.
　図６Ｂに示すように、キャビティ４１内に、熱硬化性樹脂からなる充填材４３を充填する。その後、充填材４３を加熱して硬化させる。充填材４３の硬化後、粘着シート４２をコア基板４０から剥離する。図６Ｃに、粘着シート４２を剥離した後のコア基板４０及び積層チップコンデンサ３０の断面図を示す。積層チップコンデンサ３０は、充填材４３によってコア基板４０に支持される。 As shown in FIG. 6B, the cavity 41 is filled with a filler 43 made of a thermosetting resin. Thereafter, the filler 43 is heated and cured. After the filler 43 is cured, the adhesive sheet 42 is peeled off from the core substrate 40. FIG. 6C shows a cross-sectional view of the core substrate 40 and the multilayer chip capacitor 30 after the adhesive sheet 42 is peeled off. The multilayer chip capacitor 30 is supported on the core substrate 40 by the filler 43.
　図６Ｄに示すように、コア基板４０、積層チップコンデンサ３０、及び充填材４３の両面に、ビルドアップ用の樹脂層４５を形成する。図６Ｅに示すように、コア基板４０及び樹脂層４５に複数のビアホール及び複数のスルーホールを形成する。ビアホール及びスルーホールの形成には、レーザ加工を用いることができる。ビアホール及びスルーホール内に導電部材を充填することにより、第１のビア１５、第２のビア１６、第３のビア１７、第４のビア１８、及び貫通ビア１９を形成する。貫通ビア１９は、一方の樹脂層４５、コア基板４０、及び他方の樹脂層４５の３層を貫通する。 6D, a build-up resin layer 45 is formed on both surfaces of the core substrate 40, the multilayer chip capacitor 30, and the filler 43. As shown in FIG. 6E, a plurality of via holes and a plurality of through holes are formed in the core substrate 40 and the resin layer 45. Laser processing can be used to form via holes and through holes. By filling the via hole and the through hole with a conductive member, the first via 15, the second via 16, the third via 17, the fourth via 18, and the through via 19 are formed. The through via 19 penetrates three layers of the one resin layer 45, the core substrate 40, and the other resin layer 45.
　第１のビア１５は、第１の端子１１のうち下面１０２に設けられている部分に接続される。第２のビア１６は、第１の端子１１のうち上面１０１に設けられている部分に接続される。第３のビア１７は、第２の端子１２のうち下面１０２に設けられている部分に接続される。第４のビア１８は、第２の端子１２のうち上面１０１に設けられている部分に接続される。第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８の太さは同一である。ビアの太さを揃えることにより、ビアホール形成のためのレーザ加工を簡素化することができる。 The first via 15 is connected to a portion of the first terminal 11 provided on the lower surface 102. The second via 16 is connected to a portion of the first terminal 11 provided on the upper surface 101. The third via 17 is connected to a portion provided on the lower surface 102 of the second terminal 12. The fourth via 18 is connected to a portion of the second terminal 12 provided on the upper surface 101. The thicknesses of the first via 15, the second via 16, the third via 17, and the fourth via 18 are the same. By aligning the thickness of the via, laser processing for forming the via hole can be simplified.
　図６Ｆに示すように、既に形成されている樹脂層４５に、さらに樹脂層４５を積み重ね、多層配線層を形成する。その後、下側の樹脂層４５の下面に第１のパッド４６、第２のパッド４７、及びその他の複数のパッドを形成する。上側の樹脂層４５の上面に第３のパッド４８、第４のパッド４９、及びその他の複数のパッドを形成する。 As shown in FIG. 6F, the resin layer 45 is further stacked on the already formed resin layer 45 to form a multilayer wiring layer. Thereafter, a first pad 46, a second pad 47, and a plurality of other pads are formed on the lower surface of the lower resin layer 45. A third pad 48, a fourth pad 49, and a plurality of other pads are formed on the upper surface of the upper resin layer 45.
　下側の樹脂層４５内の第１のビア１５を含む第１の電流経路５１が、第１のパッド４６と、積層チップコンデンサ３０の第１の端子１１とを接続する。上側の樹脂層４５内の第２のビア１６を含む第２の電流経路５２が、第３のパッド４８と、積層チップコンデンサ３０の第１の端子１１とを接続する。下側の樹脂層４５内の第３のビア１７を含む第３の電流経路５３が、第２のパッド４７と、積層チップコンデンサ３０の第２の端子１２とを接続する。上側の樹脂層４５内の第４のビア１８を含む第４の電流経路５４が、第４のパッド４９と、積層チップコンデンサ３０の第２の端子１２とを接続する。下側の樹脂層４５の下面の一部のパッドは、貫通ビア１９を介して、上側の樹脂層４５の上面のパッドに接続されている。 The first current path 51 including the first via 15 in the lower resin layer 45 connects the first pad 46 and the first terminal 11 of the multilayer chip capacitor 30. A second current path 52 including the second via 16 in the upper resin layer 45 connects the third pad 48 and the first terminal 11 of the multilayer chip capacitor 30. A third current path 53 including the third via 17 in the lower resin layer 45 connects the second pad 47 and the second terminal 12 of the multilayer chip capacitor 30. A fourth current path 54 including the fourth via 18 in the upper resin layer 45 connects the fourth pad 49 and the second terminal 12 of the multilayer chip capacitor 30. Some pads on the lower surface of the lower resin layer 45 are connected to pads on the upper surface of the upper resin layer 45 through the through vias 19.
　実施例２による配線基板は、例えばマザーボードと集積回路素子との間に介在するインターポーザとして利用される。 The wiring board according to the second embodiment is used as, for example, an interposer interposed between a mother board and an integrated circuit element.
　図７に、実施例２による配線基板と、マザーボード及び集積回路素子の概略断面図を示す。マザーボード６０に配線基板５０を介して集積回路素子７０が実装されている。マザーボード６０の実装面に、複数のパッド６１が形成されている。集積回路素子７０の下面に複数のパッド７１が形成されている。配線基板５０の下面の第１のパッド４６、第２のパッド４７、及びその他のパッドが、半田ボールを介してマザーボード６０のパッド６１に接続される。配線基板５０の上面の第３のパッド４８、第４のパッド４９、及びその他のパッドが、半田ボールを介して集積回路素子７０のパッド７１に接続される。 FIG. 7 shows a schematic cross-sectional view of the wiring board, the mother board, and the integrated circuit element according to the second embodiment. An integrated circuit element 70 is mounted on the mother board 60 via the wiring board 50. A plurality of pads 61 are formed on the mounting surface of the mother board 60. A plurality of pads 71 are formed on the lower surface of the integrated circuit element 70. The first pad 46, the second pad 47, and other pads on the lower surface of the wiring board 50 are connected to the pads 61 of the mother board 60 through solder balls. The third pad 48, the fourth pad 49, and other pads on the upper surface of the wiring substrate 50 are connected to the pads 71 of the integrated circuit element 70 through solder balls.
　積層チップコンデンサ３０の第１の端子１１が、第１の電流経路５１及び第１のパッド４６を介して、マザーボードのグランド用のパッド６１に接続されるとともに、第２の電流経路５２及び第３のパッド４８を介して、集積回路素子７０のグランド用のパッド７１に接続される。積層チップコンデンサ３０の第２の端子１２が、第３の電流経路５３及び第２のパッド４７を介して、マザーボード６０の電源用のパッド６１に接続されるとともに、第４の電流経路５４及び第４のパッド４９を介して、集積回路素子７０の電源用のパッド７１に接続される。 The first terminal 11 of the multilayer chip capacitor 30 is connected to the ground pad 61 of the motherboard via the first current path 51 and the first pad 46, and the second current path 52 and the third The pad 48 is connected to the ground pad 71 of the integrated circuit element 70 through the pad 48. The second terminal 12 of the multilayer chip capacitor 30 is connected to the power supply pad 61 of the mother board 60 through the third current path 53 and the second pad 47, and the fourth current path 54 and the 4 is connected to the power supply pad 71 of the integrated circuit element 70 via the pad 49.
　図６Ｆに示した第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８が、図２Ａ～図２Ｃに示した第１のビア１５、第２のビア１６、第３のビア１７、及び第４のビア１８と同様の構成とされている。このため、マザーボード６０から集積回路素子７０への安定した電源の供給が可能になる。 The first via 15, the second via 16, the third via 17, and the fourth via 18 shown in FIG. 6F are the same as the first via 15 and the second via 16 shown in FIGS. 2A to 2C. The third via 17 and the fourth via 18 have the same configuration. For this reason, stable power supply from the mother board 60 to the integrated circuit element 70 becomes possible.
　次に、図８Ａを参照して、実施例３による積層チップコンデンサユニットについて説明する。実施例３による積層チップコンデンサユニットは、図１Ａ～図４に示した実施例１による積層チップコンデンサを複数個含む。 Next, the multilayer chip capacitor unit according to the third embodiment will be described with reference to FIG. 8A. The multilayer chip capacitor unit according to the third embodiment includes a plurality of multilayer chip capacitors according to the first embodiment shown in FIGS. 1A to 4.
　図８Ａに、実施例３による積層チップコンデンサユニットの概略断面図を示す。実施例３による積層チップコンデンサユニットは、高さ方向に積み重ねられた３個の積層チップコンデンサ３０で構成される。３個の積層チップコンデンサ３０の第１の端子１１同士が接続され、第２の端子１２同士が接続される。上下の２つの積層チップコンデンサ３０は、上面１０１同士、または下面１０２同士が対向する姿勢で積み重ねられている。すなわち、第１の端子１１の相対的に広い部分同士が対向して接続され、狭い部分同士が対向して接続される。第２の端子１２においても、同様に、相対的に広い部分同士が対向して接続され、相対的に狭い部分同士が対向して接続される。３個の積層チップコンデンサ３０は、電気的には並列に接続される。 FIG. 8A shows a schematic cross-sectional view of the multilayer chip capacitor unit according to the third embodiment. The multilayer chip capacitor unit according to the third embodiment includes three multilayer chip capacitors 30 stacked in the height direction. The first terminals 11 of the three multilayer chip capacitors 30 are connected to each other, and the second terminals 12 are connected to each other. The upper and lower multilayer chip capacitors 30 are stacked such that the upper surfaces 101 or the lower surfaces 102 face each other. That is, relatively wide portions of the first terminals 11 are connected to face each other, and narrow portions are connected to face each other. Similarly, in the second terminal 12, relatively wide portions are connected to face each other, and relatively narrow portions are connected to face each other. The three multilayer chip capacitors 30 are electrically connected in parallel.
　奇数個の積層チップコンデンサ３０を積み重ねる場合、積層チップコンデンサユニットの最も上の面には、第１の端子１１の相対的に広い部分と、第２の端子１２の相対的に狭い部分とが現れる。最も下の面には、第１の端子１１の相対的に狭い部分と、第２の端子１２の相対的に広い部分とが現れる。このため、実施例３による積層チップコンデンサユニットにおいては、実施例１と同様のビア配置を採用することが可能である。さらに、複数の積層チップコンデンサ３０を並列に接続することにより、大きなキャパシタンスを実現することができる。このため、より安定した電源の供給が可能になる。 When an odd number of multilayer chip capacitors 30 are stacked, a relatively wide portion of the first terminal 11 and a relatively narrow portion of the second terminal 12 appear on the uppermost surface of the multilayer chip capacitor unit. . On the bottom surface, a relatively narrow portion of the first terminal 11 and a relatively wide portion of the second terminal 12 appear. For this reason, in the multilayer chip capacitor unit according to the third embodiment, the same via arrangement as that of the first embodiment can be adopted. Furthermore, a large capacitance can be realized by connecting a plurality of multilayer chip capacitors 30 in parallel. This makes it possible to supply more stable power.
　図８Ｂに示すように、図８Ａに示した積層チップコンデンサユニットを横方向に並べて、第１の端子１１の端面同士を接続してもよい。このとき、積層チップコンデンサユニットの最も上の面に、第１の端子１１の相対的に広い部分と、第２の端子１２の相対的に狭い部分とが現れる。最も下の面には、第１の端子１１の相対的に狭い部分と、第２の端子１２の相対的に広い部分とが現れる。さらに、並列接続される積層チップコンデンサ３０の個数が多くなるため、より大きなキャパシタンスが実現される。このため、より安定した電源の供給が可能になる。 As shown in FIG. 8B, the end surfaces of the first terminals 11 may be connected by arranging the multilayer chip capacitor units shown in FIG. 8A in the horizontal direction. At this time, a relatively wide portion of the first terminal 11 and a relatively narrow portion of the second terminal 12 appear on the uppermost surface of the multilayer chip capacitor unit. On the bottom surface, a relatively narrow portion of the first terminal 11 and a relatively wide portion of the second terminal 12 appear. Furthermore, since the number of multilayer chip capacitors 30 connected in parallel increases, a larger capacitance is realized. This makes it possible to supply more stable power.
　各実施例は例示であり、異なる実施例で示した構成の部分的な置換または組み合わせが可能であることは言うまでもない。複数の実施例の同様の構成による同様の作用効果については実施例ごとには逐次言及しない。さらに、本発明は上述の実施例に制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。 Each example is an exemplification, and needless to say, partial replacement or combination of configurations shown in different examples is possible. About the same effect by the same composition of a plurality of examples, it does not refer to every example one by one. Furthermore, the present invention is not limited to the embodiments described above. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
１０　本体
１１　第１の端子
１２　第２の端子
１５　第１のビア
１６　第２のビア
１７　第３のビア
１８　第４のビア
１９　貫通ビア
２１　第１の電極層
２２　第２の電極層
２３　誘電体層
３０　積層チップコンデンサ
４０　コア基板
４１　キャビティ
４２　粘着シート
４３　充填材
４５　樹脂層
４６　第１のパッド
４７　第２のパッド
４８　第３のパッド
４９　第４のパッド
５０　配線基板
５１　第１の電流経路
５２　第２の電流経路
５３　第３の電流経路
５４　第４の電流経路
６０　マザーボード
６１　パッド
７０　集積回路素子
７１　パッド
１０１　上面
１０２　下面
１０３　側面
１０４、１０５　端面 DESCRIPTION OF SYMBOLS 10 Main body 11 1st terminal 12 2nd terminal 15 1st via 16 2nd via 17 3rd via 18 4th via 19 Through-via 21 1st electrode layer 22 2nd electrode layer 23 Dielectric Layer 30 Multilayer chip capacitor 40 Core substrate 41 Cavity 42 Adhesive sheet 43 Filler 45 Resin layer 46 First pad 47 Second pad 48 Third pad 49 Fourth pad 50 Wiring board 51 First current path 52 First Second current path 53 Third current path 54 Fourth current path 60 Motherboard 61 Pad 70 Integrated circuit element 71 Pad 101 Upper surface 102 Lower surface 103 Side surface 104, 105 End surface

Claims (5)

  1. 　上面及び下面を有する基板と、
    　第１の端子及び第２の端子を含み、前記基板に埋め込まれた積層チップコンデンサと、
    　前記基板の下面に設けられている第１のパッド及び第２のパッドと、
    　前記基板の上面に設けられている第３のパッド及び第４のパッドと、
    　前記第１のパッドと前記第１の端子とを接続する第１の電流経路と、
    　前記第３のパッドと前記第１の端子とを接続する第２の電流経路と、
    　前記第２のパッドと前記第２の端子とを接続する第３の電流経路と、
    　前記第４のパッドと前記第２の端子とを接続する第４の電流経路と
    を有し、
    　前記積層チップコンデンサは、上面及び下面を有する本体を含み、
    　前記第１の端子は、前記本体の上面及び下面の各々の一部の領域に設けられており、
    　前記第２の端子は、前記本体の上面及び下面の各々の一部の領域に設けられており、
    　前記第１の端子のうち、前記本体の上面に設けられている部分が、前記本体の下面に設けられている部分より広い面積を占め、
    　前記第２の端子のうち、前記本体の下面に設けられている部分が、前記本体の上面に設けられている部分より広い面積を占める配線基板。     A substrate having an upper surface and a lower surface;
    A multilayer chip capacitor including a first terminal and a second terminal and embedded in the substrate;
    A first pad and a second pad provided on the lower surface of the substrate;
    A third pad and a fourth pad provided on the upper surface of the substrate;
    A first current path connecting the first pad and the first terminal;
    A second current path connecting the third pad and the first terminal;
    A third current path connecting the second pad and the second terminal;
    A fourth current path connecting the fourth pad and the second terminal;
    The multilayer chip capacitor includes a main body having an upper surface and a lower surface,
    The first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body,
    The second terminal is provided in a partial region of each of the upper surface and the lower surface of the main body,
    Of the first terminal, the portion provided on the upper surface of the main body occupies a larger area than the portion provided on the lower surface of the main body,
    A wiring board in which a portion of the second terminal provided on the lower surface of the main body occupies a larger area than a portion provided on the upper surface of the main body.
  2. 　前記第１の電流経路は、前記第１の端子のうち、前記本体の下面に設けられている部分に接触する少なくとも１本の第１のビアを含み、
    　前記第２の電流経路は、前記第１の端子のうち、前記本体の上面に設けられている部分に接触する複数の第２のビアを含み、
    　前記第２のビアの本数は、前記第１のビアの本数より多く、
    　前記第３の電流経路は、前記第２の端子のうち、前記本体の下面に設けられている部分に接触する複数の第３のビアを含み、
    　前記第４の電流経路は、前記第２の端子のうち、前記本体の上面に設けられている部分に接触する少なくとも１本の第４のビアを含み、
    　前記第３のビアの本数は、前記第４のビアの本数より多い請求項１に記載の配線基板。     The first current path includes at least one first via that contacts a portion of the first terminal provided on the lower surface of the main body,
    The second current path includes a plurality of second vias in contact with a portion of the first terminal provided on the upper surface of the main body,
    The number of the second vias is greater than the number of the first vias,
    The third current path includes a plurality of third vias in contact with a portion of the second terminal provided on the lower surface of the main body,
    The fourth current path includes at least one fourth via that contacts a portion of the second terminal provided on the upper surface of the main body,
    The wiring board according to claim 1, wherein the number of the third vias is larger than the number of the fourth vias.
  3. 　前記第１のビア、前記第２のビア、前記第３のビア、及び前記第４のビアは、同一の太さを有する請求項２に記載の配線基板。 3. The wiring board according to claim 2, wherein the first via, the second via, the third via, and the fourth via have the same thickness.
  4. 　第１の電極層、第２の電極層、前記第１の電極層と前記第２の電極層との間に配置された誘電体層を含み、誘電体が露出した上面及び下面が画定された本体と、
    　前記上面の一部の領域及び前記下面の一部の領域に設けられ、前記第１の電極層に電気的に接続された第１の端子と、
    　前記上面の一部の領域及び前記下面の一部の領域に設けられ、前記第２の電極層に電気的に接続された第２の端子と
    を有し、
    　前記第１の端子のうち、前記上面に設けられている部分が、前記下面に設けられている部分より広い面積を占め、
    　前記第２の端子のうち、前記下面に設けられている部分が、前記上面に設けられている部分より広い面積を占める積層チップコンデンサ。     A first electrode layer; a second electrode layer; and a dielectric layer disposed between the first electrode layer and the second electrode layer, wherein upper and lower surfaces from which the dielectric is exposed are defined. The body,
    A first terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the first electrode layer;
    A second terminal provided in a partial region of the upper surface and a partial region of the lower surface and electrically connected to the second electrode layer;
    Of the first terminal, the portion provided on the upper surface occupies a larger area than the portion provided on the lower surface,
    A multilayer chip capacitor in which a portion provided on the lower surface of the second terminal occupies a larger area than a portion provided on the upper surface.
  5. 　前記本体は、幅方向の寸法より長手方向の寸法の方が長い外形を有し、
    　前記第１の端子は、前記本体の上面及び下面の各々の、前記本体の前記長手方向の一方の端面に連続する一部の領域に設けられており、
    　前記第２の端子は、前記本体の上面及び下面の各々の、前記本体の前記長手方向の他方の端面に連続する一部の領域に設けられており、
    　前記第１の端子のうち、前記本体の上面に設けられている部分の、前記長手方向に関する寸法が、前記本体の下面に設けられている部分の、前記長手方向に関する寸法より長く、
    　前記第２の端子のうち、前記本体の下面に設けられている部分の、前記長手方向に関する寸法が、前記本体の上面に設けられている部分の、前記長手方向に関する寸法より長い請求項４に記載の積層チップコンデンサ。
          The main body has an outer shape in which the dimension in the longitudinal direction is longer than the dimension in the width direction,
    The first terminal is provided in a partial region of each of the upper surface and the lower surface of the main body that is continuous with one end surface in the longitudinal direction of the main body,
    The second terminal is provided in each of the upper surface and the lower surface of the main body in a partial region that is continuous with the other end surface in the longitudinal direction of the main body,
    Of the first terminal, the dimension in the longitudinal direction of the portion provided on the upper surface of the main body is longer than the dimension in the longitudinal direction of the portion provided on the lower surface of the main body,
    5. The dimension of the portion of the second terminal provided on the lower surface of the main body with respect to the longitudinal direction is longer than the size of the portion of the second terminal provided on the upper surface of the main body with respect to the longitudinal direction. The multilayer chip capacitor as described.
PCT/JP2016/059099 2015-04-21 2016-03-23 Wiring board and laminated chip capacitor WO2016170894A1 (en)

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