WO2016170590A1 - Procédé de fabrication de dispositif à semi-conducteur et dispositif de fabrication de semi-conducteur - Google Patents

Procédé de fabrication de dispositif à semi-conducteur et dispositif de fabrication de semi-conducteur Download PDF

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Publication number
WO2016170590A1
WO2016170590A1 PCT/JP2015/062039 JP2015062039W WO2016170590A1 WO 2016170590 A1 WO2016170590 A1 WO 2016170590A1 JP 2015062039 W JP2015062039 W JP 2015062039W WO 2016170590 A1 WO2016170590 A1 WO 2016170590A1
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Prior art keywords
pattern
manufacturing
semiconductor device
pattern film
dot
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PCT/JP2015/062039
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English (en)
Japanese (ja)
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田中　博司
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus for forming a pattern film on the surface of a base layer such as a semiconductor wafer or a semiconductor chip.
  • the conventional pattern film forming method is realized through the following six steps (a) to (f). That is, (a) film formation step, (b) resist coating step, (c) exposure step, (d) development step, (e) etching step, (f) resist removal step, steps (b) to (d).
  • the pattern film can be obtained by the etching treatment in step (e) on the etching target film formed in step (a) ⁇ ⁇ ⁇ using the resist patterned in as a mask.
  • Such a conventional method for forming a patterned film is disclosed in, for example, Patent Document 1.
  • the manufacturing method of the semiconductor device including the above steps (a) to (f) is a pattern film forming method generally performed in the manufacturing process of a semiconductor wafer.
  • the conventional process flow for forming a pattern film is intended to form a fine pattern film, it can be achieved only by preparing a set of highly accurate and expensive semiconductor manufacturing apparatuses.
  • the processing time of all the processes in the conventional pattern film forming method is the addition of the processing time for each transport unit in each process, for example, an average of about 1 hour is taken for 25 units of semiconductor wafers in each process. Assuming that the processes are performed in step (a) to (f), it will take at least 6 hours to execute all the steps (a) to (f).
  • the conventional pattern film forming method has a problem in that it requires an expensive and long-time process in terms of productivity.
  • the conventional pattern film forming method also has problems in its formation contents.
  • an etching target film is formed on the entire surface of the underlayer of the semiconductor wafer or the like, but after the curing process by heat or light, film stress is applied to the entire etching target film. Since the film stress concentrates on the edge of the pattern film during the processes (b) to (f) in steps (b) to (f), when the pattern film is made of a material having low adhesion to the underlayer, the edge of the pattern film The part may peel off, and measures such as adding an adhesion reinforcing agent are required. However, when an adhesion enhancing agent is added, it becomes difficult to remove, and it may be impossible to regenerate the base layer from which the pattern film has been removed (re-formation of the pattern film).
  • the present invention solves the above-described problems and can form a patterned film on the underlayer with good adhesion.
  • the method of manufacturing a semiconductor device and a semiconductor capable of reducing the processing time at low cost An object is to provide a manufacturing apparatus.
  • a pattern film forming material is deposited in the form of dots on the surface of the underlayer, and a completed pattern film having a fixed shape is formed by at least one dot pattern. is doing.
  • a pattern film can be formed on the underlayer with good adhesion by forming each of at least one dot-like pattern short to suppress the film stress of the pattern film. .
  • peeling of the pattern film can be suppressed even when the pattern film is formed with a material having low adhesion to the base layer.
  • FIG. 6 is a cross-sectional view schematically showing the formation content of the pattern film in the method for manufacturing the semiconductor device of the first embodiment.
  • FIG. 10 is a plan view schematically showing the formation content of a pattern film in the method for manufacturing a semiconductor device of the second embodiment.
  • FIG. 10 is a plan view schematically showing the formation content of a pattern film in the method for manufacturing a semiconductor device of the third embodiment.
  • FIG. 4 is a cross-sectional view showing the AA cross-sectional structure of FIG. 3.
  • FIG. 10 is a plan view schematically showing the formation content of a pattern film in the method for manufacturing a semiconductor device of the fourth embodiment.
  • FIG. 6 is a cross-sectional view showing a BB cross-sectional structure of FIG. 5.
  • FIG. 10 is a flowchart showing a processing procedure of a manufacturing method of a semiconductor device according to a fifth embodiment. It is a top view which shows typically the formation content of the pattern film in the manufacturing method of the semiconductor device of Embodiment 6.
  • FIG. 8B is a cross-sectional view showing the CC cross-sectional structure of the bag.
  • FIG. 25 is a plan view schematically showing the formation content of the pattern film in the method for manufacturing a semiconductor device in the seventh embodiment.
  • FIG. 10C is a cross-sectional view showing a DD cross-sectional structure of the bag.
  • FIG. 10 (d) is a cross-sectional view showing an EE cross section of the bag.
  • FIG. 20 is an explanatory diagram schematically showing a configuration of a semiconductor manufacturing apparatus in an eighth embodiment.
  • ⁇ Embodiment 1> 1 is a cross-sectional view schematically showing the formation contents of a pattern film in the method of manufacturing a semiconductor device according to the first embodiment of the present invention. As shown in the figure, dotted pattern films 20 and 21 are formed on a semiconductor wafer upper layer portion 10 serving as a base layer.
  • the semiconductor wafer upper layer portion 10 is an upper layer portion of the semiconductor wafer 1 and is composed of a combination of a conductor layer 11 and an adjacent layer 12 (other layers) that are connected to each other, and a conductor layer interface between the conductor layer 11 and the adjacent layer 12. 11x.
  • the dotted pattern film 20 is formed on the conductive layer surface 11a of the conductive layer 11, and the dotted pattern film 21 is formed on the conductive layer surface 11a and the adjacent layer surface 12a of the adjacent layer 12 so as to straddle the conductive layer interface 11x. Is done.
  • the dotted pattern films 20 and 21 are both formed in a dotted pattern.
  • the “dot pattern” in this specification means “a pattern that is formed by intermittent discharge once in a nozzle that intermittently discharges a material for forming a pattern film, or a plurality of patterns without changing the position of the nozzle. "Pattern formed by overlapping intermittent discharges", ideally, the dimensions in two directions that intersect each other (for example, the vertical direction and the horizontal direction) are equal, such as a circular shape in plan view. Meaning a pattern.
  • each of the dotted pattern films 20 and 21 Since the formation length of each of the dotted pattern films 20 and 21 is sufficiently short, both the pattern film stresses 20s and 21s reflecting the formation length are reduced.
  • the pattern film stress 20 s of the dotted pattern film 20 after the curing process is generated in the dotted pattern film 20 and concentrated on the end portion of the dotted pattern film 20.
  • the pattern film stress 20s concentrated on the end portion increases as the formation length (diameter) increases.
  • the adhesiveness with the semiconductor wafer upper layer portion 10 which is the underlayer is the same regardless of the location, if the pattern film stress 20s exceeds the adhesive strength with the conductor layer surface 11a at the end portion, the dot pattern The end portion of the film 20 is peeled off from the upper layer portion 10 of the semiconductor wafer.
  • the formation length of the dot pattern film 20 so that the pattern film stress 20s does not exceed the adhesion force.
  • the dot pattern film 20 is formed in a dot pattern, the adhesion The formation length can be made sufficiently short so as to be less than the force. The same applies to the pattern film stress 21 s of the dotted pattern film 21.
  • each of the dotted pattern films 20 and 21 is formed as a completed pattern film at a completed stage whose shape is determined. That is, each of the dotted pattern films 20 and 21 is a completed pattern film.
  • each of the dot pattern films 20 and 21 (at least one dot pattern) is formed short, and the pattern film stresses 20s and 21s of each of the dot pattern films 20 and 21 (complete pattern film) are sufficiently low.
  • the dotted pattern films 20 and 21 can be formed on the semiconductor wafer upper layer portion 10 which is the underlayer with good adhesion.
  • the peeling of the dotted pattern films 20 and 21 can be suppressed.
  • the dotted pattern film 20 is formed with good adhesion even on the conductor layer surface 11a of the conductor layer 11 where the peeling is particularly concerned in relation to the pattern film forming material. Can be formed.
  • the dotted pattern film 21 is formed on the conductor layer surface 11a and the adjacent layer surface 12a across the conductor layer interface 11x. Therefore, when the adhesion force with the adjacent layer 12 becomes higher than the adhesion force with the conductor layer 11, the dotted pattern film 21 can strengthen the suppression force against peeling more than the dotted pattern film 20.
  • the adjacent layer 12 which is another layer is made of a material having higher adhesion to the dotted pattern film 21 than the conductor layer 11, It can be expected to improve the adhesion between the semiconductor wafer upper layer portion 10 and the dotted pattern film 21.
  • each of the dotted pattern films 20 and 21 is described as a completed pattern film.
  • the completed pattern film having various functions is mostly handled by an aggregate thereof.
  • FIG. 2 is a plan view schematically showing the formation contents of the pattern film in the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
  • a plurality of dot-like pattern films 22 are formed in a dispersed manner on the conductor layer surface 11a of the semiconductor wafer upper layer portion 10 serving as a base layer.
  • symbol is attached
  • an aggregate of a plurality of dotted pattern films 22 is formed as a completed pattern film.
  • the completed pattern film of the second embodiment is used when, for example, a fluid material such as solder or metal paste is enclosed in a predetermined range on the conductor layer surface 11a.
  • a fluid material such as solder or metal paste
  • an adherend layer is bonded to a base layer such as the semiconductor wafer upper layer portion 10 by soldering
  • an aggregate of a plurality of dot pattern films 22 dispersed on the base layer is formed as a completed pattern film. It means an embodiment in which after the solder is provided on the surface of the underlayer on which the completed pattern film is not formed, the underlayer and the adherend layer are adhered by the solder.
  • the dot-like pattern film 22 is formed by the viscosity of the fluid material for forming the dot-like pattern film 22, the surface tension on the conductor layer surface 11 a, and the repellency of the material.
  • the film stress of the dotted pattern film 22 after the curing process should be kept sufficiently low like the pattern film stresses 20s and 21s of the first embodiment. Can do.
  • the method of manufacturing the semiconductor device according to the second embodiment suppresses the film stress of the aggregate of the plurality of dot-like pattern films 22 as the completed pattern film to the film stress of each of the plurality of dot-like pattern films 22.
  • a completed pattern film can be formed on the conductor layer 11 (semiconductor wafer upper layer portion 10), which is a base layer, with good adhesion.
  • FIG. 3 is a plan view schematically showing the formation contents of the pattern film in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • XY coordinate axes are shown.
  • a plurality of dot-like pattern films 23 are arranged in the X direction (pattern forming direction) on the conductor layer surface 11a and the adjacent layer surface 12a of the semiconductor wafer upper layer portion 10 serving as an underlayer.
  • X direction pattern forming direction
  • symbol is attached
  • FIG. 4 is a cross-sectional view showing the AA cross-sectional structure of FIG.
  • the dotted pattern film linear connection body 23G which is a completed pattern film has a plurality of dot pattern films 23 (a plurality of dot patterns) connected to each other in the X direction (pattern). It is arranged in a line along the (formation direction) and formed in a line in plan view.
  • the pattern film stress 23s in the dotted pattern film linear connector 23G after the curing process occurs in the entire dotted pattern film linear connector 23G.
  • Pattern film stress 23s is concentrated at the end portions of the dotted pattern film 23 at both ends in the X direction of the body 23G. Therefore, the formation length (diameter) of each dot pattern film 23 increases, and the pattern film stress 23s concentrated at the end tends to increase as the formation length L23 of the dot pattern film linear connector 23G increases.
  • the adhesiveness with the semiconductor wafer upper layer part 10 is not location-dependent, when the pattern film stress 23s exceeds the adhesive force with the semiconductor wafer upper layer part 10, the end of the dotted pattern film linear connector 23G peels off. There is a case. Therefore, it is necessary to set the formation length L of each of the dotted pattern films 23 and the formation length L23 of the dotted pattern film linear connector 23G so that the pattern film stress 23s is sufficiently small.
  • the completed pattern film is formed by the plurality of dotted pattern film linear connectors 23G.
  • the completed pattern film of the third embodiment is similar to the second embodiment, for example, when a fluid material such as solder or metal paste is enclosed in a predetermined range on the conductor layer surface 11a and the adjacent layer surface 12a. Can be used. In this case, it is suitable for a material having higher fluidity than in the second embodiment.
  • the viscosity of the fluid material for forming the dotted pattern film 23 the surface tension on the conductor layer surface 11a and the adjacent layer surface 12a, and the repellency by the above material
  • the dot formation length (diameter) of the dot pattern film 23 and the formation length L23 of the dot pattern film linear connector 23G and the dispersion interval By optimizing the dot formation length (diameter) of the dot pattern film 23 and the formation length L23 of the dot pattern film linear connector 23G and the dispersion interval, the dot pattern film wire after the curing treatment is obtained.
  • the pattern film stress 23s of the link body 23G can be kept low so that the dotted pattern film linear link body 23G does not peel off.
  • the pattern film stress in the completed pattern film which is an aggregate of the plurality of dotted pattern film linear connectors 23G, is dotted. It becomes equal to the pattern film stress 23s of each pattern film linear connector 23G.
  • a part of the dotted pattern film 23 of the dotted pattern film linear connector 23G is formed on the conductor layer surface 11a and the adjacent layer surface 12a across the conductor layer interface 11x. Therefore, when the adhesion strength with the adjacent layer 12 becomes higher than the adhesion strength with the conductor layer 11, it can be expected that the adhesion strength of the dotted pattern film linear connector 23G to the semiconductor wafer upper layer portion 10 is increased.
  • each of the plurality of dotted pattern film linear connectors 23G to be the completed pattern film is connected in the X direction (with the plurality of dotted pattern films 23 connected to each other). It is arranged in a line along the pattern formation direction) and formed in a line in plan view.
  • the film stress of the completed pattern film is suppressed to the pattern film stress 23s that reflects the formation length L23 of the point-like pattern film linear connector 23G at a maximum, thereby improving the adhesion to the semiconductor wafer upper layer portion 10 that is the underlayer.
  • a completed pattern film can be formed.
  • FIG. 5 is a plan view schematically showing the formation contents of the pattern film in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.
  • XY coordinate axes are shown.
  • a plurality of dot pattern films 24 (a plurality of dot patterns) are connected to each other on the conductor layer surface 11a and the adjacent layer surface 12a of the semiconductor wafer upper layer portion 10 serving as an underlayer while connecting them in the X direction ( By arranging in a line along the first pattern forming direction) and in a line along the Y direction (second pattern forming direction) perpendicular to the X direction, the surface shape in plan view A point-like pattern film planar connector 24G is formed.
  • symbol is attached
  • the cross-sectional structure in the X direction of FIG. 5 is the same as that of the third embodiment shown in FIG. That is, the dotted pattern film planar connecting body 24G is arranged in a line along the X direction while connecting a plurality of dotted pattern films 24 (dotted patterns) to each other.
  • FIG. 6 is a cross-sectional view showing the BB cross-sectional structure of FIG.
  • the dotted pattern film planar connector 24G is linear along the Y direction in addition to the X direction while connecting a plurality of dotted pattern films 24 (dot patterns) to each other. Is arranged.
  • the pattern film stress 24s in the Y direction in the central dotted pattern film planar connector 24G after the curing treatment reflects the formation length LY24 in the Y direction, and the dotted pattern film planar connector. Pattern film stress 24s is concentrated at the end portions of the dotted pattern film 24 at both ends in the Y direction of 24G.
  • the pattern film stress in the X direction in the dotted pattern film planar connection body 24G reflects the formation length LX24 in the X direction, and the dotted pattern films on both ends in the X direction of the dotted pattern film planar connection body 24G. The pattern film stress is concentrated on the end portion of 24.
  • the dotted pattern film planar connector 24G will be described on the assumption that the formation length LY24 is longer than the formation length LX24.
  • the pattern film stress in the entire central dotted pattern film surface connecting body 24G is equal to the pattern film stress 24s.
  • the dotted pattern film planar connecting body 24G is not connected between the dotted pattern films 24 and 24 in the diagonal direction in plan view.
  • the completed pattern film is formed by the plurality of dotted pattern film planar connectors 24G.
  • the completed pattern film of Embodiment 4 is made of a material having fluidity such as solder or metal paste in a predetermined range on the conductor layer surface 11a and the adjacent layer surface 12a. It can be used when enclosing. In this case, it is suitable for a material having higher fluidity than in the second embodiment.
  • the viscosity of the fluid material for forming the dotted pattern film 24 the surface tension on the conductor layer surface 11a and the adjacent layer surface 12a, and the repellency by the above material.
  • the pattern film stress in the completed pattern film which is an aggregate of the plurality of dotted pattern film planar connectors 24G, is dotted. It becomes equal to the pattern film stress 24s of each pattern film planar connector 24G.
  • a part of the dotted pattern film 24 of the dotted pattern film planar connector 24G is formed on the conductor layer surface 11a and the adjacent layer surface 12a across the conductor layer interface 11x. Therefore, when the adhesive force with the adjacent layer 12 becomes higher than the adhesive force with the conductor layer 11, it can be expected that the adhesive force of the dotted pattern film planar connector 24G to the semiconductor wafer upper layer portion 10 is increased.
  • each of the plurality of dotted pattern film planar connectors 24G to be the completed pattern film is connected to the X direction ( By arranging in a line along the first pattern forming direction) and in a line along the Y direction (second pattern forming direction) intersecting at right angles to the X direction, It is formed in a planar shape.
  • the completed pattern film can be formed on the semiconductor wafer upper layer portion 10 which is the underlayer with good adhesion.
  • the dotted pattern film planar connector 24 ⁇ / b> G is formed in a square shape in plan view.
  • the present invention is not limited to this, and the conductor is not limited to the end of the finished pattern film. You may make it form in the frame shape which has a hollow so that the perimeter of the layer surface 11a may be surrounded.
  • FIG. 7 is a flowchart showing a processing procedure of a semiconductor device manufacturing method according to the fifth embodiment of the present invention. It should be noted that the completed pattern film of the first to fourth embodiments (an assembly of the dotted pattern films 20 and 21 and the dotted pattern film 22, the dotted pattern is formed by the semiconductor device manufacturing method of the fifth embodiment. An aggregate of the patterned film linear connectors 23G and an aggregate of the dotted pattern film planar connectors 24G).
  • pattern film formation of an organic insulating film such as formation of a pattern film by thermosetting polyimide after electrode formation, formation of a pattern film by a photocurable material, or the like can be considered.
  • a surface cleaning process (surface layer cleaning process) is performed in step S1. Since the organic matter contained in the atmosphere is adsorbed on the surface (surface layer surface) of the semiconductor wafer upper layer portion 10 left in the atmosphere, in step S1, it adsorbs on the surface of the semiconductor wafer upper layer portion 10. It is necessary to remove the organic matter. For this reason, as a specific means for realizing the cleaning process, it is the simplest to irradiate ultraviolet light (UV light), and when ozone is used together, the time required for the cleaning process can be further shortened.
  • UV light ultraviolet light
  • step S2 after step S1, a material coating process for coating the pattern film forming material on the semiconductor wafer upper layer portion 10 is executed.
  • the material of the pattern film is deposited as a dot pattern on the surface of the upper layer portion 10 of the semiconductor wafer to form a temporary pattern film constituted by a dot pattern alone or a combination of dot patterns.
  • the dot pattern film 20 or the dot pattern film 21 of the first embodiment can be considered, and as a combination of the dot patterns, an assembly of a plurality of dot pattern films 22 each of which is discrete,
  • the dotted pattern film linear connection body 23G, the dotted pattern film surface connection body 24G, etc. can be considered.
  • the application process using an inkjet nozzle is currently the finest and the processing time is short.
  • a dispenser may be selected to lower.
  • step S3 the material temporary curing process of step S3 is executed.
  • the material for forming the pattern film applied in step S2 is temporarily cured as long as it can be regenerated with a chemical solution.
  • a material for forming the pattern film not only a thermosetting material containing a solvent such as polyimide, but also a photocurable material obtained by adding a photopolymerization initiator to an acrylate or methacrylate monomer or oligomer, for example.
  • the thermosetting material is temporarily cured by heating, and the photocurable material is temporarily cured by light.
  • Step S2 and step S3 may be repeated. In this case, it is possible to return to step S2 and to repeatedly execute step S2 and step S3 by return R3 after temporary material curing after execution of step S3.
  • step S3 is a completed stage in which the shape of the pattern film composed of at least one applied dot pattern is determined. That is, a completed pattern film is formed after the last step S3.
  • step S3 it is desirable to perform both an application pattern inspection process (step S4) for inspecting the quality of the application pattern and an inspection determination process (step S5) for determining the inspection result of the application pattern inspection process.
  • step S5 If a defect in the coating pattern is determined by the inspection determination process in step S5, the process of the semiconductor device manufacturing method (pattern film forming method) can be forcibly terminated, and the process can proceed to the semiconductor wafer 1 regeneration process. . On the other hand, if the inspection determination process in step S5 determines good, and if it is necessary to repeat step S2 and step S3, the process returns to step S2 by the post-inspection determination return R5 after execution of step S5. S3 can be repeatedly executed.
  • step S2 and the material temporary curing process in step S3 are repeated in a situation where the processes in steps S4 and S5 are not provided, the material pre-curing work is accumulated as the previously applied material is accumulated. Therefore, there is a high possibility that regeneration with a chemical solution becomes difficult. Therefore, attention must be paid to the number of times steps S2 and S3 are repeated.
  • the quality of the coating pattern is periodically determined by executing steps S4 and S5 at a rate of once after the execution of step S3 or once after the execution of step S3.
  • the manufacturing method of the semiconductor device according to the fifth embodiment performs steps S1 to S3 to perform a series of steps of film formation, resist coating, development, exposure, etching, and resist removal that have been conventionally performed.
  • the completed pattern film can be formed at a relatively low cost because it is not necessary to perform this process.
  • the quality of the coating pattern in the pattern film forming material is determined, and the manufacturing of the defective coating pattern is appropriately stopped.
  • the process can be shifted to the reproduction process, so that the yield of the semiconductor device can be improved.
  • the cleaning process in step S1 can be performed in a relatively short time by ultraviolet light irradiation.
  • a fine dot pattern can be formed in a relatively short time by using an ink jet nozzle in the material application process in step S2.
  • a photocuring material is used as the pattern film forming material, and the temporary curing process in step S3 can be performed in a relatively short time by light irradiation.
  • FIG. 8 is a plan view schematically showing the formation contents of the pattern film in the method of manufacturing a semiconductor device according to the sixth embodiment of the present invention.
  • XY coordinate axes are shown.
  • a plurality of dotted pattern films 25 and 26 are formed on the conductor layer surface 11a and the adjacent layer surface 12a of the semiconductor wafer upper layer portion 10 serving as the underlayer.
  • the dotted pattern film linear connector 26G which is a linear pattern film in a plan view, obtained by arranging the linear pattern) along the X direction (pattern forming direction) along the Y direction.
  • symbol is attached
  • FIG. 9 is a cross-sectional view showing the CC cross-sectional structure of FIG. 8 (b).
  • FIG. 8 and FIG. 9 a processing procedure of the semiconductor device manufacturing method of the sixth embodiment will be described.
  • step S2 material coating process
  • step S3 material temporary curing process
  • a plurality of lower layer dotted pattern films 25 are formed along the X direction without being connected to each other.
  • the plurality of lower layer dot pattern films 25 are formed in a plurality of rows and dispersed along the Y direction.
  • the film stress of the lower layer dotted pattern film 25 is separated in units of the pattern film stress 25s. Further, a part of the plurality of lower layer dot pattern films 25 is formed so as to straddle the conductor layer interface 11x.
  • a plurality of upper layer dotted pattern films 26 are formed along the X direction without being connected to each other.
  • a linear completed pattern in plan view A dotted pattern film linear connector 26G is formed as a film.
  • the plurality of dotted pattern film linear connected bodies 26G are formed in a plurality of rows and dispersed along the Y direction.
  • the plurality of upper layer dot pattern films 26 are adapted to the plurality of lower layer dot pattern films 25 already temporarily cured in the first step S3.
  • the pattern film stress 26s of each of the plurality of upper layer dot pattern films 26 is separated by the lower layer dot pattern film 25 provided between the upper layer dot pattern films 26 and 26.
  • the dotted pattern film linear connected bodies 26G adjacent in the Y direction are separated from each other, film stress does not act on each other.
  • the plurality of dotted pattern film linear connected bodies 26G manufactured by the method of manufacturing a semiconductor device according to the sixth embodiment each have a connecting structure in which the linear connected patterns are formed.
  • the temporary curing of the film 25 and the upper dot pattern film 26 is performed separately, and as shown in FIG. 9, the pattern film stress 25s and the pattern film stress 26s remain separated in dot units, As a whole, the stress concentration on the end portion of the dotted pattern film linear connected body 26G is relieved greatly.
  • a plurality of lower layer dot pattern films 25 and a plurality of upper layer dot pattern films 26 are formed in separate processes, and the lower layer dot pattern films 25 and 25 are formed as upper layer dots.
  • a method of applying a material for forming a pattern film so as to be connected by the pattern film 26 may be referred to as a “stepwise material application manufacturing method”.
  • the semiconductor device manufacturing method according to the sixth embodiment is completed by combining the plurality of lower layer dot pattern films 25 and the plurality of upper layer dot pattern films 26 after the execution of step S3 twice. While the film stress of the pattern film is suppressed to the pattern film stress 25s and the pattern film stress 26s of the lower layer dot pattern film 25 and the upper layer dot pattern film 26, respectively, a linear completed pattern film can be formed in plan view. .
  • steps S4 and S5 of the fifth embodiment are incorporated after the first and second steps S3 may be employed.
  • the manufacturing of the semiconductor device is immediately stopped.
  • the process returns to step S2 with a return R5 after inspection determination, and when the second application pattern is normal, the process proceeds to the next main curing process.
  • the main curing process is performed under a high temperature condition (example of polyimide: 300 ° C./60 minutes) exceeding the glass transition point.
  • the pattern film forming material is a photo-curing material
  • this curing process is performed by irradiating with high energy light to eliminate unreacted monomers (example of acrylic acrylate: 300 to 1000 mJ with UV: 365 nm peak metal halide lamp) / cm 2 ) or heating to release the monomer (example of acrylic acrylate: 150 ° C./60 minutes).
  • the quality of the coating pattern in the material for forming the lower layer dot pattern film 25 and the upper layer dot pattern film 26 is determined during the execution of step S4, and defective application is performed.
  • the production of the pattern can be stopped as appropriate to improve the yield of the semiconductor device.
  • FIG. 10 is a plan view schematically showing the formation contents of the pattern film in the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.
  • XY coordinate axes are shown.
  • a plurality of dotted pattern films 27 and 28 (a plurality of first and second points) are formed on the conductor layer surface 11a and the adjacent layer surface 12a of the semiconductor wafer upper layer portion 10 serving as the underlayer.
  • a plurality of dot pattern films 29 and 30 (a plurality of third and fourth dot patterns) arranged in a line along the X direction (first pattern formation direction).
  • the dotted pattern film planar connected bodies 30G which are planar pattern films in plan view, are formed in a plurality of rows dispersed along the Y direction (second pattern formation direction).
  • symbol is attached
  • FIG. 11 is a cross-sectional view showing the DD cross-sectional structure of FIG. 10 (c)
  • FIG. 12 is a cross-sectional view showing the EE cross section of FIG. 10 (d).
  • FIG. 10D, FIG. 11 and FIG. 12 is the same as that shown in FIG. 7 in the method for manufacturing the semiconductor device of the fifth embodiment, in which step S2 (material coating process) and step S3 (material temporary curing process) are performed. This is realized by repeating 4 times.
  • a plurality of lower layer dotted pattern films 27 are formed along the X direction without being connected to each other.
  • the plurality of lower layer dotted pattern films 27 are formed in a plurality of rows and dispersed along the Y direction. That is, the plurality of lower layer dot pattern films 27 are classified into a group of a plurality of lower layer dot pattern films 27 (a plurality of first dot pattern groups) along the Y direction orthogonal to the X direction.
  • the film stress of the lower layer dot pattern film 27 is the pattern film.
  • the stress is separated into 27 s units.
  • a part of the plurality of lower layer dotted pattern films 27 is formed so as to straddle the conductor layer interface 11x.
  • a plurality of upper layer dotted pattern films 28 are formed along the X direction without being connected to each other.
  • the plurality of lower layer dotted pattern films 28 are formed in a plurality of rows and dispersed along the Y direction. That is, the plurality of upper layer dot pattern films 28 correspond to the group of the plurality of lower layer dot pattern films 27 along the Y direction. Type pattern group).
  • the group of the plurality of sets of upper layer dot pattern films 28 includes an upper layer dot pattern film 28 between a pair of lower layer dot pattern films 27 and 27 adjacent to each other in the X direction among the plurality of lower layer dot pattern films 27 in each group. It is connected through.
  • the plurality of upper layer dot pattern films 28 have already been temporarily cured in the first step S3. 27, the pattern film stress 28 s of each of the plurality of upper layer dot pattern films 28 is separated by the lower layer dot pattern film 27 provided between the upper layer dot pattern films 28, 28.
  • a plurality of lower layer dotted pattern films 29 are formed along the X direction without being connected to each other by performing the third steps S2 and S3.
  • the plurality of lower layer dotted pattern films 29 are formed in a plurality of rows and dispersed along the Y direction. That is, the plurality of lower layer dot pattern films 29 are classified into a group of a plurality of lower layer dot pattern films 29 (a plurality of third dot pattern groups) along the Y direction orthogonal to the X direction.
  • the plurality of lower layer dot pattern films 29 have already been temporarily cured in the first and second steps S3, and the plurality of lower layer dot pattern films 27 and the plurality of upper layer dot pattern films 28.
  • the pattern film stress 29 s of each of the plurality of upper layer dot pattern films 29 is separated by the lower layer dot pattern film 27 provided between the lower layer dot pattern films 29 and 29.
  • a plurality of upper layer dotted pattern films 30 are formed along the X direction without being connected to each other, and a plurality of lower layers are formed.
  • a pair of lower layer dotted pattern films 29 and 29 adjacent to each other in the X direction are connected through an upper layer dotted pattern film 30 and between a plurality of sets of upper layer dotted pattern films 28.
  • a pair of upper layer dot pattern films 28, 28 adjacent to each other in the Y direction are connected via an upper layer dot pattern film 30, so that a planar dot pattern film surface connection body 30 ⁇ / b> G in plan view is obtained. Is formed as a completed pattern film.
  • the plurality of upper layer dot pattern films 30 correspond to the group of the plurality of lower layer dot pattern films 29 along the Y direction. Type pattern group).
  • the plurality of upper layer dot pattern films 30 are the plurality of lower layer dot pattern films 27, the plurality of upper layer dot pattern films 27 which have already been temporarily cured in the first to third steps S3. 28 and a plurality of lower layer dotted pattern films 29 are spread out. Then, the pattern film stress 30s of each of the plurality of upper layer dot pattern films 30 in the X direction is separated by the lower layer dot pattern film 29 provided between the upper layer dot pattern films 30 and 30, and in the Y direction, FIG. As shown in FIG. 5, the pattern film stress 30 s of each of the plurality of upper layer dot pattern films 30 is separated by the upper layer dot pattern film 28 provided between the upper layer dot pattern films 30 and 30.
  • the plurality of dotted pattern film planar connected bodies 30G manufactured by the semiconductor device manufacturing method of the seventh embodiment have a connecting structure in which the whole is connected in a planar shape.
  • the temporary curing of the pattern film 27, the upper dot pattern film 28, the lower dot pattern film 29, and the upper dot pattern film 30 is performed separately.
  • the pattern film stress 27s, the pattern film The stress 28s, the pattern film stress 29s, and the pattern film stress 30s remain separated in dot units. For this reason, the stress concentration to the end of the dotted pattern film planar connector 30G as a whole is greatly relieved.
  • a plurality of lower layer dot pattern films 27, a plurality of upper layer dot pattern films 28, and a plurality of lower layer dot patterns are obtained by performing step S3 four times.
  • a completed pattern film is formed by a combination of the film 29 and a plurality of upper-layer dot pattern films 30.
  • the seventh embodiment is similar to the sixth embodiment in that a plurality of lower layer dot pattern films 27, a plurality of upper layer dot pattern films 28, a plurality of lower layer dot pattern films 29, and a plurality of upper layer dot patterns.
  • a stepwise material coating method is used in which the pattern film 30 is formed in a separate process.
  • the lower dot pattern films 27 and 27 are connected by the upper dot pattern film 28, and the lower dot pattern films 29 and 29 are connected by the upper dot pattern film 30 and in the Y direction.
  • the lower dot pattern films 27 and 27 can be connected by the lower dot pattern film 29, and the upper dot pattern films 28 and 28 can be connected by the upper dot pattern film 30.
  • a pattern film can be formed.
  • the dotted pattern film planar connecting body 30G is formed in a square shape.
  • the present invention is not limited to this, and surrounds the entire circumference of the conductor layer surface 11a as long as the end of the completed pattern film does not peel off.
  • it may be formed in a frame shape having a hollow.
  • steps S4 and S5 of the fifth embodiment are incorporated after each of the first to fourth steps S3 may be adopted.
  • the manufacture of the semiconductor device is immediately stopped.
  • the process returns to step S2 with a return R5 after inspection determination, and if the fourth application pattern is normal, the process proceeds to the next main curing process.
  • the quality of the coating pattern in the material for forming the lower layer dot pattern films 27 and 29 and the upper layer dot pattern films 28 and 30 is determined when step S4 is executed.
  • the production of defective coating patterns can be stopped as appropriate to improve the yield of semiconductor devices.
  • FIG. 13 is an explanatory diagram schematically showing a configuration of a semiconductor manufacturing apparatus according to Embodiment 8 of the present invention.
  • the positional relationship on the plane of each component part 41-48 of the semiconductor manufacturing apparatus 4 of Embodiment 8 is shown.
  • the semiconductor manufacturing apparatus 4 of the eighth embodiment is an apparatus for realizing the semiconductor device manufacturing method of the first to seventh embodiments.
  • XYZ coordinate axes are shown.
  • the semiconductor manufacturing apparatus 4 includes a plurality of wafer cassettes 41, a transfer robot 42, an alignment unit 43, a stage 44, a surface cleaning unit 45, a material application unit 46, a material temporary curing unit 47, and an application pattern inspection.
  • the unit 48 is configured.
  • the transfer robot 42 performs a transfer process of taking out the semiconductor wafer 1 from the wafer cassette 41 and placing it on the stage 44, or holding the semiconductor wafer 1 on the stage 44 and returning it to the wafer cassette 41.
  • the stage 44 is normally disposed in the alignment unit 43, but can be moved to the surface cleaning unit 45, the material application unit 46, the material temporary curing unit 47, and the application pattern inspection unit 48 as necessary.
  • the semiconductor wafer 1 stored in the wafer cassette 41 is pulled out by the transfer robot 42, and the semiconductor wafer 1 is placed on the alignment unit 43 in the stage 44 by the transfer robot 42.
  • the alignment unit 43 drives the X, Y, Z, ⁇ axes and the like in the spherical coordinate system of the internal stage 44 by image processing to adjust the position and angle of the semiconductor wafer 1 to the coating coordinate system.
  • step S1 in the semiconductor device manufacturing method of the fifth embodiment corresponds to step S1 in the semiconductor device manufacturing method of the fifth embodiment (see FIG. 7).
  • the stage 44 is moved to the material application unit 46, and a pattern film forming material (hereinafter simply referred to as “material” in some cases) is applied to the surface of the semiconductor wafer 1 from an inkjet nozzle.
  • material hereinafter simply referred to as “material” in some cases
  • the stage 44 is moved toward the alignment unit 43 in the ⁇ Y direction at a constant speed, and the material is temporarily cured by light irradiation of the passing material temporary curing unit 47.
  • the light irradiation process by the material temporary curing portion 47 having the light irradiation function corresponds to step S3 in the method for manufacturing the semiconductor device of the fifth embodiment.
  • the stage 44 is moved to the coating pattern inspection unit 48, and it is inspected for abnormality in the coating pattern of the material by image processing.
  • the inspection process of the coating pattern inspection unit 48 having the inspection function corresponds to step S4 in the method for manufacturing the semiconductor device of the fifth embodiment.
  • the inspection determination process is subsequently performed by the coating pattern inspection unit 48.
  • This process corresponds to step S5 in the method for manufacturing the semiconductor device of the fifth embodiment.
  • an alarm of the application pattern abnormality is issued.
  • the stage 44 is moved to the alignment unit 43, the semiconductor wafer 1 on the stage 44 is stored in the original wafer cassette 41 by the transfer robot 42, and the alarm log is linked to the wafer log.
  • the main curing process is performed in another apparatus of the semiconductor manufacturing apparatus 4.
  • the coating pattern inspection step and the subsequent inspection determination step are repeated as many times as necessary. For example, in the case of the sixth embodiment, it is repeated twice, and in the case of the seventh embodiment, it is repeated four times.
  • inspection determination step is also considered.
  • the semiconductor manufacturing apparatus 4 has the surface cleaning unit 45, the material application unit 46, and the material pre-curing unit 47 in an integrated manner. It can be formed in a short time.
  • the manufacturing method of the fifth embodiment shown in FIG. 7 is executed by the semiconductor manufacturing apparatus 4 of the eighth embodiment, all can be processed at high speed.
  • Surface cleaning by the surface cleaning unit 45 is 10 seconds
  • material application by the material application unit 46 is 10 seconds
  • temporary curing processing by the material temporary curing unit 47 is 10 seconds
  • application pattern inspection processing by the application pattern inspection unit 48 is 10 seconds. You can do it. That is, considering the integration of the components 41 to 48 into one semiconductor manufacturing apparatus 4, the processing time of steps S1 to S5 of the semiconductor device manufacturing method of the fifth embodiment is shortened.
  • the semiconductor manufacturing apparatus 4 forms a defective coating pattern by integrating the coating pattern inspection unit 48 in addition to the surface cleaning unit 45, the material coating unit 46, and the material temporary curing unit 47.
  • An accurate pattern film can be formed in a relatively short time while the processed semiconductor wafer 1 is regenerated.
  • the semiconductor manufacturing apparatus 4 can reduce the size and weight of the apparatus by integrating and integrating the components 41 to 48.
  • the material application unit 46 uses an ink jet nozzle to make the material use efficiency about 90%, and the material use efficiency by the spin coater used in the conventional film forming process is significantly higher than about 30%. Can be improved. Further, since the resist coating and development processes are not required as in the prior art, the amount of raw materials can be reduced.
  • the semiconductor manufacturing apparatus 4 of the eighth embodiment can be integrated as compared with the conventional semiconductor manufacturing apparatus constituted by a plurality of apparatuses, and overall energy saving can be achieved by shortening the processing time.
  • the semiconductor manufacturing apparatus 4 of the eighth embodiment it is possible to reduce the amount of raw materials described above and to relieve the film stress at the time of forming a completed pattern film by combining a point pattern film alone or a point pattern film.
  • the yield of the semiconductor device manufactured by executing the manufacturing method of the semiconductor device according to the first to seventh embodiments can be improved.
  • the semiconductor wafer 1 is shown as an example. However, it is needless to say that the present invention can be applied to a semiconductor chip formed into chips.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé de fabrication de dispositif à semi-conducteur, selon lequel un film à motif peut être formé ayant une excellente adhérence sur une couche de base. La présente invention forme des films à motifs en forme de point (20, 21) en guise de films à motifs finis par dépôt d'un matériau de formation de film à motif selon des formes de points sur une surface d'une section (10) de couche supérieure de plaquette de semi-conducteur, qui est conçue à partir d'une couche conductrice (11) et d'une couche adjacente (12) et qui présente une interface (11x) de couche conductrice entre la couche conductrice (11) et la couche adjacente (12). Le film à motif (20) en forme de point est formé sur une surface (11a) de couche conductrice de la couche conductrice (11) et le film à motif (21) en forme de point est formé sur la surface (11a) de couche conductrice et une surface (12a) de couche adjacente de la couche adjacente (12), de sorte que le film à motif en forme de point chevauche l'interface (11x) de couche conductrice.
PCT/JP2015/062039 2015-04-21 2015-04-21 Procédé de fabrication de dispositif à semi-conducteur et dispositif de fabrication de semi-conducteur WO2016170590A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11339642A (ja) * 1994-12-16 1999-12-10 Canon Inc 電子薄膜基板の製造装置
JP2003318133A (ja) * 2002-04-22 2003-11-07 Seiko Epson Corp 膜パターンの形成方法、膜パターン形成装置、導電膜配線、半導体チップの実装構造、半導体装置、発光装置、電気光学装置、電子機器、並びに非接触型カード媒体
JP2004335849A (ja) * 2003-05-09 2004-11-25 Seiko Epson Corp 膜パターンの形成方法、膜パターンの形成装置、導電膜配線、電気光学装置、電子機器、並びに非接触型カード媒体
JP2007088382A (ja) * 2005-09-26 2007-04-05 Ricoh Co Ltd 膜パターン及びその製造方法
JP2009272350A (ja) * 2008-04-30 2009-11-19 Ricoh Co Ltd パターン配列シート、その製造方法、電子デバイスチップ及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11339642A (ja) * 1994-12-16 1999-12-10 Canon Inc 電子薄膜基板の製造装置
JP2003318133A (ja) * 2002-04-22 2003-11-07 Seiko Epson Corp 膜パターンの形成方法、膜パターン形成装置、導電膜配線、半導体チップの実装構造、半導体装置、発光装置、電気光学装置、電子機器、並びに非接触型カード媒体
JP2004335849A (ja) * 2003-05-09 2004-11-25 Seiko Epson Corp 膜パターンの形成方法、膜パターンの形成装置、導電膜配線、電気光学装置、電子機器、並びに非接触型カード媒体
JP2007088382A (ja) * 2005-09-26 2007-04-05 Ricoh Co Ltd 膜パターン及びその製造方法
JP2009272350A (ja) * 2008-04-30 2009-11-19 Ricoh Co Ltd パターン配列シート、その製造方法、電子デバイスチップ及びその製造方法

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