WO2016165253A1 - 一种阵列基板和显示装置 - Google Patents

一种阵列基板和显示装置 Download PDF

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WO2016165253A1
WO2016165253A1 PCT/CN2015/087497 CN2015087497W WO2016165253A1 WO 2016165253 A1 WO2016165253 A1 WO 2016165253A1 CN 2015087497 W CN2015087497 W CN 2015087497W WO 2016165253 A1 WO2016165253 A1 WO 2016165253A1
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line
signal line
signal
array substrate
disposed
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PCT/CN2015/087497
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English (en)
French (fr)
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李文波
李盼
程鸿飞
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京东方科技集团股份有限公司
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Priority to US14/907,040 priority Critical patent/US10026755B2/en
Publication of WO2016165253A1 publication Critical patent/WO2016165253A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • the existing display panel generally includes an array substrate and a color film substrate, and the array substrate is one of important components of the display panel.
  • a plurality of signal lines such as gate lines, data lines, gate detection lines, data detection lines, and common electrode lines, are usually disposed in the array substrate. Due to the large number of signal lines in the array substrate, multiple signal lines often cross. The phenomenon that when an electrostatic discharge signal occurs in at least one of the plurality of signal lines that intersect, an electrostatic charge is accumulated at an intersection of the plurality of signal lines, so that a cross-region of the plurality of signal lines is capacitively coupled, thereby Interference occurs at the intersection of a plurality of signal lines, which in turn reduces the performance of the array substrate.
  • the present invention provides the following technical solutions:
  • the present invention provides an array substrate including a substrate substrate, a plurality of first signal lines and a plurality of second signal lines disposed across the substrate substrate;
  • the first signal line includes a line end and a second line end, and a conductive layer opposite to the second signal line for connecting the first line end and the second line end, and an insulating layer is disposed between the conductive layer and the second signal line,
  • a plurality of first antistatic structures are respectively disposed at the connection between the first line end, the second line end and the conductive layer.
  • first line end and the second line end of each of the first signal lines may be respectively provided with via holes for conducting with the conductive layer.
  • the second signal line and the one side or both sides of the corresponding area of the conductive layer are provided with a plurality of second antistatic structures.
  • the first or second antistatic structure may be a discharge tip.
  • the plurality of the second signal lines may be disposed in different layers or in the same layer.
  • first line end and the second line end of the first signal line may be disposed in a same layer, and the second signal line and the first line end and the second line end of the first signal line may be Different layer settings.
  • first line end and the second line end of the first signal line are disposed in the same layer and are disposed in the same layer as the at least one of the second signal lines.
  • first line end and the second line end of the first signal line are disposed in different layers, and one of the first line end and the second line end of the first signal line and the at least one line end
  • the second signal lines can be disposed in the same layer.
  • the first signal line may be a gate detection line
  • the second signal line may be a data detection line
  • the first signal line may be a switch line or a data detection line
  • the second signal line may be a common electrode line
  • the conductive layer may be an indium tin oxide layer.
  • the present invention provides a display device comprising the array substrate according to any one of the above aspects.
  • the first signal line and the second signal line are disposed to intersect with each other, wherein the first signal line includes a first line end, a second line end, and a conductive line that turns on the first line end and the second line end
  • An insulating layer is disposed between the conductive layer and the second signal line, so that the vertical distance between the first signal line and the second signal line increases at an intersection of the first signal line and the second signal line, and the distance is reduced.
  • the capacitive coupling of the intersecting first signal line and the second signal line is alleviated, the interference phenomenon of the intersection area of the first signal line and the second signal line is alleviated, and the performance of the array substrate is improved.
  • FIG. 1 is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a first signal line in the array substrate according to the present invention.
  • Figure 3 is a cross-sectional view of the array substrate shown in Figure 1 taken along line A-A' of Figure 1;
  • FIG. 4 is a schematic plan view showing a planar structure of an array substrate according to another embodiment of the present invention.
  • Figure 5 is a cross-sectional view of the array substrate shown in Figure 4 taken along line B-B' in Figure 4;
  • Figure 6 is a cross-sectional view of the array substrate taken along line B-B' of Figure 4, in accordance with another embodiment of the present invention.
  • FIG. 7 is a schematic plan view showing a planar structure of an array substrate according to still another embodiment of the present invention.
  • Figure 8 is a cross-sectional view of the array substrate shown in Figure 7 taken along line C-C' of Figure 7;
  • FIG. 9 is a cross-sectional view of an array substrate in accordance with still another embodiment of the present invention.
  • the array substrate may include: a substrate substrate 10 , a first signal line 18 and a second signal line 11 disposed across the substrate substrate 10 , wherein
  • the first signal line 18 or the second signal line 11 may be a gate line, a data line, a data detection line, a common electrode line, a test signal line or a short-circuit ring, etc.; as shown in FIG. 2, the first signal line 18 may include a a line end 12, a second line end 13 and a conductive layer 14 opposite to the second signal line 11 for connecting the first line end 12 and the second line end 13, please refer to FIG. 1 and FIG.
  • a plurality of first antistatic structures 16 may be disposed at the junction of the terminal 13 and the conductive layer 14.
  • the first signal line 18 and the second signal line 11 are disposed, wherein the first signal line 18 includes a first line end 12, a second line end 13 and The conductive layer 14 of the first line end 12 and the second line end 13 is turned on, and the insulating layer 15 is disposed between the conductive layer 14 and the second signal line 11 so that the intersection of the first signal line 18 and the second signal line 11
  • the vertical distance between the first signal line 18 and the second signal line 11 is increased to reduce the electrostatic charge accumulated by the first signal line 18 and the second signal line 11 being too close, in the first signal line 18
  • a plurality of first antistatic structures 16 are disposed at a junction of the first end 12 and the second end 13 and the conductive layer 14 respectively, and the first antistatic structure 16 can be on the first signal line 18 and/or the second signal line 11 When an electrostatic discharge signal occurs, the electrostatic charge accumulated at the intersection of the first signal line 18 and the second signal line 11 is loosened and released, thereby reducing the capaci
  • the first antistatic structure 16 may be formed simultaneously with the first line end or the second line end as a portion of the first line end or the second line end of the first signal line 18.
  • first line end 12 and the second line end 13 of the first signal line 18 may be disposed in the same layer, and the second signal line 11 and the first line end 12 and the second line end 13 of the first signal line 18 It may be disposed in a different layer, wherein the first signal line 18 may be a gate detection line, and the second signal line 11 may be a data detection line.
  • the number of the second signal lines 11 crossing a first signal line 18 may be one, or may be multiple, at the first line end 12 of the first signal line 18 and The second line end 13 is disposed in the same layer, and the second signal line 11 is disposed in a different layer from the first line end 12 and the second line end 13.
  • the plurality of second signal lines 11 may be disposed in the same layer or in different layers, such as As shown in FIG.
  • the first line end 12 and the second line end 13 of the first signal line 18 are disposed in the same layer, and the second signal line 11 is disposed in a different layer from the first line end 12 and the second line end 13, and the second signal is The line 11 is two, and the two second signal lines 11 are disposed in the same layer.
  • the second signal line 11 may be an odd data detection line and an even data detection line; for example, as shown in FIG. 6, the first signal line The first line end 12 and the second line end 13 of the 18 are disposed in the same layer, and the second signal line 11 is disposed in a different layer from the first line end 12 and the second line end 13 , and the second signal line 11 is two and two second The signal line 11 is arranged in a different layer.
  • the conductive layer for conducting the first line end 12 and the second line end 13 may be an indium tin oxide layer.
  • the first line end 12 and the second line end 13 are respectively provided with via holes 17 for conducting with the conductive layer 14.
  • the hole 17 or other regions having a small radius of curvature are also easy to collect electrostatic charges, and the first antistatic structure 16 disposed on the first wire end 12 and the second wire end 13 can also release and unblock the electrostatic charge near the via hole; As shown in FIG.
  • the second signal line 11 and one or both sides of the corresponding area of the conductive layer 14 are provided with a plurality of second antistatic structures 19, specifically
  • the second antistatic structure 19 can be a discharge tip.
  • the second antistatic structure 19 on one or both sides of the second signal line 11 may be formed simultaneously with the second signal line 11 as a part of the second signal line 11.
  • first line end 12 and the second line end 13 of the first signal line 18 are disposed in the same layer and are disposed in the same layer as the at least one second signal line 11.
  • the first signal line 18 may be a test signal line or a data detection line
  • the second signal line 11 may be a common electrode line.
  • the second signal line 11 crossing the first signal line 18 may be one or more, and the first line end 12 and the second line end 13 of the first signal line 18 are disposed in the same layer.
  • the second signal line 11 crossing the first signal line 18 may be one, and the first of the first signal line 18
  • the line end 12 is disposed in the same layer as the second line end 13 and is disposed in the same layer as the second signal line 11.
  • the conductive layer 14 of the first signal line 18 bypasses the second signal line 11 and turns on the first line end 12 and the second line. End 13.
  • the conductive layer 14 may be an indium tin oxide layer.
  • the plurality of second signal lines 11 may be disposed in the same layer, that is, the first of the first signal lines 18
  • the line end 12 is disposed in the same layer as the second line end 13 and is disposed in the same layer as the plurality of second signal lines 11; or, the plurality of second signal lines 11 may be disposed in different layers, that is, the first signal line 18
  • the first line end 12 is disposed in the same layer as the second line end 13 and is disposed in the same layer as the at least one second signal line 11 of the plurality of second signal lines 11, and the other second signal lines 11 and the first line end 12,
  • the second line end 13 is arranged in a different layer.
  • FIGS. 4, 5, and 6 An embodiment of the structure of the array substrate having the plurality of second signal lines 11 and the positional relationship between the plurality of second signal lines 11 can be referred to FIGS. 4, 5, and 6. It is worth mentioning that the specific description of the structure of the first line end 12, the via hole 17 on the second line end 13, and the second antistatic structure 19 on the second signal line 11 can be referred to the previous embodiment. This will not be repeated here.
  • first line end 12 and the second line end 13 of the first signal line 18 may be disposed in different layers, and one of the first line end 12 and the second line end 13 of the first signal line 18 may be It is disposed in the same layer as at least one second signal line 11.
  • the conductive layer 14 is disposed.
  • the first line end 12 and the second line end 13 provided in different layers are turned on bypassing the second signal line 11. It should be noted that if there are multiple second signal lines 11 crossing the same first signal line 18, the plurality of second signal lines 11 may be disposed in the same layer. For example, the first line end 12 may be multiple with the second line.
  • the signal line 11 is disposed in the same layer, and the second line end 13 is disposed in a different layer from the plurality of second signal lines 11; or, the plurality of second signal lines 11 may be disposed in different layers, for example, the first line end 12 and the plurality of lines At least one of the second signal lines 11 is disposed in the same layer, and the other second signal lines 11 are disposed in a different layer from the first line end 12.
  • An embodiment of the structure of the array substrate having the plurality of second signal lines 11 and the positional relationship between the plurality of second signal lines 11 can be referred to FIGS. 4, 5, and 6. It is worth mentioning that the specific description of the structure of the first line end 12, the via hole 17 on the second line end 13, and the second antistatic structure 19 on the second signal line 11 can be referred to the previous embodiment. This will not be repeated here.
  • the embodiment of the present invention further provides a display device, which may include the array substrate described in any of the above embodiments, and the array substrate of the display device has the same advantages as the array substrate in the above embodiment. , will not repeat them here. Since the interference phenomenon generated by the intersection of the signal lines in the array substrate is reduced, the performance of the array substrate is improved, and thus the display performance of the display device is improved.
  • the display device can be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板和显示装置，涉及显示技术领域。所述阵列基板包括衬底基板（10），交叉设置在衬底基板（10）上方的多条第一信号线（18）和多条第二信号线（11）；第一信号线（18）包括第一线端（12）和第二线端（13），以及与第二信号线（11）相对用于连接第一线端（12）和第二线端（13）的导电层（14），且导电层（14）与第二信号线（11）之间设有绝缘层（15），第一线端（12）、第二线端（13）与导电层（14）的连接处分别设有多个第一防静电结构（16）。所述显示装置包括上述技术方案所提的阵列基板。所述阵列基板和显示装置可减小交叉的多条信号线之间的干扰。

Description

一种阵列基板和显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板和显示装置。
背景技术
随着电子设备的迅速发展，显示面板越来越多的应用于电子设备中。现有的显示面板通常包括阵列基板和彩膜基板，而阵列基板是显示面板的重要组成之一。
在阵列基板中通常设有多条信号线，比如栅线、数据线、栅检测线、数据检测线以及公共电极线等，由于阵列基板中的信号线数量众多，经常会出现多条信号线交叉的现象，当交叉的多条信号线中的至少一条信号线中出现静电释放信号时，在多条信号线的交叉区域会聚集有静电电荷，使得多条信号线的交叉区域产生电容耦合，从而在多条信号线的交叉区域产生干扰现象，进而会降低阵列基板的性能。
发明内容
本发明的目的在于提供一种阵列基板和显示装置，用于减轻多条信号线的交叉区域产生的干扰现象，提高阵列基板的性能。
为了实现上述目的，本发明提供如下技术方案：
一方面，本发明提供了一种阵列基板，该阵列基板包括衬底基板，交叉设置在衬底基板上方的多条第一信号线和多条第二信号线；所述第一信号线包括第一线端和第二线端，以及与所述第二信号线相对用于连接第一线端和第二线端的导电层，且所述导电层与所述第二信号线之间设有绝缘层，所述第一线端、所述第二线端与所述导电层的连接处分别设有多个第一防静电结构。
在一个实施例中，每条所述第一信号线的所述第一线端、所述第二线端上可分别设有用于与所述导电层导通的过孔。
在另一实施例中，所述第二信号线与所述导电层对应区域的一侧或两侧设有多个第二防静电结构。
在实施例中，所述第一或第二防静电结构可以为放电尖端。
在另一实施例中，多条所述第二信号线可以异层设置或同层设置。
在另一实施例中，所述第一信号线的第一线端和第二线端可同层设置，所述第二信号线与所述第一信号线的第一线端、第二线端可异层设置。
在又一实施例中，所述第一信号线的第一线端与第二线端可同层设置，且与至少一条所述第二信号线同层设置。
在又一实施例中，所述第一信号线的第一线端和第二线端可异层设置，所述第一信号线的第一线端和第二线端中的一个线端与至少一条所述第二信号线可同层设置。
在一个实施例中，所述第一信号线可以为栅检测线，所述第二信号线可以为数据检测线。
在另一实施例中，所述第一信号线可以为开关线或数据检测线，所述第二信号线可以为公共电极线。
在前述的各实施中，所述导电层可以为氧化铟锡层。
另一方面，本发明提供了一种显示装置，包括上述技术方案中任一技术方案所述的阵列基板。
本发明提供的阵列基板和显示装置中，第一信号线与第二信号线交叉设置，其中，第一信号线包括第一线端、第二线端以及导通第一线端和第二线端的导电层，导电层与第二信号线之间设有绝缘层，使得在第一信号线和第二信号线的交叉区域，第一信号线和第二信号线之间的垂直距离增大，减少了聚集在第一信号线和第二信号线的交叉区域的静电电荷；而且，由于在第一信号线的第一线端、第二线端与导电层的连接处分别设有多个第一防静电结构，该第一防静电结构能够在第一信号线和/或第二信号线中出现静电释放信号时，将第一信号线和第二信号线的交叉区域聚集的静电电荷疏导、释放，从而减轻交叉的第一信号线和第二信号线的电容耦合，减轻了第一信号线和第二信号线的交叉区域的干扰现象，进而提高了阵列基板的性能。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为根据本发明的一个实施例的阵列基板的平面结构示意图；
图2为根据本如图1所示的阵列基板中的第一信号线的结构示意图；
图3为图1所示的阵列基板沿着图1中的A-A’线条得到的剖视图；
图4为根据本发明的另一实施例的阵列基板的平面结构示意图；
图5为图4所示的阵列基板沿着图4中的B-B’线条得到的剖视图；
图6为根据本发明的另一实施例的阵列基板沿着图4中的B-B’线条得到的剖视图；
图7为根据本发明的又一实施例的阵列基板的平面结构示意图；
图8为图7所示的阵列基板沿着图7中的C-C’线条得到的剖视图；
图9为根据本发明的又一实施例的阵列基板的剖视图。
附图标记：
10-衬底基板，             11-第二信号线，
12-第一线端，             13-第二线端，
14-导电层，               15-绝缘层，
16-第一防静电结构，       17-过孔，
18-第一信号线             19-第二防静电结构。
具体实施方式
为了进一步说明本发明实施例提供的阵列基板和显示装置，下面结合说明书附图进行详细描述。
请参阅图1、图2和图3，本发明实施例提供的阵列基板可包括：衬底基板10，交叉设置在衬底基板10上方的第一信号线18和第二信号线11，其中，第一信号线18或第二信号线11可以为栅线、数据线、数据检测线、公共电极线、测试信号线或短路环等等；如图2所示，第一信号线18可包括第一线端12、第二线端13以及与第二信号线11相对用于连接第一线端12和第二线端13的导电层14，请参阅图1和图3，其中，导电层14与第二信号线11之间可设有绝缘层15，从而使得导电层14绕过第二信号线11，避免与第二信号线11接触，且第一信号线18的第一线端12、第二线端13与导电层14的连接处可设有多个第一防静电结构16。
本发明实施例提供的阵列基板中，第一信号线18与第二信号线11交叉设置，其中，第一信号线18包括第一线端12、第二线端13以及 导通第一线端12和第二线端13的导电层14，导电层14与第二信号线11之间设有绝缘层15，使得在第一信号线18和第二信号线11的交叉区域，第一信号线18和第二信号线11之间的垂直距离增大，减少因第一信号线18和第二信号线11距离过近而聚集的静电电荷，在第一信号线18的第一线端12、第二线端13分别与导电层14的连接处设有多个第一防静电结构16，该第一防静电结构16能够在第一信号线18和/或第二信号线11中出现静电释放信号时，将第一信号线18和第二信号线11的交叉区域聚集的静电电荷疏导、释放，从而减轻交叉的第一信号线18和第二信号线11的电容耦合，减少了第一信号线18和第二信号线11的交叉区域产生的干扰现象，进而提高了阵列基板的性能。同时，通过第一防静电结构16释放静电电荷还可以防止静电电荷烧毁导电层14。第一防静电结构16可以作为第一信号线18的第一线端或第二线端的一部分与第一线端或第二线端同时形成。
在前述实施例的基础上，根据第一信号线18的第一线端12、第二线端13和第二信号线11之间的位置关系，还可以存在多种其它的结构形式的阵列基板的实施例。
在另一实施例中，第一信号线18的第一线端12和第二线端13可以同层设置，第二信号线11与第一信号线18的第一线端12、第二线端13可以异层设置，其中，第一信号线18可以为栅检测线，第二信号线11可以为数据检测线。
请参阅图4、图5和图6，与一条第一信号线18交叉的第二信号线11的数目可以为一条，也可以为多条，在第一信号线18的第一线端12和第二线端13同层设置，第二信号线11与第一线端12、第二线端13异层设置的场景下，多条第二信号线11可以同层设置，也可异层设置，比如：如图5所示，第一信号线18的第一线端12和第二线端13同层设置，第二信号线11与第一线端12、第二线端13异层设置，第二信号线11为两条，且两条第二信号线11同层设置，例如：第二信号线11可以为奇数据检测线和偶数据检测线；又比如：如图6所示，第一信号线18的第一线端12和第二线端13同层设置，第二信号线11与第一线端12、第二线端13异层设置，第二信号线11为两条，且两条第二信号线11异层设置。
在上述结构的基础上，需要说明的是，用于导通第一线端12和第二线端13的导电层可以为氧化铟锡层。其中，第一线端12、第二线端13上可分别设有用于与导电层14导通的过孔17，在制备阵列基板的过程中，比如在导电层14的蒸镀流程中，在过孔17或者其他一些曲率半径很小的区域也很容易聚集静电电荷，第一线端12、第二线端13上设置的第一防静电结构16还能够释放、疏导过孔附近的静电电荷；而且，如图4所示，为了进一步释放第二信号线11上的静电电荷，第二信号线11与导电层14对应区域的一侧或两侧设有多个第二防静电结构19，具体的第二防静电结构19可以为放电尖端。第二信号线11的一侧或两侧的第二防静电结构19可以作为第二信号线11的一部分与第二信号线11同时形成。
在另一实施例中，第一信号线18的第一线端12与第二线端13可同层设置，且与至少一条第二信号线11同层设置。其中，第一信号线18可以为测试信号线或数据检测线，第二信号线11可以为公共电极线。
与之前的实施例相似，与一条第一信号线18交叉的第二信号线11可以为一条也可以为多条，对于第一信号线18的第一线端12与第二线端13同层设置，且与至少一条第二信号线11同层设置的场景，请参阅图7和图8，其中与第一信号线18交叉的第二信号线11可以为一条，第一信号线18的第一线端12与第二线端13同层设置，且与第二信号线11同层设置，第一信号线18的导电层14绕过第二信号线11而导通第一线端12和第二线端13。导电层14可以为氧化铟锡层。需要说明的是，在与第一信号线18交叉的第二信号线11为多条的情形中，多条第二信号线11可以同层设置，也就是说，第一信号线18的第一线端12与第二线端13同层设置，且与多条第二信号线11同层设置；或者，多条第二信号线11也可以异层设置，也就是说，第一信号线18的第一线端12与第二线端13同层设置，且与多条第二信号线11中的至少一条第二信号线11同层设置，其他的第二信号线11与第一线端12、第二线端13异层设置。具有多条第二信号线11的阵列基板的结构，以及多条第二信号线11之间的位置关系的实施例可以参考图4、图5和图6。值得一提的是，关于第一线端12、第二线端13上的过孔17，以及第二信号线11上的第二防静电结构19等结构的具体说明可参照之前的实施例，在此不再赘述。
在又一实施例中，第一信号线18的第一线端12和第二线端13可以异层设置，第一信号线18的第一线端12和第二线端13中的一个线端可以与至少一条第二信号线11同层设置。
请参阅图9，在第一信号线18的第一线端12和一条第二信号线11同层设置，第二线端13与第一线端11异层设置的场景下，其中，导电层14绕过第二信号线11而导通设于不同层的第一线端12和第二线端13。需要说明的是，若与同一条第一信号线18交叉的第二信号线11为多条，多条第二信号线11可以同层设置，比如，第一线端12可以与多条第二信号线11同层设置，第二线端13与上述多条第二信号线11异层设置；或者，多条第二信号线11也可以异层设置，比如，第一线端12与多条第二信号线11中的至少一条第二信号线11同层设置，其他的第二信号线11与第一线端12异层设置。具有多条第二信号线11的阵列基板的结构，以及多条第二信号线11之间的位置关系的实施例可以参考图4、图5和图6。值得一提的是，关于第一线端12、第二线端13上的过孔17，以及第二信号线11上的第二防静电结构19等结构的具体说明可参照之前的实施例，在此不再赘述。
本发明实施例还提供了一种显示装置，该显示装置可包括上述实施例中的任意实施例所描述的阵列基板，所述显示装置的阵列基板与上述实施例中的阵列基板具有的优势相同，此处不再赘述。由于减少了阵列基板中信号线交叉区域产生的干扰现象，提高了阵列基板的性能，因此，提高了显示装置的显示性能。该显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种阵列基板，该阵列基板包括：衬底基板，交叉设置在衬底基板上方的多条第一信号线和多条第二信号线；其中所述第一信号线包括第一线端和第二线端，以及与所述第二信号线相对用于连接所述第一线端和所述第二线端的导电层，且所述导电层与所述第二信号线之间设有绝缘层，所述第一线端、所述第二线端与所述导电层的连接处分别设有多个第一防静电结构。
  2. 根据权利要求1所述的阵列基板，其中每条所述第一信号线的所述第一线端、所述第二线端上分别设有用于与所述导电层导通的过孔。
  3. 根据权利要求1所述的阵列基板，其中所述第二信号线与所述导电层对应区域的一侧或两侧设有多个第二防静电结构。
  4. 根据权利要求1或3所述的阵列基板，其中所述第一防静电结构或第二防静电结构为放电尖端。
  5. 根据权利要求1所述的阵列基板，其中多条所述第二信号线异层设置或同层设置。
  6. 根据权利要求1-3中任意一项所述的阵列基板，其中所述第一信号线的第一线端和第二线端同层设置，所述第二信号线与所述第一信号线的第一线端、第二线端异层设置。
  7. 根据权利要求1、2、3或5所述的阵列基板，其中所述第一信号线的第一线端与第二线端同层设置，且与至少一条所述第二信号线同层设置。
  8. 根据权利要求1、2、3或5所述的阵列基板，其中所述第一信号线的第一线端和第二线端异层设置，所述第一信号线的第一线端和第二线端中的一个线端与至少一条所述第二信号线同层设置。
  9. 根据权利要求6所述的阵列基板，其中所述第一信号线为栅检测线，所述第二信号线为数据检测线。
  10. 根据权利要求7所述的阵列基板，其中所述第一信号线为测试信号线或数据检测线，所述第二信号线为公共电极线。
  11. 根据权利要求1-3中任意一项所述的阵列基板，其中所述导电层为氧化铟锡层。
  12. 一种显示装置，所述显示装置包括权利要求1-11中任意一项所述的阵列基板。
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