WO2016155612A1

WO2016155612A1 - Improved cascode radio frequency power amplifier

Info

Publication number: WO2016155612A1
Application number: PCT/CN2016/077787
Authority: WO
Inventors: 陈高鹏; 陈俊; 刘磊; 张辉; 黄清华
Original assignee: 宜确半导体（苏州）有限公司
Priority date: 2015-03-31
Filing date: 2016-03-30
Publication date: 2016-10-06
Also published as: CN104702226A

Abstract

An improved cascode radio frequency power amplifier. A common-source-stage transistor gate G1, a common-source-stage transistor source S, a common-gate-stage transistor gate G2 and a common-gate-stage transistor drain D are transversely disposed on a substrate. A radio frequency input end RFin is connected to the common-source-stage transistor gate G1 by means of a metal wire, the common-source-stage transistor source S is connected to a grounding hole array (402) by means of a metal wire, the common-gate-stage transistor gate G2 is connected to a bias circuit by means of a metal wire (403), and the common-gate-stage transistor drain D is connected to a radio frequency output end RFout by means of a metal wire. By using a cascode structure and optimizing a layout structure, the radio frequency power amplifier has performance advantages of high gain, high power, high linearity, high efficiency and the like; a layout area equivalent to that of a single-transistor common-source structure radio frequency power amplifier is maintained, so that low-cost advantages are achieved.

Description

An improved cascode RF power amplifier

Technical field

The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to an improved cascode radio frequency power amplifier.

Background technique

The RF power amplifier is an indispensable key component in various wireless communication applications for power amplifying the modulated RF signal output by the transceiver to meet the power requirements of the RF signal required for wireless communication. RF power amplifiers are large-signal devices, and therefore semiconductor devices for manufacturing RF power amplifiers are required to have high breakdown voltage, high current density, and the like. Compared with small-signal circuits such as digital circuits and analog circuits, Si-based CMOS processes, GaAs-based HBT, pHEMT, etc., due to their high breakdown voltage and carrier mobility, in the field of RF power amplifiers It has been widely used.

As shown in Figure 1, a typical RF power amplifier circuit, transistor 103 as an important active device in the RF power amplifier, is usually fabricated in Si or GaAs process in practice; RF power amplifier input signal port RFin through the input matching network 101 is coupled to the gate of transistor 103; the gate of transistor 103 is also coupled to bias voltage port Vbias of the RF power amplifier via bias circuit 102; the source of transistor 103 is coupled to ground; the drain of transistor 103 is passed through a choke inductor 104 is coupled to the supply voltage port Vcc of the RF power amplifier; the supply voltage port Vcc is also coupled to one end of the decoupling capacitor 105, the other end of the decoupling capacitor 105 is coupled to ground; the drain of the transistor 103 is also coupled through the output matching network 106 The output signal port RFout of the RF power amplifier. The input signal voltage swing of the RF power amplifier is low, and after the power amplification of the transistor 103, the voltage swing of the output signal is greatly increased. For a typical Class-A/B/AB RF power amplifier, operating at supply voltage Vcc, the voltage swing across the transistor's drain can typically reach 2 × Vcc. For example, when the supply voltage Vcc of the RF power amplifier is 5V, the voltage swing on the drain of the transistor will reach 10V. If the RF power amplifier is operating in the Class-E state, the voltage swing across the drain of the transistor will be higher, above 3.5 × Vcc. It can be seen that the transistor in the RF power amplifier will withstand a swing much higher than the supply voltage, and breakdown of the transistor. Voltage and reliability put forward high requirements. The use of semiconductor processes with sufficiently high breakdown voltages to fabricate RF power amplifiers will severely limit the choice, losing design flexibility and reducing integration.

In order to enable smaller breakdown voltage semiconductor processes to be used to fabricate RF power amplifiers, the industry typically increases the breakdown voltage of devices by designing the RF power amplifier circuit as a cascode structure. As shown in Figure 2, it is a typical cascode RF power amplifier. The transistor 203 and the transistor 204 are active devices for realizing power amplification in the radio frequency power amplifier, and are usually fabricated by a Si or GaAs process in practice; the input signal port RFin of the radio frequency power amplifier is connected to the gate of the transistor 203 through the input matching network 201; The gate of transistor 203 is also coupled to bias voltage port Vbias1 of the RF power amplifier via bias circuit 202; the source of transistor 203 is coupled to ground; the drain of transistor 203 is coupled to the source of transistor 204; the gate of transistor 204 Connected to the bias voltage port Vbias2 of the RF power amplifier via bias circuit 205; the gate of transistor 204 is also coupled to one end of decoupling capacitor 206, the other end of decoupling capacitor 206 is coupled to ground; the drain of transistor 204 is passed through 扼The flow inductor 207 is coupled to the supply voltage port Vcc of the RF power amplifier; the supply voltage port Vcc is also coupled to one end of the decoupling capacitor 208, the other end of the decoupling capacitor 208 is coupled to ground; and the drain of the transistor 207 is also coupled through the output matching network 209. Connect to the output signal port RFout of the RF power amplifier. The input signal voltage swing of the RF power amplifier is low, and after the power amplification of the transistor 203 and the transistor 204, the voltage swing of the output signal is greatly increased. In a cascode RF power amplifier, transistor 203 is a common source stage and transistor 204 is a common gate; such a cascode structure has a higher power gain and a higher inverse than a single transistor common source structure. To the isolation; more importantly, the cascode structure has a higher breakdown voltage than the single transistor common source structure, allowing the RF power amplifier to have a higher operating voltage.

As shown in Figure 2, the cascode RF power amplifier operating in the Class-A/AB/B state has a RF voltage swing of 2 × Vcc at the drain of the transistor 204 and a RF voltage swing at the drain of the transistor 203. Not more than Vcc. Therefore, the voltage swing between the drain and the source of the transistor 203 and the transistor 204 does not exceed 2 × Vcc, which ensures that the transistor operates in a safe region.

The layout of the semiconductor device is designed to be a necessary step before chip fabrication for properly distributing the various portions of the same transistor on the silicon substrate in accordance with the designed circuit. In layout design, minimizing the area of the chip device is the ultimate goal of the designer.

As shown in FIG. 3a, it is a schematic diagram of a cascode structure, which is composed of a common source transistor 301 and a total The gate transistor 302 is composed; as shown in FIG. 3b, the circuit layout corresponding to the cascode structure. In Figure 3b, transistor 301 and transistor 302 are typically multi-gate finger structures on the layout, i.e., a plurality of transistors having a smaller gate width are connected in parallel to form transistor 301 and transistor 302 having a larger total gate width. The RF input signal is connected to the gate of the common source stage transistor 301 through a metal trace. The respective gate fingers of the transistor are labeled G in FIG. 3b; the source of the common source stage transistor 301 is connected to the ground hole array 303 through a metal trace. The source of the transistor is labeled S in Figure 3b; the drain of the common source transistor 301 is connected to the source of the common-gate transistor 302 through a metal trace, the drain of which is labeled D in Figure 3b; The gates of transistors 302 are connected together by metal traces 304 for biasing the gates of common gate stage transistors 302; the drains of common gate stage transistors 302 are connected together by metal traces and are connected to the RF The output signal port of the power amplifier is RFout.

It can be seen from the above that the cascode RF power amplifier has a performance advantage over the single-transistor common-source RF power amplifier, but the layout area of the cascode structure is almost twice that of the single-transistor common source structure. The single-transistor common source structure is more costly.

Summary of the invention

The object of the present invention is to provide an improved cascode RF power amplifier, adopting a cascode structure and optimizing a layout structure, so that the RF power amplifier has high gain, high power, high linearity, high efficiency and the like. The advantages, while maintaining a layout area comparable to a single-transistor common-source RF power amplifier, give it a cost advantage.

The technical solution of the present invention is:

An improved cascode RF power amplifier with a common source stage transistor gate G1, a common source stage transistor source S, a common gate stage transistor gate G2, and a common gate stage transistor drain D on a substrate The RF input terminal RFin is connected to the common source stage transistor gate G1 through a metal trace, and the common source stage transistor source S is connected to the ground hole array through a metal trace, and the common gate transistor gate G2 is connected to the bias circuit through a metal trace. The drain D of the common-gate transistor is connected to the RF output terminal RFout through a metal trace.

Further, the common source stage transistor is an enhanced pHEMT transistor, and the common gate stage transistor is a depletion type pHEMT transistor.

The advantages of the invention are:

1. The double gate transistor layout structure proposed by the invention has a very compact structure and simplifies The connection relationship of the traditional cascode transistor structure reduces the parasitic capacitance between the metal traces on the layout, which helps to improve the performance of the RF power amplifier; more importantly, the dual gate transistor structure is more conventional than the conventional The source common-gate transistor structure can reduce the layout area by at least 40%, and even has a considerable area with a single-transistor common-source structure, which has a high cost advantage.

2. The common source transistor is an enhancement transistor, and the common gate transistor is a depletion transistor. The RF power amplifier only needs a positive voltage and does not need a negative voltage to operate normally. At the same time, GaAs E/D pHEMT dual-gate transistors can greatly improve the leakage current characteristics of RF power amplifiers in individually enhanced pHEMT devices.

DRAWINGS

The present invention is further described below in conjunction with the accompanying drawings and embodiments:

1 is a circuit diagram of a typical RF power amplifier;

2 is a circuit diagram of a conventional RF power amplifier of a common cascode structure;

3a is a schematic diagram of a conventional cascode RF power amplifier;

3b is a circuit layout of a conventional cascode RF power amplifier;

4a is an equivalent schematic diagram of a radio frequency power amplifier of a cascode structure of the present invention;

4b is a circuit layout diagram of a radio frequency power amplifier of a cascode structure of the present invention;

4c is a cross-sectional view of a radio frequency power amplifier of a cascode structure of the present invention.

detailed description

The present invention will be further described in detail below with reference to the specific embodiments thereof and the accompanying drawings. It is to be understood that the description is not intended to limit the scope of the invention. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the inventive concept.

Example 1:

As shown in Figure 4a, in principle, a cascode transistor structure can be simplified to a transistor with four ports: common source transistor gate G1, common source transistor source S, common gate transistor gate Pole G2, common gate transistor drain D. The drain of the common source transistor is connected to the source of the common gate transistor and does not need to be connected to the outside world, so this node does not need to be embodied on the circuit; this cascode transistor structure as shown in FIG. 4a , defined in the present invention It is a "double gate transistor".

Figure 4b shows the layout structure of the dual gate transistor proposed in the present invention. The dual gate transistor 401 is depicted as a common multi-gate finger structure on the layout, that is, a plurality of transistors having a small gate width are connected in parallel to form a transistor 401 having a larger total gate width. The RF input signal RFin is connected to the common source stage transistor gate G1 of the dual gate transistor 401 through a metal trace; the common source stage transistor source S is connected to the ground hole array 402 through a metal trace, and the common gate transistor gate G2 passes through the metal Traces 403 are connected together for bias supply of the common-gate transistor gate G2; the common-gate transistor drain D is connected by metal traces and is connected to the output signal port RFout of the RF power amplifier.

As shown in FIG. 4c, which is a cross-sectional view of a dual gate transistor structure, on the semiconductor structure, the port pull-out structure of the node of the common-source transistor drain-common gate transistor source is omitted.

In summary, the dual gate transistor layout structure proposed by the present invention has a very compact structure, which simplifies the connection relationship of the conventional cascode transistor structure, thereby reducing the parasitic capacitance between the metal traces on the layout. Helps improve the performance of RF power amplifiers; more importantly, the dual-gate transistor structure can reduce the layout area by at least 40% compared to the traditional cascode transistor structure, even with a single-transistor common-source structure, which is very high. Cost advantage.

As a specific embodiment of the present invention, a dual gate transistor can be fabricated using a gallium arsenide enhancement/depletion mode high electron mobility field effect transistor process, namely a GaAs E/D pHEMT dual gate transistor. Also, the common-source stage of the dual-gate transistor uses an enhanced pHEMT device, and the common-gate stage uses a depletion-type pHEMT device. In this configuration, the dual gate transistor has a very high breakdown voltage and can be used in high supply voltage applications; thus the dual gate transistor also has higher output power margin, as well as higher gain characteristics, reverse isolation. And other indicators. Since the common source of the GaAs E/D pHEMT dual-gate transistor is an enhancement transistor and the common-gate stage is a depletion transistor, the RF power amplifier requires only a positive voltage and does not require a negative voltage to operate normally. At the same time, GaAs E/D pHEMT dual-gate transistors can greatly improve the leakage current characteristics of RF power amplifiers in individually enhanced pHEMT devices.

The above-described embodiments of the present invention are intended to be illustrative only and not to limit the invention. Therefore, any modifications, equivalent substitutions, improvements, etc., which are made without departing from the spirit and scope of the invention, are intended to be included within the scope of the invention. Rather, the scope of the appended claims is intended to cover all such modifications and modifications

Claims

An improved cascode RF power amplifier characterized in that a common source stage transistor gate G1, a common source stage transistor source S, a common gate stage transistor gate G2, and a common gate level are laterally disposed on a substrate. Transistor drain D; RF input terminal RFin is connected to common source transistor gate G1 through metal trace, common source transistor source S is connected to ground hole array through metal trace, and common gate transistor gate G2 is connected by metal trace The bias circuit, the drain D of the common-gate transistor is connected to the RF output terminal RFout through a metal trace.
The improved cascode radio frequency power amplifier of claim 1 wherein said common source stage transistor is an enhanced pHEMT transistor and said common gate stage transistor is a depletion mode pHEMT transistor.