WO2016155169A1 - 像素晶体管的栅极驱动方法和栅极驱动电路以及显示设备 - Google Patents

像素晶体管的栅极驱动方法和栅极驱动电路以及显示设备 Download PDF

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WO2016155169A1
WO2016155169A1 PCT/CN2015/085567 CN2015085567W WO2016155169A1 WO 2016155169 A1 WO2016155169 A1 WO 2016155169A1 CN 2015085567 W CN2015085567 W CN 2015085567W WO 2016155169 A1 WO2016155169 A1 WO 2016155169A1
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Prior art keywords
voltage
transistor
gate driving
pixel row
transistor turn
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Ceased
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PCT/CN2015/085567
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English (en)
French (fr)
Inventor
胡巍浩
廖燕平
郭鲁强
苏文刚
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/913,295 priority Critical patent/US10032427B2/en
Publication of WO2016155169A1 publication Critical patent/WO2016155169A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a gate driving method and a gate driving circuit of a pixel transistor and a display device including the same.
  • a pixel circuit for each pixel, a pixel circuit is provided for displaying corresponding pixels.
  • a pixel transistor and a pixel capacitor are disposed in each pixel circuit.
  • a liquid crystal display device is provided with a gate driving circuit for gate driving the pixel transistors in each pixel circuit, that is, controlling the switching of the pixel transistors. When the pixel transistor is turned on, the data voltage charges the pixel capacitor through the pixel transistor, and the charged pixel capacitor can control the output of the corresponding optical signal.
  • the gate driving circuit is provided with a plurality of output ports, each of which is connected to a gate driving line of one pixel row, the gate driving line being connected to a gate of a pixel transistor of all pixel circuits in the pixel row.
  • the gate driving circuit outputs a driving voltage to the connected gate driving line through an output port to control turning on and off of the pixel transistors of all the pixel circuits in the corresponding pixel row.
  • Resistor and parasitic capacitance are present on the gate drive line of each pixel row, which delays the transmission of the drive voltage.
  • the turn-on of the pixel transistor away from the gate driving circuit is subject to a large delay, so that the charging time of the corresponding pixel capacitor is insufficient, resulting in inaccurate pixel display.
  • embodiments of the present invention provide a gate driving method and a gate driving circuit of a pixel transistor and a display device including the same.
  • a gate driving method of a pixel transistor comprising:
  • the gate driving circuit Before a transistor on time of one pixel row, the gate driving circuit outputs a preset first voltage to a gate driving line of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage;
  • the gate driving circuit outputs a transistor turn-on voltage to a gate driving line of the pixel row when the transistor turn-on timing is reached.
  • the first voltage is less than the transistor turn-on voltage.
  • the gate driving circuit before the transistor turn-on time of the pixel row, the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row, including:
  • the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row from a preset time period before the transistor turning-on timing of the pixel row.
  • the preset duration is less than a time difference between a transistor off time of the preset pixel row and a transistor turn-on time.
  • the method further includes: when reaching a transistor turn-off timing of the pixel row, the gate driving circuit stops outputting the transistor turn-on voltage to a gate driving line of the pixel row, and The gate drive line output transistor turns off the voltage.
  • the gate driving circuit before the transistor turn-on time of the pixel row, the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row, including:
  • the gate driving circuit Before the transistor turn-on timing of the pixel row, the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row under the control of the first control signal.
  • the gate driving circuit when the transistor turn-on time is reached, the gate driving circuit outputs a transistor turn-on voltage to a gate driving line of the pixel row, including:
  • the gate driving circuit stops outputting the first voltage to the gate driving line under the control of the second control signal, and turns on the output transistor to the gate driving line Voltage.
  • the method further includes: when the transistor turn-off timing of the pixel row is reached, the gate driving circuit stops outputting the gate driving line to the gate driving line under the control of the second control signal The transistor turns on a voltage and outputs a transistor turn-off voltage to the gate drive line.
  • a gate driving circuit comprising:
  • a pre-charging module for outputting a preset first voltage to a gate driving line of the pixel row before a transistor turning-on time of a pixel row, wherein the first voltage is greater than a transistor Turn off the voltage
  • a control module configured to output a transistor turn-on voltage to the gate driving line of the pixel row when the transistor turn-on timing is reached.
  • the first voltage is less than the transistor turn-on voltage.
  • the pre-charging module is configured to:
  • a preset first voltage is output to the gate driving line of the pixel row from a preset time period before the transistor turn-on timing of the pixel row.
  • the preset duration is less than a time difference between a transistor turn-off timing of the pixel row and a transistor turn-on time.
  • control module is further configured to:
  • the transistor turn-off timing of the pixel row When the transistor turn-off timing of the pixel row is reached, the transistor turn-on voltage is stopped outputting to the gate drive line, and the transistor turn-off voltage is output to the gate drive line.
  • the pre-charging module is configured to:
  • a predetermined first voltage is output to the gate driving line of the pixel row under the control of the first control signal before the transistor turning-on timing of the pixel row.
  • control module is configured to:
  • control module is further configured to:
  • a display device comprising any one of the gate drive circuits as described above.
  • the parasitic capacitance on the gate drive line is charged before the transistor is turned on, so that when the gate drive circuit outputs a transistor turn-on voltage to the gate drive line when the transistor is turned on, the delay of the transistor turn-on voltage transmission can be reduced. Increase the charging time of the pixel capacitor to improve the accuracy of the pixel display.
  • FIG. 1 is a flow chart of a gate driving method of a pixel transistor according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an equivalent parasitic capacitance of a gate driving line according to an embodiment of the invention
  • 3a, 3b, and 3c are waveform diagrams of voltages at different positions of a gate driving line provided by the prior art
  • 4a, 4b, 4c are waveform diagrams of voltages at different positions of a gate drive line according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an input signal and an output signal of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 6 is a waveform diagram of input signals and output signals of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • a gate driving method of a pixel transistor is provided according to an embodiment of the present invention. As shown in FIG. 1, the processing of the method includes the following steps:
  • Step 101 Before a transistor turn-on timing of a pixel row, the gate driving circuit outputs a preset first voltage to a gate driving line of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage.
  • Step 102 when the transistor turn-on timing is reached, the gate drive circuit outputs a transistor turn-on voltage to the gate drive line of the pixel row.
  • the gate drive circuit stops outputting the first voltage to the gate drive line and outputs the transistor turn-on voltage to the gate drive line.
  • the above method can be applied to any row of pixels of a display device.
  • the above method can drive each row of pixels of a display device row by row.
  • the parasitic capacitance on the gate driving line is charged before the transistor is turned on, so that when the transistor is turned on, the gate driving circuit outputs a transistor turn-on voltage to the gate driving line, thereby reducing the transistor turn-on voltage transmission.
  • the delay is delayed, so that the charging time of the pixel capacitor can be increased, and the accuracy of the pixel display is improved.
  • a gate driving method of a pixel transistor is provided according to an embodiment of the present invention.
  • the execution body of the method may be a gate driving circuit in the display device, and the gate driving circuit may perform switching control on the pixel transistors of the plurality of pixel rows.
  • the gate drive circuit can include a plurality of output ports, each of which is coupled to a gate drive line of one pixel row.
  • Step 101 Before a transistor turn-on timing of a pixel row, the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row.
  • the gate driving line is a line connecting the output port of the gate driving circuit and the gate of the pixel transistor of each pixel circuit in the corresponding pixel row.
  • the equivalent parasitic capacitance of the gate drive line can be as shown in Figure 2.
  • the pixel rows described in Figures 1 and 2 can be any pixel row controlled by the gate drive circuit.
  • the transistor turn-on timing is a timing at which the transistor turn-on voltage VGH is input to the gate of the pixel transistor in the pixel row. Although in this particular implementation, the transistor turn-on voltage is at a high level VGH, one of ordinary skill in the art will recognize that in other implementations the transistor turn-on voltage can also be low.
  • the first voltage may be referred to as a pre-charge voltage, which may be referred to as VGM, for charging a parasitic capacitance in the gate drive line, and may set the first voltage to be greater than the transistor turn-off voltage.
  • a transistor turn-on time and a transistor turn-off time may be set for each pixel row, and the time period between the two times is the turn-on period of the corresponding transistor, that is, the data voltage of each pixel in the corresponding pixel row is The period during which the pixel capacitor is charged.
  • the period corresponding to each pixel row is sequentially arranged in time series, that is, the transistor turn-off timing of the second pixel row after the transistor turn-off timing of the first pixel row, and the transistor turn-on of the third pixel row after the transistor turn-off timing of the second pixel row Moments, and so on.
  • the gate driving circuit can output the precharge voltage VGM to the gate driving line of the pixel row through the corresponding output port at some time before the transistor is turned on.
  • the gate drive circuit outputs the transistor turn-off voltage VGL to the gate drive line. Since VGM is greater than VGL, when VGM is output, VGM starts charging the parasitic capacitance on the gate drive line.
  • the gate drive circuit can realize the output VGM in a variety of ways. It can add two input signals to the gate drive circuit, one input VGM constant signal, and the other input corresponding enable signal, which is used to trigger the gate drive circuit to externally.
  • the VGM is output, and the corresponding processing will be explained in detail later.
  • the input signal of the transistor turn-on voltage in the original gate drive circuit may be adjusted from the constant signal of VGH to a signal of alternating VGM level and VGH level without changing the input signal (VGM jumps to VGH).
  • the time point is the transistor turn-on time), and the time of the transistor turn-on voltage enable signal is advanced by a certain length of time.
  • the voltage range of the first voltage may be further defined such that the first voltage is less than the transistor turn-on voltage.
  • VGH can range from 25V to 35V
  • VGL can range from -4V to -8V.
  • VGM can be set between VGH and VGL, such as 3V.
  • VGM Since the value of VGM is between VGH and VGL, the pixel transistor of the pixel row enters a micro-on state at this time, so the charge of the pixel capacitor is less, and the data voltage of the pixel of the previous row can be reduced for the pixel row. influences.
  • step 101 may be as follows: the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row from a preset time period before the transistor turning-on time of the pixel row.
  • the preset duration may be set to be smaller than a time difference between a transistor turn-off timing of the pixel row and a transistor turn-on time, that is, less than an on-time of the transistor.
  • a smaller duration value may be selected as the preset duration according to actual requirements.
  • the preset duration may be 10% of the time difference between the transistor turn-off time and the transistor turn-on time, that is, the turn-on duration of the transistor. 10%.
  • Step 102 when the transistor turn-on timing is reached, the gate drive circuit outputs a transistor turn-on voltage to the gate drive line of the pixel row.
  • the gate drive circuit stops outputting the first voltage to the gate drive line and outputs the transistor turn-on voltage to the gate drive line.
  • the output voltage can be changed from VGM to VGH, and at this time, the data voltage is changed from the data voltage of the previous row of pixels of the pixel row to the data voltage of the pixel row.
  • the pixel transistors of the pixel row enter an on state, and the current data voltage charges the pixel capacitance of the pixel row.
  • the pixel transistor can be turned off later.
  • the following processing may be performed: when the transistor turn-off timing of the pixel row is reached, the gate driving circuit stops outputting the transistor turn-on voltage to the gate driving line of the pixel row, and outputs the transistor turn-on voltage to the gate driving line. The transistor turns off the voltage.
  • the output voltage can be transitioned from VGH to VGL when the transistor is turned off, and at this point, the data voltage of the pixel row ends.
  • the pixel transistor of the pixel row enters a closed state, and stops charging the pixel capacitor. At this time, each pixel of the pixel row outputs a voltage, and displays corresponding pixel content.
  • 3a, 3b, and 3c are waveform diagrams of voltages at different positions of the gate drive line in the case where the VGM is not output in the prior art.
  • the waveform of the voltage at the output port of the gate driving circuit can be as shown in FIG. 3a.
  • the waveform of the gate input voltage of the pixel transistor closer to the output port can be shown in FIG. 3b, and the pixel farther away from the output port.
  • the waveform of the gate input voltage of the transistor can be shown in Figure 3c.
  • 4a, 4b, and 4c are waveform diagrams of voltages at different positions of the gate drive lines when the above-described processing flow of the above embodiment is employed.
  • the waveform of the voltage at the output port of the gate driving circuit can be as shown in FIG.
  • step 101 The following may be as follows: Before the transistor turn-on timing of the pixel row, the gate driving circuit outputs a preset first voltage to the gate driving line of the pixel row under the control of the first control signal.
  • step 102 the processing of step 102 may be as follows: when the transistor turn-on time is reached, the gate driving circuit stops outputting the first voltage to the gate driving line under the control of the second control signal, and outputs the first voltage to the gate driving line.
  • the processing after the step 102 may be as follows: when the transistor turn-off timing of the pixel row is reached, the gate driving circuit stops outputting the transistor turn-on voltage to the gate driving line of the pixel row under the control of the second control signal, and The transistor turn-off voltage is output to the gate drive line.
  • the input signal and the output signal of the gate driving circuit can be as shown in FIG. 5, and the waveform of each signal can be as shown in FIG. 6.
  • the STV is a frame start signal
  • the CPV is a line switching signal for switching the current pixel row.
  • Constant signals VGH, VGM, and VGL are input to the input terminals VGH, VGM, and VGL, respectively.
  • Output 1, output 2, ... output n corresponds to a plurality of output ports of the gate drive circuit, each output port is connected to a gate drive line of one pixel row for connection to the gate drive line
  • the driving voltage is output to drive the pixel transistors of all the pixel circuits in the corresponding pixel row.
  • the output port is used for the output transistor turn-on voltage VGH, the transistor turn-off voltage VGL, or the pre-charge voltage VGM.
  • OE1 is the enable signal of VGH and is used to control the start and end of the VGH output.
  • OE3 is the enable signal of VGM and is used to trigger the output VGM.
  • the rising edge of OE3 triggers the gate drive circuit output VGM.
  • the falling edge of OE1 triggers the gate drive circuit to stop outputting VGM and output VGH, that is, the timing of this falling edge is the transistor turn-on time, and the rising edge of OE1 triggers the gate drive circuit to stop outputting VGH and output VGL, that is, the time of this rising edge is The transistor is turned off.
  • the parasitic capacitance on the gate drive line is charged before the transistor is turned on, so that the transistor turn-on voltage can be reduced when the gate drive circuit outputs a transistor turn-on voltage to the gate drive line when the transistor is turned on.
  • the delay of transmission can increase the charging time of the pixel capacitor and improve the accuracy of pixel display.
  • a gate driving circuit is provided, and the gate driving method of the pixel transistor in the above embodiment is based on the same technical concept, and specific processing of each module in the gate driving circuit The method can be referred to the corresponding content in the above method.
  • the gate driving circuit includes:
  • the pre-charging module 710 is configured to output a preset first voltage to a gate driving line of the pixel row before a transistor turning-on time of a pixel row, wherein the first voltage is greater than a crystal Tube closing voltage;
  • the control module 720 is configured to output a transistor turn-on voltage to a gate driving line of the pixel row when the transistor turn-on timing is reached. In a specific implementation, when the transistor turn-on time is reached, the control module 720 stops outputting the first voltage to a gate driving line of the pixel row, and outputs a transistor turn-on voltage to the gate driving line. .
  • the first voltage is less than the transistor turn-on voltage.
  • the pre-charging module 710 is configured to:
  • a preset first voltage is output to the gate driving line of the pixel row from a preset time period before the transistor turn-on timing of the pixel row.
  • the preset duration is less than a time difference between a transistor turn-off timing of the pixel row and a transistor turn-on time.
  • control module 720 is further configured to:
  • the transistor turn-off timing of the pixel row When the transistor turn-off timing of the pixel row is reached, the transistor turn-on voltage is stopped outputting to the gate drive line of the pixel row, and the transistor turn-off voltage is output to the gate drive line.
  • the pre-charging module 710 is configured to:
  • a predetermined first voltage is output to the gate driving line of the pixel row under the control of the first control signal before the transistor turning-on timing of the pixel row.
  • control module 720 is configured to:
  • control module 710 is further configured to:
  • a display device comprising any one of the gate driving circuits as described above for gate driving each pixel row of the display device.
  • the gate drive circuit and the corresponding gate drive method have been described in detail above and will not be repeated here.
  • the parasitic capacitance on the gate drive line is charged before the transistor is turned on, so that when the transistor is turned on, the gate drive circuit outputs a transistor turn-on voltage to the gate drive line, which can be reduced.
  • the transistor is delayed by the voltage transmission, which can increase the charging time of the pixel capacitor and improve the accuracy of the pixel display.
  • any reference signs placed in parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of the elements or the The word “a” or “an” or “an”
  • the invention may be implemented by means of hardware comprising several discrete elements, or by suitably programmed software or firmware, or by any combination thereof.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

公开了一种像素晶体管的栅极驱动方法和栅极驱动电路以及包括该栅极驱动电路的显示设备。该方法包括：在一像素行的晶体管开启时刻之前，栅极驱动电路向该像素行的栅极驱动线输出预设的第一电压（101）；其中，该第一电压大于晶体管关闭电压；当达到该晶体管开启时刻时，该栅极驱动电路向该栅极驱动线输出晶体管开启电压（102）。采用该方法，可以提高像素显示的准确度。

Description

像素晶体管的栅极驱动方法和栅极驱动电路以及显示设备 技术领域
本发明涉及显示技术领域，特别涉及一种像素晶体管的栅极驱动方法和栅极驱动电路以及包括所述栅极驱动电路的显示设备。
背景技术
在液晶显示设备中，对于每个像素，设置有一个像素电路，用于显示相应的像素。每个像素电路中设置有像素晶体管和像素电容。液晶显示设备中设置有栅极驱动电路，用于对各像素电路中像素晶体管进行栅极驱动，即对像素晶体管的开关进行控制。像素晶体管开启时，数据电压则会通过像素晶体管对像素电容进行充电，充电后的像素电容可以控制输出相应的光信号。
一般地，栅极驱动电路设置有多个输出端口，每个输出端口与一个像素行的栅极驱动线连接，该栅极驱动线与该像素行中所有像素电路的像素晶体管的栅极连接。栅极驱动电路通过某输出端口向连接的栅极驱动线输出驱动电压，以控制对应的像素行中所有像素电路的像素晶体管的开启和关闭。当驱动电压为高电平的晶体管开启电压VGH时，像素晶体管开启，当驱动电压为低电平的晶体管关闭电压VGL时，像素晶体管关闭。
发明内容
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：
每个像素行的栅极驱动线上都会存在电阻和寄生电容，它们会使得驱动电压的传输受到延迟。这样，远离栅极驱动电路的像素晶体管的开启则会受到较大的延迟，使相应的像素电容的充电时间不足，进而导致像素显示不准确。
为了解决或缓解上述现有技术中的至少一个缺陷或问题，本发明实施例提供了一种像素晶体管的栅极驱动方法和栅极驱动电路以及包括所述栅极驱动电路的显示设备。
根据本发明的一方面，提供了一种像素晶体管的栅极驱动方法，所述方法包括：
在一像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，其中所述第一电压大于晶体管关闭电压；
当达到所述晶体管开启时刻时，所述栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压。
可选地，所述第一电压小于所述晶体管开启电压。
可选地，在所述像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，包括：
从所述像素行的晶体管开启时刻之前预设时长时起，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压。
可选地，所述预设时长小于预设的像素行的晶体管关闭时刻与晶体管开启时刻的时间差。
可选地，所述方法还包括：当达到所述像素行的晶体管关闭时刻时，所述栅极驱动电路停止向所述像素行的栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
可选地，在所述像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，包括：
在所述像素行的晶体管开启时刻之前，栅极驱动电路在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。
可选地，当达到所述晶体管开启时刻时，所述栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压，包括：
当达到所述晶体管开启时刻时，所述栅极驱动电路在第二控制信号的控制下，停止向所述栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
可选地，所述方法还包括：当达到所述像素行的晶体管关闭时刻时，所述栅极驱动电路在所述第二控制信号的控制下，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
根据本发明的另一方面，提供了一种栅极驱动电路，所述栅极驱动电路包括：
预充模块，用于在一像素行的晶体管开启时刻之前，向所述像素行的栅极驱动线输出预设的第一电压，其中所述第一电压大于晶体管 关闭电压；
控制模块，用于当达到所述晶体管开启时刻时，向所述像素行的栅极驱动线输出晶体管开启电压。
可选地，所述第一电压小于所述晶体管开启电压。
可选地，所述预充模块，用于：
从所述像素行的晶体管开启时刻之前预设时长时起，向所述像素行的栅极驱动线输出预设的第一电压。
可选地，所述预设时长小于所述像素行的晶体管关闭时刻与晶体管开启时刻的时间差。
可选地，所述控制模块，还用于：
当达到所述像素行的晶体管关闭时刻时，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
可选地，所述预充模块，用于：
在所述像素行的晶体管开启时刻之前，在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。
可选地，所述控制模块，用于：
当达到所述晶体管开启时刻时，在第二控制信号的控制下，停止向所述栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
可选地，所述控制模块，还用于：
当达到所述像素行的晶体管关闭时刻时，在所述第二控制信号的控制下，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
根据本发明的另一方面，提供了一种显示设备，该显示设备包括如上所述的任何一个栅极驱动电路。
本发明实施例提供的技术方案可以实现如下有益效果中的至少一个有益效果和/或其它有益效果：
在晶体管开启时刻之前，对栅极驱动线上的寄生电容进行充电，这样，当晶体管开启时刻栅极驱动电路向栅极驱动线输出晶体管开启电压时，可以减少晶体管开启电压传输所受的延迟，增加像素电容的充电时间，提高像素显示的准确度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。应当意识到，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明一个实施例提供的像素晶体管的栅极驱动方法的流程图；
图2是根据本发明一个实施例提供的栅极驱动线的等效寄生电容示意图；
图3a、3b、3c是现有技术提供的栅极驱动线不同位置的电压的波形图；
图4a、4b、4c是根据本发明一个实施例提供的栅极驱动线不同位置的电压的波形图；
图5是根据本发明一个实施例提供的栅极驱动电路的输入信号和输出信号的示意图；
图6是根据本发明一个实施例提供的栅极驱动电路的输入信号和输出信号的波形图；
图7是根据本发明一个实施例提供的栅极驱动电路的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
根据本发明一个实施例提供了一种像素晶体管的栅极驱动方法。如图1所示，该方法的处理过程包括如下步骤：
步骤101，在一像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，其中第一电压大于晶体管关闭电压。
步骤102，当达到晶体管开启时刻时，栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压。在一个具体实现中，当达到晶体管开启时刻时，栅极驱动电路停止向栅极驱动线输出第一电压，并向栅极驱动线输出晶体管开启电压。
需要指出的是，上述方法可以适用于显示设备的任意一行像素。 不过，本领域普通技术人员可以意识到的是，上述方法可以逐行驱动显示设备的每一行像素。
通过上述方法，在晶体管开启时刻之前，对栅极驱动线上的寄生电容进行充电，这样，当晶体管开启时刻栅极驱动电路向栅极驱动线输出晶体管开启电压时，可以减少晶体管开启电压传输所受的延迟，从而可以增加像素电容的充电时间，提高像素显示的准确度。
根据本发明一个实施例提供了一种像素晶体管的栅极驱动方法。该方法的执行主体可以为显示设备中的栅极驱动电路，该栅极驱动电路可以对多个像素行的像素晶体管进行开关控制。该栅极驱动电路可以包括多个输出端口，每个输出端口分别与一个像素行的栅极驱动线连接。
下面将结合具体的实施过程，对图1所示的处理流程进行详细，内容可以如下：
步骤101，在一像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压。
其中，栅极驱动线是将栅极驱动电路的输出端口与对应的像素行中各像素电路的像素晶体管的栅极连接在一起的线路。栅极驱动线的等效寄生电容可以如图2所示。图1以及图2中所述的像素行可以是栅极驱动电路控制的任意像素行。晶体管开启时刻是向像素行中的像素晶体管的栅极输入晶体管开启电压VGH的时刻。尽管在这个具体实现中，晶体管开启电压为高电平VGH，但是本领域普通技术人员可以意识到，在其它实现中晶体管开启电压也可以为低电平。所述第一电压可以称作预充电压，可记做VGM，用于对栅极驱动线中的寄生电容进行充电，可以设置第一电压大于晶体管关闭电压。
在一个具体实现中，可以为每个像素行设置晶体管开启时刻和晶体管关闭时刻，此两个时刻之间的时段即为相应晶体管的开启时段，也就是相应的像素行中各像素的数据电压为像素电容充电的时段。每个像素行对应的时段按时序顺次排列，即第一像素行的晶体管关闭时刻之后为第二像素行的晶体管开启时刻，第二像素行的晶体管关闭时刻之后为第三像素行的晶体管开启时刻，依此类推。对于任意一个像素行，在其晶体管开启时刻之前的某个时刻，栅极驱动电路可以通过相应的输出端口向该像素行的栅极驱动线输出预充电压VGM。在输出 VGM之前，栅极驱动电路向该栅极驱动线输出的是晶体管关闭电压VGL，因为VGM大于VGL，所以在输出VGM时，VGM开始对栅极驱动线上的寄生电容进行充电。
栅极驱动电路实现输出VGM的方式可以多种多样，可以为栅极驱动电路增加两路输入信号，一路输入VGM的恒定信号，另一路输入对应的使能信号，用于触发栅极驱动电路对外输出VGM，相应的处理在后面内容中会由详细阐述。或者，也可以不增加输入信号，将原有的栅极驱动电路中晶体管开启电压的输入信号由VGH的恒定信号，调整为VGM电平、VGH电平交替变化的信号(VGM跳变为VGH的时间点为晶体管开启时刻)，并将晶体管开启电压的使能信号的时间提前一定时长。
可选地，可以进一步对第一电压的电压范围进行限定，使第一电压小于晶体管开启电压。
在一个具体实现中，VGH的取值范围可以为25V～35V，VGL的取值范围可以为-4V～-8V，相应的可以设置VGM的取值在VGH和VGL之间，如3V等。栅极驱动电路通过一像素行的栅极驱动线，将VGM输入所述像素行的像素晶体管的栅极时，因为还没有到达所述像素行的晶体管开启时刻，所以这时通过像素晶体管的数据电压是所述像素行的上一行像素的数据电压。由于VGM的取值在VGH和VGL之间，所以此时所述像素行的像素晶体管进入微开启状态，因此像素电容的充电电荷较少，可以减少上一行像素的数据电压对所述像素行的影响。
可选地，可以为第一电压设置一个合理的输出时长。相应地，步骤101的处理可以如下：从像素行的晶体管开启时刻之前预设时长时起，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压。
进一步可选地，可以设置该预设时长小于所述像素行的晶体管关闭时刻与晶体管开启时刻的时间差，也就是小于晶体管的开启持续时间。
在一个具体实现中，可以根据实际需求选择一个较小的时长值作为上述预设时长，例如，预设时长可以为晶体管关闭时刻与晶体管开启时刻的时间差的10％，即晶体管的开启持续时间的10％。栅极驱动电路通过像素行的栅极驱动线，将VGM输入所述像素行的像素晶体管的栅极时，因为还没有到达所述像素行的晶体管开启时刻，所以这时 通过像素晶体管的数据电压是所述像素行的上一行像素的数据电压。因为上述预设时长设置的比较短，所以像素电容的充电电荷较少，可以减少上一行像素的数据电压对所述像素行的影响。
步骤102，当达到晶体管开启时刻时，栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压。在一个具体实现中，当达到晶体管开启时刻时，栅极驱动电路停止向栅极驱动线输出第一电压，并向栅极驱动线输出晶体管开启电压。
在一个具体实现中，到达晶体管开启时刻时，输出电压则可以由VGM跳变为VGH，而且此时，数据电压由所述像素行的上一行像素的数据电压变化到所述像素行的数据电压。所述像素行的像素晶体管进入开启状态，当前的数据电压为所述像素行的像素电容充电。
可选地，后续还可以对像素晶体管进行关闭。相应地，在步骤102之后还可以进行如下处理：当达到像素行的晶体管关闭时刻时，栅极驱动电路停止向所述像素行的栅极驱动线输出晶体管开启电压，并向栅极驱动线输出晶体管关闭电压。
在一个具体实现中，到达晶体管关闭时刻时，输出电压则可以由VGH跳变到VGL，而且此时，像素行的数据电压结束输入。所述像素行的像素晶体管进入关闭状态，停止对像素电容充电，此时，所述像素行的每个像素电容输出电压，显示相应的像素内容。
图3a、3b、3c是现有技术中未输出VGM的情况下栅极驱动线不同位置的电压的波形图。栅极驱动电路输出端口处电压的波形可以如图3a所示，离输出端口距离较近处的像素晶体管的栅极输入电压的波形可以入图3b所示，离输出端口距离较远处的像素晶体管的栅极输入电压的波形可以入图3c所示。图4a、4b、4c是采用上述实施例的上述处理流程时栅极驱动线不同位置的电压的波形图。栅极驱动电路输出端口处电压的波形可以如图4a所示，离输出端口距离较近处的像素晶体管的栅极输入电压的波形可以入图4b所示，离输出端口距离较远处的像素晶体管的栅极输入电压的波形可以入图4c所示。可见，通过上述实施例的处理流程，可以有效延长像素电容的有效充电时长。
如前所述，为了实现上述流程的处理，可以为栅极驱动电路增加两路输入信号，一路输入VGM的恒定信号，另一路输入对应的使能信号，用于触发栅极驱动电路对外输出VGM。相应地，步骤101的处理 可以如下：在一像素行的晶体管开启时刻之前，栅极驱动电路在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。相应地，步骤102的处理可以如下：当达到晶体管开启时刻时，栅极驱动电路在第二控制信号的控制下，停止向栅极驱动线输出所述第一电压，并向栅极驱动线输出晶体管开启电压。另外，步骤102之后的处理可以如下：当达到像素行的晶体管关闭时刻时，栅极驱动电路在第二控制信号的控制下，停止向所述像素行的栅极驱动线输出晶体管开启电压，并向栅极驱动线输出晶体管关闭电压。
在一个具体实现中，栅极驱动电路的输入信号和输出信号可以如图5所示，各信号的波形可以如图6所示。其中，STV为帧开始信号，CPV为行切换信号，用于对当前像素行进行切换。输入端VGH、VGM和VGL处分别输入恒定信号VGH、VGM和VGL。输出1、输出2、......输出n对应于栅极驱动电路的多个输出端口，每个输出端口与一个像素行的栅极驱动线连接，用于向连接的栅极驱动线输出驱动电压，以驱动对应的像素行中所有像素电路的像素晶体管。在这个实施例中，所述输出端口用于输出晶体管开启电压VGH、晶体管关闭电压VGL或预充电压VGM。OE1为VGH的使能信号，用于控制VGH输出的开始和结束。OE3为VGM的使能信号，用于触发输出VGM。OE3的上升沿触发栅极驱动电路输出VGM。OE1的下降沿触发栅极驱动电路停止输出VGM并输出VGH，即此下降沿的时刻为晶体管开启时刻，OE1的上升沿触发栅极驱动电路停止输出VGH并输出VGL，即此上升沿的时刻为晶体管关闭时刻。
在上述实施例中，在晶体管开启时刻之前，对栅极驱动线上的寄生电容进行充电，这样，当晶体管开启时刻栅极驱动电路向栅极驱动线输出晶体管开启电压时，可以减少晶体管开启电压传输所受的延迟，从而可以增加像素电容的充电时间，提高像素显示的准确度。
根据本发明另一个实施例提供了一种栅极驱动电路，该栅极驱动电路与上述实施例中像素晶体管的栅极驱动方法是基于相同的技术构思，栅极驱动电路中各模块的具体处理方式可以参见上述方法中的相应内容。如图7所示，该栅极驱动电路包括：
预充模块710，用于在一像素行的晶体管开启时刻之前，向所述像素行的栅极驱动线输出预设的第一电压，其中所述第一电压大于晶体 管关闭电压；
控制模块720，用于当达到所述晶体管开启时刻时，向所述像素行的栅极驱动线输出晶体管开启电压。在一个具体实现中，当达到所述晶体管开启时刻时，所述控制模块720停止向所述像素行的栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
可选地，所述第一电压小于所述晶体管开启电压。
可选地，所述预充模块710，用于：
从所述像素行的晶体管开启时刻之前预设时长时起，向所述像素行的栅极驱动线输出预设的第一电压。
可选地，所述预设时长小于所述像素行的晶体管关闭时刻与晶体管开启时刻的时间差。
可选地，所述控制模块720，还用于：
当达到所述像素行的晶体管关闭时刻时，停止向所述像素行的栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
可选地，所述预充模块710，用于：
在所述像素行的晶体管开启时刻之前，在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。
可选地，所述控制模块720，用于：
当达到所述晶体管开启时刻时，在第二控制信号的控制下，停止向所述像素行的栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
可选地，所述控制模块710，还用于：
当达到所述像素行的晶体管关闭时刻时，在所述第二控制信号的控制下，停止向所述像素行的栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
根据本发明另一个实施例提供了一种显示设备，该显示设备包括如上所述的任意一个栅极驱动电路，用于栅极驱动所述显示设备的各像素行。该栅极驱动电路以及相应的栅极驱动方法已经在上面详细阐述了，在此就不再重复了。
需要说明的是：上述实施例仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要将上述功能分配给不同的功能模块 完成。可以将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述一个模块的功能可以由多个模块来完成，上述多个模块的功能也可以集成到一个模块中完成。
在本发明的上述实施例中，在晶体管开启时刻之前，对栅极驱动线上的寄生电容进行充电，这样，当晶体管开启时刻栅极驱动电路向栅极驱动线输出晶体管开启电压时，可以减少晶体管开启电压传输所受的延迟，从而可以增加像素电容的充电时间，提高像素显示的准确度。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。本发明的保护范围应以所附权利要求的保护范围为准。
本申请所使用的术语“和/或”仅仅是被用来描述一种关联对象的关联关系，表示可以存在三种关系。例如，“A和/或B”可以表示如下这三种情况：单独存在A，同时存在A和B，单独存在B。另外，本文中字符“/”一般表示前后关联对象是一种“或”的关系。
本申请用了诸如“第一”、“第二”、“第三”等之类的措词。在无附加上下文时，使用这样的措词并不旨在暗示排序而实际上用于标识目的。例如短语“第一版本”和“第二版本”未必意味着第一版本恰为第一个版本或者是在第二版本之前创建的或者甚至在第二版本之前请求或者操作第一版本。实际上，这些短语用来标识不同版本。
在权利要求书中，任何置于括号中的附图标记都不应当解释为限制权利要求。术语“包括”并不排除除了权利要求中所列出的元件或步骤之外的元件或步骤的存在。元件前的词语“一”或“一个”并不排除存在多个这样的元件。本发明可以借助于包括若干分离元件的硬件来实现，也可以通过适当编程的软件或固件来实现，或者通过它们的任意组合来实现。
在列举了若干装置的设备或系统权利要求中，这些装置中的一个或多个能够在同一个硬件项目中体现。仅仅某个措施记载在相互不同的从属权利要求中这个事实并不表明这些措施的组合不能被有利地使用。

Claims (17)

  1. 一种像素晶体管的栅极驱动方法，所述方法包括：
    在一像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，其中所述第一电压大于晶体管关闭电压；
    当达到所述晶体管开启时刻时，所述栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压。
  2. 根据权利要求1所述的方法，其中，所述第一电压小于所述晶体管开启电压。
  3. 根据权利要求1所述的方法，其中，在所述像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，包括：
    从所述像素行的晶体管开启时刻之前预设时长时起，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压。
  4. 根据权利要求3所述的方法，其中，所述预设时长小于所述像素行的晶体管关闭时刻与晶体管开启时刻的时间差。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    当达到所述像素行的晶体管关闭时刻时，所述栅极驱动电路停止向所述像素行的栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
  6. 根据权利要求1所述的方法，其中，在所述像素行的晶体管开启时刻之前，栅极驱动电路向所述像素行的栅极驱动线输出预设的第一电压，包括：
    在所述像素行的晶体管开启时刻之前，栅极驱动电路在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。
  7. 根据权利要求6所述的方法，其中，当达到所述晶体管开启时刻时，所述栅极驱动电路向所述像素行的栅极驱动线输出晶体管开启电压，包括：
    当达到所述晶体管开启时刻时，所述栅极驱动电路在第二控制信号的控制下，停止向所述栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    当达到所述像素行的晶体管关闭时刻时，所述栅极驱动电路在所述第二控制信号的控制下，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
  9. 一种栅极驱动电路，所述栅极驱动电路包括：
    预充模块，用于在一像素行的晶体管开启时刻之前，向所述像素行的栅极驱动线输出预设的第一电压，其中所述第一电压大于晶体管关闭电压；
    控制模块，用于当达到所述晶体管开启时刻时，向所述像素行的栅极驱动线输出晶体管开启电压。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述第一电压小于所述晶体管开启电压。
  11. 根据权利要求9所述的栅极驱动电路，其中，所述预充模块，用于：
    从所述像素行的晶体管开启时刻之前预设时长时起，向所述像素行的栅极驱动线输出预设的第一电压。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述预设时长小于所述像素行的晶体管关闭时刻与晶体管开启时刻的时间差。
  13. 根据权利要求9所述的栅极驱动电路，其中，所述控制模块，还用于：
    当达到所述像素行的晶体管关闭时刻时，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
  14. 根据权利要求9所述的栅极驱动电路，其中，所述预充模块，用于：
    在所述像素行的晶体管开启时刻之前，在第一控制信号的控制下，向所述像素行的栅极驱动线输出预设的第一电压。
  15. 根据权利要求14所述的栅极驱动电路，其中，所述控制模块，用于：
    当达到所述晶体管开启时刻时，在第二控制信号的控制下，停止向所述栅极驱动线输出所述第一电压，并向所述栅极驱动线输出晶体管开启电压。
  16. 根据权利要求15所述的栅极驱动电路，其中，所述控制模块， 还用于：
    当达到所述像素行的晶体管关闭时刻时，在所述第二控制信号的控制下，停止向所述栅极驱动线输出所述晶体管开启电压，并向所述栅极驱动线输出晶体管关闭电压。
  17. 一种显示设备，包括如权利要求9到16中任何一项所述的栅极驱动电路，用于栅极驱动所述显示设备的各像素行。
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