WO2016148460A1 - Transistor à couches minces à deux grilles - Google Patents

Transistor à couches minces à deux grilles Download PDF

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Publication number
WO2016148460A1
WO2016148460A1 PCT/KR2016/002509 KR2016002509W WO2016148460A1 WO 2016148460 A1 WO2016148460 A1 WO 2016148460A1 KR 2016002509 W KR2016002509 W KR 2016002509W WO 2016148460 A1 WO2016148460 A1 WO 2016148460A1
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layer
polymer
semiconductor layer
thin film
ion
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PCT/KR2016/002509
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Korean (ko)
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노용영
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동국대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • the present invention relates to a dual gate thin film transistor, and more particularly, to a dual gate thin film transistor including an electric dipole insulating film as one insulating film and the other insulating film as an ion layer.
  • the thin film transistor (TFT) capable of low temperature process in solution state can be applied to various flexible electronic devices implemented on polymer substrates such as driving devices of next-generation flexible displays or ultra low-cost RFID (Radio frequency identification) tag logic circuits. Due to the possibility of active research in recent years.
  • TFT thin film transistor
  • the semiconductor and insulator materials used in the solution process TFTs include organic semiconductor inks, metal oxide inks, nanomaterial-based semiconductor inks such as CNT and QD. Since they can be processed in solution, they can be manufactured cheaply through various printing processes, and they can be applied to roll-to-roll in the future and can mass-produce them at low processing speeds at low cost. As it is expected to be lowered, it can be said to have great commercial advantages.
  • the gate insulating film must exist between the semiconductor layer and the gate electrode in the transistor to have a high insulating property to prevent the current of the gate electrode from flowing directly into the semiconductor layer. At this time, the current flowing from the gate electrode to the semiconductor layer through the insulating film is called a gate leakage current. The higher the gate leakage current, the higher the power consumption of the manufactured electronic circuit and the greater the chance that the circuit will not function properly.
  • the organic insulating film has a relatively flexible characteristics compared to the inorganic insulating film has an advantageous property for the implementation of the next-generation flexible display or electronic circuit has been actively studied recently.
  • the organic insulating film made of a polymer has a relatively low dielectric constant and thus has a limit in lowering the driving voltage of the transistor due to the low capacitance.
  • One way to increase the capacitance is to apply a thin insulating film, but the polymer has a large amount of air voids and pinholes in the thin film and the density is low, so it is not easy to secure the desired insulating properties with a thin thickness. .
  • ion gel insulating films containing various ions and polymer insulators which impart the characteristics of the gate insulating film through ion dipoles, have a high dielectric constant and capacitance to drive the driving voltage of the transistor.
  • Conventional polymer insulating film has a capacitance of 1 to 100 nF / cm 2 Level or ion gel insulating film 1 ⁇ 100 uF / cm 2 Usually more than 100 times High charges can be induced at the same gate voltage.
  • the ion gel insulating film can effectively reduce the driving voltage, but since the formation of a double layer (electrical double layer) through the movement of ions and induces charge through it, the driving speed is significantly low, which is not practically applied commercially. .
  • the dual gate transistor refers to a transistor in which two gate electrodes, a top gate and a bottom gate, exist in one device with one semiconductor layer and two insulator layers interposed therebetween.
  • a structure is provided in which a conductive electrode and an insulating film are provided to the top gate and the gate insulating film, respectively, and a conductive electrode and a conventional polymer insulating film or an oxide insulating film are provided to the bottom gate and the gate insulating film with the semiconductor layer in the middle.
  • ions move by the gate voltage to form an electrical double layer.
  • a transistor using an ion gel as an insulating film shows a very low charge transfer rate.
  • the disadvantage of such an ion gel is that the ion has a relatively slow moving speed compared to the dipole, and thus the driving speed of the transistor is very slow due to the slow response speed of ions for fast switching to the gate voltage.
  • an object of the present invention is to provide a dual gate transistor capable of obtaining a high capacitance and at the same time having a high driving speed.
  • Another object of the present invention is to provide a dual gate transistor capable of driving a stable transistor with easy voltage correction.
  • the present invention to achieve the above object; A bottom gate electrode on the substrate; A gate insulating layer including the bottom gate electrode over the entire surface of the substrate; Source / drain electrodes spaced apart from each other on the gate insulating layer; A semiconductor layer located over an entire gate insulating layer including the source / drain electrodes; An ion layer located on the front surface of the semiconductor layer; And a top gate electrode positioned on the ion layer.
  • the present invention also provides a substrate; A bottom gate electrode on the substrate; An ion layer positioned over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer on the ion layer; A source / drain electrode included in an upper layer of the semiconductor layer and spaced apart from each other; A gate insulating layer disposed over an entire surface of the semiconductor layer on the source / drain electrodes; And a top gate electrode disposed on the gate insulating layer.
  • the thickness (h) of the semiconductor layer of the present invention provides a dual gate thin film transistor, characterized in that 1 ⁇ 10nm.
  • the ion layer of the present invention provides a dual gate thin film transistor comprising at least one of an ion gel, a solid electrolyte and an ionic liquid.
  • the ion gel or the solid electrolyte of the present invention is prepared by mixing an ionic liquid and a polymer, the polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride It provides a dual gate thin film transistor, characterized in that at least one selected from -hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE.
  • polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride It provides a dual gate thin film transistor, characterized in that at least one selected from -hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-Tr
  • the present invention provides a dual gate thin film transistor, characterized in that the mixing ratio of the ionic liquid and the polymer in the ion gel or the solid electrolyte is mixed in a weight ratio of 0.1: 9.9 to 9.9: 0.1.
  • the ionic liquid of the present invention is characterized in that at least one selected from the group consisting of [EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6 ], and [EMIM] [OctSO 4 ].
  • a dual gate thin film transistor is provided.
  • the gate insulating layer of the present invention is an organic polymer, polystyrene (PS, polystyrene), polymethacrylate (PMMA, polymethylmethacrylate), phenolic polymer, acrylic polymer, imide polymer, arylether polymer, amide polymer, fluorine At least one selected from the group consisting of a polymer, a p-xylene polymer, a vinyl alcohol polymer, and parylene, or as an oxide, SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3, and Ta.
  • a dual gate thin film transistor characterized in that at least one selected from the group consisting of 2 O 5 .
  • the present invention forms a high charge in the semiconductor layer due to the ion layer when the voltage is applied, a high charge amount in the channel is moved by diffusion, driving speed is improved on the source / drain electrode, characterized in that to provide.
  • the dual gate transistor when the ion layer is formed under the top gate, an ion gel or a solid electrolyte material is applied as the top gate insulating layer, thereby accumulating very high charges on the top of the semiconductor layer. If thin within 10 nm, this large amount of charge diffuses to the lower portion of the relatively low charge semiconductor layer, and a voltage is applied to the bottom gate electrode to move in the lower channel of the dual gate transistor. Since the bottom gate and the high gate speed can be simultaneously acquired due to the charge mobility, there is an effect of providing a transistor with significantly improved charge mobility and the driving speed. In other words, the high charge provided by the ion layer is diffused to the bottom of the semiconductor layer to be driven by the bottom gate.
  • the dual gate transistor when the ion layer is formed on the bottom gate, an ion gel or a solid electrolyte material is applied as the bottom gate insulating film to accumulate high charge under the semiconductor layer, and to diffuse it into the upper semiconductor layer. Since the voltage is applied to the top gate electrode to move in the upper channel of the dual gate transistor, it is possible to simultaneously obtain high charge mobility due to the bottom gate electrode and the ion layer and high driving speed due to the top gate. The effect is to provide an improved transistor.
  • the semiconductor thin film is thin, the high charge amount formed by the ion layer is moved into the channel to another gate, and the high charge amount is driven to a gate other than the ion layer to improve driving speed on the source / drain electrode. It works.
  • the transistor according to the present invention can be corrected by adjusting the voltage of the gate electrode in contact with the ion layer in order to prevent operation instability, thereby enabling stable transistor driving.
  • FIG. 1 schematically illustrates a thin film transistor manufacturing process according to an embodiment of the present invention.
  • FIG. 2 shows a thin film transistor structure according to an embodiment of the present invention.
  • 3 shows the amount of charge according to the height position when the semiconductor layer thickness of the transistor is 100 nm and 10 nm.
  • Figure 4 shows the change in voltage applied to the thin film transistor according to an embodiment of the present invention.
  • FIG. 5 shows a thin film transistor structure according to another embodiment of the present invention.
  • 1 schematically illustrates a thin film transistor manufacturing process according to an embodiment of the present invention.
  • 2 shows a thin film transistor structure according to an embodiment of the present invention.
  • a substrate is provided, a bottom gate electrode disposed on the substrate is formed, a bottom gate electrode is formed on the bottom gate electrode, and a gate insulating layer is disposed over the entire surface of the substrate.
  • a top gate electrode disposed on the ion layer to manufacture a thin film transistor.
  • the substrate may be a flexible substrate such as a transparent substrate such as glass, a silicon substrate, a plastic substrate or a metal foil substrate.
  • the plastic substrate include polyethersulphone, polyacrylate, polyetherimide, polyethyelenen napthalate, polyethyeleneterepthalate, polyphenylene sulfide , Polyallylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate and the like can be used.
  • a bottom gate electrode may be formed on the substrate.
  • the bottom gate electrode may form a gate electrode through thin film deposition or inkjet printing in a high vacuum chamber.
  • the gate electrode may include aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), molybdenum alloy (Mo-alloy), silver nanowires, gallium indium eutectic, PEDOT; It may be formed of any one selected from the PSS.
  • the bottom gate electrode may use the above materials as an ink to manufacture the gate electrode using a printing process such as inkjet printing or spraying. Through the printing process, the bottom gate electrode can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.
  • the bottom gate electrode may include the bottom gate electrode to form a gate insulating layer disposed over the entire surface of the substrate.
  • the gate insulating layer is preferably made of an organic polymer, but is not limited thereto, and may be formed of an oxide.
  • the organic polymer include polystyrene (PS), polymethacrylate (PMMA, polymethylmethacrylate), phenolic polymer, acrylic polymer, imide polymer such as polyimide, arylether polymer, amide polymer, fluorine polymer, p -It is preferable to use at least one selected from the group consisting of a zyrylene-based polymer, a vinyl alcohol-based polymer, parylene (parylene) and the like.
  • the gate insulating layer is preferably selected from one or more selected from the group consisting of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3, and Ta 2 O 5 .
  • the role of the gate insulating layer allows electrons to form inductive dipoles, thereby allowing the accumulation of charge.
  • the gate insulating layer has a high driving voltage due to a high dielectric constant, but allows the transistor to be driven at a high driving speed. High drive speeds in transistors of electronic devices such as computers that are currently used are obtained using such gate insulating layers.
  • Source / drain electrodes may be formed on the gate insulating layer to be spaced apart from each other.
  • the source / drain electrode may be formed of a single layer selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, or an alloy thereof, and may be bonded to Ti, Cr or Ni to improve adhesion. Further comprising a metal layer can be formed into a multi-layer.
  • a printing process such as inkjet printing or spraying. Through the printing process, the source / drain electrodes can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.
  • the semiconductor layer may be formed over the entire gate insulating layer by including the source / drain electrodes on the source / drain electrodes.
  • the semiconductor layer may be an N-type organic semiconductor, a P-type organic semiconductor, or an oxide semiconductor.
  • the N-type organic semiconductor is an acene-based material, a fully fluorinated acene-based material, a partially fluorinated acene-based material, a partially fluorinated oligothiophene-based material, a fullerene-based material, a fullerene-based material having a substituent, Fully fluorinated phthalocyanine-based materials, partially fluorinated phthalocyanine-based materials, perylene tetracarboxylic diimide-based materials, perylene tetracarboxylic dianhydride-based materials, naphthalene It is preferable to include any one of tetracarboxylic diimide-based material or naphthalene tetracarboxylic dianhydride-based material.
  • the acene-based material may be selected from anthracene,
  • the P-type organic semiconductor is acene (acene), poly-thienylenevinylene (poly-thienylenevinylene), poly-3-hexylthiophene (poly-3-hexylthiophen), alpha-hexathienylene ( ⁇ -hexathienylene), Naphthalene, alpha-6-thiophene, alpha-4-thiophene, alpha-4-thiophene, rubrene, polythiophene, polyparaphenylene Vinylene (polyparaphenylenevinylene), polyparaphenylene, polyfluorene, polythiophenevinylene, polythiophene-heterocyclicaromatic copolymer, triarylamine ( triarylamine) or derivatives thereof, wherein the acene group is any one of pentacene, perylene, tetratracene or anthracene.
  • an oxide semiconductor layer can be formed using IGZO, IZO, ZnO, etc. as an oxide semiconductor layer.
  • the semiconductor layer may be formed into a thin film by thermal evaporation or sputtering in a vacuum chamber. Solvent-soluble materials are also formed on source / drain electrodes through spin coating, spray, inkjet, flexography, screen, dip-coating and gravure. .
  • the pattern may be formed on the electrode and the local region of the substrate, and heat treatment or optical exposure may be performed to improve device performance such as semiconductor crystallinity and stability after forming the semiconductor layer.
  • the thickness h of the semiconductor layer is preferably 1 to 10 nm.
  • the thickness of the semiconductor layer refers to the gap between the upper portion of the source and drain electrodes and the lower portion of the ion layer.
  • the thickness of the transistor channel formed at the interface between the semiconductor and the insulator through the application of a gate voltage in an organic transistor and an oxide transistor which is usually driven in an accumulation mode is known to be about 1 to 5 nm (2 to 3 molecular layers).
  • the channel formed at the upper portion of the dual gate is mixed with the lower portion and the formed channel so that the charge formed at the upper portion or the lower portion can diffuse to the lower portion or the upper portion. This effect is doubled as the thickness of the semiconductor layer is thinner.
  • 3 shows the amount of charge according to the height position when the semiconductor layer thickness of the transistor is 100 nm and 10 nm.
  • an IGZO oxide semiconductor layer was formed as a semiconductor layer.
  • the semiconductor layer is 100 nm, the high charge amount due to the channels formed on the upper and lower portions is not effectively transferred to the middle of the semiconductor layer, and thus the charge amount on the upper and lower portions.
  • the amount of charge in the and the intermediate layer is greatly different.
  • the semiconductor layer is 10 nm, the charges formed on the upper and lower sides are effectively diffused in the intermediate layer, so that the amount of charge in the semiconductor layer is evenly spread in the semiconductor.
  • the semiconductor layer within 10 nm when the semiconductor layer within 10 nm is used, the high charge on the semiconductor layer formed by the ion gel is effectively diffused to the lower part of the semiconductor layer, so that the high driving speed can be obtained by the disappearance of the lower gate. It can be implemented at the same time.
  • An ion layer may be formed over the entire surface of the semiconductor layer.
  • the ionic layer may be formed of an ionic liquid, and may be formed of an ion gel or a solid electrolyte mixed with an ionic liquid and a polymer.
  • the ionic liquid may be formed by appropriately mixing a specific polymer.
  • the ion gel may be formed in a gel shape, and the solid electrolyte may be in a solid shape and have a more rigid form or elasticity than the ion gel.
  • Ionic liquids include 1-Ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6 ], and [EMIM] [OctSO 4 ]. You can choose one or more from the group you have made up.
  • the ion gel or the solid electrolyte is mixed with an ionic liquid and a polymer
  • the polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride-hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE, etc.
  • PS-PMMA-PS poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride-hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE, etc.
  • PS-PMMA-PS poly (styrene-b-methylmethacrylate-b-styrene) [PS-
  • the mixing ratio of the ionic liquid and the polymer may be mixed in a ratio of 0.1: 9.9 to 9.9: 0.1 by weight.
  • a solvent such as methylene chloride is required for mixing.
  • the mixing ratio of the ionic liquid, the polymer and the solvent is mixed at a weight ratio of about 10:90.
  • a solvent is prepared by mixing a ionic liquid and a polymer in a solvent, and then heating the solution on a hot plate at about 80 ° C. for about 6 hours.
  • the material may be completely dissolved and mixed in the ion gel to prepare an ion gel or a solid electrolyte.
  • Figure 4 shows the change in voltage applied to the thin film transistor according to an embodiment of the present invention.
  • the present invention a large amount of charges are formed in the semiconductor layer due to the ion layer positioned on the semiconductor layer, and the formed charges are easily diffused to the lower portion because the semiconductor layer is thin and driven by controlling the bottom gate electrode.
  • ⁇ charge is accumulated on the ion layer due to the + voltage application of the top gate electrode, and ⁇ charge is diffused and accumulated at the bottom due to the thin semiconductor layer, and the driving speed is fast between the source / drain electrodes.
  • a top gate electrode may be formed on the ion layer.
  • the top gate electrode may be formed in the same manner as the bottom gate electrode, and may be formed of aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), molybdenum alloy (Mo-alloy), It may be formed of any one selected from silver nanowire, gallium indium eutectic, and PEDOT.
  • the thin film transistor according to the embodiment of the present invention can be completed.
  • FIG. 5 shows a thin film transistor structure according to another embodiment of the present invention.
  • an ion layer may be formed on the bottom gate electrode, the substrate; A bottom gate electrode on the substrate; An ion layer positioned over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer on the ion layer; A source / drain electrode included in an upper layer of the semiconductor layer and spaced apart from each other; A gate insulating layer disposed over an entire surface of the semiconductor layer on the source / drain electrodes; And a top gate electrode disposed on the gate insulating layer.
  • the dual gate thin film transistor may be provided.
  • the thickness h of the semiconductor layer is preferably 1 to 10 nm, and the thickness of the semiconductor layer may be regarded as a gap between the lower portion of the source / drain electrode and the upper portion of the ion layer.
  • a glass substrate is prepared and a gate insulating layer is formed on the substrate.
  • the insulating layer is melted in n-butyl acetate using polystyrene (PS) and then spin coated. Using to form a gate insulating layer.
  • PS polystyrene
  • a source / drain electrode was formed on the gate insulating layer, and then P3HT was used to form the semiconductor layer, and the thickness h of the semiconductor layer was 10 nm.
  • a top gate electrode was formed in a portion of the upper portion of the ion layer, and aluminum (Al) was formed by evaporation to manufacture a thin film transistor.
  • a layer was formed on the gate insulating layer with the same material as that used for the ion layer.
  • a layer was formed on the ion layer with the same material as that used for the gate insulating layer.
  • Example 1 As a result, in Example 1, a very high charge is accumulated in the semiconductor layer and a voltage is applied to the bottom gate electrode to move in the channel of the transistor, so that the top gate electrode and the ion layer cause the bottom gate electrode with high charge mobility. High driving speed can be obtained at the same time.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un transistor à couches minces à deux grilles. Plus précisément, la présente invention concerne un transistor à couches minces à deux grilles comprenant : un substrat ; une électrode de grille inférieure positionnée sur le substrat ; une couche d'isolation de grille positionnée sur toute la surface du substrat y compris l'électrode de grille inférieure ; des électrodes de source/drain (S/D) positionnées sur la couche d'isolation de grille de manière à être espacées l'une de l'autre ; une couche semi-conductrice positionnée sur toute la surface de la couche d'isolation de grille y compris les électrodes de source/drain ; une couche ionisée positionnée sur toute la surface de la couche semi-conductrice ; et une électrode de grille supérieure positionnée sur la couche ionisée.
PCT/KR2016/002509 2015-03-17 2016-03-14 Transistor à couches minces à deux grilles WO2016148460A1 (fr)

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KR10-2015-0036433 2015-03-17
KR1020150036433A KR20160112030A (ko) 2015-03-17 2015-03-17 듀얼게이트 박막트랜지스터

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CN107393965A (zh) * 2017-07-17 2017-11-24 华南理工大学 平面双栅氧化物薄膜晶体管及其制备方法
CN108847424A (zh) * 2018-04-24 2018-11-20 京东方科技集团股份有限公司 薄膜晶体管、传感器、生物检测装置和方法
WO2019139577A1 (fr) * 2018-01-10 2019-07-18 Intel Corporation Transistors à couches minces à faible résistance de contact

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KR102251277B1 (ko) * 2019-04-03 2021-05-11 재단법인대구경북과학기술원 정전용량식 터치센서, 압전센서 및 듀얼게이트 트랜지스터를 포함하는 트랜지스터 모듈
KR102205569B1 (ko) * 2019-04-09 2021-01-20 중앙대학교 산학협력단 전기적으로 안정한 이온성 전해질 기반 유기 트랜지스터 및 이의 제조 공정

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EP2811525A1 (fr) * 2013-03-14 2014-12-10 Karlsruher Institut für Technologie Transistor à effet de champ commandé éledctro-chimiquement, procédé de sa fabrication, son utilisation, et électronique comprenant un tel transistor à effet de champ
JP2014229643A (ja) * 2013-05-20 2014-12-08 富士電機株式会社 有機トランジスタ及びその製造方法

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CN107393965A (zh) * 2017-07-17 2017-11-24 华南理工大学 平面双栅氧化物薄膜晶体管及其制备方法
WO2019139577A1 (fr) * 2018-01-10 2019-07-18 Intel Corporation Transistors à couches minces à faible résistance de contact
US11189733B2 (en) 2018-01-10 2021-11-30 Intel Corporation Thin-film transistors with low contact resistance
US11742429B2 (en) 2018-01-10 2023-08-29 Intel Corporation Thin-film transistors with low contact resistance
CN108847424A (zh) * 2018-04-24 2018-11-20 京东方科技集团股份有限公司 薄膜晶体管、传感器、生物检测装置和方法
CN108847424B (zh) * 2018-04-24 2021-09-03 京东方科技集团股份有限公司 薄膜晶体管、传感器、生物检测装置和方法

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