WO2016148460A1

WO2016148460A1 - Dual gate thin film transistor

Info

Publication number: WO2016148460A1
Application number: PCT/KR2016/002509
Authority: WO
Inventors: 노용영
Original assignee: 동국대학교 산학협력단
Priority date: 2015-03-17
Filing date: 2016-03-14
Publication date: 2016-09-22
Also published as: KR20160112030A

Abstract

The present invention relates to a dual gate thin film transistor. More specifically, the present invention provides a dual gate thin film transistor comprising: a substrate; a bottom gate electrode positioned on the substrate; a gate insulating layer positioned across the entire surface of the substrate including the bottom gate electrode; source/drain electrodes positioned on the gate insulating layer so as to be spaced apart from each other; a semiconductor layer positioned across the entire surface of the gate insulating layer including the source/drain electrodes; an ionized layer positioned on the entire surface of the semiconductor layer; and a top gate electrode positioned on the ionized layer.

Description

Dual Gate Thin Film Transistor

The present invention relates to a dual gate thin film transistor, and more particularly, to a dual gate thin film transistor including an electric dipole insulating film as one insulating film and the other insulating film as an ion layer.

The thin film transistor (TFT) capable of low temperature process in solution state can be applied to various flexible electronic devices implemented on polymer substrates such as driving devices of next-generation flexible displays or ultra low-cost RFID (Radio frequency identification) tag logic circuits. Due to the possibility of active research in recent years.

Recently, as various wearable devices have been introduced to the market, interest in flexible electronic circuits and devices has exploded, and manufacturing electronic devices and displays through the printing process will drastically lower manufacturing costs as printing newspapers on such flexible substrates. Can be. The semiconductor and insulator materials used in the solution process TFTs include organic semiconductor inks, metal oxide inks, nanomaterial-based semiconductor inks such as CNT and QD. Since they can be processed in solution, they can be manufactured cheaply through various printing processes, and they can be applied to roll-to-roll in the future and can mass-produce them at low processing speeds at low cost. As it is expected to be lowered, it can be said to have great commercial advantages.

However, current transistors manufactured through such a printing process have lower performance in charge mobility and poor device uniformity than silicon transistors manufactured by vacuum process. In particular, organic thin film transistors based on organic semiconductors have a low theoretical mobility of 100 cm2 / Vs due to the nature of organic materials, and actual mobility is difficult to be applied to devices requiring high performance of 10 cm2 / Vs at the current level. In addition, oxide-based transistors (eg IGZO) have a mobility of only 10-30 cm2 / Vs, requiring improvement.

On the other hand, in the transistor, physical properties required for the gate insulating film are high insulation properties and high dielectric constant. The gate insulating film must exist between the semiconductor layer and the gate electrode in the transistor to have a high insulating property to prevent the current of the gate electrode from flowing directly into the semiconductor layer. At this time, the current flowing from the gate electrode to the semiconductor layer through the insulating film is called a gate leakage current. The higher the gate leakage current, the higher the power consumption of the manufactured electronic circuit and the greater the chance that the circuit will not function properly.

In addition, a high dielectric constant is required so that a relatively large amount of current is induced in the semiconductor layer with respect to the voltage applied from the gate electrode. In particular, the organic insulating film has a relatively flexible characteristics compared to the inorganic insulating film has an advantageous property for the implementation of the next-generation flexible display or electronic circuit has been actively studied recently.

However, the organic insulating film made of a polymer has a relatively low dielectric constant and thus has a limit in lowering the driving voltage of the transistor due to the low capacitance. One way to increase the capacitance is to apply a thin insulating film, but the polymer has a large amount of air voids and pinholes in the thin film and the density is low, so it is not easy to secure the desired insulating properties with a thin thickness. .

Therefore, in order to effectively lower the driving voltage of a transistor to be applied to a display or an electronic device, a lot of research and development on materials and process technologies for a flexible organic insulating film having high dielectric constant and high insulating property are required.

Recently, ion gel insulating films containing various ions and polymer insulators, which impart the characteristics of the gate insulating film through ion dipoles, have a high dielectric constant and capacitance to drive the driving voltage of the transistor. There have been numerous reports of effective lowering. Conventional polymer insulating film has a capacitance of 1 to 100 nF / cm ² Level or ion gel insulating film 1 ~ 100 uF / cm ² Usually more than 100 times High charges can be induced at the same gate voltage.

However, the ion gel insulating film can effectively reduce the driving voltage, but since the formation of a double layer (electrical double layer) through the movement of ions and induces charge through it, the driving speed is significantly low, which is not practically applied commercially. .

Meanwhile, the dual gate transistor refers to a transistor in which two gate electrodes, a top gate and a bottom gate, exist in one device with one semiconductor layer and two insulator layers interposed therebetween. In the dual gate transistor, a structure is provided in which a conductive electrode and an insulating film are provided to the top gate and the gate insulating film, respectively, and a conductive electrode and a conventional polymer insulating film or an oxide insulating film are provided to the bottom gate and the gate insulating film with the semiconductor layer in the middle.

In the case of applying an ion gel insulating film to such a dual gate transistor, that is, forming an ion gel insulating film and applying a gate voltage, instead of forming a dipole, ions move by the gate voltage to form an electrical double layer. Although high capacitance can be obtained, through this, a transistor using an ion gel as an insulating film shows a very low charge transfer rate. The disadvantage of such an ion gel is that the ion has a relatively slow moving speed compared to the dipole, and thus the driving speed of the transistor is very slow due to the slow response speed of ions for fast switching to the gate voltage.

Accordingly, there is a demand for the development of a dual gate transistor capable of obtaining high capacitance and at the same time having a high driving speed.

[Preceding technical literature]

United States Patent Application Publication No. 2008-0191200, Korea Patent Application Publication No. 2012-0034349

SUMMARY OF THE INVENTION In order to overcome the above problems, an object of the present invention is to provide a dual gate transistor capable of obtaining a high capacitance and at the same time having a high driving speed.

Another object of the present invention is to provide a dual gate transistor capable of driving a stable transistor with easy voltage correction.

The present invention to achieve the above object; A bottom gate electrode on the substrate; A gate insulating layer including the bottom gate electrode over the entire surface of the substrate; Source / drain electrodes spaced apart from each other on the gate insulating layer; A semiconductor layer located over an entire gate insulating layer including the source / drain electrodes; An ion layer located on the front surface of the semiconductor layer; And a top gate electrode positioned on the ion layer.

The present invention also provides a substrate; A bottom gate electrode on the substrate; An ion layer positioned over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer on the ion layer; A source / drain electrode included in an upper layer of the semiconductor layer and spaced apart from each other; A gate insulating layer disposed over an entire surface of the semiconductor layer on the source / drain electrodes; And a top gate electrode disposed on the gate insulating layer.

In addition, the thickness (h) of the semiconductor layer of the present invention provides a dual gate thin film transistor, characterized in that 1 ~ 10nm.

In addition, the ion layer of the present invention provides a dual gate thin film transistor comprising at least one of an ion gel, a solid electrolyte and an ionic liquid.

In addition, the ion gel or the solid electrolyte of the present invention is prepared by mixing an ionic liquid and a polymer, the polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride It provides a dual gate thin film transistor, characterized in that at least one selected from -hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE.

In another aspect, the present invention provides a dual gate thin film transistor, characterized in that the mixing ratio of the ionic liquid and the polymer in the ion gel or the solid electrolyte is mixed in a weight ratio of 0.1: 9.9 to 9.9: 0.1.

In addition, the ionic liquid of the present invention is characterized in that at least one selected from the group consisting of [EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF ₆ ], and [EMIM] [OctSO ₄ ]. A dual gate thin film transistor is provided.

In addition, the gate insulating layer of the present invention is an organic polymer, polystyrene (PS, polystyrene), polymethacrylate (PMMA, polymethylmethacrylate), phenolic polymer, acrylic polymer, imide polymer, arylether polymer, amide polymer, fluorine At least one selected from the group consisting of a polymer, a p-xylene polymer, a vinyl alcohol polymer, and parylene, or as an oxide, SiO ₂ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Y ₂ O _3, and Ta. Provided is a dual gate thin film transistor, characterized in that at least one selected from the group consisting of ₂ O ₅ .

In addition, the present invention forms a high charge in the semiconductor layer due to the ion layer when the voltage is applied, a high charge amount in the channel is moved by diffusion, driving speed is improved on the source / drain electrode, characterized in that to provide.

In the dual gate transistor according to the present invention, when the ion layer is formed under the top gate, an ion gel or a solid electrolyte material is applied as the top gate insulating layer, thereby accumulating very high charges on the top of the semiconductor layer. If thin within 10 nm, this large amount of charge diffuses to the lower portion of the relatively low charge semiconductor layer, and a voltage is applied to the bottom gate electrode to move in the lower channel of the dual gate transistor. Since the bottom gate and the high gate speed can be simultaneously acquired due to the charge mobility, there is an effect of providing a transistor with significantly improved charge mobility and the driving speed. In other words, the high charge provided by the ion layer is diffused to the bottom of the semiconductor layer to be driven by the bottom gate.

In addition, in the dual gate transistor according to the present invention, when the ion layer is formed on the bottom gate, an ion gel or a solid electrolyte material is applied as the bottom gate insulating film to accumulate high charge under the semiconductor layer, and to diffuse it into the upper semiconductor layer. Since the voltage is applied to the top gate electrode to move in the upper channel of the dual gate transistor, it is possible to simultaneously obtain high charge mobility due to the bottom gate electrode and the ion layer and high driving speed due to the top gate. The effect is to provide an improved transistor.

In the dual gate transistor according to the present invention, since the semiconductor thin film is thin, the high charge amount formed by the ion layer is moved into the channel to another gate, and the high charge amount is driven to a gate other than the ion layer to improve driving speed on the source / drain electrode. It works.

In addition, the transistor according to the present invention can be corrected by adjusting the voltage of the gate electrode in contact with the ion layer in order to prevent operation instability, thereby enabling stable transistor driving.

1 schematically illustrates a thin film transistor manufacturing process according to an embodiment of the present invention.

2 shows a thin film transistor structure according to an embodiment of the present invention.

3 shows the amount of charge according to the height position when the semiconductor layer thickness of the transistor is 100 nm and 10 nm.

Figure 4 shows the change in voltage applied to the thin film transistor according to an embodiment of the present invention.

5 shows a thin film transistor structure according to another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, it should be noted that in the drawings, the same components or parts denote the same reference numerals as much as possible. In describing the present invention, detailed descriptions of related well-known functions or configurations are omitted in order not to obscure the subject matter of the present invention.

As used herein, the terms “about”, “substantially”, and the like, are used at, or in close proximity to, numerical values when manufacturing and material tolerances inherent in the meanings indicated are intended to aid the understanding of the invention. Accurate or absolute figures are used to assist in the prevention of unfair use by unscrupulous infringers.

1 schematically illustrates a thin film transistor manufacturing process according to an embodiment of the present invention. 2 shows a thin film transistor structure according to an embodiment of the present invention.

1 and 2, a substrate is provided, a bottom gate electrode disposed on the substrate is formed, a bottom gate electrode is formed on the bottom gate electrode, and a gate insulating layer is disposed over the entire surface of the substrate. Forming a source / drain electrode spaced apart from each other on the gate insulating layer, forming a semiconductor layer located over the entire surface of the gate insulating layer including the source / drain electrode, and forming an ion layer on the front surface of the semiconductor layer And a top gate electrode disposed on the ion layer to manufacture a thin film transistor.

To provide a substrate in the manufacture of the thin film transistor of the present invention, the substrate may be a flexible substrate such as a transparent substrate such as glass, a silicon substrate, a plastic substrate or a metal foil substrate. Examples of the plastic substrate include polyethersulphone, polyacrylate, polyetherimide, polyethyelenen napthalate, polyethyeleneterepthalate, polyphenylene sulfide , Polyallylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate and the like can be used.

A bottom gate electrode may be formed on the substrate. The bottom gate electrode may form a gate electrode through thin film deposition or inkjet printing in a high vacuum chamber. The gate electrode may include aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), molybdenum alloy (Mo-alloy), silver nanowires, gallium indium eutectic, PEDOT; It may be formed of any one selected from the PSS. The bottom gate electrode may use the above materials as an ink to manufacture the gate electrode using a printing process such as inkjet printing or spraying. Through the printing process, the bottom gate electrode can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.

The bottom gate electrode may include the bottom gate electrode to form a gate insulating layer disposed over the entire surface of the substrate.

The gate insulating layer is preferably made of an organic polymer, but is not limited thereto, and may be formed of an oxide. Examples of the organic polymer include polystyrene (PS), polymethacrylate (PMMA, polymethylmethacrylate), phenolic polymer, acrylic polymer, imide polymer such as polyimide, arylether polymer, amide polymer, fluorine polymer, p -It is preferable to use at least one selected from the group consisting of a zyrylene-based polymer, a vinyl alcohol-based polymer, parylene (parylene) and the like. In addition, as the oxide, the gate insulating layer is preferably selected from one or more selected from the group consisting of SiO ₂ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Y ₂ O _3, and Ta ₂ O ₅ .

The role of the gate insulating layer allows electrons to form inductive dipoles, thereby allowing the accumulation of charge. The gate insulating layer has a high driving voltage due to a high dielectric constant, but allows the transistor to be driven at a high driving speed. High drive speeds in transistors of electronic devices such as computers that are currently used are obtained using such gate insulating layers.

Source / drain electrodes may be formed on the gate insulating layer to be spaced apart from each other.

The source / drain electrode may be formed of a single layer selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, or an alloy thereof, and may be bonded to Ti, Cr or Ni to improve adhesion. Further comprising a metal layer can be formed into a multi-layer. In addition, by using graphene, carbon nanotube (CNT) and PEDOT: PSS conductive polymer silver nanowire, devices that are more flexible to elasticity than conventional metals can be manufactured. Thus, the source / drain electrodes may be manufactured using a printing process such as inkjet printing or spraying. Through the printing process, the source / drain electrodes can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.

The semiconductor layer may be formed over the entire gate insulating layer by including the source / drain electrodes on the source / drain electrodes.

The semiconductor layer may be an N-type organic semiconductor, a P-type organic semiconductor, or an oxide semiconductor. The N-type organic semiconductor is an acene-based material, a fully fluorinated acene-based material, a partially fluorinated acene-based material, a partially fluorinated oligothiophene-based material, a fullerene-based material, a fullerene-based material having a substituent, Fully fluorinated phthalocyanine-based materials, partially fluorinated phthalocyanine-based materials, perylene tetracarboxylic diimide-based materials, perylene tetracarboxylic dianhydride-based materials, naphthalene It is preferable to include any one of tetracarboxylic diimide-based material or naphthalene tetracarboxylic dianhydride-based material. Here, the acene-based material may be selected from anthracene, tetracene, pentacene, perylene or conorene.

In addition, the P-type organic semiconductor is acene (acene), poly-thienylenevinylene (poly-thienylenevinylene), poly-3-hexylthiophene (poly-3-hexylthiophen), alpha-hexathienylene (α-hexathienylene), Naphthalene, alpha-6-thiophene, alpha-4-thiophene, alpha-4-thiophene, rubrene, polythiophene, polyparaphenylene Vinylene (polyparaphenylenevinylene), polyparaphenylene, polyfluorene, polythiophenevinylene, polythiophene-heterocyclicaromatic copolymer, triarylamine ( triarylamine) or derivatives thereof, wherein the acene group is any one of pentacene, perylene, tetratracene or anthracene.

In addition, an oxide semiconductor layer can be formed using IGZO, IZO, ZnO, etc. as an oxide semiconductor layer.

The semiconductor layer may be formed into a thin film by thermal evaporation or sputtering in a vacuum chamber. Solvent-soluble materials are also formed on source / drain electrodes through spin coating, spray, inkjet, flexography, screen, dip-coating and gravure. . The pattern may be formed on the electrode and the local region of the substrate, and heat treatment or optical exposure may be performed to improve device performance such as semiconductor crystallinity and stability after forming the semiconductor layer.

In the present invention, the thickness h of the semiconductor layer is preferably 1 to 10 nm. The thickness of the semiconductor layer refers to the gap between the upper portion of the source and drain electrodes and the lower portion of the ion layer. When the thickness of the semiconductor layer is thin, high charge accumulation caused by the ion layer diffuses to the lower semiconductor layer with high efficiency. It can be effectively moved to the lower channel. That is, a fast driving speed can be obtained.

The thickness of the transistor channel formed at the interface between the semiconductor and the insulator through the application of a gate voltage in an organic transistor and an oxide transistor which is usually driven in an accumulation mode is known to be about 1 to 5 nm (2 to 3 molecular layers). Advanced Materials 25 (31), 4210-4244 (2013))

Therefore, when the thickness of the semiconductor layer is less than 10 nm, the channel formed at the upper portion of the dual gate is mixed with the lower portion and the formed channel so that the charge formed at the upper portion or the lower portion can diffuse to the lower portion or the upper portion. This effect is doubled as the thickness of the semiconductor layer is thinner.

Referring to FIG. 3, an IGZO oxide semiconductor layer was formed as a semiconductor layer. When the semiconductor layer is 100 nm, the high charge amount due to the channels formed on the upper and lower portions is not effectively transferred to the middle of the semiconductor layer, and thus the charge amount on the upper and lower portions. The amount of charge in the and the intermediate layer is greatly different.

On the other hand, if the semiconductor layer is 10 nm, the charges formed on the upper and lower sides are effectively diffused in the intermediate layer, so that the amount of charge in the semiconductor layer is evenly spread in the semiconductor.

Therefore, when the semiconductor layer within 10 nm is used, the high charge on the semiconductor layer formed by the ion gel is effectively diffused to the lower part of the semiconductor layer, so that the high driving speed can be obtained by the disappearance of the lower gate. It can be implemented at the same time.

When a voltage is applied to the top gate electrode and the bottom gate electrode, a large amount of electric charge is accumulated through a high dielectric constant and capacitance by the ion layer, and the source / drain electrode is made thin by making the semiconductor layer thin. It can be quickly moved to the channel of the semiconductor layer.

An ion layer may be formed over the entire surface of the semiconductor layer.

In this case, the ionic layer may be formed of an ionic liquid, and may be formed of an ion gel or a solid electrolyte mixed with an ionic liquid and a polymer. When the ionic layer is formed of an ion gel or a solid electrolyte, the ionic liquid may be formed by appropriately mixing a specific polymer. The ion gel may be formed in a gel shape, and the solid electrolyte may be in a solid shape and have a more rigid form or elasticity than the ion gel.

Ionic liquids include 1-Ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) amide ([EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF ₆ ], and [EMIM] [OctSO ₄ ]. You can choose one or more from the group you have made up.

In the case of forming the ion gel or the solid electrolyte, the elasticity is good, which will help in the future manufacturing of the stretchable device. The ion gel or the solid electrolyte is mixed with an ionic liquid and a polymer, the polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride-hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra-PEG), PVDF-TrFE, etc. can be selected from one or more, and can be used without limitation as long as the polymer can be mixed with the ionic liquid. have.

When the ion gel or solid electrolyte is prepared, the mixing ratio of the ionic liquid and the polymer may be mixed in a ratio of 0.1: 9.9 to 9.9: 0.1 by weight. At this time, a solvent such as methylene chloride is required for mixing. The mixing ratio of the ionic liquid, the polymer and the solvent is mixed at a weight ratio of about 10:90.

In the method of preparing an ion layer using an ion gel or a solid electrolyte, a solvent is prepared by mixing a ionic liquid and a polymer in a solvent, and then heating the solution on a hot plate at about 80 ° C. for about 6 hours. The material may be completely dissolved and mixed in the ion gel to prepare an ion gel or a solid electrolyte.

When the ion layer is formed between the semiconductor layer and the top gate insulating film while the bottom gate electrode and the bottom gate insulating film are formed, very high charge is accumulated in the semiconductor layer due to the application of the ion gel or the solid electrolyte material as the top gate insulating film. Since a voltage is applied to the bottom gate electrode to move in the channel of the transistor, a high driving speed can be simultaneously obtained due to the bottom gate along with a high charge mobility due to the top gate electrode and the ion layer.

That is, when a voltage is applied to the top gate electrode, a high amount of charge is accumulated in the semiconductor layer due to the influence of the ion layer, and when a voltage is applied to the bottom gate electrode, movement occurs in the channel of the transistor, so that a high driving speed is achieved. Will occur.

In the present invention, a large amount of charges are formed in the semiconductor layer due to the ion layer positioned on the semiconductor layer, and the formed charges are easily diffused to the lower portion because the semiconductor layer is thin and driven by controlling the bottom gate electrode.

When the thickness of the semiconductor layer is thinner than 10 nm, high charge accumulation caused by the ion layer diffuses to the lower semiconductor layer with high efficiency to efficiently move to the lower channel, thereby obtaining a fast driving speed.

Referring to FIG. 4, −charge is accumulated on the ion layer due to the + voltage application of the top gate electrode, and −charge is diffused and accumulated at the bottom due to the thin semiconductor layer, and the driving speed is fast between the source / drain electrodes. Will have

A top gate electrode may be formed on the ion layer. The top gate electrode may be formed in the same manner as the bottom gate electrode, and may be formed of aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), molybdenum alloy (Mo-alloy), It may be formed of any one selected from silver nanowire, gallium indium eutectic, and PEDOT.

Thus, the thin film transistor according to the embodiment of the present invention can be completed.

Referring to FIG. 5, an ion layer may be formed on the bottom gate electrode, the substrate; A bottom gate electrode on the substrate; An ion layer positioned over the entire surface of the substrate including the bottom gate electrode; A semiconductor layer on the ion layer; A source / drain electrode included in an upper layer of the semiconductor layer and spaced apart from each other; A gate insulating layer disposed over an entire surface of the semiconductor layer on the source / drain electrodes; And a top gate electrode disposed on the gate insulating layer. The dual gate thin film transistor may be provided.

In this case, each structure is the same as described above, so a detailed description thereof will be omitted. However, the thickness h of the semiconductor layer is preferably 1 to 10 nm, and the thickness of the semiconductor layer may be regarded as a gap between the lower portion of the source / drain electrode and the upper portion of the ion layer.

Hereinafter, specific embodiments of the present invention will be described in detail.

Example 1

Substrate Preparation and Gate Insulation Layer Formation

In manufacturing a thin film transistor, a glass substrate is prepared and a gate insulating layer is formed on the substrate. The insulating layer is melted in n-butyl acetate using polystyrene (PS) and then spin coated. Using to form a gate insulating layer.

Source / drain electrode and semiconductor layer formation

A source / drain electrode was formed on the gate insulating layer, and then P3HT was used to form the semiconductor layer, and the thickness h of the semiconductor layer was 10 nm.

Ion layer formation

1-ethyl-3-methylimidazolium bis (trifluoromethylsulfonyl) imide ([EMIM] [TFSI]) was used as the ionic liquid, and PVDF-TrFE was used as the polymer and mixed in the methylene chloride solvent. The solution was prepared by mixing the solvent by weight ratio of 0.7: 9.3: 90. The solution was heated on a hot plate at 80 ° C. for 6 hours to completely dissolve and mix the material in a solvent, thereby preparing an ion gel or a solid electrolyte, thereby forming an ion layer.

Topgate electrode formation

A top gate electrode was formed in a portion of the upper portion of the ion layer, and aluminum (Al) was formed by evaporation to manufacture a thin film transistor.

Comparative Example 1

The same as in Example 1,

Without applying the gate insulating layer, a layer was formed on the gate insulating layer with the same material as that used for the ion layer.

Comparative Example 2

The same as in Example 1,

Without applying the ion layer, a layer was formed on the ion layer with the same material as that used for the gate insulating layer.

As a result, in Example 1, a very high charge is accumulated in the semiconductor layer and a voltage is applied to the bottom gate electrode to move in the channel of the transistor, so that the top gate electrode and the ion layer cause the bottom gate electrode with high charge mobility. High driving speed can be obtained at the same time.

On the contrary, in the case of Comparative Example 1, high charge mobility occurs, but the performance of the driving speed is considerably slow. In Comparative Example 2, the driving speed is fast but the charge amount is not high.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Claims

Board;

A bottom gate electrode on the substrate;

A gate insulating layer including the bottom gate electrode over the entire surface of the substrate;

Source / drain electrodes spaced apart from each other on the gate insulating layer;

A semiconductor layer located over an entire gate insulating layer including the source / drain electrodes;

An ion layer located on the front surface of the semiconductor layer; And

And a top gate electrode positioned on the ion layer.
Board;

A bottom gate electrode on the substrate;

An ion layer positioned over the entire surface of the substrate including the bottom gate electrode;

A semiconductor layer on the ion layer;

A source / drain electrode included in an upper layer of the semiconductor layer and spaced apart from each other;

A gate insulating layer disposed over an entire surface of the semiconductor layer on the source / drain electrodes; And

And a top gate electrode disposed on the gate insulating layer.
The method according to claim 1 or 2,

The thickness of the semiconductor layer (h) is a dual gate thin film transistor, characterized in that 1 ~ 10nm.
The method according to claim 1 or 2,

The ion layer is a dual gate thin film transistor, characterized in that it comprises at least one of an ion gel, a solid electrolyte and an ionic liquid.
The method of claim 4, wherein

The ion gel or the solid electrolyte is prepared by mixing an ionic liquid and a polymer,

The polymer is poly (styrene-b-methylmethacrylate-b-styrene) [PS-PMMA-PS], poly (vinylidene fluoride-hexafluoro propylene), P (VDF-HFP), tetra-arm poly (ethylene glycol) (Tetra- PEG), PVDF-TrFE dual gate thin film transistor, characterized in that at least one selected.
The method of claim 5,

The mixing ratio of the ionic liquid and the polymer is a dual gate thin film transistor, characterized in that mixed in a weight ratio of 0.1: 9.9 to 9.9: 0.1.
The method of claim 4, wherein

The ionic liquid is at least one selected from the group consisting of [EMI] [TFSA]), [EMIM] [TFSI], [BMIM] [PF 6 ], and [EMIM] [OctSO 4 ]. Thin film transistor.
The method according to claim 1 or 2,

The gate insulating layer is an organic polymer, polystyrene (PS), polymethacrylate (PMMA, polymethylmethacrylate), phenolic polymer, acrylic polymer, imide polymer, arylether polymer, amide polymer, fluorine polymer, p- One or more selected from the group consisting of a zyrylene-based polymer, a vinyl alcohol-based polymer, and parylene,

A dual gate thin film transistor, characterized in that at least one selected from the group consisting of SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 and Ta 2 O 5 as the oxide.
The method according to claim 1 or 2,

2. The dual gate thin film transistor of claim 2, wherein the ion layer forms a high charge in the semiconductor layer when the voltage is applied, and a high charge amount is moved in the channel by diffusion, thereby improving driving speed on the source / drain electrode.