WO2011139006A1 - Organic thin-film transistor having improved charge injectability, and method for manufacturing same - Google Patents

Organic thin-film transistor having improved charge injectability, and method for manufacturing same Download PDF

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Publication number
WO2011139006A1
WO2011139006A1 PCT/KR2010/005917 KR2010005917W WO2011139006A1 WO 2011139006 A1 WO2011139006 A1 WO 2011139006A1 KR 2010005917 W KR2010005917 W KR 2010005917W WO 2011139006 A1 WO2011139006 A1 WO 2011139006A1
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injection layer
substrate
source
hole injection
thin film
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PCT/KR2010/005917
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French (fr)
Korean (ko)
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노용영
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한밭대학교산학협력단
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80Constructional details
    • H10K10/82Electrodes
    • H10K10/84Ohmic electrodes, e.g. source or drain electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40Organic transistors
    • H10K10/46Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462Insulated gate field-effect transistors [IGFETs]
    • H10K10/466Lateral bottom-gate IGFETs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/30Organic light-emitting transistors

Definitions

  • the present invention relates to a method for manufacturing an organic thin film transistor, a bipolar organic thin film transistor, an organic light emitting transistor, and a digital circuit including the same.
  • AM matrix active matrix driving method.
  • Inorganic thin film transistors such as silicon, which are currently used, have a high manufacturing temperature and are easily broken when bent or bent, so there is a limitation in applying them to flexible displays. Therefore, research on organic thin film transistors (OTFTs), which can be easily manufactured at low temperatures and can withstand bending or bending, is being actively conducted.
  • the organic thin film transistor is not only actively researched as a driving device of the next generation display device, but also can be applied to the production of RFID (Radio Frequency Identification Tag) tags that can be applied to the recognition of individual item units. It is expected.
  • the organic thin film transistor (OTFT) uses an organic semiconductor film instead of a silicon film as a semiconductor layer.
  • the organic thin film transistor (OTFT) is a low molecular organic thin film transistor such as oligothiophene or pentacene, depending on the material of the organic film. It is classified into a polymer organic thin film transistor such as polythiophene series.
  • the RFID tag When the RFID tag is manufactured using the organic thin film transistor as described above, the RFID tag can be manufactured at a lower manufacturing cost, and thus, it can be applied to all individual consumer goods.
  • CMOS metal oxide semiconductor
  • CMOS metal oxide semiconductor
  • high electron and hole injection with one electrode material mostly gold
  • Efficiency must be obtained.
  • the contact resistance generated between the electrode and the organic semiconductor is inevitable.
  • CMOS type organic digital devices inverters and ring oscillators manufactured using gold electrodes have a very low performance due to the high contact resistance between the gold electrodes and the N type organic semiconductors.
  • the method mainly used until the metal salt is inserted between the gold (Au) electrode and the N-type organic semiconductor between the two It is characterized by effectively lowering the contact resistance.
  • a prior art for solving the above problems which is a patent comprising a mixture consisting of a mixture of an organic material and a metal salt of the same component as the N-type organic semiconductor on the top of the source / drain electrode
  • the present invention relates to a technique for reducing contact resistance by coating.
  • Specific configurations for achieving this include a substrate; A gate electrode located on the substrate; A gate insulating film disposed over the entire surface of the substrate including the gate electrode; Source and drain electrodes spaced apart from each other on a portion of the gate insulating layer; A mixed layer disposed on the source / drain electrode and including an organic material and a metal salt; And an N-type organic semiconductor layer located on the substrate including the mixed layer.
  • the application of the above technique produces an effect of effectively lowering the contact resistance by inserting a very thin layer of a metal salt intermediate layer of several nanometers.
  • the above technique manufactures a mixture of organic salts and metal salts having the same composition as the N-type organic semiconductors to reduce the contact resistance between the source / drain electrodes and the organic semiconductor by vacuum deposition, the metal salt is selectively applied to only one of the charge injection electrodes. It is very difficult or impossible to do, and all the processes are done in a high vacuum deposition chamber, which makes the work process cumbersome and expensive, which is uneconomical.
  • the contact resistance of the N-type transistor can be improved to improve performance.
  • the P-type transistor has a fatal disadvantage of causing a decrease in performance by increasing the contact resistance. This is because only one direction change is possible to increase or decrease the work function of the Au electrode depending on the type of metal salt used. For this reason, if one type of metal salt layer is applied to the entire surface of the source / drain electrodes of all the transistors in the electronic circuit, the contact resistance of the N-type transistor can be improved to effectively increase the performance, but the contact resistance of the P-type transistor is increased.
  • the metal salt suitable for the hole injection is completely coated by vacuum deposition, the hole injection property can be effectively improved, but the electron injection property is deteriorated.
  • the metal salt charge transfer layer is formed through the deposition method, the electron and hole injection characteristics are improved simultaneously when the bipolar transistor or the organic light emitting transistor using the same can be transported in one transistor. It is impossible to bet.
  • the prior art method requires a relatively high temperature and high pressure process by depositing a metal salt in a high vacuum chamber to improve electron injection, which is not suitable for processing on a plastic substrate for implementing a flexible device.
  • a metal salt layer may be selectively applied to only one electrode among source / drain charge injection electrodes to improve contact resistance of N-type and P-type transistors simultaneously.
  • ink using an organic salt solution such as CS 2 CO 3 selectively on one of the source / drain electrodes is selectively applied to only one electrode through various printing methods, thereby effectively lowering the contact resistance of the N-type organic semiconductor.
  • the main object of the present invention is to provide a method of simultaneously improving the performance of N-type and P-type organic transistors by maintaining the contact resistance of P-type organic semiconductors.
  • the present invention is to provide a method for effectively improving the performance of the CMOS digital circuit consisting of N-type and P-type organic transistor through the selective application of the organic salt solution as described above.
  • the amphipathic organic thin film improves the N-type and P-type charge injection by effectively improving the contact resistance of the N-type and P-type in an ambipolar OTFT using an amphiphilic polymer semiconductor.
  • Another object of the present invention is to provide a method of manufacturing a transistor.
  • the present invention provides a method of manufacturing an organic light emitting transistor that can emit light using an amphiphilic organic thin film transistor with improved performance.
  • a gate insulating film disposed over the entire surface of the substrate including the gate electrode
  • Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer
  • organic thin film transistor comprising a; organic semiconductor layer located on the substrate including the electron and hole injection layer.
  • the contact resistance between the source / drain electrode made of gold and the N-type can be greatly reduced, and the contact resistance between the source / drain electrode and the P-type organic semiconductor having low contact resistance is It can be kept in a low state, thereby providing a high performance amphiphilic organic thin film transistor and organic light emitting transistor having high electron and hole injection characteristics.
  • 1 is a cross-sectional view showing a conventional organic thin film transistor.
  • FIG. 2 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a bottom gate.
  • FIG. 3 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a top gate.
  • FIG. 4 is a cross-sectional view illustrating an organic thin film transistor having a bottom gate type according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating an organic thin film transistor having a top gate type according to another embodiment of the present invention.
  • FIG. 6 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
  • FIG. 7 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
  • FIG. 8 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state in which Cs 2 CO 3 is applied to only one electrode.
  • FIG. 9 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in which Cs 2 CO 3 is applied to only one electrode.
  • FIG. 10 is a schematic diagram illustrating a step of selectively applying a metal salt solution to only P-type and N-type one organic transistor electrodes using spray coating.
  • FIG. 11 is a diagram illustrating a circuit diagram of an organic CMOS inverter fabricated after applying Cs 2 CO 3 to only an N-type organic thin film transistor source / drain electrode and a gain value according to an output curve and a gate voltage.
  • Source / drain electrodes of Au were formed through the printing process of inkjet printing using gold nanoparticles on a silicon substrate. The spacing between the two electrodes was spaced at 50 nm.
  • a shadow mask which has already been patterned, was placed on the substrate on which the source / drain electrodes were formed. Then, the ink prepared by dissolving Cs 2 CO 3 in a 2-ethoxyethanol solvent at a concentration of 1 mg / ml was applied using a spray coating machine at a distance of 8 cm from the sample for 10 seconds. Thereafter, the resultant was heated at 100 ° C. for 15 minutes using a hotplate to evaporate the remaining metal salt solvent.
  • pentacene a P-type organic semiconductor
  • a vacuum chamber In order to deposit the organic semiconductor, pentacene, a P-type organic semiconductor, was placed in a vacuum chamber, and then sublimed by applying a heat of 200 ° C. at 10 ⁇ 6 torr and then applied to a thickness of 30 to 70 nm.
  • PMMA After applying PMMA to the thickness of 200 nm by spin coating, an organic thin film transistor was manufactured by depositing a gate electrode having a thickness of 60 nm using Al only in the channel region of the transistor using a shadow mask.
  • FIG. 1 is a cross-sectional view showing a conventional organic thin film transistor.
  • a gate electrode 110 is formed on the substrate 100, and a gate insulating layer 120 is formed over the entire surface of the substrate including the gate electrode 110.
  • Source / drain electrodes 130 are formed on the gate insulating layer 120 to be spaced apart from each other, and the organic semiconductor layer 150 formed on the source / drain electrodes 130 and the gate insulating layer 120 is formed.
  • the conventional organic thin film transistor having such a structure has a problem that the contact resistance between the source / drain electrodes and the organic semiconductor layer is large. Since the source and drain electrodes serve to inject charge into the organic thin film, it is important to reduce the energy barrier between the electrode and the organic thin film which interferes with this.
  • a lot of gold is used as an electrode.
  • the work function of gold is 5.1 eV, and the charge injection is consistent with 5.1 eV, which is the highest Occupied Molecular Orbital (HOMO) value of pentacene. This is because the energy barrier for them is low.
  • the organic semiconductor layer provided in the organic thin film transistor cannot be doped with high concentration. Accordingly, the contact resistance between the source / drain electrode and the organic semiconductor layer is increased. The problem arises that an ohmic contact cannot be formed.
  • This problem of contact resistance is more important when an n-type OTFT and a p-type OTFT are used at the same time.
  • gold is used as the electron or hole injection source / drain electrode of the OTFT, and due to the work function (5.1 eV) of gold, it is possible to simultaneously obtain an ohmic contact that satisfies both N-type and P-type organic semiconductors.
  • the transistor performance is very low compared to the P type.
  • silicon materials are doped with N-type and P-type, respectively, to overcome these problems.
  • such selective doping is very difficult and many techniques for patterning the same. Not developed.
  • the bottom gate type organic thin film transistor provides a substrate, forms a gate electrode on the substrate, forms a gate insulating film to cover the gate electrode, and source / drain electrodes spaced apart from each other on a portion of the gate insulating film.
  • the organic semiconductor layer may be formed by selectively applying a metal salt to only one of the source / drain electrodes.
  • FIG. 3 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a top gate.
  • An organic thin film transistor in the form of a top gate provides a substrate, and forms a source / drain electrode thereon so as to be spaced apart from each other, and then selectively applies a metal salt to only one of the source / drain electrodes and spreads the organic material over the entire surface thereon.
  • a gate insulating film is applied over the entire surface, and finally a gate electrode is formed between the source / drain electrodes of the transistor.
  • the substrate may be formed of a transparent substrate such as glass, a silicon substrate, or plastic.
  • the plastic substrate material is polyethersulphone (PES), polyacrylate (PAR, polyacrylate), polyetherimide (PET, polyetherimide), polyethylene naphthalate (PEN, polyethyelenen napthalate), polyethylene terephthalate (PET, polyethyeleneterepthalate (PPS) polyphenylene sulfide (PPS), polyallylate (polyallylate), polyimide (polyimide), polycarbonate (PC), cellulose tri acetate (TAC), cellulose acetate propinoate Use any one selected from).
  • a transparent substrate such as glass capable of UV transmission is used.
  • the gate electrode is made of gold (Au), nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), and molybdenum alloy (Mo-alloy). It may be formed of any one selected from, it is more preferable to form a molybdenum-tungsten (MoW) alloy.
  • the gate electrode may be formed through various printing processes. In general, the gate electrode may be manufactured using a printing process such as inkjet printing using a metal nanoparticle solution or a PEDOT: PSS conductive polymer as an ink. Through the printing process, the gate electrode can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.
  • a gate insulating film is formed over the entire surface of the substrate including the gate electrode.
  • the gate insulating film is composed of a single film or a multilayer film of an organic insulating film or an inorganic insulating film, or an organic-inorganic hybrid film.
  • the inorganic insulating film any one or more selected from silicon oxide film, silicon nitride film, Al2O3, Ta2O5, BST, and PZT is used.
  • the organic insulating film may include polymethacrylate (PMMA, polymethylmethacrylate), polystyrene (PS, polystyrene), phenolic polymer, acrylic polymer, imide polymer such as polyimide, arylether polymer, amide polymer, fluorine polymer, p -Use any one or more selected from xyrene-based polymer, vinyl alcohol-based polymer, parylene (parylene).
  • PMMA polymethacrylate
  • PS polystyrene
  • phenolic polymer acrylic polymer
  • imide polymer such as polyimide, arylether polymer, amide polymer, fluorine polymer
  • p -Use any one or more selected from xyrene-based polymer, vinyl alcohol-based polymer, parylene (parylene).
  • Source / drain electrodes are formed on the gate insulating layer to be spaced apart from each other.
  • the source / drain electrode may be formed of a single layer selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, or an alloy thereof, and may improve adhesion to the gate insulating layer and prevent undercut phenomenon.
  • an adhesive metal layer such as Ti, Cr or Al may be formed in a multi-layer.
  • One of the electrodes on the source / drain electrodes includes Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na to reduce contact resistance between the organic semiconductor layer and the source / drain electrodes and improve electron injection properties.
  • An ink solution for forming a metal salt electron injection layer selected from metal salts such as 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO, or a mixture thereof is prepared.
  • an ink solution for forming a metal salt hole injection layer selected from metal salts or organic substances such as V 2 O 5 , MoO 3 , F 4 TCNQ, or a mixture thereof is prepared.
  • the ink concentration plays a very important role in controlling the thickness of the metal salt layer of the metal salt, it is necessary to use a metal concentration ink of a constant concentration to obtain the effect of improving the electron or hole injection property.
  • the concentration of the ink used may vary slightly depending on the printing method used. However, if the metal salt layer having a thickness of 0.1-2 nm is applied using a concentration of 0.1 mg / ml-10 mg / ml, the expected effect can be obtained. Can be.
  • the metal salt electron injection layer or hole injection layer is achieved by applying the above-described metal salt ink solution using ink jet printing, screen printing, spray coating, gravure printing, gravure offset printing, reverse gravure offset printing, nozzle printing, pad printing method. .
  • the metal salt electron and hole injection layer has a thickness of less than 2 nm, preferably 0.1 to 2 nm.
  • the thickness of the metal salt solution layer is formed to be 0.1 nm or more, the electron or hole injection efficiency may be improved.
  • the metal salt solution layer is formed to be more than 2 nm, the electron and hole injection effects may be reduced. do.
  • the metal salt charge injection layer when the metal salt charge injection layer is to be applied to a CMOS electronic circuit or a bipolar organic thin film transistor, it is preferable to apply the metal salt charge injection layer to only one of a source or a drain electrode.
  • CMOS digital circuit including both an N-type semiconductor and a P-type semiconductor, the contact resistance of the N-type transistor is reduced and the contact resistance of the P-type transistor is maintained as it is.
  • the organic semiconductor layer is formed over the entire surface of the substrate including the metal salt solution layer.
  • the organic semiconductor layer may be an N-type organic semiconductor or a P-type organic semiconductor.
  • the N-type organic semiconductor is an acene-based material, a fully fluorinated acene-based material, a partially fluorinated acene-based material, a partially fluorinated oligothiophene-based material, a fullerene-based material, a fullerene-based material having a substituent, Fully fluorinated phthalocyanine materials, partially fluorinated phthalocyanine materials, perylene tetracarboxylic diimide materials, perylene tetracarboxylic dianhydride materials, naphthalene It is preferable to include either tetracarboxylic diimide (naphthalene tetracarboxylic diimide) material or naphthalene tetracarboxylic dianhydride (
  • the P-type organic semiconductor is acene (acene), poly-thienylenevinylene (poly-thienylenevinylene), poly-3-hexylthiophene (poly-3-hexylthiophen), alpha-hexathienylene ( ⁇ -hexathienylene), Naphthalene, alpha-6-thiophene, alpha-4-thiophene, alpha-4-thiophene, rubrene, polythiophene, polyparaphenylene Polyparaphenylenevinylene, polyparaphenylene, polyfluorene, polythiophenevinylene, polythiophene-heterocyclicaromatic copolymer, triarylamine ( triarylamine) or a derivative thereof, wherein the acene group is any one of pentacene, perylene, tetratracene or anthracene.
  • FIG. 4 is a cross-sectional view illustrating an organic thin film transistor having a bottom gate type according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating an organic thin film transistor having a top gate type according to another embodiment of the present invention.
  • FIG. 6 is a diagram showing a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3.
  • the organic polymer semiconductor used is ActivInk P2100 material purchased from Polyera, USA. It is a conjugated polymer based on thiophene and is a material with high hole mobility. 6 shows that P2100 is coated on a glass substrate on which Au source / drain electrodes are pre-patterned by spin coating, and then PMMA insulator is applied by spin coating, and an Al electrode is formed as a gate. The result obtained by measurement. As shown in FIG. 6, the P2100 OTFT showed the performance of a typical p-type OTFT and obtained a hole mobility of 0.16 to 0.54 cm2 / Vs when a drain voltage of -40 to -100 V was applied.
  • FIG. 7 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
  • the Polyera P2100 organic polymer semiconductor material is a hole transport polymer
  • electron mobility was relatively low.
  • FIG. 7 when a positive voltage is applied to the source / drain electrodes and the gate electrode of the P2100 OTFT, the characteristics of the n-type OTFT are shown in FIG. 7, but the performance is 10 compared to the p-type characteristics of FIG. 6.
  • the drain voltage of 40 to 100 V was applied, the electron mobility of 0.016 to 0.022 cm2 / Vs was obtained. Due to the imbalance in mobility of p-type and n-type, when a CMOS circuit is constructed using P2100 material or the speed of the circuit is reduced and a bipolar organic light emitting transistor is fabricated, light emission does not occur.
  • FIG. 8 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state in which Cs 2 CO 3 is applied to only one electrode.
  • the result of FIG. 8 is to apply the technique proposed in the present invention when fabricating the P2100 OTFT of the top gate structure by applying Cs2CO3 to one electrode by spray coating method to improve the electron injection characteristics and at the same time to minimize the effect on the hole injection It was.
  • the P2100 OTFT showed the performance of a typical p-type OTFT, and showed a hole mobility of 0.13 to 0.40 cm2 / Vs when a drain voltage of -40 to -100 V was applied.
  • the Cs 2 CO 3 was applied to Cs 2 CO 3 , but the Cs 2 CO 3 was applied to only one electrode of the source / drain to reduce the hole injection efficiency.
  • Spray application conditions were prepared by dissolving Cs 2 CO 3 in 2-ethoxyethanol solvent at a concentration of 1 mg / ml.
  • the prepared ink was applied at a distance of 8 cm from the sample for 10 seconds using a spray coating machine.
  • a time between 6-20 seconds high electron or hole injection properties can be obtained, and too thin or too thick thickness is formed to apply a time shorter than 6 seconds or longer than 20 seconds. It is difficult to obtain an improvement in the injection characteristics of holes.
  • FIG. 9 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in which Cs 2 CO 3 is applied to only one electrode.
  • FIG. 9 The results of FIG. 9 were measured through the same transistors from which the results of FIG. 8 were obtained, and the characteristics of n-type OTFT were improved by applying Cs 2 CO 3 by applying a positive voltage to the source / drain electrodes and the gate electrode. Observed. As shown in FIG. 9, when a drain voltage of 40 to 100 V was applied, an electron mobility of 0.14 to 0.24 cm 2 / Vs was obtained. This will also improve the electromigration obtained more than 10 times compared to devices that are not coated with Cs 2 CO 3 because the electron injecting capability increased by the Cs 2 CO 3 treatment.
  • FIG. 10 is a schematic diagram showing a step of selectively applying a metal salt solution to only one electrode using a spray coating.
  • a source / drain electrode of Au is formed through the photolithography process on the glass, Si wafer, or plastic substrate.
  • the spacing between Au source / drain electrodes is on the order of several um-several hundred um.
  • spray coating or other printing equipment described above may be used to selectively apply metal salt ink to the electrodes.
  • a metal salt solution to be applied is injected into the equipment, and a shadow mask, which is already patterned, is placed on the substrate on which the source / drain electrodes are formed.
  • the metal salt solution is applied to only one electrode of the source / drain and the other electrode is not applied.
  • printing equipment such as inkjet printing capable of tens of um high-resolution patterns by the equipment itself does not require such a shadow mask process and can be applied only to desired electrodes directly through the printing equipment.
  • the solvent is evaporated by applying heat to the substrate above the evaporation temperature of the used solvent to evaporate the used solvent and leave only the solid metal salt layer. Since the evaporation temperature of a conventional organic solvent is between 50 and 250 degrees Celsius, the temperature is added to the sample for 10 minutes through a hotplate to evaporate the solvent of the metal salt.
  • FIG. 11 is a diagram illustrating a circuit diagram of an organic CMOS inverter fabricated after applying Cs 2 CO 3 to only an N-type electrode, and a gain value according to an output curve and a gate voltage.
  • the CMOS inverter is a circuit in which a P-type OTFT and an N-type OTFT are 1: 1 coupled, and a detailed circuit diagram thereof is shown in FIG. 11.
  • the semiconductor used is P2100 manufactured by Polyera, which is the same as the above result. In general, P2100 is a hole-transfer polymer, and thus, if Cs 2 CO 3 is not selectively applied to only one electrode, the P TYPE OTFT shows 10 times or more performance as shown in FIGS.
  • the fabricated CMOS inverter shows a very low voltage gain of about 10-30, as shown in FIG.
  • a high voltage gain of about 70 may be obtained as shown in FIG. 11. This corresponds to the highest voltage gain of organic CMOS inverters reported to date.
  • Source / drain electrodes of Au were formed through a printing process of inkjet printing using gold nanoparticles on a silicon substrate. The spacing between the two electrodes was spaced at 50 nm.
  • a shadow mask which has already been patterned, was placed on the substrate on which the source / drain electrodes were formed. Then, the ink prepared by dissolving Cs 2 CO 3 in a 2-ethoxyethanol solvent at a concentration of 1 mg / ml was applied using a spray coating machine at a distance of 8 cm from the sample for 10 seconds. Thereafter, the resultant was heated at 100 ° C. for 15 minutes using a hotplate to evaporate the remaining metal salt solvent.
  • pentacene a P-type organic semiconductor
  • a vacuum chamber In order to deposit the organic semiconductor, pentacene, a P-type organic semiconductor, was placed in a vacuum chamber, and then sublimed by applying a heat of 200 ° C. at 10 ⁇ 6 torr and then applied to a thickness of 30 to 70 nm.
  • PMMA After applying PMMA to the thickness of 200 nm by spin coating, an organic thin film transistor was manufactured by depositing a gate electrode having a thickness of 60 nm using Al only in the channel region of the transistor using a shadow mask.
  • CMOS metal oxide semiconductor
  • OTFT was prepared by applying poly (9,9-dioctylfluorene-co-benzothiadiazole) (F8BT), an organic semiconductor material having bipolarity.
  • F8BT poly (9,9-dioctylfluorene-co-benzothiadiazole)
  • OTFT was prepared in the same manner as in Example 1 by applying poly (9,9-dioctylfluorene-co-benzothiadiazole) (F8BT), a bipolar organic semiconductor material having excellent luminescence properties.
  • F8BT poly (9,9-dioctylfluorene-co-benzothiadiazole)

Abstract

The present invention relates to an organic thin-film transistor in which a solution of CS2CO3 is applied to only one of the source/drain electrodes on a substrate to thereby improve electron injectability, and to a complementary metal oxide semiconductor (CMOS) digital circuit using same. The organic thin-film transistor comprises: a substrate; a gate electrode disposed on the substrate; a gate dielectric disposed over the substrate that includes the gate electrode; source/drain electrodes disposed separately on portions of the gate dielectric; an electron-injection layer applied to one of the source/drain electrodes; and an organic semiconductor layer disposed on the substrate that includes the electron-injection layer.

Description

전하 주입성을 향상시킨 유기박막트랜지스터 및 이의 제조방법Organic thin film transistor with improved charge injection property and manufacturing method thereof
본 발명은 유기박막트랜지스터, 양극성 유기박막트랜지스터, 유기발광트랜지스터의 제조방법 및 이를 포함한 디지털 회로에 관한 것이다.The present invention relates to a method for manufacturing an organic thin film transistor, a bipolar organic thin film transistor, an organic light emitting transistor, and a digital circuit including the same.
최근 들어 휠 수 있는 디스플레이(flexible display)가 많은 관심을 받고 있다. 사람들은 어디서나 가지고 다닐 수 있으면서도 좀 더 큰 화면을 원하기 때문에 접거나 구부리거나, 말수 있는 디스플레이의 개발이 요구되고 있다. 또한 롤투롤(Roll to Roll) 공정이 가능해지면 이러한 디스플레이를 보다 낮은 가격으로 대량 생산할수 있다. 하지만 이를 위해서는 플라스틱이나 스테인리스 스틸과 같이 휠 수 있는 기판을 사용해야하는데 이를 위해서는 공정온도를 300℃ 이하의 온도로 낮추어줄 필요가 있다.Recently, a flexible display has received much attention. People want to have a bigger screen that they can carry anywhere, so they need to develop displays that can be folded, bent or rolled. The roll-to-roll process also enables mass production of these displays at lower prices. However, this requires the use of warp substrates such as plastic or stainless steel, which requires lowering the process temperature to below 300 ° C.
한편 고해상도와 저전력 구동을 위해서는 능동형(AM matrix) 구동방식이 필요한데 현재 사용되고 있는 실리콘과 같은 무기 박막트랜지스터는 그 제조온도가 높고, 휘거나 구부렸을 때 쉽게 깨어지기 때문에 플렉서블 디스플레이에 적용하기에는 한계가 있다. 따라서 저온에서 쉽게 제조할 수 있고 휘거나 구부렸을 때도 견딜 수 있는 유기박막 트랜지스터 (Organic Thin Film Transistor, OTFT)에 대한 연구가 활발히 진행되고 있다.On the other hand, high-resolution and low-power driving requires an active matrix (AM matrix) driving method. Inorganic thin film transistors such as silicon, which are currently used, have a high manufacturing temperature and are easily broken when bent or bent, so there is a limitation in applying them to flexible displays. Therefore, research on organic thin film transistors (OTFTs), which can be easily manufactured at low temperatures and can withstand bending or bending, is being actively conducted.
유기박막트랜지스터는 이러한 차세대 디스플레이 장치의 구동소자로서 활발한 연구가 진행되고 있을 뿐 아니라 개별물품단위의 인식에 응용될 수 있는 RFID (Radio Frequency Identification Tag, 무선인식단말소자) 태그 제작에도 응용될 수 있을 것으로 기대된다. 유기박막트랜지스터(OTFT: organic thin film transistor)는 반도체층으로 실리콘막 대신에 유기반도체막을 사용하는 것으로, 유기막의 재료에 따라 올리코티오펜(oligothiophene), 펜타센(pentacene) 등과 같은 저분자 유기물 박막트랜지스터와 폴리티오펜(polythiophene) 계열 등과 같은 고분자 유기물 박막트랜지스터로 분류된다.The organic thin film transistor is not only actively researched as a driving device of the next generation display device, but also can be applied to the production of RFID (Radio Frequency Identification Tag) tags that can be applied to the recognition of individual item units. It is expected. The organic thin film transistor (OTFT) uses an organic semiconductor film instead of a silicon film as a semiconductor layer. The organic thin film transistor (OTFT) is a low molecular organic thin film transistor such as oligothiophene or pentacene, depending on the material of the organic film. It is classified into a polymer organic thin film transistor such as polythiophene series.
이와 같은 유기박막트랜지스터를 사용하여 RFID tag을 제작하면 보다 낮은 제조단가로 RFID tag의 제조할 수 있으므로 모든 개별 소비재 물품에 적용이 가능한 장점이 있다. 그러나 이러한 프린팅, 플렉서블 RFID tag를 제조하기 위해서는 N형 반도체와 P형 반도체로 이루어지는 금속산화막반도체(CMOS)형 디지털 회로를 구현하여야 하고 이를 위해서는 한가지 전극물질 (주로 금을 사용)로 높은 전자 및 정공 주입 효율을 얻어야만 한다. 하지만 금이 지닌 일함수 (work function) 와 N형 및 P형 유기반도체 물질의 에너지 레벨 (HOMO 혹은 LUMO 레벨)의 차이에 의해 전극과 유기반도체 사이에 발생되는 접촉저항을 피할 수 없게 된다. 통상적으로 P형 유기반도체와 금 전극은 접촉저항이 낮고 N형 유기반도체와 금 전극은 접촉저항이 매우 높은 것으로 알려져 있다. 그러므로 금 전극을 사용하여 제조된 CMOS형 유기 디지털 소자 (인버터, 링오실레이터)는 금 전극과 N형 유기반도체 간의 높은 접촉저항으로 인해 성능이 매우 낮은 것이 현실이다.When the RFID tag is manufactured using the organic thin film transistor as described above, the RFID tag can be manufactured at a lower manufacturing cost, and thus, it can be applied to all individual consumer goods. However, in order to manufacture the printing and flexible RFID tag, a metal oxide semiconductor (CMOS) type digital circuit consisting of N-type semiconductor and P-type semiconductor must be implemented. For this purpose, high electron and hole injection with one electrode material (mostly gold) is used. Efficiency must be obtained. However, due to the difference in the work function of gold and the energy level (HOMO or LUMO level) of N-type and P-type organic semiconductor materials, the contact resistance generated between the electrode and the organic semiconductor is inevitable. Typically, P-type organic semiconductors and gold electrodes have a low contact resistance, and N-type organic semiconductors and gold electrodes have a high contact resistance. Therefore, the CMOS type organic digital devices (inverters and ring oscillators) manufactured using gold electrodes have a very low performance due to the high contact resistance between the gold electrodes and the N type organic semiconductors.
상기와 같은 N형 유기반도체와 금 전극을 사용한 유기박막트랜지스터의 높은 접촉 저항의 문제점을 해결하기 위하여 지금까지 주로 사용된 방법은 금속염을 금(Au)전극과 N형 유기반도체 사이에 삽입하여 둘 사이의 접촉저항을 효과적으로 낮추는 것을 특징으로 하고 있다. 대표적인 것으로 상기한 문제를 해결하기 위한 선행기술로는 등록특허 10-0807558를 들 수 있는데, 상기문헌은 소스/드레인 전극의 상부에 N형 유기반도체와 동일한 성분의 유기물과 금속염의 혼합물로 구성된 혼합물을 도포하여 접촉 저항을 줄이는 기술에 관한 것이다. 이를 달성하기 위한 구체적인 구성으로는 기판; 상기 기판 상에 위치한 게이트 전극; 상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막; 상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소오스/드레인 전극; 상기 소오스/드레인 전극 상에 위치하고, 유기물과 금속염을 포함하는 혼합층; 및 상기 혼합층을 포함하는 기판 상에 위치하는 N형 유기반도체층로 구성된다.In order to solve the problem of the high contact resistance of the organic thin film transistor using the N-type organic semiconductor and the gold electrode as described above, the method mainly used until the metal salt is inserted between the gold (Au) electrode and the N-type organic semiconductor between the two It is characterized by effectively lowering the contact resistance. As a representative example, there is a prior art for solving the above problems, which is a patent comprising a mixture consisting of a mixture of an organic material and a metal salt of the same component as the N-type organic semiconductor on the top of the source / drain electrode The present invention relates to a technique for reducing contact resistance by coating. Specific configurations for achieving this include a substrate; A gate electrode located on the substrate; A gate insulating film disposed over the entire surface of the substrate including the gate electrode; Source and drain electrodes spaced apart from each other on a portion of the gate insulating layer; A mixed layer disposed on the source / drain electrode and including an organic material and a metal salt; And an N-type organic semiconductor layer located on the substrate including the mixed layer.
상기 기술을 적용하면 수나노 미터 정도의 매우 얇은 층의 금속염 중간층을 삽입하여 접촉저항을 효과적으로 낮출 수 있는 효과가 발생된다. 그러나 상기 기술은 소스/드레인 전극과 유기반도체의 접촉저항을 줄이기 위한 N형 유기반도체와 동일한 성분의 유기물과 금속염의 혼합물을 진공 증착공정으로 제조하기 때문에 전하주입 전극 중 한쪽 전극에만 선택적으로 금속염을 도포하는 것이 매우 어렵거나 불가능하고, 모든 공정이 고진공 증착 챔버에서 이루어져서 작업공정이 번거롭고 제조원가가 많이 소요되어 비경제적이다. 따라서 상기한 기술처럼 금속염층이 소스/드레인 양쪽 전극에 모두 존재하고 이를 통해서 N형 반도체 와 P형 반도체를 모두 포함하는 CMOS형 디지털 회로를 구현할시에는 N형 트랜지스터의 접촉저항을 향상시켜서 성능을 높일수 있으나, P형 트랜지스터의 접촉저항을 높여서 성능저하를 유발하는 치명적인 단점을 지니고 있다. 이는 사용된 금속염의 종류에 따라서 Au 전극의 일함수를 높이거나 혹은 낮추는 한가지 방향으로만의 변화만이 가능하기 때문이다. 이렇기 때문에 증착공정으로 한가지 종류의 금속염층을 전자회로내의 모든 트랜지스터의 소스/드레인 전극의 전면에 도포하게 되면 N형 트랜지스터의 접촉저항을 향상시켜서 성능을 효과적으로 높일수 있으나, P형 트랜지스터 접촉저항은 증가시켜 소자성능을 감소시킬 수 밖에 없다. 반대로 정공주입에 적합한 금속염을 진공증착으로 전면도포하게되면 정공주입성은 효과적으로 향상시킬 수 있으나, 전자주입성은 저하되계된다. 또한 이러한 증착방법을 통해서 금속염 전하 전달층을 형성하게 되면 한 개의 트랜지스터에서 전자나 정공이 모두 전달될 수 있는 양극성 트랜지스터나 이를 이용한 유기발광트랜지스터를 제조할때에 전자와 정공의 주입특성 향상을 동시에 얻어내기가 불가능하다.The application of the above technique produces an effect of effectively lowering the contact resistance by inserting a very thin layer of a metal salt intermediate layer of several nanometers. However, since the above technique manufactures a mixture of organic salts and metal salts having the same composition as the N-type organic semiconductors to reduce the contact resistance between the source / drain electrodes and the organic semiconductor by vacuum deposition, the metal salt is selectively applied to only one of the charge injection electrodes. It is very difficult or impossible to do, and all the processes are done in a high vacuum deposition chamber, which makes the work process cumbersome and expensive, which is uneconomical. Therefore, as described above, when the metal salt layer is present at both the source / drain electrodes, and the CMOS digital circuit including both the N-type semiconductor and the P-type semiconductor is implemented, the contact resistance of the N-type transistor can be improved to improve performance. However, the P-type transistor has a fatal disadvantage of causing a decrease in performance by increasing the contact resistance. This is because only one direction change is possible to increase or decrease the work function of the Au electrode depending on the type of metal salt used. For this reason, if one type of metal salt layer is applied to the entire surface of the source / drain electrodes of all the transistors in the electronic circuit, the contact resistance of the N-type transistor can be improved to effectively increase the performance, but the contact resistance of the P-type transistor is increased. It is inevitable to reduce the device performance. On the contrary, when the metal salt suitable for the hole injection is completely coated by vacuum deposition, the hole injection property can be effectively improved, but the electron injection property is deteriorated. In addition, when the metal salt charge transfer layer is formed through the deposition method, the electron and hole injection characteristics are improved simultaneously when the bipolar transistor or the organic light emitting transistor using the same can be transported in one transistor. It is impossible to bet.
또한 선행기술의 방법은 고진공 챔버내에서 금속염을 증착하여 전자주입성을 향상시키므로 비교적 고온, 고압의 공정이 요구되며 이는 플렉서블한 소자를 구현하기위한 플라스틱 기판위에 공정하기에는 적합하지 않은 측면이 있다. In addition, the prior art method requires a relatively high temperature and high pressure process by depositing a metal salt in a high vacuum chamber to improve electron injection, which is not suitable for processing on a plastic substrate for implementing a flexible device.
그러므로 유기박막트랜지스터가 다양한 디지털 회로나 유기발광트랜지스터, 유기발광 레이져등에 폭넓게 쓰이기 위해서는 금속염층을 소스/드레인 전하 주입전극중 선택적으로 한쪽 전극에만 도포하여 N형과 P형 트랜지스터의 접촉저항을 동시에 향상시킬 수 있는 방법과 진공이나 고온 열증착이 아닌 용액공정이나 인쇄공정을 통해 간편하게 도포할 수 있는 방법에 대한 연구가 절실히 요구되는 실정이다. Therefore, in order for organic thin film transistors to be widely used in various digital circuits, organic light emitting transistors, and organic light emitting lasers, a metal salt layer may be selectively applied to only one electrode among source / drain charge injection electrodes to improve contact resistance of N-type and P-type transistors simultaneously. There is an urgent need for research on the method that can be easily applied through a solution process or a printing process rather than a vacuum or high temperature thermal evaporation.
본 발명은 소스/드레인 전극 중 어느 하나에 선택적으로 CS2C03 등의 유기염 용액을 이용한 잉크를 다양한 인쇄 방법을 통해서 한쪽 전극에만 선택적으로 도포하여 N-형 유기반도체의 접촉 저항은 효과적으로 낮추고 반면 P-형 유기반도체의 접촉저항을 그대로 유지하여 N-형 과 P-형 유기트랜지스터의 성능을 동시에 향상시키는 방법을 제공하는 것을 주된 목적으로 한다.According to the present invention, ink using an organic salt solution such as CS 2 CO 3 selectively on one of the source / drain electrodes is selectively applied to only one electrode through various printing methods, thereby effectively lowering the contact resistance of the N-type organic semiconductor. The main object of the present invention is to provide a method of simultaneously improving the performance of N-type and P-type organic transistors by maintaining the contact resistance of P-type organic semiconductors.
또한 본 발명에서는 상기와 같은 유기염 용액의 선택적 도포를 통해 N-형과 P-형 유기 트랜지스터로 이루어진 CMOS 형 디지털 회로의 성능을 효과적으로 향상 시키는 방법을 제공하고자 한다.In addition, the present invention is to provide a method for effectively improving the performance of the CMOS digital circuit consisting of N-type and P-type organic transistor through the selective application of the organic salt solution as described above.
나아가 본 발명에서는 양친성 고분자 반도체를 이용한 양극성 유기박막트랜지스터(ambipolar OTFT)에서 N-형 과 P-형의 접촉저항을 효과적으로 향상시켜서 소자의 N형과 P형의 전하 주입을 향상시킨 양친성 유기박막 트랜지스터의 제조방법을 제시하는 것을 또 다른 목적으로 한다. Furthermore, in the present invention, the amphipathic organic thin film improves the N-type and P-type charge injection by effectively improving the contact resistance of the N-type and P-type in an ambipolar OTFT using an amphiphilic polymer semiconductor. Another object of the present invention is to provide a method of manufacturing a transistor.
또한 이러한 성능이 향상된 양친성 유기박막 트랜지스터를 이용하여 빛을 발광할수 있는 유기발광트랜지스터 (organic light emitting transistor)의 제조방법을 제공하고자 한다.In addition, the present invention provides a method of manufacturing an organic light emitting transistor that can emit light using an amphiphilic organic thin film transistor with improved performance.
상기한 과제는 본 발명에서 제시되는The above problems are presented in the present invention
기판;Board;
상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
상기 소스/드레인 전극 중 어느 하나에만 도포된 전자 및 정공주입층;An electron and hole injection layer applied to only one of the source / drain electrodes;
상기 전자 및 정공주입층을 포함하는 기판 상에 위치하는 유기반도체층;을 포함하는 것을 특징으로 하는 유기박막트랜지스터를 통해 해결될 수 있다.It can be solved through an organic thin film transistor comprising a; organic semiconductor layer located on the substrate including the electron and hole injection layer.
본 발명의 유기박막트랜지스터를 사용하면 금으로 제조된 소스/드레인 전극과 N-형 사이의 접촉저항을 대폭 줄일 수 있으며 원래 접촉저항이 낮은 소스/드레인 전극과 P-형 유기반도체사이의 접촉저항은 낮은 상태로 유지시킬수 있어서, 높은 전자 및 정공 주입특성을 지닌 고성능 양친성 유기박막 트랜지스터 및 유기발광트랜지스터를 제공할 수 있다.By using the organic thin film transistor of the present invention, the contact resistance between the source / drain electrode made of gold and the N-type can be greatly reduced, and the contact resistance between the source / drain electrode and the P-type organic semiconductor having low contact resistance is It can be kept in a low state, thereby providing a high performance amphiphilic organic thin film transistor and organic light emitting transistor having high electron and hole injection characteristics.
또한 각종 인쇄공정을 통해서 소스/드레인 전극 중 어느 하나에만 선택적으로 금속염으로 구성된 잉크용액을 도포하여 N-형 유기박막트랜지스터의 접촉저항을 효과적으로 줄일수 있으므로 제조공정을 단순화하고 제조원가를 줄일 수 있는 경제적인 효과도 기대된다.In addition, it is possible to effectively reduce the contact resistance of N-type organic thin film transistor by applying ink solution composed of metal salt to only one of the source / drain electrodes through various printing processes, thus simplifying the manufacturing process and reducing the manufacturing cost. The effect is also expected.
도 1 은 종래의 유기박막트랜지스터를 도시한 단면도이다.1 is a cross-sectional view showing a conventional organic thin film transistor.
도 2는 본 발명의 유기박막트랜지스터를 bottom gate 형태로 제조하는 단계를 나타내는 순서도이다.2 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a bottom gate.
도 3는 본 발명의 유기박막트랜지스터를 top gate 형태로 제조하는 단계를 나타내는 순서도이다.3 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a top gate.
도 4는 본 발명의 일 실시예에 따른 bottom gate 형태의 유기박막트랜지스터를 도시한 단면도이다.4 is a cross-sectional view illustrating an organic thin film transistor having a bottom gate type according to an embodiment of the present invention.
도 5은 본 발명의 또 다른 실시예에 따른 top gate 형태의 유기박막트랜지스터를 도시한 단면도이다.5 is a cross-sectional view illustrating an organic thin film transistor having a top gate type according to another embodiment of the present invention.
도 6은 Cs2CO3로 처리하지 않은 상태의 양극성 top gate 형태의 유기박막트랜지스터의 P-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 6 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
도 7은 Cs2CO3로 처리하지 않은 상태의 양극성 top gate 형태의 유기박막트랜지스터의 N-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 7 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
도 8은 Cs2CO3를 한 쪽 전극에만 도포한 상태의 양극성 top gate 형태의 유기박막트랜지스터의 P-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 8 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state in which Cs 2 CO 3 is applied to only one electrode.
도 9는 Cs2CO3를 한 쪽 전극에만 도포한 상태의 양극성 top gate 형태의 유기박막트랜지스터의 N-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 9 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in which Cs 2 CO 3 is applied to only one electrode.
도 10은 스프레이 코팅을 이용하여 P-형 및 N-형 한 쪽 유기트랜지스터 전극에만 선택적으로 금속염 용액을 도포하는 단계를 나타내는 모식도이다.FIG. 10 is a schematic diagram illustrating a step of selectively applying a metal salt solution to only P-type and N-type one organic transistor electrodes using spray coating.
도 11은 Cs2CO3를 N형 유기박막트랜지스터 소스/드레인 전극에만 도포한 후 제작된 유기 CMOS 인버터의 회로도와 출력곡선 및 게이트 전압에 따른 이득 값을 나타내는 도면이다.FIG. 11 is a diagram illustrating a circuit diagram of an organic CMOS inverter fabricated after applying Cs 2 CO 3 to only an N-type organic thin film transistor source / drain electrode and a gain value according to an output curve and a gate voltage.
실리콘 기판에 금나노 입자를 이용하여 잉크젯 프린팅의 인쇄공정을 통해서 Au의 소스/드레인 전극을 형성하였다. 두 전극 사이의 간격은 50nm로 이격시켰다. 소스 전극에만 선택적으로 금속염을 도포하기 위해서 이미 패터닝이되어 있는 shadow 마스크를 소스/드레인 전극이 형성되어 있는 기판위에 위치시켰다. 그런 다음 Cs2CO3를 2-ethoxyethanol 용매에 1mg/ml의 농도로 녹여 제조된 잉크를 스프레이 코팅기를 이용해서 10초간 샘플과 8cm의 이격을 가지고 도포했다. 이후 잔존하는 금속염 용매를 증발시키기 위하여 hotplate를 사용하여 100℃에서 15분간 가열했다.Source / drain electrodes of Au were formed through the printing process of inkjet printing using gold nanoparticles on a silicon substrate. The spacing between the two electrodes was spaced at 50 nm. In order to selectively apply metal salts only to the source electrode, a shadow mask, which has already been patterned, was placed on the substrate on which the source / drain electrodes were formed. Then, the ink prepared by dissolving Cs 2 CO 3 in a 2-ethoxyethanol solvent at a concentration of 1 mg / ml was applied using a spray coating machine at a distance of 8 cm from the sample for 10 seconds. Thereafter, the resultant was heated at 100 ° C. for 15 minutes using a hotplate to evaporate the remaining metal salt solvent.
유기반도체를 증착시키기 위하여 P-형 유기반도체인 펜타센을 진공챔버에 넣은 후 10-6 torr에서 200℃의 열을 가하여 승화시킨 다음 30 - 70 nm의 두께로 도포시켰다. 그 위에 PMMA를 200 nm의 두께로 스핀코팅 법을 통해서 도포한 후, shadow 마스크를 이용해서 트랜지스터의 채널 영역에만 Al을 이용해서 gate 전극을 60 nm의 두께로 증착시켜 유기박막트랜지스터를 제조하였다. In order to deposit the organic semiconductor, pentacene, a P-type organic semiconductor, was placed in a vacuum chamber, and then sublimed by applying a heat of 200 ° C. at 10 −6 torr and then applied to a thickness of 30 to 70 nm. After applying PMMA to the thickness of 200 nm by spin coating, an organic thin film transistor was manufactured by depositing a gate electrode having a thickness of 60 nm using Al only in the channel region of the transistor using a shadow mask.
이하 도면과 실시예를 참조하여 본 발명을 더욱 상세히 설명한다. 본 발명의 명세서 전반에 걸쳐 사용된 용어는 본 발명을 더욱 구체적으로 설명하기 위하여 예시한 것에 불과할 뿐 본 발명이 이에 한정되어 해석되어서는 아니됨은 명백하다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Terms used throughout the specification of the present invention are merely illustrated to explain the present invention in more detail, it is obvious that the present invention is not limited thereto.
도 1은 종래의 유기박막트랜지스터를 도시한 단면도이다. 도시된 바와 같이 기판(100) 상에 게이트 전극(110)이 형성되어 있고, 상기 게이트 전극(110)을 포함하는 기판 전면에 걸쳐 게이트 절연막(120)이 형성되어 있다. 상기 게이트 절연막(120) 상에 소스/드레인 전극(130)이 서로 이격되어 형성되어 있고, 상기 소스/드레인 전극(130) 및 상기 게이트 절연막(120)에 형성된 유기반도체층(150)을 형성한다.1 is a cross-sectional view showing a conventional organic thin film transistor. As illustrated, a gate electrode 110 is formed on the substrate 100, and a gate insulating layer 120 is formed over the entire surface of the substrate including the gate electrode 110. Source / drain electrodes 130 are formed on the gate insulating layer 120 to be spaced apart from each other, and the organic semiconductor layer 150 formed on the source / drain electrodes 130 and the gate insulating layer 120 is formed.
이와 같은 구조를 갖는 종래의 유기박막트랜지스터는 소스/드레인 전극과 유기반도체층 사이의 접촉 저항이 크다는 문제점이 발생한다. 소스 및 드레인 전극은 유기 박막으로 전하를 주입하는 역할을 하므로 이를 방해하는 전극-유기박막 사이의 에너지 장벽을 줄이는 것이 중요하다. 예를 들어 펜타센을 유기반도체로 사용하는 경우 전극으로 금이 많이 사용되는데 이는 금의 일함수(work function)가 5.1eV 로 펜타센의 HOMO(Highest Occupied Molecular Orbital)값인 5.1eV와 일치하여 전하 주입을 위한 에너지 장벽이 낮기 때문이다.The conventional organic thin film transistor having such a structure has a problem that the contact resistance between the source / drain electrodes and the organic semiconductor layer is large. Since the source and drain electrodes serve to inject charge into the organic thin film, it is important to reduce the energy barrier between the electrode and the organic thin film which interferes with this. For example, when pentacene is used as an organic semiconductor, a lot of gold is used as an electrode. The work function of gold is 5.1 eV, and the charge injection is consistent with 5.1 eV, which is the highest Occupied Molecular Orbital (HOMO) value of pentacene. This is because the energy barrier for them is low.
그러나 종래의 실리콘 박막트랜지스터에 구비된 실리콘 반도체층과 달리 유기박막트랜지스터에 구비된 유기반도체층에는 고농도의 도핑을 실시할 수 없으며, 이에 따라 소스/드레인 전극과 유기반도체층 사이의 접촉 저항이 증가되어 오믹 컨택(ohmic contact)을 형성할 수 없다는 문제점이 발생된다.However, unlike the silicon semiconductor layer provided in the conventional silicon thin film transistor, the organic semiconductor layer provided in the organic thin film transistor cannot be doped with high concentration. Accordingly, the contact resistance between the source / drain electrode and the organic semiconductor layer is increased. The problem arises that an ohmic contact cannot be formed.
이러한 접촉저항의 문제점은 전자전달형 (n-type) OTFT 와 정공 전달형 (p-type) OTFT가 동시에 사용될 때 더욱 중요하게 부각된다. 전술한 바와 같이 OTFT의 전자나 정공 주입 소스/드레인 전극으로는 금을 사용하는데, 금이 갖는 일함수 (5.1eV)로 인해서 N형 유기반도체와 P형 유기반도체에 모두 만족할 만한 오믹컨택을 동시에 얻을 수는 없다. 이러한 점은 N형과 P형 트랜지스터를 모두 포함하고 이는 CMOS형 디지털 회로를 구현할 때는 매우 심각하게 작용하여 대부분의 유기 CMOS 형 디지털 회로가 N형 트랜지스터에 매우 높은 접촉저항을 유도시키고 이로 인해서 N형 유기트랜지스터 성능이 P형 비해서 매우 낮은 실정이다. 보통 실리콘 재료에서는 이러한 문제점을 해결하기 위해서 N형과 P형에 각각 N형 과 P형 도핑을 해주어서 이러한 문제점을 극복하고 있으나, 유기반도체의 경우 이러한 선택적인 도핑이 매우 어렵고 이를 패터닝하는 기술도 많이 개발되지 않았다. This problem of contact resistance is more important when an n-type OTFT and a p-type OTFT are used at the same time. As described above, gold is used as the electron or hole injection source / drain electrode of the OTFT, and due to the work function (5.1 eV) of gold, it is possible to simultaneously obtain an ohmic contact that satisfies both N-type and P-type organic semiconductors. There is no number. This includes both N-type and P-type transistors, which are very serious when implementing CMOS type digital circuits, and most organic CMOS type digital circuits induce very high contact resistance in the N type transistors, resulting in N type organic. The transistor performance is very low compared to the P type. In order to solve this problem, in general, silicon materials are doped with N-type and P-type, respectively, to overcome these problems. However, in the case of organic semiconductors, such selective doping is very difficult and many techniques for patterning the same. Not developed.
도 2는 본 발명의 유기박막트랜지스터를 bottom gate 형태로 제조하는 단계를 나타내는 순서도이다. 버텀 게이트 형태의 유기박막트랜지스터는 기판을 제공하고, 상기 기판 상에 게이트 전극을 형성시킨 후, 상기 게이트 전극을 덮도록 게이트 절연막을 형성하고, 상기 게이트 절연막 상의 일부 영역에 서로 이격되게 소스/드레인 전극을 형성시킨 후, 상기 소스/드레인 전극 중 어느 하나의 전극에만 선택적으로 금속염을 도포하여 기판 전면에 걸쳐 유기반도체층을 형성하는 단계로 구성된다. 2 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a bottom gate. The bottom gate type organic thin film transistor provides a substrate, forms a gate electrode on the substrate, forms a gate insulating film to cover the gate electrode, and source / drain electrodes spaced apart from each other on a portion of the gate insulating film. After forming a metal salt, the organic semiconductor layer may be formed by selectively applying a metal salt to only one of the source / drain electrodes.
도 3은 본 발명의 유기박막트랜지스터를 top gate 형태로 제조하는 단계를 나타내는 순서도이다. 탑 게이트 형태의 유기박막트랜지스터는 기판을 제공하고, 그위에 서로 이격되게 소스/드레인 전극을 형성 시킨후, 상기 소스/드레인 전극 중 어느 하나의 전극에만 선택적으로 금속염을 도포하고 그위에 전면에 걸쳐 유기반도체층을 형성한후 게이트 절연막을 그위에 전면에 걸쳐서 도포하고 마지막으로 트랜지스터의 소스/드레인 전극 사이에 게이트 전극을 형성하는 단계로 구성된다.3 is a flowchart illustrating a step of manufacturing the organic thin film transistor of the present invention in the form of a top gate. An organic thin film transistor in the form of a top gate provides a substrate, and forms a source / drain electrode thereon so as to be spaced apart from each other, and then selectively applies a metal salt to only one of the source / drain electrodes and spreads the organic material over the entire surface thereon. After forming the semiconductor layer, a gate insulating film is applied over the entire surface, and finally a gate electrode is formed between the source / drain electrodes of the transistor.
상기 기판은 유리와 같은 투명기판, 실리콘 기판 또는 플라스틱으로 형성될 수 있다. 상기 플라스틱 기판 물질로는 폴리에테르술폰(PES, polyethersulphone), 폴리아크릴레이트(PAR, polyacrylate), 폴리에테르 이미드(PET, polyetherimide), 폴리에틸렌 나프탈레이트(PEN, polyethyelenen napthalate), 폴리에틸렌테레프탈레이드(PET, polyethyeleneterepthalate) 폴리페닐렌 설파이드(PPS, polyphenylene sulfide), 폴리아릴레이트(polyallylate), 폴리이미드(polyimide), 폴리카보네이트(PC), 셀룰로오스 트리 아세테이트(TAC), 셀룰로오스 아세테이트 프로피오네이트(CAP: cellulose acetate propinoate) 중에서 선택되는 어느 하나를 사용한다. 바람직하게는 UV 투과가 가능한 유리 같은 투명기판을 사용한다.The substrate may be formed of a transparent substrate such as glass, a silicon substrate, or plastic. The plastic substrate material is polyethersulphone (PES), polyacrylate (PAR, polyacrylate), polyetherimide (PET, polyetherimide), polyethylene naphthalate (PEN, polyethyelenen napthalate), polyethylene terephthalate (PET, polyethyeleneterepthalate (PPS) polyphenylene sulfide (PPS), polyallylate (polyallylate), polyimide (polyimide), polycarbonate (PC), cellulose tri acetate (TAC), cellulose acetate propinoate Use any one selected from). Preferably, a transparent substrate such as glass capable of UV transmission is used.
상기 게이트 전극은 금 (Au), 니켈 (Ni), 구리 (Cu), 은 (Ag), 알루미늄(Al), 알루미늄 합금(Al-alloy), 몰리브덴(Mo), 몰리브덴 합금(Mo-alloy) 중 에서 선택되는 어느 하나로 형성할 수 있으며, 몰리브덴-텅스텐(MoW) 합금으로 형성하는 것이 더욱 바람직하다. 또한 게이트 전극을 여러 가지 인쇄공정을 통해서 형성 할 수 있으며 통상적으로 금속 나노입자용액이나 PEDOT:PSS 전도성 고분자를 잉크로 사용하여 잉크젯 프린팅 등의 인쇄공정을 이용하여 게이트 전극을 제조할 수 있다. 이러한 인쇄공정을 통해서 게이트전극을 형성하며 진공공정을 배제 할 수 있어서 제조비용의 절감효과를 기대할 수 있다. The gate electrode is made of gold (Au), nickel (Ni), copper (Cu), silver (Ag), aluminum (Al), aluminum alloy (Al-alloy), molybdenum (Mo), and molybdenum alloy (Mo-alloy). It may be formed of any one selected from, it is more preferable to form a molybdenum-tungsten (MoW) alloy. In addition, the gate electrode may be formed through various printing processes. In general, the gate electrode may be manufactured using a printing process such as inkjet printing using a metal nanoparticle solution or a PEDOT: PSS conductive polymer as an ink. Through the printing process, the gate electrode can be formed and the vacuum process can be excluded, thereby reducing the manufacturing cost.
상기 게이트 전극을 포함하는 기판 전면에 걸쳐 게이트 절연막을 형성한다. A gate insulating film is formed over the entire surface of the substrate including the gate electrode.
상기 게이트 절연막은 유기절연막 또는 무기절연막의 단일막 또는 다층막으로 구성되거나 유-무기 하이브리드 막으로 구성된다. 상기 무기절연막으로는 실리콘 산화막, 실리콘 질화막, Al2O3, Ta2O5, BST, PZT 중에서 선택되는 어느 하나 또는 다수개를 사용한다. 상기 유기절연막으로는 폴리메타아크릴레이트(PMMA, polymethylmethacrylate), 폴리스타이렌(PS, polystyrene), 페놀계 고분자, 아크릴계 고분자, 폴리이미드와 같은 이미드계 고분자, 아릴에테르계 고분자, 아마이드계 고분자, 불소계 고분자, p-자이리렌계 고분자, 비닐알콜계 고분자, 파릴렌(parylene) 중에서 선택되는 어느 하나 또는 다수개를 사용한다. The gate insulating film is composed of a single film or a multilayer film of an organic insulating film or an inorganic insulating film, or an organic-inorganic hybrid film. As the inorganic insulating film, any one or more selected from silicon oxide film, silicon nitride film, Al2O3, Ta2O5, BST, and PZT is used. The organic insulating film may include polymethacrylate (PMMA, polymethylmethacrylate), polystyrene (PS, polystyrene), phenolic polymer, acrylic polymer, imide polymer such as polyimide, arylether polymer, amide polymer, fluorine polymer, p -Use any one or more selected from xyrene-based polymer, vinyl alcohol-based polymer, parylene (parylene).
상기 게이트 절연막상에 서로 이격되게 소스/드레인 전극을 형성한다. 상기 소스/드레인 전극은 Au, Al, Ag, Mg, Ca, Yb, Cs-ITO 또는 이들의 합금 중에서 선택되는 단일층으로 형성될 수 있으며, 게이트 절연막과의 접착성을 향상시키고 언더컷 현상을 방지하기 위하여 Ti, Cr 또는 Al과 같은 접착 금속층을 더욱 포함하여 다중층으로 형성될 수 있다.Source / drain electrodes are formed on the gate insulating layer to be spaced apart from each other. The source / drain electrode may be formed of a single layer selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO, or an alloy thereof, and may improve adhesion to the gate insulating layer and prevent undercut phenomenon. In order to further include an adhesive metal layer such as Ti, Cr or Al may be formed in a multi-layer.
상기 소스/드레인 전극 상의 어느 하나의 전극에는 유기반도체층과 소스/드레인 전극 사이의 접촉저항을 줄이고 전자주입성을 향상시키기 위하여 Cs2CO3, CsF, Rb2CO3, K2CO3, Na2CO3, LiF, CaF2, MgF2, NaCl, MgO 과 같은 금속염 중에서 선택되거나 이들의 혼합물로부터 선택되는 금속염 전자주입층을 형성하기 위한 잉크용액을 제조한다. 또한 정공 주입특성을 향상시키기 위해서 V2O5, MoO3, F4TCNQ 등과 같은 금속염이나 유기물 중에서 선택되거나 이들의 혼합물로부터 선택되는 금속염 정공주입층을 형성하기 위한 잉크용액을 제조한다. 잉크의 농도는 금속염의 금속염층의 두께를 조절하는데 매우 중요한 역할을 담당하므로 반드시 일정한 농도의 금속명 잉크를 사용해야만 전자나 정공주입성 향상의 효과를 얻을수 있다. 사용한 잉크의 농도는 사용한 인쇄방법에 따라서 다소 달라질수 잇으나 일반적으로 0.1 mg/ml - 10 mg/ml 정도의 농도를 사용하여 0.1 - 2 nm 정도의 두께의 금속염층을 도포한다면 기대하는 효과를 얻을 수 있다. One of the electrodes on the source / drain electrodes includes Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na to reduce contact resistance between the organic semiconductor layer and the source / drain electrodes and improve electron injection properties. An ink solution for forming a metal salt electron injection layer selected from metal salts such as 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO, or a mixture thereof is prepared. In addition, to improve the hole injection characteristics, an ink solution for forming a metal salt hole injection layer selected from metal salts or organic substances such as V 2 O 5 , MoO 3 , F 4 TCNQ, or a mixture thereof is prepared. Since the ink concentration plays a very important role in controlling the thickness of the metal salt layer of the metal salt, it is necessary to use a metal concentration ink of a constant concentration to obtain the effect of improving the electron or hole injection property. The concentration of the ink used may vary slightly depending on the printing method used. However, if the metal salt layer having a thickness of 0.1-2 nm is applied using a concentration of 0.1 mg / ml-10 mg / ml, the expected effect can be obtained. Can be.
상기 금속염 전자주입층 또는 정공주입층은 전술한 금속염 잉크용액을 잉크젯 프린팅, 스크린 인쇄, 스프레이 코팅, 그라비아 프린팅, 그라비아 옵셋 프린팅, 리버스 그라비아 옵셋 프린팅, 노즐프린팅, 패드프린팅 방법을 이용하여 도포함으로써 달성된다.The metal salt electron injection layer or hole injection layer is achieved by applying the above-described metal salt ink solution using ink jet printing, screen printing, spray coating, gravure printing, gravure offset printing, reverse gravure offset printing, nozzle printing, pad printing method. .
상기 금속염 전자 및 정공주입층은 두께를 2 nm 미만으로 하며 바람직하게는 0.1 ~ 2 nm인 것을 특징으로 한다. 상기 금속염 용액층의 두께가 0.1 nm이상으로 형성되어야 전자 혹은 정공 주입 효율 향상이라는 효과를 나타낼 수 있으며, 2 nm을 초과하여 형성하면 이들이 저항으로 작용하여 전자 및 정공 주입효과가 오히려 감소하는 문제점이 발생한다.The metal salt electron and hole injection layer has a thickness of less than 2 nm, preferably 0.1 to 2 nm. When the thickness of the metal salt solution layer is formed to be 0.1 nm or more, the electron or hole injection efficiency may be improved. When the metal salt solution layer is formed to be more than 2 nm, the electron and hole injection effects may be reduced. do.
또한 상기 금속염 전하주입층을 CMOS형 전자회로나 양극성 유기박막 트랜지스터에 적용하고자 할때는 소스 또는 드레인 전극 중 어느 하나의 전극에만 도포하는 것이 바람직하다. 전술한 바와 같이 N형 반도체 와 P형 반도체를 모두 포함하는 CMOS형 디지털 회로를 구현할시 N형 트랜지스터의 접촉저항을 줄이고 P형 트랜지스터의 접촉저항은 그대로 유지하기 위함이다. In addition, when the metal salt charge injection layer is to be applied to a CMOS electronic circuit or a bipolar organic thin film transistor, it is preferable to apply the metal salt charge injection layer to only one of a source or a drain electrode. As described above, when implementing a CMOS digital circuit including both an N-type semiconductor and a P-type semiconductor, the contact resistance of the N-type transistor is reduced and the contact resistance of the P-type transistor is maintained as it is.
상기 금속염 용액층을 포함하는 기판 전면에 걸쳐 유기반도체층을 형성한다. 상기 유기반도체층은 N형 유기반도체 또는 P형 유기반도체를 사용할 수도 있다. 상기 N형 유기반도체는 아센계 물질, 완전 불화된 아센계 물질, 부분 불화된 아센계 물질, 부분 불화된 올리고티오펜(oligothiophene)계 물질, 플러렌(fullerene)계 물질, 치환기를 갖는 플러렌계 물질, 완전 불화된 프탈로시아닌(phthalocyanine)계 물질, 부분 불화된 프탈로시아닌계 물질, 페릴렌 테트라카르복실릭 디이미드(perylene tetracarboxylic diimide)계 물질, 페릴렌 테트라카르복실 디안하이드라이드(perylene tetracarboxylic dianhydride)계 물질, 나프탈렌 테트라카르복실릭 디이미드(naphthalene tetracarboxylic diimide)계 물질 또는 나프탈렌 테트라카르복실릭 디안하이드라이드(naphthalene tetracarboxylic dianhydride)계 물질 중에서 어느 하나를 포함하는 것이 바람직하다. 여기서 상기 아센(acene)계 물질은 안트라센, 테트라센, 펜타센, 페릴렌 또는 코노렌 중에서 선택될 수 있다.An organic semiconductor layer is formed over the entire surface of the substrate including the metal salt solution layer. The organic semiconductor layer may be an N-type organic semiconductor or a P-type organic semiconductor. The N-type organic semiconductor is an acene-based material, a fully fluorinated acene-based material, a partially fluorinated acene-based material, a partially fluorinated oligothiophene-based material, a fullerene-based material, a fullerene-based material having a substituent, Fully fluorinated phthalocyanine materials, partially fluorinated phthalocyanine materials, perylene tetracarboxylic diimide materials, perylene tetracarboxylic dianhydride materials, naphthalene It is preferable to include either tetracarboxylic diimide (naphthalene tetracarboxylic diimide) material or naphthalene tetracarboxylic dianhydride (material). Here, the acene-based material may be selected from anthracene, tetracene, pentacene, perylene or conorene.
또한 상기 P형 유기반도체는 아센(acene), 폴리-티에닐렌비닐렌(poly-thienylenevinylene), 폴리-3-헥실티오펜(poly-3-hexylthiophen), 알파-헥사티에닐렌(α-hexathienylene), 나프탈렌(naphthalene), 알파-6-티오펜(α-6-thiophene), 알파-4-티오펜 (α-4-thiophene), 루브렌(rubrene), 폴리티오펜(polythiophene), 폴리파라페닐렌비닐렌(polyparaphenylenevinylene), 폴리파라페닐렌(polyparaphenylene), 폴리플로렌(polyfluorene), 폴리티오펜비닐렌(polythiophenevinylene), 폴리티오펜-헤테로고리방향족 공중합체(polythiophene-heterocyclicaromatic copolymer), 트리아릴아민(triarylamine)을 포함하는 물질 또는 이들의 유도체 중에서 선택될 수 있는 데, 여기서 상기 아센족 물질은 펜타센(pentacene), 페릴렌(perylene), 테트라센(tetracene) 또는 안트라센(anthracene) 중에서 어느 하나이다.In addition, the P-type organic semiconductor is acene (acene), poly-thienylenevinylene (poly-thienylenevinylene), poly-3-hexylthiophene (poly-3-hexylthiophen), alpha-hexathienylene (α-hexathienylene), Naphthalene, alpha-6-thiophene, alpha-4-thiophene, alpha-4-thiophene, rubrene, polythiophene, polyparaphenylene Polyparaphenylenevinylene, polyparaphenylene, polyfluorene, polythiophenevinylene, polythiophene-heterocyclicaromatic copolymer, triarylamine ( triarylamine) or a derivative thereof, wherein the acene group is any one of pentacene, perylene, tetratracene or anthracene.
이로써 본 발명의 일실시예에 따른 유기박막트랜지스터를 완성한다.This completes the organic thin film transistor according to an embodiment of the present invention.
도 4는 본 발명의 일 실시예에 따른 bottom gate 형태의 유기박막트랜지스터를 도시한 단면도이다.4 is a cross-sectional view illustrating an organic thin film transistor having a bottom gate type according to an embodiment of the present invention.
도 5은 본 발명의 또 다른 실시예에 따른 top gate 형태의 유기박막트랜지스터를 도시한 단면도이다.5 is a cross-sectional view illustrating an organic thin film transistor having a top gate type according to another embodiment of the present invention.
도 6은 Cs2CO3로 처리하지 않은 상태의 양극성 top gate 형태의 유기박막트랜지스터의 P-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다. 사용된 유기 고분자 반도체는 미국 Polyera 사에서 구입한 ActivInk P2100 소재로써 티오펜을 기반으로는 공액고분자이며 보통 정공의 이동도가 매우 높은 재료이다. 도 6의 결과는 P2100을 Au 소스/드레인 전극이 미리 패터닝된 유리기판위에 스핀코팅 공정으로 도포한후 PMMA 절연체를 스핀코팅 공정으로 도포하고 Al 전극을 게이트로 형성하여 제작된 Top gate 구조의 OTFT를 측정하여 얻은 결과이다. 도 6에서 보듯이 P2100 OTFT는 전형적인 p-type OTFT의 성능을 보여주었으며, -40 ~ -100 V의 drain voltage를 가해 주었을때 0.16 ~ 0.54 cm2/Vs 의 정공이동도를 얻었다.FIG. 6 is a diagram showing a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3. The organic polymer semiconductor used is ActivInk P2100 material purchased from Polyera, USA. It is a conjugated polymer based on thiophene and is a material with high hole mobility. 6 shows that P2100 is coated on a glass substrate on which Au source / drain electrodes are pre-patterned by spin coating, and then PMMA insulator is applied by spin coating, and an Al electrode is formed as a gate. The result obtained by measurement. As shown in FIG. 6, the P2100 OTFT showed the performance of a typical p-type OTFT and obtained a hole mobility of 0.16 to 0.54 cm2 / Vs when a drain voltage of -40 to -100 V was applied.
도 7은 Cs2CO3로 처리하지 않은 상태의 양극성 top gate 형태의 유기박막트랜지스터의 N-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 7 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in a state not treated with Cs 2 CO 3 .
전술한 바와 같이 Polyera P2100 유기고분자 반도체 재료는 정공전달형 고분자이기 때문에 전자이동도는 상대적으로 낮은 값을 보여주었다. 도 7에서 보듯이 P2100 OTFT의 소스/드레인 전극과 게이트 전극에 positive 전압을 가해주면 n-type OTFT의 특성을 도 7과 같이 보여주긴 하나, 그 성능이 도 6의 앞선 p-type 특성에 비해서 10배 이상 낮아서 40 ~ 100 V의 드레인 전압를 가해 주었을때 0.016 ~ 0.022 cm2/Vs 의 전자이동도를 얻었다. 이러한 p-type 과 n-type의 이동도 불균형으로 인해서 P2100 재료를 이용해서 CMOS형 회로를 구성하거나 회로의 속도가 저하되며 양극성 유기 발광 트랜지스터를 제작하게 되면 빛의 발광이 이루어 지지 않게 된다. As described above, since the Polyera P2100 organic polymer semiconductor material is a hole transport polymer, electron mobility was relatively low. As shown in FIG. 7, when a positive voltage is applied to the source / drain electrodes and the gate electrode of the P2100 OTFT, the characteristics of the n-type OTFT are shown in FIG. 7, but the performance is 10 compared to the p-type characteristics of FIG. 6. When the drain voltage of 40 to 100 V was applied, the electron mobility of 0.016 to 0.022 cm2 / Vs was obtained. Due to the imbalance in mobility of p-type and n-type, when a CMOS circuit is constructed using P2100 material or the speed of the circuit is reduced and a bipolar organic light emitting transistor is fabricated, light emission does not occur.
도 8은 Cs2CO3를 한 쪽 전극에만 도포한 상태의 양극성 top gate 형태의 유기박막트랜지스터의 P-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 8 is a diagram illustrating a hole curve according to a gate curve and a transition curve of a P-Channel of an organic thin film transistor of a bipolar top gate type in a state in which Cs 2 CO 3 is applied to only one electrode.
도 8의 결과는 top gate 구조의 P2100 OTFT를 제작시 본 발명에서 제안한 기술을 적용하여 한쪽 전극에 Cs2CO3를 스프레이 코팅법으로 적용하여 도포하여서 전자의 주입특성은 향상시키며 동시에 정공 주입에는 영향을 최소화 하도록 하였다. 도 8의 결과에서처럼 P2100 OTFT는 전형적인 p-type OTFT의 성능을 보여주었으며, -40 ~ -100 V의 drain voltage를 가해 주었을때 0.13 ~ 0.40 cm2/Vs 의 정공이동도를 보여주었으며, 이는 앞선 도 6의 Cs2CO3을 처리하지 않은 OTFT의 특성과 거의 유사한 성능을 보여주어서 Cs2CO3의 도포하였으나 이를 소스/드레인중 한전극에만 패터닝 하여 정공주입의 효율저하를 일으키지 않음을 알 수 있다. 스프레이 도포 조건은 Cs2CO3를 2-ethoxyethanol 용매에 1mg/ml의 농도로 녹여서 스프레이 잉크를 제조한다. 제조된 잉크를 스프레이 코팅기를 이용해서 10초간 샘플과 8cm의 이격을 가지고 도포를 하였다. 통상적으로 6-20초 사이의 시간을 도포하면 높은 전자나 정공 주입성의 향상을 얻을수 있으며 6초 보다 짧거나 20초 보다 긴 시간을 도포하게 너무 얇은 두께나 너무 두꺼운 두께가 형성되어서 원하는 정도의 전자나 정공의 주입 특성 향상을 얻기 어렵다. The result of FIG. 8 is to apply the technique proposed in the present invention when fabricating the P2100 OTFT of the top gate structure by applying Cs2CO3 to one electrode by spray coating method to improve the electron injection characteristics and at the same time to minimize the effect on the hole injection It was. As shown in the results of FIG. 8, the P2100 OTFT showed the performance of a typical p-type OTFT, and showed a hole mobility of 0.13 to 0.40 cm2 / Vs when a drain voltage of -40 to -100 V was applied. The Cs 2 CO 3 was applied to Cs 2 CO 3 , but the Cs 2 CO 3 was applied to only one electrode of the source / drain to reduce the hole injection efficiency. Spray application conditions were prepared by dissolving Cs 2 CO 3 in 2-ethoxyethanol solvent at a concentration of 1 mg / ml. The prepared ink was applied at a distance of 8 cm from the sample for 10 seconds using a spray coating machine. In general, if you apply a time between 6-20 seconds, high electron or hole injection properties can be obtained, and too thin or too thick thickness is formed to apply a time shorter than 6 seconds or longer than 20 seconds. It is difficult to obtain an improvement in the injection characteristics of holes.
도 9는 Cs2CO3를 한 쪽 전극에만 도포한 상태의 양극성 top gate 형태의 유기박막트랜지스터의 N-Channel의 전이곡선(transfer curve)과 게이트 전압에 따른 정공이동도를 나타내는 도면이다.FIG. 9 is a diagram illustrating a hole curve according to a gate curve and a transition curve of an N-channel of an organic thin film transistor of a bipolar top gate type in which Cs 2 CO 3 is applied to only one electrode.
도 9의 결과는 도 8의 결과를 도출한 동일한 트랜지스터를 통해서 측정이 되었으며, 소스/드레인 전극과 게이트 전극에 positive 전압을 가해주어서 Cs2CO3의 도포를 통해서 n-type OTFT의 특성을 향상을 관찰하였다. 도 9에서 보듯이 40 ~ 100 V의 드레인 전압을 가해 주었을때 0.14 ~ 0.24 cm2/Vs 의 전자이동도를 얻었다. 이는 Cs2CO3을 도포하지 않은 소자에 비해서 10배이상의 전자 이동도 향상을 얻은 것이며 이는 Cs2CO3처리에 의해서 전자 주입능력이 향상된 때문이다.The results of FIG. 9 were measured through the same transistors from which the results of FIG. 8 were obtained, and the characteristics of n-type OTFT were improved by applying Cs 2 CO 3 by applying a positive voltage to the source / drain electrodes and the gate electrode. Observed. As shown in FIG. 9, when a drain voltage of 40 to 100 V was applied, an electron mobility of 0.14 to 0.24 cm 2 / Vs was obtained. This will also improve the electromigration obtained more than 10 times compared to devices that are not coated with Cs 2 CO 3 because the electron injecting capability increased by the Cs 2 CO 3 treatment.
도 10은 스프레이 코팅을 이용하여 한 쪽 전극에만 선택적으로 금속염 용액을 도포하는 단계를 나타내는 모식도이다. 상기한 유리나 Si wafer 혹은 플라스틱 기판에 포토 리소그라피 공정을 통해서 Au의 소스/드레인 전극을 형성한다. 통상적으로 OTFT를 제조할 때 Au 소스/드레인 전극사이의 간격은 수 um - 수 백 um 정도이다. 그 위에 스프레이 코팅이나 상기한 기타 여러 인쇄장비를 이용해서 선택적으로 전극에 금속염 잉크를 도포하게된다. 스프레이 코팅의 경우 한쪽 전극에 선택적으로 금속염을 도포하기 위해서 장비에 도포하고자 하는 금속염 용액을 주입하고 이미 패터닝이되어 있는 shadow 마스크를 소스/드레인 전극이 형성되어 있는 기판위에 놓는다. 이때 마스크가 소스 혹은 드레인 전극중 한쪽 전극에만 열려 있게 되어서 그위에 스프레이 코팅기를 통해서 도포하면 소스/드레인중 한쪽 전극에만 금속염 용액이 도포되고 다른쪽 전극은 도포되지 않게 된다. 그러나 잉크젯 프린팅과 같이 수십 um의 고해상도 패턴이 장비 자체로 가능한 인쇄장비는 이러한 shadow 마스크 공정이 불필요하며 인쇄장비를 통해서 직접 원하는 전극에만 도포가 가능하게된다. 금속염의 도포가 끝나면 사용했던 용매를 증발시키고 고체상태의 금속염 층만을 남기기 위해서 사용한 용매의 증발온도이상으로 기판에 열을 가하여 용매를 증발시키게된다. 통상적인 유기용매의 증발온도가 50 - 250도 사이이므로 그정도의 온도를 hotplate를 통해서 10분이상 샘플에 가하여 금속염의 용매를 증발시킨다. 그후에 OTFT를 제작하기위해서 상기한 다양한 단분자 혹은 고분자 유기반도체를 용액혹은 진공증착 방법을 통해서 도포한다. 그위에 상기한 다양한 고분자나 SiO2등의 절연체를 용액혹은 진공증착 방법을 통해서 도포한다. 마지막으로 Al 등의 금속을 도포하면 top gate 형태의 OTFT 제작이 완료된다. 10 is a schematic diagram showing a step of selectively applying a metal salt solution to only one electrode using a spray coating. A source / drain electrode of Au is formed through the photolithography process on the glass, Si wafer, or plastic substrate. Typically, when manufacturing an OTFT, the spacing between Au source / drain electrodes is on the order of several um-several hundred um. On top of that, spray coating or other printing equipment described above may be used to selectively apply metal salt ink to the electrodes. In the case of spray coating, in order to selectively apply metal salt to one electrode, a metal salt solution to be applied is injected into the equipment, and a shadow mask, which is already patterned, is placed on the substrate on which the source / drain electrodes are formed. In this case, when the mask is open to only one of the source or drain electrodes and applied through the spray coating machine, the metal salt solution is applied to only one electrode of the source / drain and the other electrode is not applied. However, printing equipment such as inkjet printing capable of tens of um high-resolution patterns by the equipment itself does not require such a shadow mask process and can be applied only to desired electrodes directly through the printing equipment. After the application of the metal salt, the solvent is evaporated by applying heat to the substrate above the evaporation temperature of the used solvent to evaporate the used solvent and leave only the solid metal salt layer. Since the evaporation temperature of a conventional organic solvent is between 50 and 250 degrees Celsius, the temperature is added to the sample for 10 minutes through a hotplate to evaporate the solvent of the metal salt. Thereafter, various monomolecular or polymeric organic semiconductors described above are applied by a solution or vacuum deposition method to fabricate OTFT. The various polymers or insulators, such as SiO 2, are applied thereon by a solution or vacuum deposition method. Finally, the application of metals, such as Al, completes the manufacture of the top gate type OTFT.
도 11은 Cs2CO3를 N형 전극에만 도포한 후 제작된 유기 CMOS 인버터의 회로도와 출력곡선 및 게이트 전압에 따른 이득값을 나타내는 도면이다. CMOS 인버터는 P형 OTFT와 N형 OTFT가 1:1로 결합된 회로로써 구체적인 회로도는 도 11과 같다. 사용된 반도체는 상기한 결과와 동일한 Polyera 사의 P2100이며 통상적으로 P2100은 정공전달형 고분자이므로 Cs2CO3를 선택적으로 한쪽 전극에만 도포하지 않으면 도 6과 7처럼 P TYPE OTFT가 10배 이상 성능을 보여주어서 제작된 CMOS 인버터는 도 11에서 보이는 것처럼 매우 10 - 30 정도의 낮은 전압 이득을 보여준다. 하지만 본 발명에서 제안된 기술로 유기 CMOS 인버터의 한쪽 전극을 금속염으로 선택적으로 도포하여 제작하게되면 도 11에서 보이는 것처럼 70 정도의 높은 전압이득을 얻을수 있게 된다. 이는 현재까지 보고된 유기 CMOS 인버터의 가장 높은 전압이득에 해당된다.FIG. 11 is a diagram illustrating a circuit diagram of an organic CMOS inverter fabricated after applying Cs 2 CO 3 to only an N-type electrode, and a gain value according to an output curve and a gate voltage. The CMOS inverter is a circuit in which a P-type OTFT and an N-type OTFT are 1: 1 coupled, and a detailed circuit diagram thereof is shown in FIG. 11. The semiconductor used is P2100 manufactured by Polyera, which is the same as the above result. In general, P2100 is a hole-transfer polymer, and thus, if Cs 2 CO 3 is not selectively applied to only one electrode, the P TYPE OTFT shows 10 times or more performance as shown in FIGS. The fabricated CMOS inverter shows a very low voltage gain of about 10-30, as shown in FIG. However, when one electrode of the organic CMOS inverter is selectively coated with a metal salt by the proposed technique, a high voltage gain of about 70 may be obtained as shown in FIG. 11. This corresponds to the highest voltage gain of organic CMOS inverters reported to date.
[실시예 1: 전자 및 정공주입성능이 향상된 유기박막트랜지스터의 제조][Example 1: Fabrication of organic thin film transistor with improved electron and hole injection performance]
실리콘 기판에 금나노 입자를 이용하여 잉크젯 프린팅의 인쇄공정을 통해서 Au의 소스/드레인 전극을 형성하였다. 두 전극 사이의 간격은 50nm로 이격시켰다. 소스 전극에만 선택적으로 금속염을 도포하기 위해서 이미 패터닝이되어 있는 shadow 마스크를 소스/드레인 전극이 형성되어 있는 기판위에 위치시켰다. 그런 다음 Cs2CO3를 2-ethoxyethanol 용매에 1mg/ml의 농도로 녹여 제조된 잉크를 스프레이 코팅기를 이용해서 10초간 샘플과 8cm의 이격을 가지고 도포했다. 이후 잔존하는 금속염 용매를 증발시키기 위하여 hotplate를 사용하여 100℃에서 15분간 가열했다.Source / drain electrodes of Au were formed through a printing process of inkjet printing using gold nanoparticles on a silicon substrate. The spacing between the two electrodes was spaced at 50 nm. In order to selectively apply metal salts only to the source electrode, a shadow mask, which has already been patterned, was placed on the substrate on which the source / drain electrodes were formed. Then, the ink prepared by dissolving Cs 2 CO 3 in a 2-ethoxyethanol solvent at a concentration of 1 mg / ml was applied using a spray coating machine at a distance of 8 cm from the sample for 10 seconds. Thereafter, the resultant was heated at 100 ° C. for 15 minutes using a hotplate to evaporate the remaining metal salt solvent.
유기반도체를 증착시키기 위하여 P-형 유기반도체인 펜타센을 진공챔버에 넣은 후 10-6 torr에서 200℃의 열을 가하여 승화시킨 다음 30 - 70 nm의 두께로 도포시켰다. 그 위에 PMMA를 200 nm의 두께로 스핀코팅 법을 통해서 도포한 후, shadow 마스크를 이용해서 트랜지스터의 채널 영역에만 Al을 이용해서 gate 전극을 60 nm의 두께로 증착시켜 유기박막트랜지스터를 제조하였다. In order to deposit the organic semiconductor, pentacene, a P-type organic semiconductor, was placed in a vacuum chamber, and then sublimed by applying a heat of 200 ° C. at 10 −6 torr and then applied to a thickness of 30 to 70 nm. After applying PMMA to the thickness of 200 nm by spin coating, an organic thin film transistor was manufactured by depositing a gate electrode having a thickness of 60 nm using Al only in the channel region of the transistor using a shadow mask.
[실시예 2: 전자 및 정공주입성능이 향상된 금속산화막반도체(CMOS) 디지털 회로의 제조]Example 2 Fabrication of Metal Oxide Semiconductor (CMOS) Digital Circuit with Improved Electron and Hole Injection Performance
실시예 1과 동일하게 실시하되, 기판위에 포토리소그라피 공정을 통해서 도 11에 해당하는 패턴을 형성하여 금속산화막반도체(CMOS)디지털 회로를 제조하였다. In the same manner as in Example 1, a metal oxide semiconductor (CMOS) digital circuit was manufactured by forming a pattern corresponding to FIG. 11 through a photolithography process on a substrate.
[실시예 3; 전자 및 정공주입성능이 향상된 양극성 트랜지스터의 제조][Example 3; Fabrication of Bipolar Transistors with Improved Electron and Hole Injection Performance]
실시예 1과 동일하게 실시하되, 양극성을 지닌 유기반도체 재료인 poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT)를 도포하여 OTFT를 제조하였다. In the same manner as in Example 1, OTFT was prepared by applying poly (9,9-dioctylfluorene-co-benzothiadiazole) (F8BT), an organic semiconductor material having bipolarity.
[실시예 4: 전자 및 정공주입성능이 향상된 유기발광소자의 제조]Example 4 Fabrication of Organic Light Emitting Diode Improved in Electron and Hole Injection Performance
실시예 1과 동일하게 실시하되, 발광특성이 우수한 양극성 유기반도체 재료인 poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT)를 도포하여 OTFT를 제조하였다.OTFT was prepared in the same manner as in Example 1 by applying poly (9,9-dioctylfluorene-co-benzothiadiazole) (F8BT), a bipolar organic semiconductor material having excellent luminescence properties.
없음none
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Claims (20)

  1. 기판;Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극위에만 인쇄공정을 통해서 국부적으로 도포된 전자 혹은 정공주입층;An electron or hole injection layer applied locally only on the source / drain electrodes through a printing process;
    상기 전자 혹은 정공주입층을 포함하는 기판 상에 위치하는 유기반도체층;을 포함하는 것을 특징으로 하는 유기박막트랜지스터.An organic thin film transistor comprising: an organic semiconductor layer positioned on a substrate including the electron or hole injection layer.
  2. 기판; Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극 중 어느 하나에만 도포된 전자주입층;An electron injection layer applied to only one of the source / drain electrodes;
    상기 전자주입층을 포함하는 기판 상에 위치하는 유기반도체층;을 포함하는 것을 특징으로 하는 유기박막트랜지스터.An organic thin film transistor comprising: an organic semiconductor layer positioned on a substrate including the electron injection layer.
  3. 기판; Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극 중 어느 하나에만 도포된 정공주입층;A hole injection layer applied only to one of the source / drain electrodes;
    상기 전자주입층을 포함하는 기판 상에 위치하는 유기반도체층;을 포함하는 것을 특징으로 하는 유기박막트랜지스터.An organic thin film transistor comprising: an organic semiconductor layer positioned on a substrate including the electron injection layer.
  4. 제 1항 또는 제 3항 중 어느 하나의 항에 있어서The method according to any one of claims 1 to 3
    상기 전자주입층 또는 정공주입층은 용액공정으로 제조된 금속염인 것을 특징으로 한 유기박막트랜지스터.The electron injection layer or the hole injection layer is an organic thin film transistor, characterized in that the metal salt prepared by the solution process.
  5. 제 4항에 있어서,  The method of claim 4, wherein
    상기 전자주입층 또는 정공주입층은 그 두께가 0.1~5nm 인 것을 특징으로 한 유기박막트랜지스터. The electron injection layer or the hole injection layer is an organic thin film transistor, characterized in that the thickness of 0.1 ~ 5nm.
  6. 제 4항에 있어서, The method of claim 4, wherein
    상기 전자주입층은 Cs2CO3, CsF, Rb2CO3, K2CO3, Na2CO3, LiF, CaF2, MgF2, NaCl, MgO 중에서 선택되는 금속염이고,The electron injection layer is a metal salt selected from Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO,
    상기 유기반도체는 N-형 유기반도체인 것을 특징으로 한 유기박막트랜지스터 The organic semiconductor is an organic thin film transistor, characterized in that the N-type organic semiconductor
  7. 제 4항에 있어서, The method of claim 4, wherein
    상기 정공주입층은 V2O5, MoO3, F4TCNQ 중에서 선택되는 금속염이고,The hole injection layer is a metal salt selected from V 2 O 5, MoO 3 , F4TCNQ,
    상기 유기반도체는 P-형 유기반도체인 것을 특징으로 한 유기박막트랜지스터The organic semiconductor is an organic thin film transistor, characterized in that the P- type organic semiconductor.
  8. 기판을 제공하는 단계와; Providing a substrate;
    상기 기판 상에 게이트 전극을 형성하는 단계와;Forming a gate electrode on the substrate;
    상기 게이트 전극을 덮도록 게이트 절연막을 형성하는 단계와;Forming a gate insulating film to cover the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되게 소스/드레인 전극을 형성하는 단계와;Forming a source / drain electrode on a portion of the gate insulating layer to be spaced apart from each other;
    상기 소스/드레인 전극 중 어느 하나의 전극에만 선택적으로 전자주입층을 도포하는 단계와;Selectively applying an electron injection layer to only one of the source / drain electrodes;
    상기 전자주입층이 도포된 기판 전면에 걸쳐 유기반도체층을 형성하는 것을 특징으로 하는 유기박막트랜지스터의 제조방법.A method of manufacturing an organic thin film transistor, characterized in that to form an organic semiconductor layer over the entire substrate coated with the electron injection layer.
  9. 기판을 제공하는 단계와; Providing a substrate;
    상기 기판 상에 게이트 전극을 형성하는 단계와;Forming a gate electrode on the substrate;
    상기 게이트 전극을 덮도록 게이트 절연막을 형성하는 단계와;Forming a gate insulating film to cover the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되게 소스/드레인 전극을 형성하는 단계와;Forming a source / drain electrode on a portion of the gate insulating layer to be spaced apart from each other;
    상기 소스/드레인 전극 중 어느 하나의 전극에만 선택적으로 정공주입층을 도포하는 단계와;Selectively applying a hole injection layer to only one of the source / drain electrodes;
    상기 정공주입층이 도포된 기판 전면에 걸쳐 유기반도체층을 형성하는 것을 특징으로 하는 유기박막트랜지스터의 제조방법A method of manufacturing an organic thin film transistor, characterized in that to form an organic semiconductor layer over the entire surface of the substrate is coated with the hole injection layer
  10. 제 8항에 있어서. The method of claim 8.
    상기 전자주입층은 Cs2CO3, CsF, Rb2CO3, K2CO3, Na2CO3, LiF, CaF2, MgF2, NaCl, MgO 에서 선택되는 금속염 용액인 것을 특징으로 한 유기박막트랜지스터의 제조방법.The electron injection layer is an organic thin film, characterized in that the metal salt solution selected from Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO Method for manufacturing a transistor.
  11. 제 9항에 있어서, The method of claim 9,
    상기 정공주입층은 V2O5, MoO3, F4TCNQ 중에서 선택되는 금속염 용액인 것을 특징으로 한 유기박막트랜지스터의 제조방법.The hole injection layer is a method of manufacturing an organic thin film transistor, characterized in that the metal salt solution selected from V 2 O 5, MoO 3 , F4TCNQ.
  12. 제 8항 내지 제 9항 중 어느 하나의 항에 있어서, The method according to any one of claims 8 to 9,
    상기 전자주입층 또는 정공주입층의 도포는 패터닝 공정을 통해 이루어지는 것을 특징으로 하는 유기박막트랜지스터의 제조방법Coating of the electron injection layer or the hole injection layer is a method of manufacturing an organic thin film transistor, characterized in that made through a patterning process
  13. 제 12항에 있어서, The method of claim 12,
    상기 패터닝 공정은 금속염 용액을 인쇄하는 단계인 것을 특징으로 하는 유기박막트랜지스터의 제조방법.The patterning process is a method of manufacturing an organic thin film transistor, characterized in that for printing a metal salt solution.
  14. 제 13항에 있어서, The method of claim 13,
    상기 인쇄는 잉크젯 프린팅, 스크린 인쇄, 스프레이 코팅, 그라비아 프린팅, 그라비아 옵셋 프린팅, 리버스 그라비아 옵셋 프린팅, 노즐프린팅, 패드 프린팅 중에서 선택되는 것을 특징으로 한 유기박막트랜지스터의 제조방법.The printing method of manufacturing an organic thin film transistor, characterized in that selected from inkjet printing, screen printing, spray coating, gravure printing, gravure offset printing, reverse gravure offset printing, nozzle printing, pad printing.
  15. 기판; Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극 중 어느 하나의 전극에 도포된 도포된 전자주입층;A coated electron injection layer applied to any one of the source / drain electrodes;
    상기 소스/드레인 전극 중 나머지 전극에 도포된 정공주입층;A hole injection layer applied to the remaining electrodes of the source / drain electrodes;
    상기 전자주입층의 기판 상에 위치하는 N-형 유기반도체층N-type organic semiconductor layer located on the substrate of the electron injection layer
    상기 정공주입층의 기판 상에 위치하는 P-형 유기반도체층;을 A P-type organic semiconductor layer positioned on the substrate of the hole injection layer;
    상기 N-형, P-형 유기반도체를 포함한 디지탈 회로로 구성되는 금속산화막반도체(CMOS) 디지털 회로Metal Oxide Semiconductor (CMOS) digital circuit composed of digital circuit including N-type and P-type organic semiconductor
  16. 제 15항에 있어서, The method of claim 15,
    상기 전자주입층은 상기 전자주입층은 에서 선택되는 금속염 용액이며,The electron injection layer is a metal salt solution selected from the electron injection layer,
    상기 정공주입층은 V2O5, MoO3, F4TCNQ 중에서 선택되는 금속염 용액인 것을 특징으로 한 금속산화막반도체(CMOS) 디지털 회로The hole injection layer is a metal oxide semiconductor (CMOS) digital circuit, characterized in that the metal salt solution selected from V 2 O 5, MoO 3 , F4TCNQ
  17. 기판; Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극 중 어느 하나의 전극에 도포된 도포된 전자주입층;A coated electron injection layer applied to any one of the source / drain electrodes;
    상기 소스/드레인 전극 중 나머지 전극에 도포된 정공주입층;A hole injection layer applied to the remaining electrodes of the source / drain electrodes;
    상기 전자주입층의 기판 상에 위치하는 N-형 유기반도체층N-type organic semiconductor layer located on the substrate of the electron injection layer
    상기 정공주입층의 기판 상에 위치하는 P-형 유기반도체층;을 포함하는 것을 특징으로 하는 전자 및 정공 주입성능이 향상된 양극성 유기박막트랜지스터A bipolar organic thin film transistor having improved electron and hole injection performance, comprising: a P-type organic semiconductor layer positioned on a substrate of the hole injection layer
  18. 제 17항에 있어서, The method of claim 17,
    상기 전자주입층은 상기 전자주입층은 Cs2CO3, CsF, Rb2CO3, K2CO3, Na2CO3, LiF, CaF2, MgF2, NaCl, MgO 에서 선택되는 금속염 용액이며,The electron injection layer is a metal salt solution selected from Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO,
    상기 정공주입층은 V2O5, MoO3, F4TCNQ 중에서 선택되는 금속염 용액인 것을 특징으로 한 전자 및 정공 주입성능이 향상된 양극성 유기박막트랜지스터The hole injection layer is a bipolar organic thin film transistor with improved electron and hole injection performance, characterized in that the metal salt solution selected from V 2 O 5, MoO 3 , F4TCNQ.
  19. 기판; Board;
    상기 기판 상에 위치한 게이트 전극;A gate electrode located on the substrate;
    상기 게이트 전극을 포함하는 기판 전면에 걸쳐 위치한 게이트 절연막;A gate insulating film disposed over the entire surface of the substrate including the gate electrode;
    상기 게이트 절연막 상의 일부 영역에 서로 이격되어 위치하는 소스/드레인 전극;Source / drain electrodes spaced apart from each other in a portion of the gate insulating layer;
    상기 소스/드레인 전극 중 어느 하나의 전극에 도포된 도포된 전자주입층;A coated electron injection layer applied to any one of the source / drain electrodes;
    상기 소스/드레인 전극 중 나머지 전극에 도포된 정공주입층;A hole injection layer applied to the remaining electrodes of the source / drain electrodes;
    상기 전자주입층의 기판 상에 위치하는 N-형 유기반도체층N-type organic semiconductor layer located on the substrate of the electron injection layer
    상기 정공주입층의 기판 상에 위치하는 P-형 유기반도체층;을 포함하는 것을 특징으로 하는 전자 및 정공 주입성능이 향상된 유기발광트랜지스터P-type organic semiconductor layer positioned on the substrate of the hole injection layer; characterized in that the organic light emitting transistor with improved electron and hole injection performance
  20. 제 19항에 있어서, The method of claim 19,
    상기 전자주입층은 상기 전자주입층은 Cs2CO3, CsF, Rb2CO3, K2CO3, Na2CO3, LiF, CaF2, MgF2, NaCl, MgO 에서 선택되는 금속염 용액이며,The electron injection layer is a metal salt solution selected from Cs 2 CO 3 , CsF, Rb 2 CO 3 , K 2 CO 3 , Na 2 CO 3 , LiF, CaF 2 , MgF 2 , NaCl, MgO,
    상기 정공주입층은 V2O5, MoO3, F4TCNQ 중에서 선택되는 금속염 용액인 것을 특징으로 한 전자 및 정공 주입성능이 향상된 유기발광트랜지스터The hole injection layer is an organic light emitting transistor with improved electron and hole injection performance, characterized in that the metal salt solution selected from V 2 O 5, MoO 3 , F4TCNQ
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