WO2016148395A1 - Dispositif de mémoire - Google Patents

Dispositif de mémoire Download PDF

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Publication number
WO2016148395A1
WO2016148395A1 PCT/KR2016/001137 KR2016001137W WO2016148395A1 WO 2016148395 A1 WO2016148395 A1 WO 2016148395A1 KR 2016001137 W KR2016001137 W KR 2016001137W WO 2016148395 A1 WO2016148395 A1 WO 2016148395A1
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WIPO (PCT)
Prior art keywords
layer
magnetic
magnetization
memory device
capping
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PCT/KR2016/001137
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English (en)
Korean (ko)
Inventor
박재근
이두영
Original Assignee
한양대학교 산학협력단
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Priority claimed from KR1020150045174A external-priority patent/KR101698532B1/ko
Application filed by 한양대학교 산학협력단 filed Critical 한양대학교 산학협력단
Priority to CN201680016463.4A priority Critical patent/CN107710433B/zh
Publication of WO2016148395A1 publication Critical patent/WO2016148395A1/fr
Priority to US15/707,491 priority patent/US10580964B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

Definitions

  • the present invention relates to a memory device, and more particularly to a magnetic memory device using a magnetic tunnel junction (MTJ).
  • MTJ magnetic tunnel junction
  • next-generation nonvolatile memory devices which consume less power and have higher integration than flash memory devices.
  • Such next-generation nonvolatile memory devices include phase change RAM (PRAM) using a state change of a phase change material such as a chalcogenide alloy, and a magnetic tunnel junction according to the magnetization state of a ferromagnetic material.
  • PRAM phase change RAM
  • MRAM Magnetic RAM
  • Ferroelectric memory using polarization of ferroelectric material
  • ReRAM Resistance change RAM
  • STT-MRAM Spin-Transfer Torque Magnetic Random Access Memory
  • STT-MRAM devices each include a pinned layer and a free layer formed of ferromagnetic material, and a magnetic tunnel junction having a tunnel barrier formed therebetween.
  • the magnetic tunnel junction has a low resistance state because the magnetization directions of the free layer and the pinned layer are the same (i.e., parallel), so that the current flows easily. Indicates the resistance state.
  • the magnetization direction should change only in the direction perpendicular to the substrate, so the free layer and the pinned layer should have the vertical magnetization value.
  • STT-MRAM devices can theoretically cycle beyond 10 15 and can switch at as fast as nanoseconds.
  • the vertical magnetization type STT-MRAM device has no scaling limit in theory, and research is being actively conducted as a next-generation memory device that can replace the DRAM device due to the advantage that the current density of the driving current can be lowered as the scaling progresses. Is going on. Meanwhile, an example of the STT-MRAM device is shown in Korean Patent Registration No. 10-1040163.
  • a seed layer is formed below the free layer, a capping layer is formed on the fixed layer, and a synthetic exchange diamagnetic layer and an upper electrode are formed on the capping layer.
  • a silicon oxide film is formed on a silicon substrate, and a seed layer and a magnetic tunnel junction are formed thereon.
  • a selection element such as a transistor may be formed on the silicon substrate, and the silicon oxide film may be formed to cover the selection element.
  • the STT-MRAM device has a stacked structure of a silicon oxide film, a seed layer, a free layer, a tunnel barrier, a pinned layer, a capping layer, a synthetic exchange diamagnetic layer, and an upper electrode on a silicon substrate on which the selection element is formed.
  • the seed layer and the capping layer are formed using tantalum (Ta)
  • the synthetic exchange diamagnetic layer has a structure in which a lower magnetic layer and an upper magnetic layer in which magnetic metals and nonmagnetic metals are alternately stacked, and a nonmagnetic layer are formed therebetween.
  • magnetic tunnel junctions are based on SiO 2 or MgO substrates, and do not have a bottom electrode, or a structure using a Ta / Ru bottom electrode.
  • a capacitor in order to implement an STT-MRAM device, a capacitor must be replaced by a magnetic tunnel junction in a 1T1C structure of a conventional DRAM.
  • a lower electrode must be formed using materials for reducing transistor resistance and preventing metal diffusion.
  • magnetic tunnel junctions fabricated using conventional SiO 2 or MgO substrates are not directly applicable to memory fabrication in consideration of their incorporation into actual cell transistors.
  • the material of the synthetic exchange diamagnetic layer may diffuse into the tunnel barrier of the magnetic tunnel junction to worsen the bcc (100) crystal of the magnetic tunnel junction. . Therefore, the magnetization direction of the magnetic tunnel junction cannot be changed rapidly, which may cause a problem that the operation speed of the memory is lowered or does not operate.
  • the present invention provides a memory device capable of improving the crystallinity of a magnetic tunnel junction and thereby rapidly changing the magnetization direction.
  • the present invention provides a memory device capable of improving the crystallinity of a magnetic tunnel junction by preventing the material of the synthetic exchange diamagnetic layer from diffusing into the magnetic tunnel junction.
  • a lower electrode, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, a synthetic exchange diamagnetic layer, and an upper electrode are stacked on a substrate, and the capping layer is formed of at least two layers. do.
  • the lower electrode is made of a polycrystalline conductive material.
  • the semiconductor device may further include a buffer layer formed between the lower electrode and the seed layer and formed of a material including tantalum.
  • the free layer includes a first magnetization layer having a horizontal magnetization, a separation layer having no magnetization, and a second magnetization layer having a vertical magnetization.
  • the first and second free layers are formed of a material including CoFeB, and the first free layer is formed thicker than the second free layer.
  • the capping layer is formed of a material in which a first capping layer adjacent to the magnetic tunnel junction is formed of a material of a bcc structure, and a second capping layer adjacent to the synthetic exchange diamagnetic layer prevents the bottom diffusion of the synthetic exchange diamagnetic layer material. do.
  • the first capping layer is formed of W, and the second capping layer is formed of Ta.
  • the synthetic exchange diamagnetic layer is formed of a laminated structure of a first magnetic layer, a nonmagnetic layer, and a second magnetic layer, and the first and second magnetic layers are formed of a material including Pt.
  • the first magnetic layer is formed of a single layer of Co / Pt
  • the second magnetic layer is formed of a multilayer structure in which Co / Pt is stacked at least twice.
  • the embodiment of the present invention can be applied to an actual memory process using 1T1M (1 transistor and 1 MTJ), which is a basic structure of STT-MRAM, using a lower electrode using a polycrystalline conductive material.
  • 1T1M (1 transistor and 1 MTJ)
  • a seed layer of polycrystal on the lower electrode, an amorphous magnetic tunnel junction formed thereon is formed along the crystal structure of the seed layer, and then has a more improved crystal structure by heat treatment. Therefore, the change in the magnetization direction of the magnetic tunnel junction can be made drastically, and the operation speed can be increased.
  • the diffusion of the synthetic exchange diamagnetic layer can be prevented and the bcc of the fixed layer can be maintained, so that the characteristics are not degraded even after the subsequent heat treatment process. Therefore, the magnetization direction of the magnetic tunnel junction can be changed drastically, and the operation speed of the memory can be improved.
  • FIG. 1 is a cross-sectional view of a memory device according to an exemplary embodiment of the present invention.
  • 2 and 3 are graphs of magnetic characteristics according to temperature of a memory device according to a conventional example.
  • 4 and 5 are graphs of magnetic characteristics according to temperature of a memory device according to an exemplary embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a memory device according to an exemplary embodiment of the present invention, and a cross-sectional view of an STT-MRAM device.
  • a memory device may include a lower electrode 110, a buffer layer 120, a seed layer 130, a free layer 140, and a tunnel barrier formed on a substrate 100.
  • 150 a pinned layer 160, a capping layer 170, a synthetic exchange diamagnetic layer 180, and an upper electrode 190.
  • the free layer 140, the tunnel barrier 150, and the pinned layer 160 form a magnetic tunnel junction.
  • the free layer 140, the tunnel barrier 150, and the pinned layer 160 may form a magnetic tunnel junction
  • the capping layer 170 may include first and second capping layers 172 and 174.
  • the substrate 100 may use a semiconductor substrate.
  • the substrate 100 may use a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a silicon oxide substrate, or the like.
  • a silicon substrate is used.
  • a selection device including a transistor may be formed on the substrate 100.
  • An insulating layer 105 may be formed on the substrate 100. That is, the insulating layer 105 may be formed to cover a predetermined structure such as a selection device, and a contact hole exposing at least a portion of the selection device may be formed in the insulating layer 105.
  • the insulating layer 105 may be formed using an amorphous silicon oxide film (SiO 2 ) or the like.
  • the lower electrode 110 is formed on the insulating layer 105.
  • the lower electrode 110 may be formed using a conductive material such as metal or metal nitride.
  • the lower electrode 110 of the present invention may be formed of at least one layer.
  • the lower electrode 110 may be formed on the insulating layer 105, or may be formed inside the insulating layer 105.
  • the lower electrode 110 may be formed in or on the insulating layer 105 to be connected to the selection element formed on the substrate 100.
  • the lower electrode 110 may be formed of a polycrystal material. That is, the lower electrode 110 may be formed of a conductive material having a bcc structure.
  • the lower electrode 110 may be formed of a metal nitride such as titanium nitride (TiN).
  • TiN titanium nitride
  • the lower electrode 110 may be formed of at least two layers including titanium nitride.
  • the lower electrode 110 may be formed of a stacked structure of a metal nitride such as titanium nitride and a metal such as tungsten (W). That is, when the lower electrode 110 is formed in a double structure, tungsten may be formed on the insulating layer 105, and titanium nitride may be formed on tungsten.
  • the buffer layer 120 is formed on the lower electrode 110.
  • the buffer layer 120 may be formed of a material having excellent conformity with the lower electrode 110 in order to resolve the lattice constant mismatch between the lower electrode 110 and the seed layer 130.
  • the buffer layer 120 may be formed using tantalum (Ta) having excellent lattice matching with TiN.
  • Ta tantalum
  • Ta is amorphous, but since the lower electrode 110 is polycrystalline, the amorphous buffer layer 120 may be grown along the crystal direction of the polycrystalline lower electrode 110, and then the crystallinity may be improved by heat treatment. have.
  • the buffer layer 120 may be formed to have a thickness of, for example, 2 nm to 10 nm.
  • the seed layer 130 is formed on the buffer layer 120.
  • the seed layer 130 is formed of a polycrystalline material, for example, a conductive material having a bcc structure.
  • the seed layer 130 may be formed of tungsten (W).
  • W tungsten
  • the crystallinity of the magnetic tunnel junction including the free layer 140, the tunnel barrier 150, and the pinned layer 160 formed thereon may be improved. That is, when the polycrystalline seed layer 130 is formed, an amorphous magnetic tunnel junction formed on the top thereof is grown along the crystal direction of the seed layer 130, and when the heat treatment is performed for vertical magnetic anisotropy, the magnetic tunnel junction is formed. Crystallinity can be improved than before.
  • crystallization is performed after a high temperature heat treatment of 400 ° C. or higher, for example, 400 ° C. to 500 ° C., so that the buffer layer material, the capping layer material, or the synthetic exchange diamagnetic layer material into the tunnel barrier 150.
  • a high temperature heat treatment 400 ° C. or higher, for example, 400 ° C. to 500 ° C.
  • the buffer layer material, the capping layer material, or the synthetic exchange diamagnetic layer material into the tunnel barrier 150.
  • the seed layer 130 may be formed to have a thickness of, for example, 1 nm to 3 nm.
  • the free layer 140 is formed on the seed layer 130 and is formed of a ferromagnetic material.
  • the free layer 140 may be changed from one direction to another direction in which magnetization is not fixed in one direction. That is, the free layer 140 may have the same magnetization direction as that of the pinned layer 160 (ie, parallel), or may be opposite (ie, anti-parallel).
  • the magnetic tunnel junction may be used as a memory device by mapping information of '0' or '1' to resistance values that vary depending on the magnetization arrangement of the free layer 140 and the pinned layer 160. For example, when the magnetization direction of the free layer 140 is parallel to the pinned layer 160, the resistance value of the magnetic tunnel junction becomes small, and this case may be defined as data '0'.
  • the free layer 140 may be formed by alternately stacking a full-heusler semimetal alloy, an amorphous rare earth element alloy, a ferromagnetic metal, and a nonmagnetic metal. It can be formed using a ferromagnetic material such as a multilayer thin film, an alloy having an L10 type crystal structure, or a cobalt-based alloy.
  • the full-heussler semimetal-based alloys include CoFeAl, CoFeAlSi and the like, and amorphous rare earth element alloys include alloys such as TbFe, TbCo, TbFeCo, DyTbFeCo, and GdTbCo.
  • amorphous rare earth element alloys include alloys such as TbFe, TbCo, TbFeCo, DyTbFeCo, and GdTbCo.
  • the alloy having a L10 type crystal structure includes Fe 50 Pt 50, Fe 50 Pd 50, Co 50 Pt 50, Fe 30 Ni 20 Pt 50, Co 30 Ni 20 Pt 50, and the like.
  • Cobalt-based alloys include CoCr, CoPt, CoCrPt, CoCrTa, CoCrPtTa, CoCrNb, CoFeB and the like.
  • the CoFeB single layer may be formed thicker than the multilayer structure of CoFeB and Co / Pt or Co / Pd, thereby increasing the magnetoresistance ratio.
  • CoFeB is easier to etch than a metal such as Pt or Pd
  • a CoFeB single layer is easier to manufacture than a multilayer structure containing Pt or Pd.
  • CoFeB may have horizontal magnetization as well as vertical magnetization by adjusting the thickness.
  • an embodiment of the present invention forms a pinned layer 160 using a CoFeB monolayer, and CoFeB is formed into an amorphous and then textured into the BCC 100 by heat treatment.
  • the free layer 140 may be formed in a stacked structure of a first free layer, a separation layer, and a second free layer.
  • the first and second free layers may have magnetizations in the same direction and may have magnetizations in different directions.
  • the first and second free layers may each have a vertical magnetization
  • the first free layer may have a horizontal magnetization
  • the second free layer may have a vertical magnetization
  • the separation layer may be formed of a material having a bcc structure having no magnetization. That is, the first free layer may be magnetized vertically, the separation layer may not be magnetized, and the second free layer may be magnetized vertically or horizontally.
  • the switching energy can be lowered through the magnetic resonance of the first and second free layers.
  • the switching energy of the free layer 140 may be lowered by magnetic resonance with the first free layer of horizontal magnetization.
  • the first and second free layers are each formed of CoFeB, and the first free layer is formed thicker than the second free layer.
  • the first free layer is formed with a thickness of 1 nm to 4 nm using CoFeB
  • the second free layer is formed with a thickness of 0.8 nm to 1.2 nm using CoFeB
  • the separation layer has a bcc structure.
  • the material can be formed to a thickness of 0.4 nm to 2 nm.
  • the tunnel barrier 150 is formed on the free layer 140 to separate the free layer 140 and the pinned layer 160.
  • Tunnel barrier 150 enables quantum mechanical tunneling between free layer 140 and pinned layer 160.
  • the tunnel barrier 150 may include magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), tantalum oxide (Ta 2 O 5 ), silicon nitride (SiNx), aluminum nitride (AlNx), or the like. It can be formed as.
  • polycrystalline magnesium oxide is used as the tunnel barrier 150. The magnesium oxide is then textured into bcc 100 by heat treatment.
  • the pinned layer 160 is formed on the tunnel barrier 150.
  • the pinned layer 160 is fixed in one direction in a magnetic field within a predetermined range, and may be formed of a ferromagnetic material.
  • magnetization may be fixed in a direction from top to bottom.
  • the pinned layer 160 has, for example, a full-heusler semimetal alloy, an amorphous rare earth element alloy, a multilayer thin film in which magnetic metals and nonmagnetic metals are alternately stacked, or an L10 type crystal structure. It may be formed of a ferromagnetic material such as an alloy. In this case, the pinned layer 160 may be formed of the same ferromagnetic material as the free layer 140.
  • the capping layer 170 is formed on the pinned layer 160 to magnetically separate the pinned layer 160 and the synthetic exchange diamagnetic layer 180 from each other. As the capping layer 170 is formed, the magnetization of the synthetic exchange diamagnetic layer 180 and the pinned layer 160 is generated independently of each other. In addition, the capping layer 170 may be formed in consideration of the magnetoresistance ratio of the free layer 140 and the pinned layer 160 for the operation of the magnetic tunnel junction. The capping layer 170 maintains the bcc crystal structure from the seed layer 130 to the pinned layer 160 while allowing the synthetic exchange diamagnetic layer 180 to grow crystals and the material of the synthetic exchange diamagnetic layer 180. It may be formed of a material for preventing the diffusion.
  • the capping layer 170 may include a first capping layer 172 under the capping layer 170, and a first and second magnetic layers 181 and 183 of the synthetic exchange diamagnetic layer 180.
  • a second capping layer 174 is provided to allow growth in the desired crystal direction and to prevent the material of the synthetic exchange diamagnetic layer 180 from diffusing.
  • the first capping layer 172 may be formed of a conductive material having a bcc structure. For example, tungsten (W) may be used.
  • the second capping layer 174 is formed such that the first and second magnetic layers 181 and 183 of the synthetic exchange diamagnetic layer 180 are oriented in the (111) direction or hexagon of, for example, a face centered cubic (FCC).
  • FCC face centered cubic
  • the second capping layer 174 may include tantalum (Ta), ruthenium (Ru), titanium (Ti), palladium (Pd), platinum (Pt), magnesium (Mg), cobalt (Co), and aluminum (Al). It may include a metal selected from the group consisting of) or alloys thereof, preferably tantalum may be used.
  • the first capping layer 172 may be formed to a thickness of 0.2 nm to 0.5 nm
  • the second capping layer 174 may be formed to a thickness of 0.2 nm to 1 nm.
  • the magnetization direction of the pinned layer 160 is fixed only when the first magnetic layer 181 of the pinned layer 160 and the synthetic exchange diamagnetic layer 180 is ferrocoupled, but the second capping layer 174 is 1.
  • the thickness is formed to be greater than or equal to nm
  • the magnetization direction of the pinned layer 160 is not fixed due to an increase in the thickness of the capping layer 170, and has the same magnetization direction as that of the free layer 150. It does not occur and does not operate as a memory.
  • the synthetic exchange diamagnetic layer 180 is formed on the capping layer 170.
  • the synthetic exchange diamagnetic layer 180 serves to fix the magnetization of the pinned layer 160.
  • the synthetic exchange diamagnetic layer 180 includes a first magnetic layer 181, a nonmagnetic layer 182, and a second magnetic layer 183. That is, in the synthetic exchange diamagnetic layer 180, the first magnetic layer 181 and the second magnetic layer 183 are antiferromagnetically coupled to each other through the nonmagnetic layer 182. At this time, the magnetization directions of the first magnetic layer 181 and the second magnetic layer 183 are antiparallel to each other.
  • the first magnetic layer 181 may be magnetized in an upward direction (ie, the upper electrode 190 direction), and the second magnetic layer 183 may be magnetized in a downward direction (ie, the magnetic tunnel junction direction).
  • the first magnetic layer 181 and the second magnetic layer 183 may have a structure in which magnetic metals and nonmagnetic metals are alternately stacked.
  • a magnetic metal a single metal or an alloy thereof selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), and the like may be used, and chromium (Cr), platinum (Pt), palladium as a nonmagnetic metal may be used.
  • a single metal or alloy thereof selected from the group consisting of (Pd), iridium (Ir), rhodium (Rh), ruthenium (Ru), osmium (Os), rhenium (Re), gold (Au) and copper (Cu) can be used.
  • the first magnetic layer 181 and the second magnetic layer 183 may be formed of [Co / Pd] n, [Co / Pt] n or [CoFe / Pt] n (where n is an integer of 1 or more).
  • the second magnetic layer 183 may be formed thicker than the first magnetic layer 181.
  • a second buffer layer (not shown) may be formed between the capping layer 170 and the first magnetic layer 181.
  • the second buffer layer is formed to solve the lattice constant mismatch between the capping layer 170 and the first magnetic layer 181, and may be formed of the same material as the first magnetic layer 181, for example.
  • the second buffer layer may be formed of a single layer in which Co and Pt are stacked.
  • the first magnetic layer 181 may be formed of a single layer
  • the second magnetic layer 183 may be formed of a plurality of layers.
  • the first magnetic layer 181 may be formed of a single stacked structure, that is, a magnetic metal and a nonmagnetic metal
  • the second magnetic layer 183 may be a structure in which a magnetic metal and a nonmagnetic metal are repeatedly stacked a plurality of times. It can be formed as.
  • the nonmagnetic layer 182 is formed between the first magnetic layer 181 and the first magnetic layer 183, and is a nonmagnetic material for allowing the first magnetic layer 181 and the second magnetic layer 183 to perform semimagnetic coupling. Is formed.
  • the nonmagnetic layer 182 may be formed of a single or alloy thereof selected from the group consisting of ruthenium (Ru), rhodium (Rh), osmium (Os), rhenium (Re), and chromium (Cr).
  • ruthenium ruthenium
  • Rh rhodium
  • Os osmium
  • Re rhenium
  • Cr chromium
  • the upper electrode 190 is formed on the synthetic exchange diamagnetic layer 180.
  • the upper electrode 180 may be formed using a conductive material, and may be formed of metal, metal oxide, metal nitride, or the like.
  • the upper electrode 170 is a single selected from the group consisting of tantalum (Ta), ruthenium (Ru), titanium (Ti), palladium (Pd), platinum (Pt), magnesium (Mg) and aluminum (Al). It may be formed of a metal or an alloy thereof.
  • the memory device forms the lower electrode 110 using a polycrystalline conductive material, for example, TiN, to 1T1M (1 transistor and 1 MTJ), which is a basic structure of the STT-MRAM. It is possible to apply to the actual memory process.
  • the magnetic tunnel junction is formed by forming the capping layer 170 between the magnetic tunnel junction and the synthetic exchange diamagnetic layer 180 in at least a double structure, and forming the lower first capping layer 172 with a material having a bcc structure.
  • the upper second capping layer 174 is formed of a material that prevents the diffusion of the material of the synthetic exchange diamagnetic layer 180. Therefore, even after the subsequent heat treatment process, diffusion of the synthetic exchange diamagnetic layer material into the magnetic tunnel junction can be prevented, so that the magnetic tunnel junction can maintain the bcc structure, thereby maintaining the characteristics of the memory device.
  • FIGS. 4 and 5 are magnetization graphs of a magnetic tunnel junction using a double capping layer of the present invention.
  • 2 and 4 are magnetization graphs of the magnetic tunnel junction after 350 ° C. heat treatment
  • FIGS. 3 and 5 are magnetization graphs of the magnetic tunnel junction after 400 ° C. heat treatment. That is, a SiO 2 insulating layer, a TiN lower electrode, a Ta buffer layer, a W seed layer, a CoFeB free layer, an MgO tunnel barrier, and a CoFeB fixed layer were stacked on a silicon substrate, and in the conventional case, a bcc capping layer was formed as a single layer. In the case of the invention, a double structure of a bcc first capping layer and a Ta second capping layer was formed. And, after heat treatment at 350 °C and 400 °C each magnetization characteristics were specified.
  • the difference between the sum of the magnetizations of the pinned layer and the first magnetic layer and that of the second magnetic layer is similar as 80uemu after heat treatment at 350 ° C. as shown in FIGS. 2 and 4.
  • the difference between the sum of the magnetizations of the pinned layer and the first magnetic layer and the magnetization of the second magnetic layer is conventionally -30uemu as shown in FIG. 3, and the present invention is shown in FIG. 5. 60uemu.
  • the difference in the degree of magnetization as shown in FIGS. 2 and 3, and FIGS. 4 and 5 indicates the extent to which the magnetization of the fixed layer is degraded by the material diffusion of the synthetic exchange semi-magnetic layer.
  • the difference between 350 ° C. and 400 ° C. is 110uemu, which is similar to the magnetization degree of the fixed layer.
  • the degree of degradation is less than when using a single capping layer to the extent. Therefore, in the case of the present invention, even if the heat treatment temperature is increased, it can be seen that the synthetic exchange diamagnetic layer material can prevent diffusion into the magnetic tunnel junction, thereby preventing deterioration of characteristics of the memory device.

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  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne un dispositif de mémoire dans lequel une électrode inférieure, une couche tampon, une couche germe, une jonction tunnel magnétique, une couche de recouvrement, une couche diamagnétique d'échange composite et une électrode supérieure sont empilées sur un substrat, la couche de recouvrement comprenant au moins deux couches.
PCT/KR2016/001137 2015-03-18 2016-02-02 Dispositif de mémoire WO2016148395A1 (fr)

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Application Number Priority Date Filing Date Title
CN201680016463.4A CN107710433B (zh) 2015-03-18 2016-02-02 存储器件
US15/707,491 US10580964B2 (en) 2015-03-18 2017-09-18 Memory device

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KR20150037234 2015-03-18
KR10-2015-0037234 2015-03-18
KR10-2015-0045174 2015-03-31
KR1020150045174A KR101698532B1 (ko) 2015-03-18 2015-03-31 메모리 소자

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Cited By (1)

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KR20200050382A (ko) * 2018-10-31 2020-05-11 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 랜덤 액세스 메모리

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KR20140011138A (ko) * 2012-07-17 2014-01-28 삼성전자주식회사 자기 소자 및 그 제조 방법
KR20140025165A (ko) * 2012-08-21 2014-03-04 삼성전자주식회사 자기 메모리 소자의 제조 방법
KR20150015602A (ko) * 2013-07-31 2015-02-11 한양대학교 산학협력단 메모리 소자

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200050382A (ko) * 2018-10-31 2020-05-11 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 랜덤 액세스 메모리
KR102427526B1 (ko) * 2018-10-31 2022-08-01 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 랜덤 액세스 메모리

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