WO2016145936A1

WO2016145936A1 - Flip multi-junction solar cell and preparation method thereof

Info

Publication number: WO2016145936A1
Application number: PCT/CN2016/070463
Authority: WO
Inventors: 毕京锋; 陈文浚; 林桂江; 李森林; 刘冠洲; 宋明辉; 王笃祥
Original assignee: 天津三安光电有限公司
Priority date: 2015-03-16
Filing date: 2016-01-08
Publication date: 2016-09-22
Also published as: CN104659158A

Abstract

A flip multi-junction solar cell and a preparation method thereof, the method includes steps: (1) providing a growth substrate for epitaxy growth of a semiconductor material; (2) putting the growth substrate into an MOCVD equipment, and flip growing a first epitaxy structure, which includes a multi-junction sub-cell laminated layer, over the substrate using an MOCVD method; (3) transferring the grown structure into an MBE equipment, flip growing a second epitaxy structure, which includes at least one junction sub-cell, on the grown structure using an MBE method, and forming a flip multi-junction solar cell in series; the band gap of the first epitaxy structure is greater than the band gap of the second epitaxy structure.

Description

Flip-chip multi-junction solar cell and preparation method thereof

[0001] The present invention relates to a lattice matched flip-chip multi-junction solar cell and a method of fabricating the same, and belongs to the field of semiconductor material technology.

Background technique

[0002] In recent years, concentrating multi-junction compound solar cells, which are third-generation photovoltaic power generation technologies, have attracted much attention due to their high photoelectric conversion efficiency. The traditional GalnP/GaAs/Ge triple junction solar cell does not match the short-circuit current of the top cell of InGaP and GaAs because the Ge bottom cell absorbs too much low-energy photons, so the conventional GalnP/GaAs/Ge triple junction solar cell structure It is not a combination of efficiency optimization. Chinese patent literature

CN201010193582.1 discloses a flip-chip growth method in which the length of the MR is lattice matched to the substrate GaAs. . ₅ 0&. ^ and 0-8 top cell, and then through the gradient buffer layer (InGaP, ΙηΑΙΡ or InGaAs) transition to InGaAs bottom cell and subsequent substrate stripping, new substrate bonding and other processes are gradually implemented to achieve the full structure of the entire battery . The advantage of this technology is that it can effectively reduce the dislocation density, and the stripped substrate can be recycled, which reduces the cost. The main technical difficulty is that the whole manufacturing process: overcome nm ₀ ₃ Ga from the GaAs lattice constant of 0.5653 to In.. ₇ As lattice constant 0.5775 nm transition 吋 produces a lattice mismatch of 2.15%, which is the growth of the heterojunction gradient buffer layer; and the formation of threading dislocations will inevitably occur during the growth process, these dislocations will form Composite center, reducing battery efficiency.

[0003] A GalnNAsSb quaternary nitrogen-based material that uses molecular beam epitaxy (MBE) growth and lattice matching of a GaAs substrate is disclosed in US Patent Publication No. 20110232730A1, which is incorporated herein by reference. As an ultra-high vacuum crystal growth method, MBE has not been as productive as metal organic chemical vapor deposition (MOCVD) in industrialization. Traditional MBE epitaxial growth, in order to ensure uniform structure, generally uses single-piece epitaxy, the diameter of the single source source limits the mass production capacity, while MOCVD uses vapor deposition, the reaction chamber is large, taking Vee _CO E475 as an example, single furnace (mn It can be epitaxially grown from 15 to 16 pieces, and its mass production capacity is one order higher than MBE. Even industrial grade MBE is far less productive than MOCVD. technical problem

[0004] The present invention discloses a lattice matched flip-chip multi-junction solar cell and a method of fabricating the same, which first adopts M The OCVD device performs epitaxial growth of the wide bandgap cell, and then uses MBE to grow the epitaxial structure of the narrow bandgap subcell, thereby obtaining a high efficiency flip-chip multi-junction solar cell.

Problem solution

Technical solution

[0005] A specific technical solution of the present invention is: a method for fabricating a flip-chip multi-junction solar cell, comprising the steps of: (1) providing a growth substrate for epitaxial growth of a semiconductor material; (2) using the growth substrate Placed in a M OCVD apparatus, flip-grown the first epitaxial structure over the substrate by MOCVD, having a multi-junction cell stack; (3) transferring the above-described growth-completed structure to the MBE device, using the MBE method Forming a second epitaxial structure thereon, comprising at least one junction cell, forming a series flip-chip multi-junction solar cell; wherein the band gap of the first epitaxial structure is larger than the band gap of the second epitaxial structure.

[0006] A flip-chip multijunction solar cell obtained by the method is prepared, wherein a lattice constant of the first epitaxial structure matches a lattice constant of the second epitaxial structure.

[0007] Preferably, the first epitaxial structure formed in the step (2) further includes a transfer isolation layer formed on a top surface thereof, and the transfer isolation layer is removed before the step (3) is performed. After cleaning, polishing to a directly epitaxial state (Epi-ready state), then immediately transfer the above structure to the MBE device for step (3). In some preferred embodiments, the step (2) includes the following sub-steps: forming an etch-off layer on the growth substrate; flip-chip growth with a wide band gap by MOCVD method over the etch-off layer a multi-junction cell stack for absorbing short-wavelength sunlight; forming a transfer isolation layer on the wide-bandgap multi-junction cell; after completing step (2), removing the transfer isolation layer by etching with a selective etching solution The surface is cleaned, polished to a directly epitaxial state (Epi-ready state), and then the above structure is immediately transferred to the MBE device for step (3). The transfer isolation layer is used to perform external oxidation, vulcanization, organic pollution, impurity adsorption, and water vapor adsorption in the process of switching to different growth equipment (MBE equipment) after the first epitaxial growth, before performing the next epitaxy. It erodes away along with surface impurities, thereby protecting the underlying functional layer.

[0008] Preferably, the growth temperature of the step (2) is higher than the growth temperature of the step (3). Thus, the use of flip-chip growth avoids the effects of different substrate temperatures, forming a multi-junction solar cell raft, protecting the grown wide bandgap cell from high temperature damage. In some embodiments, the growth temperature of the MOCVD in the step (2) may be 620 to 700 ° C, and the growth temperature of the MBE in the step (3) may be 5 00~600. C.

[0009] Preferably, the method for fabricating the flip-chip multi-junction solar cell further includes the step (4): performing surface cleaning, polishing, and bonding the support substrate on the epitaxial structure of the formed flip-chip multi-junction solar cell, and removing The substrate is grown, and an electrode structure is fabricated to realize a flip-chip multi-junction solar cell.

Advantageous effects of the invention

Beneficial effect

[0010] In both MBE and MOCVD epitaxial growth techniques, the MBE method involves atomic or molecular beam strikes the substrate, and may not require too high a substrate temperature to grow at a relatively low temperature. The M OCVD method uses the organic source cracking reaction chamber to deposit and grow. The substrate temperature needs to be cracked by the organic source, and then a chemical reaction occurs for deposition, so the substrate temperature is generally high. The manufacturing method of the present invention combines the difference between the two growth methods, and uses MOCVD to grow a broadband gap cell, which has a large mass production capability, but the substrate temperature is relatively high, which is superior to the MBE-grown sub-battery, which is the overall battery structure. The original intention of flip-chip epitaxy is such that high-efficiency multi-junction solar cells with high crystal quality can be obtained, while avoiding the effects of different substrate temperatures. Compared with the full structure of a multi-junction solar cell in which the same band gap structure is epitaxially grown using MBE, the growth of a partial sub-cell by MOCVD can reduce the epitaxial cost and increase the mass production capability. Compared with the full structure of the multi-junction solar cell in which the same band gap structure is epitaxially grown by MOCVD, the respective sub-cells obtained by the fabrication method of the present invention are all lattice-matched and have high crystal quality, so that the photoelectric conversion efficiency is high.

Other features and advantages of the invention will be set forth in the description which follows, and The objectives and other advantages of the invention will be realized and attained by the <RTI

Brief description of the drawing

DRAWINGS

The drawings are intended to provide a further understanding of the invention, and are intended to be a part of the description of the invention. In addition, the drawing figures are a summary of the description and are not drawn to scale.

1 is a flow chart of a method for preparing a flip-chip multi-junction solar cell according to an embodiment of the present invention.

2 to FIG. 4 show various processes of a method for fabricating a flip-chip four-junction solar cell according to an embodiment of the present invention. In the cross-sectional view of the structure, FIG. 2 is a cross-sectional view of the structure after epitaxially growing the first epitaxial structure by using the MOCVD method, and FIG. 3 is a cross-sectional view after the second epitaxial structure is completed by the MBE method, and FIG. 4 is a cross-sectional view after the completion of the chip process. A cross-sectional view of a four-junction solar cell structure.

[0015] Each reference numeral in the figure indicates:

001: growth substrate

[0017] 002: etch-off layer

[0018] 003: ohmic contact layer

[0019] 004: supporting substrate

[0020] 101: first sub-cell window layer

[0021] 102: first sub-cell emission area

[0022] 103: first sub-cell base

[0023] 104: first sub-battery back field layer

[0024] 201: second sub-cell window layer

[0025] 202: second sub-cell emission area

203: second sub-battery base region

[0027] 204: second sub-battery back field layer

[0028] 005:

[0029] 301: third sub-cell window layer

[0030] 302: third sub-cell emission area

[0031] 303: third sub-cell base

[0032] 304: third sub-battery back field layer

[0033] 401: fourth sub-cell window layer

[0034] 402: fourth sub-cell emission area

[0035] 403: fourth sub-cell base

[0036] 404: fourth sub-battery back field layer

[0037] 501: first and second sub-cell tunneling

[0038] 502: second and third sub-cell tunneling

[0039] 502: second and third sub-cell tunneling [0040] 500: heavy miscellaneous cap layer

600: anti-reflection layer

700: front metal electrode

[0043] 800: a back metal electrode.

Embodiments of the invention

The flip-chip solar cell of the present invention and its preparation method will be described in more detail below with reference to the schematic drawings, in which a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the invention described herein. The advantageous effects of the present invention are still achieved. Therefore, the following description is to be understood as a broad understanding of the invention.

[0045] Referring to FIG. 1, a flow chart of a flip-chip multi-junction solar cell includes steps S11-S31, wherein steps S11-S13 are used to grow a first epitaxial structure by MOCVD, and steps S21-S23 are employed. The M BE method grows the second epitaxial structure, and step S31 forms a flip-chip multi-junction solar cell by using a chip process, as follows:

[0046] Step S11: epitaxially growing an etch-stop layer (ESL) and an ohmic contact layer in the MOCVD device; [0047] Step S12: epitaxially growing a functional layer of the first epitaxial structure in the MOCVD device, which contains a multi-junction cell stack Layer for absorbing short-wavelength sunlight;

[0048] Step S13: epitaxially growing a transfer isolation layer in the MCVD device to perform external oxidation, vulcanization, organic pollution, impurity adsorption, and the like in the process of switching to different growth devices (MBE devices) after the first epitaxial growth. Water vapor adsorption, etc., is etched away together with surface impurities before the next epitaxy, thereby protecting the lower functional layer;

[0049] Step S21: taking the previously processed sample out of the MOCVD device, removing the transfer isolation layer, cleaning, polishing to an Epi-ready state, and transferring to the MBE device;

[0050] Step S22: epitaxially growing a functional layer of the second epitaxial structure in the MBE device, the method comprising at least a junction cell stack, and a band gap smaller than a band gap of the first epitaxial structure for absorbing long-wavelength sunlight;

[0051] Step S23: extending the raw ohmic contact layer outside the MBE device;

[0052] Step S31: forming a flip-chip multi-junction solar cell by using a chip process, including bonding a support substrate, stripping a growth substrate, removing an etch stop layer, fabricating a metal electrode, and the like. [Example 1]

3 shows an epitaxial structure of a flip-chip four-junction solar cell, and the bottom-up includes: a growth substrate 001, an etch stop layer 002, an ohmic contact layer 003, a GalnP first sub-cell 100, and GaAs. The second sub-cell 200, the GalnNAsSb third sub-cell 300, the GalnNAsSb fourth sub-battery 400, and the heavily doped cap layer 500, wherein each of the sub-cells is connected by a tunneling junction 501, 502, 503. The structure will be described in detail below in conjunction with its preparation method.

[0055] Step 1: Select a n-type GaAs substrate with a (111) crystal plane off angle of 9 as the growth substrate 001, the thickness is about 350 microns, and the impurity concentration is lxl0 ¹⁸ cm ^{-3 to} 4xl0. Between ¹⁸ cm - ³ . The substrate was placed in an MOCVD system, and an InGaP etch stop layer 002 and a GaAs ohmic contact layer 003 were sequentially grown on the substrate. The thickness of the InGaP etch stop layer 002 is 100 nm, the impurity is about 1×10 ¹⁸ cm ^-3 , and the thickness of the GaAs ohmic contact layer 003 is 200 nm, which is about 1×10 ¹⁸ cm ^-3 .

[0056] The second step: flipping the first sub-cell 100 over the GaAs ohmic contact layer 003, the band gap is

1.89~1.92eV, specifically including: window layer 101, emitter area 102, base area 103 and back field layer 104. In the present embodiment, the thickness of the η+-Α1ΙηΡ window layer 101 is 25 nm, and the impurity concentration is about 1×10 ¹⁸ cm ³ ; the thickness of the n+-InGaP emission region 102 is 100 nm, and the impurity concentration is 2×10 ¹⁸ cm ^{3 .} ;

The thickness of the p+-InGaP base region 103 is preferably 900 nm, and the impurity concentration is 5× ^{10 17} cm ^{3 .}

The thickness of the p-type AlGalnP back field layer 104 is twice the thickness of the conventional back field layer, and may be 100 nm, and the impurity concentration is about lxl0 ¹⁸ cm ^-3 .

[0057] The third step: a heavily miscellaneous p++/n++-AlGaAs/GaInP tunneling junction 501 is grown over the first subcell 100, having a thickness of 50 nm and a bulk concentration of up to 2x10 3⁄4 m -3 .

[0058] The fourth step: flip-chip growth of the GaAs second sub-cell 200 with a band gap of 1.42 eV above the tunneling junction 401, specifically including: a window layer 201, an emitter region 202, a base region 203, and a back field layer 204. In this embodiment, the thickness of the η+-Α1ΙηΡ window layer 201 is 50 nm, which is twice the thickness of the conventional window layer, and the gradual change is from the high to the low of the tunnel junction interface, and the concentration variation range is l~ 5xl0 ¹⁸ cm -3 or so; the thickness of the _n+ -GaA _S emitter region 202 is 150 nm, the impurity concentration is 2x10 ¹⁸ cm ^-3 ; the thickness of the P+-GaAs base region 203 is preferably 3200 nm, and the impurity concentration is 5x10 ¹⁷ cm - ³ ; The thickness of the p-type AlGaAs back field layer 204 is 100 nm, which is twice the thickness of the conventional back-field layer, and the gradual change is from high to low from the tunnel junction interface. l~5xl0 ¹⁸ cm ³ or so. [0059] Step 5: A heavily miscellaneous p++/n++-GaA _S tunneling junction 502 is grown over the second subcell with a thickness of 50 nm and a bulk concentration of up to 2×10 ¹⁹ cm ⁻³ .

[0060] The sixth step: forming the transfer isolation layer 005 over the tunnel junction 502, so that the first epitaxial structure is completed in the MOCVD apparatus, and its structural diagram is as shown in FIG. The transfer isolation layer 005 is mainly used to perform external oxidation, vulcanization, organic pollution, impurity adsorption, water vapor adsorption and the like in the process of switching to different growth equipment (MBE equipment) after the first epitaxial growth, in the next time It is etched away along with surface impurities prior to epitaxy to protect the underlying functional layer. In this embodiment, the transfer isolation layer 005 is made of n+-GaInP, and has a thickness of 5 nm and a habit of about 5× ^{10 18} cm ^-3 .

[0061] Step 7: Transfer the above-mentioned growth-completed structure to the MBE apparatus, etch away the transfer spacer GaInP 005 with the selective solution before transfer, and clean and polish the surface until it can be directly used for the epi-ready state.

[0062] The eighth step: flip-growing the third sub-battery 300 on the polished surface with a band gap of about 0.9~leV, specifically including: a window layer 301, an emitter region 302, a base region 303, and a back field layer 304. . In this embodiment, the thickness of the n +-GaInP window layer 301 is 25 nm, and the impurity concentration is about 1×10 ¹⁸ cm ³ ; the thickness of the n+-GaInNAsSb emitter region 302 is 250 nm, and the impurity concentration is 2×10 ¹⁸ cm − ³ ; The thickness of the P+-GaInNAsSb base region 303 is preferably 3000 nm, the impurity concentration is 5× ^{10 17} cm ^-3 ; the thickness of the p-type GalnP back field layer 304 is 50 nm, and the impurity concentration is about 1×10 ¹⁸ cm ³ .

[0063] Step 9: Epitaxially growing a heavily miscible p++/n++-GaA _S tunneling junction 503 over the third subcell, the thickness of which is 50 nm, and the impurity concentration is as high as 2x10 3⁄4 m ^-3 .

[0064] The tenth step: flipping the fourth sub-battery 400 at the tunneling junction 503, and thus completing the epitaxial growth of the flip-chip four-junction solar cell, the structure of which is shown in FIG. The band gap of the fourth sub-battery 400 is about 0.6-0.7 eV, and specifically includes: a window layer 401, a base region 403 of the emitter region 402, and a back-field layer 404. In this embodiment, the thickness of the n+-GaInP window layer 401 is 25 nm, and the impurity concentration is about 1×10 ¹⁸ cm ³ ; the thickness of the n+-GaInNAsSb emitter region 402 is 250 nm, and the impurity concentration is 2×10 3⁄4 m ^-3 ; The thickness of the P+-GaInNAsSb base region 403 is preferably 3500 nm, and the impurity concentration is 5× ^{10 17} cm ⁻³ ; the thickness of the p-type GalnP back field layer 404 is 50 nm, and the impurity concentration is about 1×10 ¹⁸ cm ⁻³ .

[0065] The eleventh step: A highly cumbersome _P ++-GaInNAsSb capping layer 500 is grown on the fourth sub-battery 400 for ohmic contact with a poor concentration of 2×10 '3⁄4 m − ³ . [0066] Step 12: After the epitaxial growth of the battery is completed, performing a chip process, including bonding the support substrate 004, stripping the growth substrate 001, removing the etch stop layer 002, evaporating the anti-reflection film 600, and fabricating the front metal The electrode 70 0 and the back metal electrode 800 complete the preparation of the flip-chip four-junction solar cell, and its structure is shown in FIG.

[0067] All of the sub-batteries obtained by the above manufacturing method have lattice matching and high crystal quality, so the photoelectric conversion efficiency is high, and high-temperature MOCVD epitaxial growth is performed first, followed by low-temperature MBE extension, and different linings are avoided. The effect of the bottom temperature.

[Embodiment 2]

[0069] This embodiment differs from Embodiment 1 in that the fourth sub-battery 400 is a Ge battery in which the thickness of the n+-Ge emitter region is 250 nm, and the impurity concentration is 2×10 ¹⁸ cm ⁻³ ; P+-Ge base region The preferred thickness is 2500 nm°

Claims

Claim

A method for manufacturing a flip-chip multi-junction solar cell, comprising the steps of:

(1) providing a growth substrate for epitaxial growth of a semiconductor material;

(2) placing the growth substrate in a MOCVD apparatus, and flip-growing a first epitaxial structure over the substrate by MOCVD, having a multi-junction cell stack;

(3) transferring the above-mentioned growth-completed structure to the MBE device, and flipping on the MBE method to form a second epitaxial structure comprising at least one junction cell to form a series flip-chip multi-junction solar cell;

The band gap of the first epitaxial structure is larger than the band gap of the second epitaxial structure.

The method of fabricating a flip-chip multi-junction solar cell according to claim 1, wherein: the first epitaxial structure formed in the step (2) further comprises a transfer isolation layer formed on a top surface thereof, in the performing step (3) Before, the transfer separation layer is removed, surface-cleaned, polished to a directly epitaxial state (Epi-ready state), and then the above structure is immediately transferred to the MBE device for the step (3).

The method of fabricating a flip-chip multi-junction solar cell according to claim 2, wherein: the step (2) comprises the following sub-steps:

Forming an etch stop layer on the growth substrate;

A multi-junction cell stack having a wide band gap is flip-chip grown over the etch stop layer by MOCVD to absorb short-wavelength sunlight;

Forming a transfer isolation layer on the wide band gap multi-junction cell for performing atmospheric oxidation, vulcanization, and organic pollution in the process of separating the external epitaxial growth and switching to the MBE device

Impurity adsorption, water vapor adsorption, and corrosion together with surface impurities before the next epitaxy, thereby protecting the lower functional layer.

A method of fabricating a flip-chip multi-junction solar cell according to claim 3, characterized in that

After the step (2) is completed, the transfer isolation layer is removed by etching with a selective etching solution, and the surface is cleaned, polished to a directly epitaxial state (Epi-ready state), and then the structure is immediately transferred to the MBE device. Step (3).

A method of fabricating a flip-chip multi-junction solar cell according to claim 1, wherein : The lattice constant of the second epitaxial structure formed using MBE is lattice matched to the first epitaxial structure formed by MOCVD.

[Claim 6] The method of fabricating a flip-chip multi-junction solar cell according to claim 1, wherein

: The growth temperature of the step (2) is higher than the growth temperature of the step (3).

[Claim 7] The method of fabricating a flip-chip multi-junction solar cell according to claim 1, wherein

The method further includes the step (4): performing surface cleaning, polishing, and bonding the supporting substrate on the epitaxial structure of the formed flip-chip multi-junction solar cell, removing the growth substrate, fabricating the electrode structure, and implementing flip-chip multi-junction Solar battery.

[Claim 8] A flip-chip multi-junction solar cell, which is obtained by the production method according to any one of claims 1 to 7.

[Claim 9] A flip-chip multi-junction solar cell according to claim 8, wherein: a lattice constant of said first epitaxial structure matches a lattice constant of said second epitaxial structure.