WO2016142484A2 - Dispositif permettant de déterminer l'état d'un commutateur, dispositif à commutateur, procédé permettant de déterminer l'état d'un commutateur et programme informatique - Google Patents

Dispositif permettant de déterminer l'état d'un commutateur, dispositif à commutateur, procédé permettant de déterminer l'état d'un commutateur et programme informatique Download PDF

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Publication number
WO2016142484A2
WO2016142484A2 PCT/EP2016/055172 EP2016055172W WO2016142484A2 WO 2016142484 A2 WO2016142484 A2 WO 2016142484A2 EP 2016055172 W EP2016055172 W EP 2016055172W WO 2016142484 A2 WO2016142484 A2 WO 2016142484A2
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WO
WIPO (PCT)
Prior art keywords
switch
semiconductor
measurement signal
signal
reference signal
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PCT/EP2016/055172
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German (de)
English (en)
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WO2016142484A3 (fr
Inventor
Klaus KOHLMANN -V. PLATEN
Holger Kapels
Jörn HINZ
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
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Publication of WO2016142484A2 publication Critical patent/WO2016142484A2/fr
Publication of WO2016142484A3 publication Critical patent/WO2016142484A3/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/3271—Testing of circuit interrupters, switches or circuit-breakers of high voltage or medium voltage devices
    • G01R31/3275—Fault detection or status indication
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2608—Circuits therefor for testing bipolar transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's

Definitions

  • Apparatus for determining a switch state switch device, method for determining a switch state and computer program
  • the present invention relates to a device for determining a state of a semiconductor-based switch, to a switching device, to a method for determining a state of a semiconductor-based switch, and to a computer program.
  • the present invention further relates to a method for determining in situ the degree of aging of a power device or a power module and extrapolating to the time of failure of the assembly.
  • a method described in DE 10 2007 024 175 A1 relates only to the detection of damage to a gate oxide.
  • the object of the present invention is to provide a concept which enables a reliable determination of a state of a switch arrangement. This object is solved by the subject matter of the independent patent claims.
  • the gist of the present invention is to have recognized that with increasing damage to the switch assembly, a voltage waveform between a control terminal and a power terminal of a semiconductor-based switch increasingly changes during a switching operation and that a measure of the deviation between a detected voltage waveform and a reference signal as a measure of damage to the switch assembly is interpretable.
  • an apparatus includes a voltmeter configured to measure a voltage between a control terminal and a power terminal of a semiconductor-based switch and to obtain a voltage signal.
  • the apparatus further comprises processing means configured to compare the measurement signal with a reference signal, and to determine based on the comparison a state of a switch arrangement comprising the semiconductor-based switch.
  • the reference signal indicates information regarding the voltage between the control terminal and the power terminal of the semiconductor-based switch when the switch arrangement has an undamaged or a tolerance-degraded state. The advantage of this is that a measure of a deviation of the measurement signal and the reference signal can be converted to an extent in which the switch arrangement has a damaged state or is damaged beyond the tolerance range.
  • the processing device is designed to compare information relating to a Miller plateau of the measurement signal with information of a Miller plateau of the reference signal.
  • the Miller plateau represents a characteristic signal portion of a gate-emitter voltage of a semiconductor-based switch during its turn-on and that the Miller plateau can be compared with respect to its amplitude height and / or time duration with corresponding signal portions of the reference signal. This enables a reliable determination of the state of the switch arrangement.
  • the processing device is designed to transform the measurement signal at least partially into a frequency range in order to obtain a transformed measurement signal, the reference signal having frequency information, and wherein the processing device is designed to compare the transformed measurement signal with the frequency information ,
  • parameters such as a switching speed (for example, from conducting to non-conducting or vice versa) can be evaluated based on frequency information and that an evaluation of the state of the switch arrangement is made possible based on these parameters.
  • the processing device is designed to store a first measurement signal, which is detected with respect to a first time interval and with respect to the semiconductor-based switch, in a reference signal memory and the first measurement signal with a second measurement signal, which relates to a second time interval the first time interval follows, to compare.
  • the processing device is designed to use the first measurement signal with respect to the second measurement signal as the reference signal.
  • a switch device comprises a switch arrangement with a semiconductor-based switch and a device for determining the state of the switch arrangement.
  • the processing device is designed to obtain a comparison result based on the comparison in order to compare the comparison result with a threshold value and to generate an output signal that has information regarding a remaining operational readiness of the switch arrangement if the comparison result relates to the predefined threshold value Deviation has.
  • the apparatus is configured to control the semiconductor-based switch and to terminate operation of the semiconductor-based switch based on the output signal or to send the output signal to another device configured to control the semiconductor-based switch.
  • future operation may be interrupted or terminated in time for failure to perform a repair before failure of the semiconductor-based switch or switch assembly occurs.
  • FIG. 1 is a schematic block diagram of a device comprising a voltmeter and a processing device according to an embodiment
  • FIG. 2 is a schematic block diagram of an apparatus configured to determine the state of a switch assembly according to one embodiment
  • FIG. 3 is a schematic block diagram of a switch device comprising the switch assembly and apparatus of FIG. 1 according to one embodiment
  • FIG. 4 shows a schematic comparison of voltage profiles during a switch-on behavior of a semiconductor-based switch according to an exemplary embodiment
  • FIG. 5 shows a schematic diagram in which a time axis is denoted on the abscissa and an ordinarily standardized parameter value is designated on the ordinate according to an exemplary embodiment
  • FIG. 6 a shows by way of example a two-dimensional matrix in which a respective parameter value is arranged in the rows according to an exemplary embodiment
  • 6b is a schematic two-dimensional diagram in which a time axis is plotted on the abscissa with times discretely applied thereto, to which the respective parameter is measured and / or compared, according to an exemplary embodiment
  • FIG. 7a is a schematic diagram of voltage traces of a gate-emitter voltage and a collector-emitter voltage according to an embodiment
  • 7b is a schematic diagram of the same voltages in which contact resistances of FIG. 7a are increased to a higher value, according to an embodiment
  • Fig. 8 is a schematic diagram of a so-called stress test according to the prior art.
  • semiconductor-based switches which, for example, may comprise base materials comprising silicon, silicon carbide (SiC) and / or gallium nitride (GaN).
  • Semiconductor-based switches can be embodied, for example, as metal-oxide semiconductor field-effect transistors (MOSFETs) or as bipolar transistors.
  • MOSFETs metal-oxide semiconductor field-effect transistors
  • Semiconductor-based switches may have a normally-conductive or normally-off configuration.
  • semiconductor-based switches may include an insulated gate electrode, such as an insulated gate MOSFET or an insulated gate bipolar transistor (IGBT). Further, semiconductor-based switches may be of an n-channel or p-channel type. Based on a concentration of carriers stored on a control capacitance (gate capacitance), a switch state, for example, conducting or blocking, can be changed, that is, the semiconductor-based switch is switched.
  • a control capacitance gate capacitance
  • semiconductor based switches will be described below as having a blocking state (ie, non-conductive or low conductive) when a concentration of carriers in the control capacitance is so low that a control potential or voltage is applied across the control capacitor Control connection is below a threshold threshold. If the concentration of charge carriers has a higher value such that the control voltage is above the threshold value, the semiconductor-based switch has a conductive state. It goes without saying that these states are mutually interchangeable based on the configuration of the semiconductor-based switch, for example normally conducting / normally blocking.
  • a non-conductive state may also be brought about or another form of semiconductor-based switch may be arranged. Subsequent labels of the semiconductor-based switch terminals, such as gate, emitter, and collector, may be interchanged based on other types of switches, such as gate, drain, and source.
  • FIG. 1 shows a schematic block diagram of a device 10 comprising a voltmeter 12 and a processing device 14.
  • the voltmeter is configured to measure a voltage U G E between a control terminal (gate G) and a power terminal of a semiconductor-based switch 16 and to convert the measured voltage U G E into a measurement signal 18.
  • the power connection may, for example, be an emitter connection E.
  • the measurement signal 18 thus has information regarding the voltage U G E.
  • the information may be the actual voltage value, a sequence of samples or the like, or a scaling of one or more voltage values.
  • the processing device 14 is designed to compare the measurement signal 18 with a reference signal 22.
  • the reference signal may be one stored (scaled or unscaled) voltage waveform, one or more (scaled or unscaled) samples.
  • the reference signal 22 may also have further information, such as a trigger voltage, in which the comparison is carried out when the measurement signal exceeds or falls below the trigger voltage.
  • the comparison can be made between similar or different types of signals or signal features.
  • the processing device can be configured to compare a respective time profile of the measurement signal 18 with a time profile of the reference signal 22.
  • a time profile can also be compared with one or more samples.
  • the comparison can be done in real time.
  • the comparison can also be carried out after a successful switching operation of the semiconductor-based switch 16.
  • the comparison can be performed at or after each switching operation.
  • the comparison can also be carried out with regard to a part of the switching operations, for example relating to leases every second, third, fifth or tenth switching operation or another value.
  • the processing device 14 is designed to determine, based on the comparison of the measurement signal 18 with the reference signal 22, a state of a switch arrangement 24 comprising the semiconductor-based switch 16.
  • the switch assembly 24 includes the semiconductor-based switch 16 and may optionally include other components, such as a board on which the semiconductor-based switch 16 is located, power terminals for contacting the semiconductor-based switch 16 with other components of a circuit or assembly, or interconnections between the semiconductor-based Include switches and other components.
  • Such a connection may be embodied as a bonding wire connection with which the semiconductor-based switch 16 is connected to the circuit board.
  • the state may also include a connection (electrical connection) of an electrical load 26, which is connected to the switch arrangement 24, to the switch arrangement 24.
  • the condition may relate to damage or aging of the semiconductor-based switch 16 and / or damage or aging of a compound of the semiconductor-based switch with the component.
  • the component may also be a circuit board on which the semiconductor-based switch 16 is arranged, so that the state of the mechanical connection of the semiconductor-based switch 16 with the board and / or on the electrical connection of the electrical connections of the semiconductor-based switch 16 and the board can relate.
  • the reference signal may include information regarding a voltage between the gate (control terminal) and the collector or emitter (power terminal) of the semiconductor-based switch 16 when the switch assembly 24 has an undamaged or a tolerance-degraded state.
  • the reference signal may indicate a profile of the gate-emitter voltage U G E in the undamaged state of the switch arrangement 24.
  • a measure of the deviation between the reference signal 22 and the measurement signal 18 can be interpreted as a measure of the damage to the switch arrangement 24.
  • the reference signal 22 may refer to a condition obtained after fabrication of the switch assembly 24 and detected with respect to the switch assembly 24, such as in the form of calibration.
  • the reference signal may also be one obtained externally Be information, such as in the form of a setpoint curve, which is created for a structure of the switch assembly 24. This allows a functional and / or quality control during commissioning of the switch assembly 24, since by means of the comparison also deviations with respect to the desired state can be determined.
  • the reference signal may at least partially also contain information regarding previous comparisons or detected voltage values.
  • the processing device can be designed to determine a development of the status based on an iteratively repeated comparison.
  • the processing device may be configured to use one or more (i.e., at least a second) preceding measurement signals as a reference signal.
  • the processing device can be designed to compare a further (third) measurement signal with the reference signal (s) used.
  • the processing device may further be configured to determine a deviation between the comparisons. This allows the determination of a rate of change with which the state of the switch assembly 24 changes.
  • Each measurement signal may be detected with respect to a time interval in which the semiconductor-based switch 16 performs a switching operation, the time intervals following each other in an order in which the switching operations with respect to which the respective measurement signal is detected are arranged in time.
  • the processing device 14 may be designed to compare a time profile of the measurement signal 18 with a time profile of the reference signal 22.
  • the processing device can also be designed to compare information extracted from the time profile of the measurement signal 18 and / or reference signal 22. Such information may be one or more time periods and / or amplitude values. For example, a time duration of a Miller plateau of the measurement signal 18 can be compared with a time duration provided by the reference signal 22. That is, the reference signal 22 may include or represent information regarding the corresponding time duration.
  • the processing device 14 may be designed to compare an amplitude of the Miller plateau of the measurement signal 18 with an amplitude value that is encompassed by the reference signal 22.
  • a start of the Miller plateau can be determined, for example, by the fact that, at the beginning of the same, a gate-emitter voltage and a collector-emitter voltage within a tolerance range are the same. Such information may, for example, be included as a trigger point of the reference signal to which the comparison device subsequently performs the measurement or the comparison.
  • the reference signal 22 may be an amplitude value or that the reference signal 22 comprises an amplitude value.
  • the device 10 comprises, for example, a memory 28 which is designed to store the reference signal 22 and to provide the reference signal 22 to the processing device 14.
  • the device 10 may be implemented without the memory 28 and receive the reference signal 22, for example in the form of an external signal.
  • FIG. 2 shows a schematic block diagram of a device 20 which is designed to determine the state of the switch arrangement 24 and is connected to the switch arrangement 24.
  • a processor 32 is configured to output a status signal 34 as compared to the processor 14 of FIG. 1.
  • the status signal 34 may include information as to whether the state of the switch assembly 24 is within or outside an allowable range (tolerance range).
  • the status signal 34 may indicate that the switch assembly 24 has failed, is about to fail, or is still suspending a certain number of switching cycles (operating time) that the switch assembly 24 or the semiconductor-based switch 16 may perform.
  • the device 20 or the processing device 32 may be designed to output the status signal 34 if the time duration of the Miller plateau the measuring signal 18 is greater than a corresponding information of the reference signal 22 by a time factor of greater than or equal to 1, 01, greater than or equal to 1, 2, greater than or equal to 1, 3 or greater than or equal to 1.
  • the processing device 32 can be formed be to determine from a time course of the reference signal 22, the corresponding time duration of the Miller plateau thereof and to compare with the time duration of the Miller plateau of the measurement signal 18.
  • the reference signal 22 may have the corresponding time indication as preprocessed information.
  • the device 20 or the processing device 32 may be designed to output the status signal 34 if the amplitude of the Miller plateau of the measurement signal 18 is at least an amplitude factor greater than or equal to 1, 01, greater than or equal to 1, 15 or greater than or equal to 1, 2 is greater than the amplitude of the Miller plateau of the reference signal 22.
  • the amplitude of the Miller plateau of the reference signal 22 may be present as an amplitude value or determined from a temporal course of the reference signal 22 from the processing device 32.
  • the processing device 32 or the processing device 14 may be designed to transform the measurement signal 18 at least partially into the frequency range, for example by a Fourier transformation, a fast Fourier transformation (FFT) and / or a wavelet transformation.
  • the processing device is designed to obtain a transformed measurement signal based on the transformation.
  • the reference signal 22 may have comparable (frequency) information with respect to the transformation.
  • the frequency information may include, for example, information regarding a switching speed or a slope of signal edges during the switching.
  • the processing device 32 may be configured to compare the frequency information of the measurement signal 18 with the reference signal 22 or its frequency information.
  • FIG. 3 shows a schematic block diagram of a switch device 30 comprising the switch arrangement 24 and the device 10.
  • the device 10 is connected at a first terminal 36a to the gate terminal of the semiconductor-based switch 16 and at a second terminal 36b to the emitter terminal of the semiconductor-based switch 16, and configured to the gate-emitter voltage U G E of the semiconductor-based switch 16 by means of the voltmeter 12 to determine.
  • the device 10 is designed to control the semiconductor-based switch 16 with a control signal 38.
  • the device 10 includes another terminal 42 connected to the gate terminal of the semiconductor-based switch 16.
  • the device 10 is designed to control the semiconductor-based switch 16 by means of the control signal 38, for example by the control signal 38 supplying or discharging charge carriers to or from the gate G.
  • the control signal 38 may be provided by a processor (not shown) of the device 10. Alternatively, the control signal 38 may also be provided by the processing device 14.
  • the device 10 is configured to enable or terminate operation of the semiconductor-based switch 16 based on the status signal 34.
  • the processing device 14 is designed to compare the comparison result with a threshold value and to generate the status signal 34 if the comparison result with respect to the threshold value has a predefined deviation (within or outside the tolerance range).
  • the status signal 34 may alternatively or additionally comprise information regarding a remaining operational readiness of the switch arrangement 24.
  • the status signal 34 may indicate that the state of the switch assembly 24 is in order or that failure of the semiconductor-based switch 16 or the switch assembly 24 is imminent.
  • the device is configured, for example, to control the semiconductor-based switch by means of the control signal 38 and to terminate the operation of the semiconductor-based switch 16 based on the status signal 34.
  • the status signal 34 contains information that the state of the semiconductor-based switch 16 or the switch arrangement 24 is in order (ie within the tolerance range) and the device 10 is configured to control the operation of the semiconductor-based switch 16 long as the status signal 34 has this information.
  • the device may be configured to send the status signal 34 to another device configured to control and / or stop operation of the semiconductor-based switch 16.
  • the switch device 30 can be designed as a device for switching the component 26.
  • the switch assembly 30 can be used as a DC / DC converter or DC / AC converter, such as For example, in the field of voltage converter, frequency converter or synchronous rectifier be executed.
  • switching devices are provided that are configured to detect a degrading or defective state of the switch assembly 24 during operation thereof.
  • the switch device may be configured to set a safe state of the entire device, or at least parts thereof, based on the degrading or defective state, before failure of the switch assembly 24 occurs (fail-safe).
  • the device 10 may be designed to determine the voltage U G E during operation of the switch arrangement 24, so that decommissioning of the switch arrangement 24 and application of reference cycles or a test scenario can be dispensed with.
  • FIG. 4 shows a schematic comparison of a voltage curve of the voltage UGE with a voltage curve of a collector-emitter voltage U C E during a switch-on behavior of a semiconductor-based switch from a non-conductive state to a conductive state. From a point in time t 0 to a point in time t- 1 , for example, there is no activation of the semiconductor-based switch, which means that it remains in the blocking state.
  • the voltage U G E ZU begins to rise, while the voltage U C E almost unchanged remains.
  • the voltage U G E reaches a value corresponding to the threshold voltage (threshold voltage), which is designated as U G E (th).
  • the voltage U C E begins to decrease, that is, the semiconductor-based switch begins to conduct increasingly.
  • the voltage U G E continues to increase when additional charge carriers are conducted to the gate of the semiconductor-based switch.
  • the voltage U GE reaches a Miller voltage, designated U GE (mil).
  • U GE Miller voltage
  • the voltage U GE remains in the region of the Miller voltage U GE (mil) until the parasitic capacitances of the semiconductor-based switch are sufficiently charged. This is done, for example, at a time t 4 .
  • the voltage U GE continues to increase while the voltage U C E continues to decrease.
  • the time interval [t 4 ; t 3 ] between the times t 3 and t 4 in which the voltage U G E remains in the range of the Miller voltage U GE (mil) can be referred to as the Miller plateau 44.
  • Additional capacitances or resistances such as material transitions on bond wires, effective capacitance through the placement of the semiconductor-based switch on a board, or other connections of the semiconductor-based switch, can affect the parasitic capacitances that are charged during the Miller plateau.
  • these capacitances or resistances may be effective as an effective capacitance and / or an effective resistance between the gate and the emitter (in the case of a FET between the gate and a drain terminal) and be referred to as Miller capacitance.
  • a change in a time duration between the times t 3 and t 4 and / or an amplitude value of the Miller voltage U GE (mil) can thus provide information about whether the properties of the semiconductor-based switch or of the switch arrangement change. For example, as bonding of the semiconductor-based switch dissipates to an increasing extent, the Miller capacitance may be of an increasing value such that the Miller voltage U GE (mil) or a time duration of the Miller plateau increases.
  • Previously described processing means may be configured to determine such a change in the Miller plateau to determine the state of the semiconductor-based switch and / or the switch assembly.
  • the parameter value may be, for example, a time duration and / or an amplitude value of the Miller Plateau.
  • measuring times are indicated, for example at discrete times, at which the parameter value is determined by the processing device by means of the comparison.
  • the ordinate also schematically indicates a threshold value.
  • the comparison may provide a value above the threshold. For example, this is a difference formation or a quotient formation between a time duration of the Miller-Plateau of the measurement signal and the reference signal and / or an amplitude value of the gate-emitter voltage.
  • results based on the comparison can also be obtained in which a changed state can be obtained in which the measured value or the comparison value lies below the threshold value. This can be done based on other mathematical comparison operations, such as addition or multiplication.
  • the processing device can be designed to be based on the comparison result, which is above or below the threshold, to determine that the switch assembly has damage, has failed or that a failure is imminent.
  • FIG. 6a shows, by way of example, a two-dimensional matrix in which an index is made in the columns with measurements taken and in the rows a respective parameter value, for example an amplitude of the Miller plateau or a time duration of the Miller plateau.
  • the processing device can be designed to store the respective comparison or measurement result in a memory, for example in the memory 28.
  • the stored results can be represented in the form of the matrix illustrated in FIG. 6a.
  • 6b shows a schematic two-dimensional diagram in which a time axis is plotted on the abscissa with times discretely applied thereto, to which the respective parameter is measured and / or compared.
  • the parameter value is schematically plotted on the ordinate of the diagram.
  • the processing device can be designed to store the respective comparison result and / or the respective measured values for at least a portion of the measurements and to predict (extrapolate) a development of the measurement results. This allows a prediction of a possible or probable instant when the switch assembly reaches a state that is out of tolerance (threshold) and / or the switch assembly fails.
  • This time can be indicated, for example, in the form of a remaining time or in the form of a remaining proportion of switching cycles.
  • the processing device may be designed to store the respective measured signal obtained for a measurement or parameters extracted therefrom as reference value or reference signal for subsequent measurements. For example, a change ⁇ between the parameter value of a previous measurement and a current measurement can thus be determined so that the change of the parameter can also be considered as the parameter to be evaluated for a successful or imminent failure of the switch arrangement.
  • the processing device can be designed to use the first or second measurement signal (a preceding measurement signal) as a reference signal and to compare a third measurement signal, which is detected with respect to a subsequent time interval, with the reference signal used.
  • the processing device can be configured to determine a deviation between the measurement signal and one or more reference signal.
  • the processing means may alternatively or additionally be configured to determine the comparison based on one or more comparisons made above.
  • Fig. 7a shows a schematic diagram of voltage waveforms of the gate-emitter voltage UGE, the collector-emitter voltage U C E and a collector-emitter current IGE-, which serves here only for clarity, whether the switch in a conductive or non-conductive state.
  • the voltage U G E essentially has the Miller voltage U G E (mil).
  • Contact resistances of the bonding wires have a first value, for example 1, 5 mOhm.
  • Fig. 7b shows a schematic diagram of the same voltages in which the contact resistances are increased towards a higher value, for example 10 mOhms.
  • a time duration ⁇ t ' is also increased compared with a corresponding time duration ⁇ t in FIG. 7a, which can be determined based on the comparison by the processing device. That is, the state change of the switch arrangement can be determined based on the extended time interval At '.
  • FIG. 8 shows a schematic diagram of a so-called power cycling test, in which a collector-emitter voltage V C E, which changes over several temperatures, is considered, for example, when an IGBT has the conducting state.
  • V C E collector-emitter voltage
  • the self-adjusting collector-emitter voltage increases with an increasing number of switching cycles, wherein a statistical determination is made after how many switching cycles threatens a failure of the module.
  • Such a method thus does not allow consideration of a changing state of the semiconductor-based switch or the switch assembly during operation.
  • Previously described embodiments allow such a consideration of the durability of a semiconductor-based switch a statement about the operational readiness of the same, which are at least partially independent of foreclosed forecasts.
  • the time profile of the gate-emitter voltage is evaluated. Due to the influence of the collector-emitter voltage on the length of the Miller-Plateau, changes in the collector-emitter voltage, which are caused, for example. By a detachment of a bonding wire or by a detachment of the device from the bottom plate detected and therefrom Aging degree of a power device or a power module (switch assembly) determined.
  • the Miller Plateau may increase to higher voltage levels and / or extend the length of the Miller Plateau.
  • a curve of the gate-emitter voltage can be recorded in the original state and stored as a calibration curve.
  • a percentage change in the length of the Miller plateau can be used as a default criterion.
  • the time profile of the gate-emitter voltage can be evaluated, for example, by Fourier transformation or wavelet analysis. As a result, a higher accuracy of the failure prediction can be achieved.
  • An evaluation can be achieved by recording the gate-emitter voltage profile during operation of the device (for example a frequency converter) or during control measurements.
  • embodiments described above can be used in semiconductor-based switches for switching inductive loads.
  • the gate-emitter voltage increases initially (possibly linearly).
  • the threshold voltage is reached, the transistor begins to conduct current and the collector-emitter voltage begins to decrease.
  • the gate-emitter voltage continues to increase until it is approximately equal to the collector-emitter voltage.
  • the gate-emitter voltage remains substantially constant (Miller plateau), while the gate charge current flows over the Miller capacitance.
  • Example embodiments described above can be used, for example, as a frequency converter (AC / AC converter), as a rectifier (AC / DC converter), in particular as a synchronous rectifier and / or as an inverter (DC / AC converter).
  • AC / AC converter frequency converter
  • AC / DC converter rectifier
  • DC / AC converter inverter
  • aspects have been described in the context of a device, it will be understood that these aspects also constitute a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Similarly, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device.
  • embodiments of the invention may be implemented in hardware or in software.
  • the implementation may be performed using a digital storage medium, such as a floppy disk, a DVD, a Blu-ray Disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or FLASH memory, a hard disk, or other magnetic disk or optical memory are stored on the electronically readable control signals that can cooperate with a programmable computer system or cooperate such that the respective method is performed. Therefore, the digital storage medium can be computer readable.
  • some embodiments according to the invention include a data carrier having electronically readable control signals capable of interacting with a programmable computer system such that one of the methods described herein is performed.
  • embodiments of the present invention may be implemented as a computer program product having a program code, wherein the program code is operable to perform one of the methods when the computer program product runs on a computer.
  • the program code can also be stored, for example, on a machine-readable carrier.
  • Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine-readable medium.
  • an embodiment of the method according to the invention is thus a computer program which has a program code for performing one of the methods described herein when the computer program runs on a computer.
  • a further embodiment of the inventive method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program is recorded for carrying out one of the methods described herein.
  • a further embodiment of the method according to the invention is thus a data stream or a sequence of signals, which represent the computer program for performing one of the methods described herein.
  • the data stream or the sequence of signals may be configured, for example, to be transferred via a data communication connection, for example via the Internet.
  • Another embodiment includes a processing device, such as a computer or a programmable logic device, that is configured or adapted to perform one of the methods described herein.
  • Another embodiment includes a computer on which the computer program is installed to perform one of the methods described herein.
  • a programmable logic device eg, a field programmable gate array, an FPGA
  • a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein.
  • the methods are performed by any hardware device. This may be a universal hardware such as a computer processor (CPU) or hardware specific to the process, such as an ASIC.
  • CPU computer processor
  • ASIC application specific integrated circuit

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  • General Physics & Mathematics (AREA)
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Abstract

La présente invention concerne un dispositif comprenant un élément de mesure de tension et un système de traitement. Ledit élément de mesure de tension est configuré pour mesurer une tension entre une borne de commande et une borne de puissance d'un commutateur à base de semiconducteur et pour obtenir un signal de mesure. Le système de traitement est conçu pour comparer ledit signal de mesure à un signal de référence et pour déterminer, sur la base de cette comparaison, un état d'un dispositif à commutateur qui comprend ledit commutateur à base de semiconducteur.
PCT/EP2016/055172 2015-03-11 2016-03-10 Dispositif permettant de déterminer l'état d'un commutateur, dispositif à commutateur, procédé permettant de déterminer l'état d'un commutateur et programme informatique WO2016142484A2 (fr)

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DE102015204343.6 2015-03-11
DE102015204343.6A DE102015204343A1 (de) 2015-03-11 2015-03-11 Vorrichtung zum bestimmen eines schalterzustands, schaltervorrichtung, verfahren zum bestimmen eines schalterzustands und computerprogramm

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112782512A (zh) * 2021-01-15 2021-05-11 中国神华能源股份有限公司国华电力分公司 一种电气设备状态判断及故障诊断方法和装置
CN113341307A (zh) * 2021-04-19 2021-09-03 云南电网有限责任公司临沧供电局 一种开放式接地开关的短路关合能力测试平台和方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3067117B1 (fr) * 2017-05-31 2021-05-07 Alstom Transp Tech Procede de determination d'une tension de sortie d'un transistor
EP3696558A1 (fr) 2019-02-15 2020-08-19 Siemens Aktiengesellschaft Dispositif et procédé de vérification automatique d'un organe de commutation
DE102021116772A1 (de) 2021-06-30 2023-01-05 Audi Aktiengesellschaft Verfahren zum Betreiben einer wenigstens ein Schaltelement umfassenden elektrischen Schaltung eines Kraftfahrzeugs und Kraftfahrzeug

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007024175A1 (de) 2007-05-24 2008-12-11 Robert Seuffer Gmbh & Co. Kg Verfahren und Vorrichtung zur Frühausfallerkennung bei einer Halbleiterschaltanordnung mit zumindest einer isolierten Steuerelektrode, und Herstellungsverfahren für eine solche

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0752593A3 (fr) * 1995-07-07 1998-01-07 Siemens Aktiengesellschaft Procédé pour la reconnaissance anticipée de pannes dans des modules de semi-conducteurs de puissance
DE10351387A1 (de) * 2003-11-04 2005-06-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Schaltervorrichtung
EP2615467B1 (fr) * 2012-01-11 2014-06-18 ABB Research Ltd. Système et procédé de surveillance en temps réel de l'état de fonctionnement d'un dispositif IGBT

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007024175A1 (de) 2007-05-24 2008-12-11 Robert Seuffer Gmbh & Co. Kg Verfahren und Vorrichtung zur Frühausfallerkennung bei einer Halbleiterschaltanordnung mit zumindest einer isolierten Steuerelektrode, und Herstellungsverfahren für eine solche

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112782512A (zh) * 2021-01-15 2021-05-11 中国神华能源股份有限公司国华电力分公司 一种电气设备状态判断及故障诊断方法和装置
CN113341307A (zh) * 2021-04-19 2021-09-03 云南电网有限责任公司临沧供电局 一种开放式接地开关的短路关合能力测试平台和方法
CN113341307B (zh) * 2021-04-19 2023-04-14 云南电网有限责任公司临沧供电局 一种开放式接地开关的短路关合能力测试平台和方法

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