WO2016132920A1 - Photoelectric conversion element and method for manufacturing photoelectric conversion element - Google Patents

Photoelectric conversion element and method for manufacturing photoelectric conversion element Download PDF

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WO2016132920A1
WO2016132920A1 PCT/JP2016/053367 JP2016053367W WO2016132920A1 WO 2016132920 A1 WO2016132920 A1 WO 2016132920A1 JP 2016053367 W JP2016053367 W JP 2016053367W WO 2016132920 A1 WO2016132920 A1 WO 2016132920A1
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amorphous semiconductor
semiconductor film
type amorphous
photoelectric conversion
conversion element
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PCT/JP2016/053367
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French (fr)
Japanese (ja)
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雄太 松本
親扶 岡本
隆 岡村
奈都子 藤原
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シャープ株式会社
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion element and a method for manufacturing the photoelectric conversion element.
  • the most manufactured and sold solar cells have a structure in which electrodes are formed on the light receiving surface on the side where sunlight enters and the back surface on the opposite side of the light receiving surface, respectively. is there.
  • FIG. 16 shows a schematic cross-sectional view of the back junction solar cell described in Patent Document 1.
  • the back junction solar cell shown in FIG. 16 has an i-type amorphous semiconductor layer 119, an n-type amorphous semiconductor layer 120, and a protective film 124 on a light-receiving surface of a substrate 111 such as an n-type single crystal silicon substrate. Are sequentially stacked.
  • the i-type amorphous semiconductor layer 112 In the n-type region 122 corresponding to the n-side electrode 116 on the back surface of the substrate 111, the i-type amorphous semiconductor layer 112, the n-type amorphous semiconductor layer 114, the insulating layer 121, and the n-side electrode are formed on the substrate 111. 116 are sequentially stacked. Further, the n-type amorphous semiconductor layer 114 and the n-side electrode 116 are connected through a hole penetrating the insulating layer 121.
  • the i-type amorphous semiconductor layer 113, the p-type amorphous semiconductor layer 115, and the p-side electrode 117 are sequentially stacked on the substrate 111. Has been.
  • the n-side electrode 116 and the p-side electrode 117 are formed by providing metal layers 116b and 117b and organic coatings 116a and 117a in this order on the transparent conductive layers 116c and 117c, respectively.
  • FIG. 17 shows a flowchart of the manufacturing method of the back junction solar cell shown in FIG.
  • the manufacturing method of the back junction type solar cell shown by FIG. 16 is demonstrated.
  • step S1a an i-type amorphous semiconductor layer 119 and an i-type amorphous semiconductor layer 112 are formed on the light-receiving surface and the back surface of the substrate 111 by a CVD method, respectively.
  • step S2a an n-type amorphous semiconductor layer 120 and an n-type amorphous semiconductor layer 120 are formed on the entire surface of the i-type amorphous semiconductor layer 119 on the light-receiving surface side of the substrate 111 and the entire surface of the i-type amorphous semiconductor layer 112 on the back surface side, respectively.
  • a type amorphous semiconductor layer 114 is formed by a CVD method.
  • step S3a the protective film 124 and the insulating layer 121 are formed on the entire surface of the n-type amorphous semiconductor layer 120 on the light-receiving surface side of the substrate 111 and the entire surface of the n-type amorphous semiconductor layer 114 on the back surface side by CVD. To form.
  • a resist pattern is formed on the insulating layer 121 in order to pattern the n-type region 122 by photolithography.
  • a resist film is formed in a region where the n-type region 122 made of a laminate of the i-type amorphous semiconductor layer 112 and the n-type amorphous semiconductor layer 114 is left, and the n-type region 122 is removed. It is formed to have an opening.
  • step S5a the n-type region 122 in the opening of the resist pattern is removed by etching.
  • step S6a the resist film remaining on the n-type region 122 is removed.
  • step S7a an i-type amorphous semiconductor layer 113 is formed by CVD so as to cover the back surface of the substrate 111 where the insulating layer 121 and the n-type region 122 remain.
  • step S8a a p-type amorphous semiconductor layer 115 is formed on the entire surface of the i-type amorphous semiconductor layer 113 by a CVD method.
  • step S9a a resist film is formed on the p-type amorphous semiconductor layer 115.
  • the resist film is formed in a region where the p-type region 123 made of a stacked body of the i-type amorphous semiconductor layer 113 and the p-type amorphous semiconductor layer 115 is left, and an opening is formed in a region where the p-type region 123 is removed. Formed to have.
  • step S10a the p-type region 123 in the opening of the resist film is removed by etching.
  • step S11a the resist film remaining on the p-type region 123 is removed.
  • step S12a the n-side electrode 116 is formed on the n-type region 122, and the p-side electrode 117 is formed on the p-type region 123, whereby the back junction solar cell shown in FIG.
  • Patent Document 1 the manufacturing method of the back junction solar cell requires the use of photolithography, and thus the manufacturing cost is high, and improvement thereof has been demanded. There is also a demand for manufacturing a highly reliable and high-performance element.
  • the embodiment disclosed herein includes a semiconductor substrate, a first conductive type amorphous semiconductor film extending in the first direction on the semiconductor substrate, and a second conductive type extending in the second direction on the semiconductor substrate.
  • An amorphous semiconductor film, the edge of the second conductive amorphous semiconductor film is located on the edge of the first conductive amorphous semiconductor film, and the first conductive amorphous semiconductor At least one of the edge portion of the film and the edge portion of the second conductive type amorphous semiconductor film is a photoelectric conversion element having undulations.
  • the embodiment disclosed herein includes a step of patterning a first conductive type amorphous semiconductor film extending in a first direction on a semiconductor substrate, and a second conductive type extending in a second direction on the semiconductor substrate.
  • the step of patterning the amorphous semiconductor film and the step of patterning the second conductive type amorphous semiconductor film include a second conductive type amorphous semiconductor layer on the edge of the patterned first conductive type amorphous semiconductor film.
  • a step of patterning the second conductive amorphous semiconductor film so that the edge of the semiconductor film is located, the edge of the edge of the first conductive amorphous semiconductor film after patterning, and the second after patterning This is a method for manufacturing a photoelectric conversion element in which at least one of the edge portions of the conductive amorphous semiconductor film has undulations.
  • the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics and a method for manufacturing the photoelectric conversion element can be provided.
  • FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1.
  • (A) is a typical expanded sectional view of the overlap region of the heterojunction type back contact cell of Embodiment 1
  • (b) is a schematic when the overlap region shown in (a) is seen from the back side. It is a top view. It is a figure which shows the curve which shows the wave
  • 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 3.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 3.
  • FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the fourth embodiment.
  • 2 is a schematic cross-sectional view of a back junction solar cell described in Patent Document 1.
  • FIG. It is a flowchart of the manufacturing method of the back junction type solar cell shown by FIG.
  • the heterojunction back contact cell and the method of manufacturing the heterojunction back contact cell of Embodiments 1 to 4 will be described as an example of the photoelectric conversion element of the embodiment disclosed herein.
  • the same reference numerals represent the same or corresponding parts.
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment.
  • the heterojunction back contact cell of Embodiment 1 includes a first conductivity type semiconductor substrate 1 having a concavo-convex structure on a first surface 1 a serving as a light receiving surface, and a back surface of the semiconductor substrate 1.
  • the first i-type amorphous semiconductor film 2 on the second surface 1b and the second i-type amorphous semiconductor film 2 adjacent to the first i-type amorphous semiconductor film 2 on the second surface 1b of the semiconductor substrate 1 The i-type amorphous semiconductor film 4, the first conductive amorphous semiconductor film 3 on the first i-type amorphous semiconductor film 2, and the second on the second i-type amorphous semiconductor film 4
  • a conductive amorphous semiconductor film 5 a first electrode 7 on the first conductive amorphous semiconductor film 3, and a second electrode 8 on the second conductive amorphous semiconductor film 5 are provided.
  • a first conductivity type region 51 is formed of a stacked body of the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3, and the second i-type amorphous semiconductor film 4 and the first conductivity-type amorphous semiconductor film 4
  • a second conductivity type region 52 is constituted by a laminate with the two conductivity type amorphous semiconductor film 5.
  • the first conductivity type semiconductor substrate 1 is an n-type single crystal silicon substrate, and the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 are i-type, respectively.
  • the first conductive amorphous semiconductor film 3 is an n-type amorphous silicon film
  • the second conductive amorphous semiconductor film 5 is a p-type amorphous silicon film
  • FIG. 2A shows a schematic enlarged cross-sectional view of the overlapping region of the heterojunction back contact cell of the first embodiment.
  • the second conductive type amorphous semiconductor film 5 is formed on the edge 3 a of the first conductive type amorphous semiconductor film 3 on the first i type amorphous semiconductor film 2. Since the edge 5a is positioned via the second i-type amorphous semiconductor film 4, the first i-type amorphous semiconductor film 2, the first conductive amorphous semiconductor film 3, and the second i An overlapping region is formed in which the type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 are sequentially overlapped.
  • the portion closest to the second electrode 8 at the edge 3a of the first conductive type amorphous semiconductor film 3 is the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3
  • a portion of the edge 5 a of the second conductive type amorphous semiconductor film 5 closest to the first electrode 7 is an end 5 b of the edge 5 a of the second conductive type amorphous semiconductor film 5.
  • FIG. 2 (b) shows a schematic plan view when the overlapping region shown in FIG. 2 (a) is viewed from the back side.
  • the first conductivity type amorphous semiconductor film 3 extends in the first direction 41, and the first conductivity type non-contact.
  • An end 3 b of the edge 3 a of the crystalline semiconductor film 3 extends while undulating in the first direction 41.
  • the second conductive type amorphous semiconductor film 5 extends in the second direction 42, and the end portion 5 b of the edge 5 a of the second conductive type amorphous semiconductor film 5 undulates in the second direction 42. While extending.
  • the first i-type amorphous semiconductor film 2 and the first electrode 7 also extend in the first direction 41, respectively, and the second i-type amorphous semiconductor film 4 and the second electrode 8 also respectively. It extends in the second direction 42.
  • first direction 41 and the second direction 42 are the same direction will be described, but the first direction 41 and the second direction 42 may be different directions.
  • the undulation curve degree of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is 1.03 or more.
  • the passivating property of the second surface 1b of the semiconductor substrate 1 is improved by the overlapping region. Therefore, the reliability of the heterojunction back contact cell of the first embodiment is improved.
  • the open-circuit voltage (Voc) increases due to the improvement in passivation of the second surface 1b of the semiconductor substrate 1, and therefore the characteristics of the heterojunction back contact cell of the first embodiment tend to be improved. .
  • the undulation curve degree of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is 3.15 or less.
  • the degree of undulation is 3.15 or less, the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is in contact with the second electrode 8 which is an electrode for reverse conductivity type. Since it becomes difficult, the reliability of the heterojunction back contact cell of Embodiment 1 tends to be improved.
  • the undulation curve of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is 1.03 or more.
  • the undulation curve degree is 1.03 or more, the passability of the second surface 1b of the semiconductor substrate 1 can be improved by the overlapping region and Voc can be increased. The characteristics of the type back contact cell tend to be improved.
  • the undulation curve degree of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is 3.15 or less.
  • the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is in contact with the first electrode 7 which is an electrode for reverse conductivity type. Since it becomes difficult, the reliability of the heterojunction back contact cell of Embodiment 1 tends to be improved.
  • the “curvature” is obtained in a projection view (FIG. 3) when light is applied to the second surface 1 b of the semiconductor substrate 1 from a direction perpendicular to the second surface 1 b.
  • the length along the curve from the start point S to the end point E in the first direction 41 or the second direction 42 of the curve indicating the undulation of the end portions 3b and 5b is a straight line from the start point S to the end point E. It is a value divided by the length of the virtual line segment when virtual.
  • i-type is not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 ⁇ 10 15 / cm 3 and the p-type impurity concentration is 1 ⁇ (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities.
  • n-type means a state where the n-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more
  • p-type means that the p-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more. Means the state.
  • the n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry.
  • amorphous silicon includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling bonds of silicon atoms such as hydrogenated amorphous silicon. In which is terminated with hydrogen.
  • a semiconductor substrate 1 having a first surface 1 a serving as a light receiving surface is prepared, and a second surface that is a surface opposite to the first surface 1 a of the semiconductor substrate 1.
  • the first i-type amorphous semiconductor film 2 is formed so as to be in contact with the entire surface of 1b, and the first conductivity-type amorphous semiconductor film 3 is formed so as to be in contact with the entire surface of the first i-type amorphous semiconductor film 2.
  • the method for forming the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is not particularly limited, and for example, a plasma CVD (Chemical Vapor Deposition) method can be used.
  • an etching resist ink 10 is placed on the first conductive type amorphous semiconductor film 3.
  • the etching resist ink 10 can be placed on the first conductive type amorphous semiconductor film 3 in a strip shape extending in the first direction 41 by, for example, coating or printing.
  • the etching resist ink 10 is installed in a region where the first conductivity type region 51 is left.
  • Waviness of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is formed by bleeding of the etching resist ink 10 at the time of application or printing of the etching resist ink 10. Therefore, by adjusting conditions such as the amount and viscosity of the etching resist ink 10 and adjusting the bleeding of the etching resist ink 10, the undulation of the edge 3 b of the edge 3 a of the first conductive type amorphous semiconductor film 3 is controlled. It becomes possible to adjust.
  • the etching resist ink 10 is cured to form a cured etching resist ink 10a on the first conductive amorphous semiconductor film 3, as shown in FIG.
  • the etching resist ink 10a can be formed by curing the etching resist ink 10 by a method such as heating or irradiation with ultraviolet light.
  • the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 are partially thickened.
  • region 51 can be performed.
  • the cured etching resist ink 10a on the first conductivity type region 51 is removed.
  • the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type is formed.
  • a second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the amorphous semiconductor film 4.
  • a method for forming the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.
  • the etching in the thickness direction of each of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is also performed by the method using the etching resist ink 10 described above. It can be carried out. Therefore, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed by bleeding of the etching resist ink 10 at the time of application or printing of the etching resist ink 10. Therefore, by adjusting the conditions such as the amount and viscosity of the etching resist ink 10 and adjusting the bleeding of the etching resist ink 10, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is controlled. It becomes possible to adjust.
  • the first electrode 7 is formed on the first conductive amorphous semiconductor film 3 and the second electrode 8 is formed on the second conductive amorphous semiconductor film 5.
  • the formation method of the 1st electrode 7 and the 2nd electrode 8 is not specifically limited, For example, a vapor deposition method etc. can be used.
  • the manufacturing cost of Embodiment 1 does not need to be manufactured using photolithography as in the conventional Patent Document 1, the manufacturing cost can be significantly reduced.
  • the manufacturing cost per one heterojunction type back contact cell should be 1/10 or less compared to the case where patterning of the first conductivity type region 51 and the second conductivity type region 52 is performed using photolithography. Can do.
  • the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 extends while undulating in the first direction 41, and the second The end portion 5 b of the edge portion 5 a of the conductive amorphous semiconductor film 5 extends while undulating in the second direction 42. Therefore, the first conductivity type amorphous on the second surface 1b of the semiconductor substrate 1 is compared with the case where the edge portions of these films are formed to extend linearly using, for example, photolithography. The formation area of the overlapping region between the edge 3a of the crystalline semiconductor film 3 and the edge 5a of the second conductive type amorphous semiconductor film 5 can be increased.
  • the passivation property of the second surface 1b of the semiconductor substrate 1 in the overlapping region can be improved, so that the reliability of the heterojunction back contact cell of the first embodiment is improved and the heterogeneity of the first embodiment is improved.
  • the Voc of the junction type back contact cell is increased and the characteristics are improved.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first conductivity type is p-type and the second conductivity type is n-type. The same effect as described above can be obtained.
  • edge part 3b of the edge part 3a of the 1st conductivity type amorphous semiconductor film 3 and the edge part 5b of the edge part 5a of the 2nd conductivity type amorphous semiconductor film 5 have a wave
  • at least one of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 and the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 has waviness. It only has to be.
  • the heterojunction back contact cell of Embodiment 2 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are each performed using an etching paste.
  • an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2 will be described.
  • a first i-type amorphous semiconductor film 2 and a first conductive amorphous semiconductor film 3 are formed in this order on the second surface 1 b of the semiconductor substrate 1.
  • an etching paste 11 is placed on the first conductive type amorphous semiconductor film 3.
  • the etching paste 11 can be placed on the first conductive type amorphous semiconductor film 3 in a strip shape extending in the first direction 41 by, for example, coating or printing.
  • the etching paste 11 is placed in a region where the first conductivity type region 51 is left.
  • the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is formed by the bleeding of the etching paste 11 when the etching paste 11 is applied or printed. Therefore, the undulation of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is adjusted by adjusting the conditions such as the amount and viscosity of the etching paste 11 and adjusting the bleeding of the etching paste 11. It becomes possible.
  • the etching paste 11 is baked by heating the etching paste 11, and the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor Each part of the film 3 is etched in the thickness direction.
  • the etching paste 11 fires through the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 while etching in the thickness direction during firing, and the fired etching paste 11a becomes the semiconductor. It contacts the second surface 1b of the substrate 1. Thereafter, the baking etching paste 11a is removed, and a part of the second surface 1b of the semiconductor substrate 1 is exposed as shown in FIG. Thereby, the patterning of the 1st conductivity type area
  • the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type non-type is formed.
  • a second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the crystalline semiconductor film 4.
  • the etching in the thickness direction of a part of each of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is also performed by the method using the etching paste 11 described above. be able to.
  • the undulation of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is formed by bleeding of the etching paste 11 when the etching paste 11 is applied or printed. Therefore, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is adjusted by adjusting conditions such as the amount and viscosity of the etching paste 11 and adjusting the bleeding of the etching paste 11. It becomes possible.
  • the heterojunction back contact cell of the second embodiment can be manufactured.
  • the heterojunction back contact cell of Embodiment 3 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are each performed using lift-off ink.
  • the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are each performed using lift-off ink.
  • lift-off ink 12 is installed on the second surface 1 b of the semiconductor substrate 1.
  • the lift-off ink 12 can be installed on the second surface 1b of the semiconductor substrate 1 in a strip shape extending in the first direction 41, for example, by coating or printing.
  • the lift-off ink 12 is installed in an area where the first conductivity type area 51 is not formed.
  • the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is formed by bleeding of the lift-off ink 12 when the lift-off ink 12 is applied or printed. Therefore, by adjusting conditions such as the amount and viscosity of the lift-off ink 12 and adjusting the bleeding of the lift-off ink 12, the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is adjusted. It becomes possible.
  • the first i-type amorphous semiconductor film 2 and the first i-type amorphous semiconductor film 2 are formed so as to cover the second surface 1 b of the semiconductor substrate 1 after the lift-off ink 12 is installed.
  • One-conductivity type amorphous semiconductor film 3 is formed in this order.
  • the lift-off ink 12 is removed together with the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 located on the lift-off ink 12, thereby forming a semiconductor substrate as shown in FIG. A part of the first second surface 1b is exposed. Thereby, the patterning of the 1st conductivity type area
  • the second conductivity type region 52 is patterned.
  • the patterning of the second conductivity type region 52 can also be performed by the method using the lift-off ink 12 described above.
  • undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed by bleeding of the lift-off ink 12 at the time of application of the lift-off ink 12 or printing. Therefore, the undulation of the edge 5b of the edge 5a of the second conductive type amorphous semiconductor film 5 is adjusted by adjusting conditions such as the amount and viscosity of the lift-off ink 12 and adjusting the bleeding of the lift-off ink 12. It becomes possible.
  • the heterojunction back contact cell of the third embodiment can be manufactured.
  • the heterojunction back contact cell of Embodiment 4 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are performed by laser ablation, respectively.
  • the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are performed by laser ablation, respectively.
  • a first i-type amorphous semiconductor film 2 and a first conductive amorphous semiconductor film 3 are formed in this order on the second surface 1 b of the semiconductor substrate 1.
  • the first conductive type amorphous semiconductor film 3 is irradiated with a laser beam 13.
  • the laser beam 13 is irradiated while being moved in a strip shape extending in the first direction 41.
  • the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 in the irradiation region of the laser beam 13 are removed in a belt shape extending in the first direction 41 by laser ablation, As shown in FIG. 8, patterning of the first conductivity type region 51 is performed.
  • the undulation of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is formed depending on the laser ablation condition. Therefore, the undulation of the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 can be adjusted by adjusting the conditions of laser ablation such as the shape and size of the irradiation region of the laser beam 13. It becomes possible.
  • the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type is formed.
  • a second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the amorphous semiconductor film 4.
  • the second conductivity type region 52 is patterned.
  • the patterning of the second conductivity type region 52 can also be performed by the laser ablation described above.
  • the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed depending on the shape of the irradiation region of the laser beam 13. Therefore, it is possible to adjust the undulation of the end portion 5 b of the edge portion 5 a of the second conductive type amorphous semiconductor film 5 by adjusting the shape of the irradiation region of the laser beam 13.
  • the heterojunction back contact cell of the fourth embodiment can be manufactured.
  • An embodiment disclosed herein includes a semiconductor substrate, a first conductivity type amorphous semiconductor film extending in a first direction on the semiconductor substrate, and a first extension extending in a second direction on the semiconductor substrate.
  • At least one of the edge part of the crystalline semiconductor film and the edge part of the second conductive type amorphous semiconductor film is a photoelectric conversion element having undulations.
  • the photoelectric conversion element of the embodiment disclosed herein may have a undulation in which the edge of the edge of the first conductive type amorphous semiconductor film extends in the first direction. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the photoelectric conversion element of the embodiment disclosed herein may have a undulation in which the edge of the edge of the second conductive amorphous semiconductor film extends in the second direction. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the degree of undulation is 1.03 or more. In this case, the characteristics of the photoelectric conversion element tend to be further improved.
  • the degree of undulation is 3.15 or less. In this case, the reliability of the photoelectric conversion element tends to be further improved.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous semiconductor film between the semiconductor substrate and the first conductive amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the first i-type amorphous semiconductor film may be in contact with each of the semiconductor substrate and the first conductivity-type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the photoelectric conversion element according to the embodiment disclosed herein may further include a second i-type amorphous semiconductor film between the semiconductor substrate and the second conductive amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the second i-type amorphous semiconductor film may be in contact with each of the semiconductor substrate and the second conductivity-type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a first electrode on the first conductive type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a second electrode on the second conductivity type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
  • a step of patterning a first conductivity type amorphous semiconductor film extending in a first direction on a semiconductor substrate, and a step of extending in a second direction on the semiconductor substrate are described.
  • the step of patterning the two-conductivity-type amorphous semiconductor film and the step of patterning the second-conductivity-type amorphous semiconductor film include the second conductivity-type on the edge of the patterned first-conductivity-type amorphous semiconductor film.
  • Including a step of patterning the second conductive type amorphous semiconductor film so that the edge of the amorphous semiconductor film is located, and the edge of the edge of the first conductive type amorphous semiconductor film after patterning and after patterning This is a method for manufacturing a photoelectric conversion element in which at least one of the edge portions of the second conductivity type amorphous semiconductor film has undulations. With such a configuration, manufacturing cost can be reduced, and a highly reliable and high-performance photoelectric conversion element can be manufactured.
  • the edge of the edge of the first conductive type amorphous semiconductor film may have a undulation extending in the first direction. Good. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the degree of undulation is 1.03 or more. In this case, a photoelectric conversion element with further improved characteristics can be manufactured.
  • the degree of undulation is 3.15 or less. In this case, a photoelectric conversion element with further improved reliability can be manufactured.
  • the step of patterning the first conductive type amorphous semiconductor film is performed from a group consisting of etching resist ink, etching paste, lift-off ink, and laser ablation.
  • a step of patterning the first conductive type amorphous semiconductor film by at least one selected method may be included. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the first conductive type amorphous semiconductor film includes patterning the first conductive type amorphous semiconductor film with an etching resist ink.
  • the step of patterning with an etching resist ink includes a step of placing the etching resist ink on a part of the first conductive type amorphous semiconductor film, a step of curing the etching resist ink, and a cured etching resist And a step of etching the first conductive type amorphous semiconductor film using the ink as a mask. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film with an etching paste.
  • the step of patterning with the etching paste includes the step of placing the etching paste on a part of the first conductive type amorphous semiconductor film, and the step of heating the etching paste to form the first conductive type amorphous semiconductor film. And an etching step. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film with lift-off ink.
  • the step of patterning with lift-off ink includes a step of installing lift-off ink on a semiconductor substrate, a step of forming a first conductivity type amorphous semiconductor film so as to cover the semiconductor substrate on which the lift-off ink is installed, and And removing the lift-off ink together with the first conductive type amorphous semiconductor film located on the lift-off ink. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film by laser ablation.
  • the step of patterning by laser ablation includes a step of forming a first conductive type amorphous semiconductor film on a semiconductor substrate and a first conductive type by irradiating the first conductive type amorphous semiconductor film with laser light. And removing a part of the type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the second conductive type amorphous semiconductor film is performed from the group consisting of etching resist ink, etching paste, lift-off ink, and laser ablation.
  • a step of patterning the second conductive type amorphous semiconductor film by at least one selected method may be included. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the second conductive type amorphous semiconductor film includes patterning the second conductive type amorphous semiconductor film with an etching resist ink.
  • the step of patterning with an etching resist ink includes a step of placing the etching resist ink on a part of the second conductive type amorphous semiconductor film, a step of curing the etching resist ink, and a cured etching resist And etching the second conductive type amorphous semiconductor film using the ink as a mask. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film with an etching paste.
  • the step of patterning with the etching paste includes a step of placing the etching paste on a part of the second conductive type amorphous semiconductor film, and a step of heating the etching paste to form the second conductive type amorphous semiconductor film. And an etching step. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film with lift-off ink.
  • the step of patterning with lift-off ink includes a step of installing lift-off ink on a semiconductor substrate, a step of forming a second conductivity type amorphous semiconductor film so as to cover the semiconductor substrate on which the lift-off ink is installed, and And removing the lift-off ink together with the second conductive type amorphous semiconductor film located on the lift-off ink. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film by laser ablation.
  • the step of patterning by laser ablation includes a step of forming a second conductive type amorphous semiconductor film on the semiconductor substrate and a second conductive type by irradiating the second conductive type amorphous semiconductor film with laser light. And removing a part of the type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
  • Embodiment disclosed here can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, and may be suitably used for the manufacturing method of a solar cell and a solar cell, Especially preferably, it is hetero. There is a possibility that it can be used in a manufacturing method of a junction type back contact cell and a hetero junction type back contact cell.

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Abstract

This photoelectric conversion element is provided with: a semiconductor substrate (1); an amorphous semiconductor film (3) of a first conductivity type, which extends in a first direction (41) on the semiconductor substrate (1); and an amorphous semiconductor film (5) of a second conductivity type, which extends in a second direction (42) on the semiconductor substrate (1). A peripheral portion (5a) of the amorphous semiconductor film (5) of the second conductivity type is positioned on a peripheral portion (3a) of the amorphous semiconductor film (3) of the first conductivity type, and at least one of the edge (3b) of the peripheral portion (3a) of the amorphous semiconductor film (3) of the first conductivity type and the edge (5b) of the peripheral portion (5a) of the amorphous semiconductor film (5) of the second conductivity type is wavy.

Description

光電変換素子および光電変換素子の製造方法Photoelectric conversion element and method for producing photoelectric conversion element
 本発明は、光電変換素子および光電変換素子の製造方法に関する。 The present invention relates to a photoelectric conversion element and a method for manufacturing the photoelectric conversion element.
 太陽光エネルギを電気エネルギに直接変換する太陽電池は、近年、特に、地球環境問題の観点から、次世代のエネルギ源としての期待が急激に高まっている。なかでも、現在、最も多く製造および販売されている太陽電池は、太陽光が入射する側の面である受光面と受光面の反対側である裏面とにそれぞれ電極が形成された構造のものである。 In recent years, expectations for solar cells that directly convert solar energy into electrical energy have increased rapidly, especially from the viewpoint of global environmental problems. Of these, the most manufactured and sold solar cells have a structure in which electrodes are formed on the light receiving surface on the side where sunlight enters and the back surface on the opposite side of the light receiving surface, respectively. is there.
 しかしながら、受光面に電極を形成した場合には、電極における太陽光の反射および吸収があることから、電極の面積分だけ入射する太陽光の量が減少する。そのため、裏面のみに電極を形成した裏面接合型太陽電池の開発が進められている(たとえば特許文献1参照)。 However, when an electrode is formed on the light receiving surface, sunlight is reflected and absorbed by the electrode, so that the amount of incident sunlight is reduced by the area of the electrode. Therefore, development of a back junction solar cell in which an electrode is formed only on the back surface is underway (see, for example, Patent Document 1).
 図16に、特許文献1に記載の裏面接合型太陽電池の模式的な断面図を示す。図16に示される裏面接合型太陽電池は、n型単結晶シリコン基板等の基板111の受光面上に、i型非晶質半導体層119、n型非晶質半導体層120、および保護膜124が順次積層された構成を有する。 FIG. 16 shows a schematic cross-sectional view of the back junction solar cell described in Patent Document 1. The back junction solar cell shown in FIG. 16 has an i-type amorphous semiconductor layer 119, an n-type amorphous semiconductor layer 120, and a protective film 124 on a light-receiving surface of a substrate 111 such as an n-type single crystal silicon substrate. Are sequentially stacked.
 基板111の裏面のn側電極116に対応するn型領域122においては、基板111上に、i型非晶質半導体層112、n型非晶質半導体層114、絶縁層121、およびn側電極116が順次積層されている。また、絶縁層121を貫通する穴を介して、n型非晶質半導体層114とn側電極116とが接続されている。 In the n-type region 122 corresponding to the n-side electrode 116 on the back surface of the substrate 111, the i-type amorphous semiconductor layer 112, the n-type amorphous semiconductor layer 114, the insulating layer 121, and the n-side electrode are formed on the substrate 111. 116 are sequentially stacked. Further, the n-type amorphous semiconductor layer 114 and the n-side electrode 116 are connected through a hole penetrating the insulating layer 121.
 基板111の裏面のp側電極117に対応するp型領域123においては、基板111上に、i型非晶質半導体層113、p型非晶質半導体層115、およびp側電極117が順次積層されている。 In the p-type region 123 corresponding to the p-side electrode 117 on the back surface of the substrate 111, the i-type amorphous semiconductor layer 113, the p-type amorphous semiconductor layer 115, and the p-side electrode 117 are sequentially stacked on the substrate 111. Has been.
 n側電極116およびp側電極117は、それぞれ、透明導電層116c,117c上に金属層116b,117bおよび有機被膜116a,117aをこの順序で設けて形成されている。 The n-side electrode 116 and the p-side electrode 117 are formed by providing metal layers 116b and 117b and organic coatings 116a and 117a in this order on the transparent conductive layers 116c and 117c, respectively.
 図17に、図16に示される裏面接合型太陽電池の製造方法のフローチャートを示す。以下、図17を参照して、図16に示される裏面接合型太陽電池の製造方法について説明する。まず、ステップS1aにおいて、基板111の受光面上および裏面上にそれぞれi型非晶質半導体層119およびi型非晶質半導体層112をCVD法により形成する。 FIG. 17 shows a flowchart of the manufacturing method of the back junction solar cell shown in FIG. Hereinafter, with reference to FIG. 17, the manufacturing method of the back junction type solar cell shown by FIG. 16 is demonstrated. First, in step S1a, an i-type amorphous semiconductor layer 119 and an i-type amorphous semiconductor layer 112 are formed on the light-receiving surface and the back surface of the substrate 111 by a CVD method, respectively.
 次に、ステップS2aにおいて、基板111の受光面側のi型非晶質半導体層119の全面および裏面側のi型非晶質半導体層112の全面にそれぞれn型非晶質半導体層120およびn型非晶質半導体層114をCVD法により形成する。 Next, in step S2a, an n-type amorphous semiconductor layer 120 and an n-type amorphous semiconductor layer 120 are formed on the entire surface of the i-type amorphous semiconductor layer 119 on the light-receiving surface side of the substrate 111 and the entire surface of the i-type amorphous semiconductor layer 112 on the back surface side, respectively. A type amorphous semiconductor layer 114 is formed by a CVD method.
 次に、ステップS3aにおいて、基板111の受光面側のn型非晶質半導体層120の全面および裏面側のn型非晶質半導体層114の全面にそれぞれ保護膜124および絶縁層121をCVD法により形成する。 Next, in step S3a, the protective film 124 and the insulating layer 121 are formed on the entire surface of the n-type amorphous semiconductor layer 120 on the light-receiving surface side of the substrate 111 and the entire surface of the n-type amorphous semiconductor layer 114 on the back surface side by CVD. To form.
 次に、ステップS4aにおいて、フォトリソグラフィによりn型領域122をパターニングするために、絶縁層121上にレジストパターンを形成する。レジストパターンは、i型非晶質半導体層112とn型非晶質半導体層114との積層体からなるn型領域122を残す領域にレジスト膜を形成し、n型領域122を除去する領域に開口部を有するように形成される。 Next, in step S4a, a resist pattern is formed on the insulating layer 121 in order to pattern the n-type region 122 by photolithography. In the resist pattern, a resist film is formed in a region where the n-type region 122 made of a laminate of the i-type amorphous semiconductor layer 112 and the n-type amorphous semiconductor layer 114 is left, and the n-type region 122 is removed. It is formed to have an opening.
 次に、ステップS5aにおいて、レジストパターンの開口部におけるn型領域122をエッチングにより除去する。 Next, in step S5a, the n-type region 122 in the opening of the resist pattern is removed by etching.
 次に、ステップS6aにおいて、n型領域122上に残存するレジスト膜を除去する。
 次に、ステップS7aにおいて、絶縁層121およびn型領域122が残存する基板111の裏面を覆うようにi型非晶質半導体層113をCVD法により形成する。
Next, in step S6a, the resist film remaining on the n-type region 122 is removed.
Next, in step S7a, an i-type amorphous semiconductor layer 113 is formed by CVD so as to cover the back surface of the substrate 111 where the insulating layer 121 and the n-type region 122 remain.
 次に、ステップS8aにおいて、i型非晶質半導体層113の全面にp型非晶質半導体層115をCVD法により形成する。 Next, in step S8a, a p-type amorphous semiconductor layer 115 is formed on the entire surface of the i-type amorphous semiconductor layer 113 by a CVD method.
 次に、ステップS9aにおいて、p型非晶質半導体層115上にレジスト膜を形成する。レジスト膜は、i型非晶質半導体層113とp型非晶質半導体層115との積層体からなるp型領域123を残す領域に形成し、p型領域123を除去する領域に開口部を有するように形成される。 Next, in step S9a, a resist film is formed on the p-type amorphous semiconductor layer 115. The resist film is formed in a region where the p-type region 123 made of a stacked body of the i-type amorphous semiconductor layer 113 and the p-type amorphous semiconductor layer 115 is left, and an opening is formed in a region where the p-type region 123 is removed. Formed to have.
 次に、ステップS10aにおいて、レジスト膜の開口部におけるp型領域123をエッチングにより除去する。 Next, in step S10a, the p-type region 123 in the opening of the resist film is removed by etching.
 次に、ステップS11aにおいて、p型領域123上に残存するレジスト膜を除去する。 Next, in step S11a, the resist film remaining on the p-type region 123 is removed.
 最後に、ステップS12aにおいて、n型領域122上にn側電極116を形成し、p型領域123上にp側電極117を形成することによって、図16に示される裏面接合型太陽電池が製造される。 Finally, in step S12a, the n-side electrode 116 is formed on the n-type region 122, and the p-side electrode 117 is formed on the p-type region 123, whereby the back junction solar cell shown in FIG. The
特開2013-211385号公報JP 2013-2111385 A
 しかしながら、特許文献1においては、裏面接合型太陽電池の製造方法はフォトリソグラフィを用いる必要があったため製造コストが高く、その改善が要望されていた。また、高信頼性および高特性の素子を作製することも要望されている。 However, in Patent Document 1, the manufacturing method of the back junction solar cell requires the use of photolithography, and thus the manufacturing cost is high, and improvement thereof has been demanded. There is also a demand for manufacturing a highly reliable and high-performance element.
 ここで開示された実施形態は、半導体基板と、半導体基板上において第1方向に延在する第1導電型非晶質半導体膜と、半導体基板上において第2方向に延在する第2導電型非晶質半導体膜と、を備え、第1導電型非晶質半導体膜の縁部上に第2導電型非晶質半導体膜の縁部が位置しており、第1導電型非晶質半導体膜の縁部の端部および第2導電型非晶質半導体膜の縁部の端部の少なくとも一方がうねりを有している光電変換素子である。 The embodiment disclosed herein includes a semiconductor substrate, a first conductive type amorphous semiconductor film extending in the first direction on the semiconductor substrate, and a second conductive type extending in the second direction on the semiconductor substrate. An amorphous semiconductor film, the edge of the second conductive amorphous semiconductor film is located on the edge of the first conductive amorphous semiconductor film, and the first conductive amorphous semiconductor At least one of the edge portion of the film and the edge portion of the second conductive type amorphous semiconductor film is a photoelectric conversion element having undulations.
 ここで開示された実施形態は、半導体基板上において第1方向に延在する第1導電型非晶質半導体膜をパターニングする工程と、半導体基板上において第2方向に延在する第2導電型非晶質半導体膜をパターニングする工程と、第2導電型非晶質半導体膜をパターニングする工程は、パターニング後の第1導電型非晶質半導体膜の縁部上に第2導電型非晶質半導体膜の縁部が位置するように第2導電型非晶質半導体膜をパターニングする工程を含み、パターニング後の第1導電型非晶質半導体膜の縁部の端部およびパターニング後の第2導電型非晶質半導体膜の縁部の端部の少なくとも一方がうねりを有している光電変換素子の製造方法である。 The embodiment disclosed herein includes a step of patterning a first conductive type amorphous semiconductor film extending in a first direction on a semiconductor substrate, and a second conductive type extending in a second direction on the semiconductor substrate. The step of patterning the amorphous semiconductor film and the step of patterning the second conductive type amorphous semiconductor film include a second conductive type amorphous semiconductor layer on the edge of the patterned first conductive type amorphous semiconductor film. A step of patterning the second conductive amorphous semiconductor film so that the edge of the semiconductor film is located, the edge of the edge of the first conductive amorphous semiconductor film after patterning, and the second after patterning This is a method for manufacturing a photoelectric conversion element in which at least one of the edge portions of the conductive amorphous semiconductor film has undulations.
 ここで開示された実施形態によれば、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子およびその製造方法を提供することができる。 According to the embodiment disclosed herein, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics and a method for manufacturing the photoelectric conversion element can be provided.
実施形態1のヘテロ接合型バックコンタクトセルの模式的な断面図である。FIG. 3 is a schematic cross-sectional view of the heterojunction back contact cell of Embodiment 1. (a)は実施形態1のヘテロ接合型バックコンタクトセルの重なり領域の模式的な拡大断面図であり、(b)は(a)に示される重なり領域を裏面側から見たときの模式的な平面図である。(A) is a typical expanded sectional view of the overlap region of the heterojunction type back contact cell of Embodiment 1, and (b) is a schematic when the overlap region shown in (a) is seen from the back side. It is a top view. 半導体基板の第2の面に対して第2の面に垂直な方向から光を当てたときの投影図において得られる端部のうねりを示す曲線を示す図である。It is a figure which shows the curve which shows the wave | undulation of the edge part obtained in the projection view when light is irradiated from the direction perpendicular | vertical to a 2nd surface with respect to the 2nd surface of a semiconductor substrate. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。6 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 1. FIG. 実施形態2のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the second embodiment. 実施形態2のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the second embodiment. 実施形態3のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 3. 実施形態3のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell of Embodiment 3. 実施形態4のヘテロ接合型バックコンタクトセルの製造方法の一例の製造工程の一部について図解する模式的な断面図である。FIG. 10 is a schematic cross-sectional view illustrating a part of the manufacturing process of the example of the method for manufacturing the heterojunction back contact cell according to the fourth embodiment. 特許文献1に記載の裏面接合型太陽電池の模式的な断面図である。2 is a schematic cross-sectional view of a back junction solar cell described in Patent Document 1. FIG. 図16に示される裏面接合型太陽電池の製造方法のフローチャートである。It is a flowchart of the manufacturing method of the back junction type solar cell shown by FIG.
 以下、ここで開示される実施形態の光電変換素子の一例として実施形態1~4のヘテロ接合型バックコンタクトセルおよびヘテロ接合型バックコンタクトセルの製造方法について説明する。なお、実施形態の説明に用いられる図面において、同一の参照符号は、同一部分または相当部分を表わすものとする。 Hereinafter, the heterojunction back contact cell and the method of manufacturing the heterojunction back contact cell of Embodiments 1 to 4 will be described as an example of the photoelectric conversion element of the embodiment disclosed herein. In the drawings used to describe the embodiments, the same reference numerals represent the same or corresponding parts.
 [実施形態1]
 <ヘテロ接合型バックコンタクトセルの構造>
 図1に、実施形態1のヘテロ接合型バックコンタクトセルの模式的な断面図を示す。図1に示されるように、実施形態1のヘテロ接合型バックコンタクトセルは、受光面となる第1の面1aに凹凸構造を備えた第1導電型の半導体基板1と、半導体基板1の裏面となる第2の面1b上の第1のi型非晶質半導体膜2と、半導体基板1の第2の面1b上において第1のi型非晶質半導体膜2に隣接する第2のi型非晶質半導体膜4と、第1のi型非晶質半導体膜2上の第1導電型非晶質半導体膜3と、第2のi型非晶質半導体膜4上の第2導電型非晶質半導体膜5と、第1導電型非晶質半導体膜3上の第1電極7と、第2導電型非晶質半導体膜5上の第2電極8とを備えている。第1のi型非晶質半導体膜2と第1導電型非晶質半導体膜3との積層体から第1導電型領域51が構成され、第2のi型非晶質半導体膜4と第2導電型非晶質半導体膜5との積層体から第2導電型領域52が構成されている。
[Embodiment 1]
<Structure of heterojunction back contact cell>
FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment. As shown in FIG. 1, the heterojunction back contact cell of Embodiment 1 includes a first conductivity type semiconductor substrate 1 having a concavo-convex structure on a first surface 1 a serving as a light receiving surface, and a back surface of the semiconductor substrate 1. The first i-type amorphous semiconductor film 2 on the second surface 1b and the second i-type amorphous semiconductor film 2 adjacent to the first i-type amorphous semiconductor film 2 on the second surface 1b of the semiconductor substrate 1 The i-type amorphous semiconductor film 4, the first conductive amorphous semiconductor film 3 on the first i-type amorphous semiconductor film 2, and the second on the second i-type amorphous semiconductor film 4 A conductive amorphous semiconductor film 5, a first electrode 7 on the first conductive amorphous semiconductor film 3, and a second electrode 8 on the second conductive amorphous semiconductor film 5 are provided. A first conductivity type region 51 is formed of a stacked body of the first i-type amorphous semiconductor film 2 and the first conductivity-type amorphous semiconductor film 3, and the second i-type amorphous semiconductor film 4 and the first conductivity-type amorphous semiconductor film 4 A second conductivity type region 52 is constituted by a laminate with the two conductivity type amorphous semiconductor film 5.
 本実施形態においては、第1導電型の半導体基板1をn型単結晶シリコン基板とし、第1のi型非晶質半導体膜2および第2のi型非晶質半導体膜4をそれぞれi型非晶質シリコン膜とし、第1導電型非晶質半導体膜3をn型非晶質シリコン膜とし、第2導電型非晶質半導体膜5をp型非晶質シリコン膜とした場合について説明する。 In the present embodiment, the first conductivity type semiconductor substrate 1 is an n-type single crystal silicon substrate, and the first i-type amorphous semiconductor film 2 and the second i-type amorphous semiconductor film 4 are i-type, respectively. A case where an amorphous silicon film is used, the first conductive amorphous semiconductor film 3 is an n-type amorphous silicon film, and the second conductive amorphous semiconductor film 5 is a p-type amorphous silicon film will be described. To do.
 図2(a)に、実施形態1のヘテロ接合型バックコンタクトセルの重なり領域の模式的な拡大断面図を示す。図2(a)に示すように、第1のi型非晶質半導体膜2上の第1導電型非晶質半導体膜3の縁部3a上に第2導電型非晶質半導体膜5の縁部5aが第2のi型非晶質半導体膜4を介して位置することによって、第1のi型非晶質半導体膜2、第1導電型非晶質半導体膜3、第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5が順次重なってなる重なり領域が構成されている。本実施形態において、第1導電型非晶質半導体膜3の縁部3aの第2電極8に最も近い部分が第1導電型非晶質半導体膜3の縁部3aの端部3bであり、第2導電型非晶質半導体膜5の縁部5aの第1電極7に最も近い部分が第2導電型非晶質半導体膜5の縁部5aの端部5bである。 FIG. 2A shows a schematic enlarged cross-sectional view of the overlapping region of the heterojunction back contact cell of the first embodiment. As shown in FIG. 2A, the second conductive type amorphous semiconductor film 5 is formed on the edge 3 a of the first conductive type amorphous semiconductor film 3 on the first i type amorphous semiconductor film 2. Since the edge 5a is positioned via the second i-type amorphous semiconductor film 4, the first i-type amorphous semiconductor film 2, the first conductive amorphous semiconductor film 3, and the second i An overlapping region is formed in which the type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 are sequentially overlapped. In the present embodiment, the portion closest to the second electrode 8 at the edge 3a of the first conductive type amorphous semiconductor film 3 is the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3, A portion of the edge 5 a of the second conductive type amorphous semiconductor film 5 closest to the first electrode 7 is an end 5 b of the edge 5 a of the second conductive type amorphous semiconductor film 5.
 図2(b)に、図2(a)に示される重なり領域を裏面側から見たときの模式的な平面図を示す。図2(b)に示すように、実施形態1のヘテロ接合型バックコンタクトセルにおいて、第1導電型非晶質半導体膜3は第1方向41に延在しているとともに、第1導電型非晶質半導体膜3の縁部3aの端部3bは第1方向41にうねりながら延在している。また、第2導電型非晶質半導体膜5は第2方向42に延在しているとともに、第2導電型非晶質半導体膜5の縁部5aの端部5bは第2方向42にうねりながら延在している。また、第1のi型非晶質半導体膜2および第1電極7もそれぞれ第1方向41に延在しているとともに、第2のi型非晶質半導体膜4および第2電極8もそれぞれ第2方向42に延在している。なお、本実施形態においては、第1方向41と第2方向42とが同一方向である場合について説明するが、第1方向41と第2方向42とは異なる方向であってもよい。 FIG. 2 (b) shows a schematic plan view when the overlapping region shown in FIG. 2 (a) is viewed from the back side. As shown in FIG. 2B, in the heterojunction back contact cell of Embodiment 1, the first conductivity type amorphous semiconductor film 3 extends in the first direction 41, and the first conductivity type non-contact. An end 3 b of the edge 3 a of the crystalline semiconductor film 3 extends while undulating in the first direction 41. The second conductive type amorphous semiconductor film 5 extends in the second direction 42, and the end portion 5 b of the edge 5 a of the second conductive type amorphous semiconductor film 5 undulates in the second direction 42. While extending. The first i-type amorphous semiconductor film 2 and the first electrode 7 also extend in the first direction 41, respectively, and the second i-type amorphous semiconductor film 4 and the second electrode 8 also respectively. It extends in the second direction 42. In the present embodiment, the case where the first direction 41 and the second direction 42 are the same direction will be described, but the first direction 41 and the second direction 42 may be different directions.
 第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりの曲線度は1.03以上であることが好ましい。当該うねりの曲線度が1.03以上である場合には、重なり領域により半導体基板1の第2の面1bのパッシベーション性が向上するため、実施形態1のヘテロ接合型バックコンタクトセルの信頼性を向上させることができる。また、この場合には、半導体基板1の第2の面1bのパッシベーション性の向上により開放電圧(Voc)が上昇するため、実施形態1のヘテロ接合型バックコンタクトセルの特性が向上する傾向にある。 It is preferable that the undulation curve degree of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is 1.03 or more. When the undulation curve degree is 1.03 or more, the passivating property of the second surface 1b of the semiconductor substrate 1 is improved by the overlapping region. Therefore, the reliability of the heterojunction back contact cell of the first embodiment is improved. Can be improved. In this case, the open-circuit voltage (Voc) increases due to the improvement in passivation of the second surface 1b of the semiconductor substrate 1, and therefore the characteristics of the heterojunction back contact cell of the first embodiment tend to be improved. .
 第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりの曲線度は3.15以下であることが好ましい。当該うねりの曲線度が3.15以下である場合には、第1導電型非晶質半導体膜3の縁部3aの端部3bが逆導電型用の電極である第2電極8と接触しにくくなることから、実施形態1のヘテロ接合型バックコンタクトセルの信頼性が向上する傾向にある。 It is preferable that the undulation curve degree of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is 3.15 or less. When the degree of undulation is 3.15 or less, the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is in contact with the second electrode 8 which is an electrode for reverse conductivity type. Since it becomes difficult, the reliability of the heterojunction back contact cell of Embodiment 1 tends to be improved.
 第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりの曲線度は1.03以上であることが好ましい。当該うねりの曲線度が1.03以上である場合には、重なり領域により半導体基板1の第2の面1bのパッシベーション性が向上してVocを上昇させることができるため、実施形態1のヘテロ接合型バックコンタクトセルの特性が向上する傾向にある。 It is preferable that the undulation curve of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is 1.03 or more. When the undulation curve degree is 1.03 or more, the passability of the second surface 1b of the semiconductor substrate 1 can be improved by the overlapping region and Voc can be increased. The characteristics of the type back contact cell tend to be improved.
 第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりの曲線度は3.15以下であることが好ましい。当該うねりの曲線度が3.15以下である場合には、第2導電型非晶質半導体膜5の縁部5aの端部5bが逆導電型用の電極である第1電極7と接触しにくくなることから、実施形態1のヘテロ接合型バックコンタクトセルの信頼性が向上する傾向にある。 It is preferable that the undulation curve degree of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is 3.15 or less. When the undulation curve degree is 3.15 or less, the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is in contact with the first electrode 7 which is an electrode for reverse conductivity type. Since it becomes difficult, the reliability of the heterojunction back contact cell of Embodiment 1 tends to be improved.
 なお、本実施形態において、「曲線度」は、半導体基板1の第2の面1bに対して第2の面1bに垂直な方向から光を当てたときの投影図(図3)において得られる端部3b,5bのうねりを示す曲線の第1方向41または第2方向42における始点S点から終点E点までの曲線に沿った長さを始点S点から終点E点までが直線であると仮想したときの当該仮想の線分の長さで割った値である。 In the present embodiment, the “curvature” is obtained in a projection view (FIG. 3) when light is applied to the second surface 1 b of the semiconductor substrate 1 from a direction perpendicular to the second surface 1 b. The length along the curve from the start point S to the end point E in the first direction 41 or the second direction 42 of the curve indicating the undulation of the end portions 3b and 5b is a straight line from the start point S to the end point E. It is a value divided by the length of the virtual line segment when virtual.
 また、本実施形態において「i型」とは、完全な真性の状態だけでなく、十分に低濃度(n型不純物濃度が1×1015個/cm3未満、かつp型不純物濃度が1×1015個/cm3未満)であればn型またはp型の不純物が混入された状態のものも含む意味である。また、本実施形態において「n型」はn型不純物濃度が1×1015個/cm3以上の状態を意味し、「p型」はp型不純物濃度が1×1015個/cm3以上の状態を意味する。n型不純物濃度およびp型不純物濃度は、たとえば二次イオン質量分析法によって測定することができる。 Further, in this embodiment, “i-type” is not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 × 10 15 / cm 3 and the p-type impurity concentration is 1 × (Less than 10 15 / cm 3 ) is meant to include n-type or p-type impurities. In the present embodiment, “n-type” means a state where the n-type impurity concentration is 1 × 10 15 / cm 3 or more, and “p-type” means that the p-type impurity concentration is 1 × 10 15 / cm 3 or more. Means the state. The n-type impurity concentration and the p-type impurity concentration can be measured by, for example, secondary ion mass spectrometry.
 また、本実施形態において「非晶質シリコン」には、シリコン原子の未結合手が水素で終端されていない非晶質シリコンだけでなく、水素化非晶質シリコンなどのシリコン原子の未結合手が水素で終端されたものも含まれるものとする。 In this embodiment, “amorphous silicon” includes not only amorphous silicon in which the dangling bonds of silicon atoms are not terminated with hydrogen, but also dangling bonds of silicon atoms such as hydrogenated amorphous silicon. In which is terminated with hydrogen.
 <ヘテロ接合型バックコンタクトセルの製造方法>
 以下、図4~図10の模式的断面図を参照して、実施形態1のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。
<Method for manufacturing heterojunction back contact cell>
Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1 will be described with reference to the schematic cross-sectional views of FIGS.
 まず、図4に示すように、受光面となる第1の面1aを備えた半導体基板1を準備して、半導体基板1の第1の面1aとは反対側の面である第2の面1bの全面に接するように第1のi型非晶質半導体膜2を形成し、第1のi型非晶質半導体膜2の全面に接するように第1導電型非晶質半導体膜3を形成する。第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3の形成方法は特に限定されないが、たとえばプラズマCVD(Chemical Vapor Deposition)法を用いることができる。 First, as shown in FIG. 4, a semiconductor substrate 1 having a first surface 1 a serving as a light receiving surface is prepared, and a second surface that is a surface opposite to the first surface 1 a of the semiconductor substrate 1. The first i-type amorphous semiconductor film 2 is formed so as to be in contact with the entire surface of 1b, and the first conductivity-type amorphous semiconductor film 3 is formed so as to be in contact with the entire surface of the first i-type amorphous semiconductor film 2. Form. The method for forming the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 is not particularly limited, and for example, a plasma CVD (Chemical Vapor Deposition) method can be used.
 次に、図5に示すように、第1導電型非晶質半導体膜3上に、エッチングレジストインク10を設置する。ここで、エッチングレジストインク10は、第1方向41に延在する帯状に、たとえば塗布または印刷によって第1導電型非晶質半導体膜3上に設置することができる。エッチングレジストインク10は、第1導電型領域51を残す領域に設置される。 Next, as shown in FIG. 5, an etching resist ink 10 is placed on the first conductive type amorphous semiconductor film 3. Here, the etching resist ink 10 can be placed on the first conductive type amorphous semiconductor film 3 in a strip shape extending in the first direction 41 by, for example, coating or printing. The etching resist ink 10 is installed in a region where the first conductivity type region 51 is left.
 エッチングレジストインク10の塗布時または印刷時のエッチングレジストインク10の滲みによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりが形成される。そのため、エッチングレジストインク10の量および粘度等の条件を調節し、エッチングレジストインク10の滲みを調節することによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりを調節することが可能となる。 Waviness of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is formed by bleeding of the etching resist ink 10 at the time of application or printing of the etching resist ink 10. Therefore, by adjusting conditions such as the amount and viscosity of the etching resist ink 10 and adjusting the bleeding of the etching resist ink 10, the undulation of the edge 3 b of the edge 3 a of the first conductive type amorphous semiconductor film 3 is controlled. It becomes possible to adjust.
 次に、エッチングレジストインク10を硬化させることによって、図6に示すように、第1導電型非晶質半導体膜3上に硬化したエッチングレジストインク10aを形成する。エッチングレジストインク10aは、たとえば加熱または紫外光の照射等の方法によってエッチングレジストインク10を硬化させることにより形成することができる。 Next, the etching resist ink 10 is cured to form a cured etching resist ink 10a on the first conductive amorphous semiconductor film 3, as shown in FIG. The etching resist ink 10a can be formed by curing the etching resist ink 10 by a method such as heating or irradiation with ultraviolet light.
 次に、図7に示すように、硬化したエッチングレジストインク10aをマスクとして、第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3のそれぞれの一部を厚さ方向にエッチングすることによって、半導体基板1の第2の面1bの一部を露出させる。これにより、第1導電型領域51のパターニングを行うことができる。その後、図8に示すように、第1導電型領域51上の硬化したエッチングレジストインク10aを除去する。 Next, as shown in FIG. 7, using the cured etching resist ink 10a as a mask, the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 are partially thickened. By etching in the direction, a part of the second surface 1b of the semiconductor substrate 1 is exposed. Thereby, the patterning of the 1st conductivity type area | region 51 can be performed. Thereafter, as shown in FIG. 8, the cured etching resist ink 10a on the first conductivity type region 51 is removed.
 次に、図9に示すように、半導体基板1の露出面および第1導電型領域51を覆うようにして第2のi型非晶質半導体膜4を形成し、その後、第2のi型非晶質半導体膜4に接するように第2導電型非晶質半導体膜5を形成する。第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5の形成方法は特に限定されないが、たとえばプラズマCVD法を用いることができる。 Next, as shown in FIG. 9, the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type is formed. A second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the amorphous semiconductor film 4. A method for forming the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.
 次に、図10に示すように、第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5のそれぞれの一部を厚さ方向にエッチングすることによって、第1導電型非晶質半導体膜3の一部を露出させる。これにより、第2導電型領域52のパターニングを行うことができる。 Next, as shown in FIG. 10, a part of each of the second i-type amorphous semiconductor film 4 and the second conductivity-type amorphous semiconductor film 5 is etched in the thickness direction to thereby obtain the first conductivity. A part of the type amorphous semiconductor film 3 is exposed. Thereby, the patterning of the 2nd conductivity type area | region 52 can be performed.
 ここで、第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5のそれぞれの一部の厚さ方向へのエッチングも、上述のエッチングレジストインク10を用いた方法により行うことができる。そのため、エッチングレジストインク10の塗布時または印刷時のエッチングレジストインク10の滲みによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりが形成される。そのため、エッチングレジストインク10の量および粘度等の条件を調節し、エッチングレジストインク10の滲みを調節することによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりを調節することが可能となる。 Here, the etching in the thickness direction of each of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is also performed by the method using the etching resist ink 10 described above. It can be carried out. Therefore, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed by bleeding of the etching resist ink 10 at the time of application or printing of the etching resist ink 10. Therefore, by adjusting the conditions such as the amount and viscosity of the etching resist ink 10 and adjusting the bleeding of the etching resist ink 10, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is controlled. It becomes possible to adjust.
 次に、図1に示すように、第1導電型非晶質半導体膜3上に第1電極7を形成するとともに、第2導電型非晶質半導体膜5上に第2電極8を形成する。第1電極7および第2電極8の形成方法は特に限定されないが、たとえば蒸着法などを用いることができる。 Next, as shown in FIG. 1, the first electrode 7 is formed on the first conductive amorphous semiconductor film 3 and the second electrode 8 is formed on the second conductive amorphous semiconductor film 5. . Although the formation method of the 1st electrode 7 and the 2nd electrode 8 is not specifically limited, For example, a vapor deposition method etc. can be used.
 以上により、図1に示す構成の実施形態1のヘテロ接合型バックコンタクトセルが完成する。 Thus, the heterojunction back contact cell according to the first embodiment having the configuration shown in FIG. 1 is completed.
 <課題解決のメカニズム>
 実施形態1のヘテロ接合型バックコンタクトセルは、従来の特許文献1のようにフォトリソグラフィを用いて製造する必要がないため製造コストを大幅に低減することができる。たとえばフォトリソグラフィを用いて第1導電型領域51および第2導電型領域52のパターニングを行った場合と比べて、ヘテロ接合型バックコンタクトセルの1枚当たりの製造コストを1/10以下とすることができる。
<Mechanism of problem solving>
Since the heterojunction back contact cell of Embodiment 1 does not need to be manufactured using photolithography as in the conventional Patent Document 1, the manufacturing cost can be significantly reduced. For example, the manufacturing cost per one heterojunction type back contact cell should be 1/10 or less compared to the case where patterning of the first conductivity type region 51 and the second conductivity type region 52 is performed using photolithography. Can do.
 また、実施形態1のヘテロ接合型バックコンタクトセルにおいては、第1導電型非晶質半導体膜3の縁部3aの端部3bは第1方向41にうねりながら延在しているとともに、第2導電型非晶質半導体膜5の縁部5aの端部5bは第2方向42にうねりながら延在している。そのため、たとえばフォトリソグラフィを用いてこれらの膜の縁部の端部が直線状に延在するように形成した場合と比べて、半導体基板1の第2の面1b上における第1導電型非晶質半導体膜3の縁部3aと第2導電型非晶質半導体膜5の縁部5aとの重なり領域の形成面積を大きくすることができる。これにより、当該重なり領域における半導体基板1の第2の面1bのパッシベーション性を向上させることができるため、実施形態1のヘテロ接合型バックコンタクトセルの信頼性が高くなるとともに、実施形態1のヘテロ接合型バックコンタクトセルのVocが上昇して特性が向上する。 In the heterojunction back contact cell of the first embodiment, the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 extends while undulating in the first direction 41, and the second The end portion 5 b of the edge portion 5 a of the conductive amorphous semiconductor film 5 extends while undulating in the second direction 42. Therefore, the first conductivity type amorphous on the second surface 1b of the semiconductor substrate 1 is compared with the case where the edge portions of these films are formed to extend linearly using, for example, photolithography. The formation area of the overlapping region between the edge 3a of the crystalline semiconductor film 3 and the edge 5a of the second conductive type amorphous semiconductor film 5 can be increased. Thereby, the passivation property of the second surface 1b of the semiconductor substrate 1 in the overlapping region can be improved, so that the reliability of the heterojunction back contact cell of the first embodiment is improved and the heterogeneity of the first embodiment is improved. The Voc of the junction type back contact cell is increased and the characteristics are improved.
 <変形例>
 なお、上記においては、第1導電型をn型とし、第2導電型をp型とした場合について説明したが、第1導電型をp型とし、第2導電型をn型とした場合でも上記と同様の効果を得ることができる。
<Modification>
In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, even when the first conductivity type is p-type and the second conductivity type is n-type. The same effect as described above can be obtained.
 また、上記においては、第1導電型非晶質半導体膜3の縁部3aの端部3bおよび第2導電型非晶質半導体膜5の縁部5aの端部5bの双方がうねりを有する場合について説明したが、第1導電型非晶質半導体膜3の縁部3aの端部3bおよび第2導電型非晶質半導体膜5の縁部5aの端部5bの少なくとも一方がうねりを有していればよい。 Moreover, in the above, when both the edge part 3b of the edge part 3a of the 1st conductivity type amorphous semiconductor film 3 and the edge part 5b of the edge part 5a of the 2nd conductivity type amorphous semiconductor film 5 have a wave | undulation. However, at least one of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 and the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 has waviness. It only has to be.
 [実施形態2]
 実施形態2のヘテロ接合型バックコンタクトセルは、第1導電型領域51のパターニングおよび第2導電型領域52のパターニングがそれぞれエッチングペーストを用いて行われていることを特徴としている。以下、実施形態2のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。
[Embodiment 2]
The heterojunction back contact cell of Embodiment 2 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are each performed using an etching paste. Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2 will be described.
 まず、図4に示すように、半導体基板1の第2の面1b上に第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3をこの順に形成する。次に、図11の模式的断面図に示すように、第1導電型非晶質半導体膜3上に、エッチングペースト11を設置する。ここで、エッチングペースト11は、第1方向41に延在する帯状に、たとえば塗布または印刷によって第1導電型非晶質半導体膜3上に設置することができる。エッチングペースト11は、第1導電型領域51を残す領域に設置される。 First, as shown in FIG. 4, a first i-type amorphous semiconductor film 2 and a first conductive amorphous semiconductor film 3 are formed in this order on the second surface 1 b of the semiconductor substrate 1. Next, as shown in the schematic cross-sectional view of FIG. 11, an etching paste 11 is placed on the first conductive type amorphous semiconductor film 3. Here, the etching paste 11 can be placed on the first conductive type amorphous semiconductor film 3 in a strip shape extending in the first direction 41 by, for example, coating or printing. The etching paste 11 is placed in a region where the first conductivity type region 51 is left.
 実施形態2においては、エッチングペースト11の塗布時または印刷時のエッチングペースト11の滲みによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりが形成される。そのため、エッチングペースト11の量および粘度等の条件を調節し、エッチングペースト11の滲みを調節することによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりを調節することが可能となる。 In the second embodiment, the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is formed by the bleeding of the etching paste 11 when the etching paste 11 is applied or printed. Therefore, the undulation of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is adjusted by adjusting the conditions such as the amount and viscosity of the etching paste 11 and adjusting the bleeding of the etching paste 11. It becomes possible.
 次に、図12の模式的断面図に示すように、エッチングペースト11を加熱することによってエッチングペースト11を焼成し、第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3のそれぞれの一部を厚さ方向にエッチングする。エッチングペースト11は、焼成時に、第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3を厚さ方向にエッチングしながらファイヤースルーし、焼成後のエッチングペースト11aが半導体基板1の第2の面1bに接する。その後、焼成後のエッチングペースト11aを除去して、図8に示すように、半導体基板1の第2の面1bの一部を露出させる。これにより、第1導電型領域51のパターニングを行うことができる。 Next, as shown in the schematic cross-sectional view of FIG. 12, the etching paste 11 is baked by heating the etching paste 11, and the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor Each part of the film 3 is etched in the thickness direction. The etching paste 11 fires through the first i-type amorphous semiconductor film 2 and the first conductive amorphous semiconductor film 3 while etching in the thickness direction during firing, and the fired etching paste 11a becomes the semiconductor. It contacts the second surface 1b of the substrate 1. Thereafter, the baking etching paste 11a is removed, and a part of the second surface 1b of the semiconductor substrate 1 is exposed as shown in FIG. Thereby, the patterning of the 1st conductivity type area | region 51 can be performed.
 次に、図9に示すように、半導体基板1の露出面および第1導電型領域51を覆うように第2のi型非晶質半導体膜4を形成し、その後、第2のi型非晶質半導体膜4に接するように第2導電型非晶質半導体膜5を形成する。 Next, as shown in FIG. 9, the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type non-type is formed. A second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the crystalline semiconductor film 4.
 次に、図10に示すように、第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5のそれぞれの一部を厚さ方向にエッチングすることによって、第1導電型非晶質半導体膜3の一部を露出させる。これにより、第2導電型領域52のパターニングを行うことができる。 Next, as shown in FIG. 10, a part of each of the second i-type amorphous semiconductor film 4 and the second conductivity-type amorphous semiconductor film 5 is etched in the thickness direction to thereby obtain the first conductivity. A part of the type amorphous semiconductor film 3 is exposed. Thereby, the patterning of the 2nd conductivity type area | region 52 can be performed.
 ここで、第2のi型非晶質半導体膜4および第2導電型非晶質半導体膜5のそれぞれの一部の厚さ方向へのエッチングも、上述のエッチングペースト11を用いた方法により行うことができる。これにより、エッチングペースト11の塗布時または印刷時のエッチングペースト11の滲みによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりが形成される。そのため、エッチングペースト11の量および粘度等の条件を調節し、エッチングペースト11の滲みを調節することによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりを調節することが可能となる。 Here, the etching in the thickness direction of a part of each of the second i-type amorphous semiconductor film 4 and the second conductive type amorphous semiconductor film 5 is also performed by the method using the etching paste 11 described above. be able to. Thereby, the undulation of the edge 5b of the edge 5a of the second conductivity type amorphous semiconductor film 5 is formed by bleeding of the etching paste 11 when the etching paste 11 is applied or printed. Therefore, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is adjusted by adjusting conditions such as the amount and viscosity of the etching paste 11 and adjusting the bleeding of the etching paste 11. It becomes possible.
 その後は、実施形態1と同様にして、実施形態2のヘテロ接合型バックコンタクトセルを作製することができる。 Thereafter, in the same manner as in the first embodiment, the heterojunction back contact cell of the second embodiment can be manufactured.
 実施形態2における上記以外の説明は実施形態1と同様であるため、その説明については繰り返さない。 Since the description other than the above in the second embodiment is the same as that in the first embodiment, the description thereof will not be repeated.
 [実施形態3]
 実施形態3のヘテロ接合型バックコンタクトセルは、第1導電型領域51のパターニングおよび第2導電型領域52のパターニングがそれぞれリフトオフインクを用いて行われていることを特徴としている。以下、実施形態3のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。
[Embodiment 3]
The heterojunction back contact cell of Embodiment 3 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are each performed using lift-off ink. Hereinafter, an example of a method for manufacturing the heterojunction back contact cell of Embodiment 3 will be described.
 まず、図13に示すように、半導体基板1の第2の面1b上にリフトオフインク12を設置する。ここで、リフトオフインク12は、第1方向41に延在する帯状に、たとえば塗布または印刷によって半導体基板1の第2の面1b上に設置することができる。リフトオフインク12は、第1導電型領域51が形成されない領域に設置される。 First, as shown in FIG. 13, lift-off ink 12 is installed on the second surface 1 b of the semiconductor substrate 1. Here, the lift-off ink 12 can be installed on the second surface 1b of the semiconductor substrate 1 in a strip shape extending in the first direction 41, for example, by coating or printing. The lift-off ink 12 is installed in an area where the first conductivity type area 51 is not formed.
 実施形態3においては、リフトオフインク12の塗布時または印刷時のリフトオフインク12の滲みによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりが形成される。そのため、リフトオフインク12の量および粘度等の条件を調節し、リフトオフインク12の滲みを調節することによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりを調節することが可能となる。 In the third embodiment, the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is formed by bleeding of the lift-off ink 12 when the lift-off ink 12 is applied or printed. Therefore, by adjusting conditions such as the amount and viscosity of the lift-off ink 12 and adjusting the bleeding of the lift-off ink 12, the undulation of the end portion 3b of the edge portion 3a of the first conductive type amorphous semiconductor film 3 is adjusted. It becomes possible.
 次に、図14の模式的断面図に示すように、リフトオフインク12が設置された後の半導体基板1の第2の面1bを覆うように第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3をこの順序で形成する。その後、リフトオフインク12をリフトオフインク12上に位置する第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3とともに除去することによって、図8に示すように、半導体基板1の第2の面1bの一部を露出させる。これにより、第1導電型領域51のパターニングを行うことができる。 Next, as shown in the schematic cross-sectional view of FIG. 14, the first i-type amorphous semiconductor film 2 and the first i-type amorphous semiconductor film 2 are formed so as to cover the second surface 1 b of the semiconductor substrate 1 after the lift-off ink 12 is installed. One-conductivity type amorphous semiconductor film 3 is formed in this order. Thereafter, the lift-off ink 12 is removed together with the first i-type amorphous semiconductor film 2 and the first conductive-type amorphous semiconductor film 3 located on the lift-off ink 12, thereby forming a semiconductor substrate as shown in FIG. A part of the first second surface 1b is exposed. Thereby, the patterning of the 1st conductivity type area | region 51 can be performed.
 次に、図10に示すように、第2導電型領域52のパターニングを行う。ここで、第2導電型領域52のパターニングも、上述のリフトオフインク12を用いた方法により行うことができる。これにより、リフトオフインク12の塗布時または印刷時のリフトオフインク12の滲みによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりが形成される。そのため、リフトオフインク12の量および粘度等の条件を調節し、リフトオフインク12の滲みを調節することによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりを調節することが可能となる。 Next, as shown in FIG. 10, the second conductivity type region 52 is patterned. Here, the patterning of the second conductivity type region 52 can also be performed by the method using the lift-off ink 12 described above. As a result, undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed by bleeding of the lift-off ink 12 at the time of application of the lift-off ink 12 or printing. Therefore, the undulation of the edge 5b of the edge 5a of the second conductive type amorphous semiconductor film 5 is adjusted by adjusting conditions such as the amount and viscosity of the lift-off ink 12 and adjusting the bleeding of the lift-off ink 12. It becomes possible.
 その後は、実施形態1と同様にして、実施形態3のヘテロ接合型バックコンタクトセルを作製することができる。 Thereafter, in the same manner as in the first embodiment, the heterojunction back contact cell of the third embodiment can be manufactured.
 実施形態3における上記以外の説明は実施形態1と同様であるため、その説明については繰り返さない。 Since the description other than the above in the third embodiment is the same as that in the first embodiment, the description thereof will not be repeated.
 [実施形態4]
 実施形態4のヘテロ接合型バックコンタクトセルは、第1導電型領域51のパターニングおよび第2導電型領域52のパターニングがそれぞれレーザアブレーションにより行われていることを特徴としている。以下、実施形態4のヘテロ接合型バックコンタクトセルの製造方法の一例について説明する。
[Embodiment 4]
The heterojunction back contact cell of Embodiment 4 is characterized in that the patterning of the first conductivity type region 51 and the patterning of the second conductivity type region 52 are performed by laser ablation, respectively. Hereinafter, an example of the manufacturing method of the heterojunction back contact cell of Embodiment 4 is demonstrated.
 まず、図4に示すように、半導体基板1の第2の面1b上に第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3をこの順に形成する。次に、図15の模式的断面図に示すように、第1導電型非晶質半導体膜3にレーザ光13を照射する。ここで、レーザ光13は、第1方向41に延在する帯状に移動させられながら照射される。これによりレーザ光13の照射領域の第1のi型非晶質半導体膜2および第1導電型非晶質半導体膜3はそれぞれレーザアブレーションにより第1方向41に延在する帯状に除去されて、図8に示すように、第1導電型領域51のパターニングが行われる。 First, as shown in FIG. 4, a first i-type amorphous semiconductor film 2 and a first conductive amorphous semiconductor film 3 are formed in this order on the second surface 1 b of the semiconductor substrate 1. Next, as shown in the schematic cross-sectional view of FIG. 15, the first conductive type amorphous semiconductor film 3 is irradiated with a laser beam 13. Here, the laser beam 13 is irradiated while being moved in a strip shape extending in the first direction 41. As a result, the first i-type amorphous semiconductor film 2 and the first conductive type amorphous semiconductor film 3 in the irradiation region of the laser beam 13 are removed in a belt shape extending in the first direction 41 by laser ablation, As shown in FIG. 8, patterning of the first conductivity type region 51 is performed.
 実施形態4においては、レーザアブレーションの条件により第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりが形成される。そのため、レーザ光13の照射領域の形状および大きさ等のレーザアブレーションの条件を調節することによって、第1導電型非晶質半導体膜3の縁部3aの端部3bのうねりを調節することが可能となる。 In the fourth embodiment, the undulation of the edge 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 is formed depending on the laser ablation condition. Therefore, the undulation of the end 3b of the edge 3a of the first conductive type amorphous semiconductor film 3 can be adjusted by adjusting the conditions of laser ablation such as the shape and size of the irradiation region of the laser beam 13. It becomes possible.
 次に、図9に示すように、半導体基板1の露出面および第1導電型領域51を覆うようにして第2のi型非晶質半導体膜4を形成し、その後、第2のi型非晶質半導体膜4に接するように第2導電型非晶質半導体膜5を形成する。 Next, as shown in FIG. 9, the second i-type amorphous semiconductor film 4 is formed so as to cover the exposed surface of the semiconductor substrate 1 and the first conductivity type region 51, and then the second i-type is formed. A second conductivity type amorphous semiconductor film 5 is formed so as to be in contact with the amorphous semiconductor film 4.
 次に、図10に示すように、第2導電型領域52のパターニングを行う。ここで、第2導電型領域52のパターニングも、上述のレーザアブレーションにより行うことができる。これにより、レーザ光13の照射領域の形状により、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりが形成される。そのため、レーザ光13の照射領域の形状を調節することによって、第2導電型非晶質半導体膜5の縁部5aの端部5bのうねりを調節することが可能となる。 Next, as shown in FIG. 10, the second conductivity type region 52 is patterned. Here, the patterning of the second conductivity type region 52 can also be performed by the laser ablation described above. Thereby, the undulation of the end portion 5b of the edge portion 5a of the second conductive type amorphous semiconductor film 5 is formed depending on the shape of the irradiation region of the laser beam 13. Therefore, it is possible to adjust the undulation of the end portion 5 b of the edge portion 5 a of the second conductive type amorphous semiconductor film 5 by adjusting the shape of the irradiation region of the laser beam 13.
 その後は、実施形態1と同様にして、実施形態4のヘテロ接合型バックコンタクトセルを作製することができる。 Thereafter, in the same manner as in the first embodiment, the heterojunction back contact cell of the fourth embodiment can be manufactured.
 実施形態4における上記以外の説明は実施形態1と同様であるため、その説明については繰り返さない。 Since the description other than the above in the fourth embodiment is the same as that in the first embodiment, the description thereof will not be repeated.
 [付記]
 (1)ここで開示された実施形態は、半導体基板と、半導体基板上において第1方向に延在する第1導電型非晶質半導体膜と、半導体基板上において第2方向に延在する第2導電型非晶質半導体膜と、を備え、第1導電型非晶質半導体膜の縁部上に第2導電型非晶質半導体膜の縁部が位置しており、第1導電型非晶質半導体膜の縁部の端部および第2導電型非晶質半導体膜の縁部の端部の少なくとも一方がうねりを有している光電変換素子である。このような構成とすることにより、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。
[Appendix]
(1) An embodiment disclosed herein includes a semiconductor substrate, a first conductivity type amorphous semiconductor film extending in a first direction on the semiconductor substrate, and a first extension extending in a second direction on the semiconductor substrate. A second conductivity type amorphous semiconductor film, the edge of the second conductivity type amorphous semiconductor film being located on the edge of the first conductivity type amorphous semiconductor film, At least one of the edge part of the crystalline semiconductor film and the edge part of the second conductive type amorphous semiconductor film is a photoelectric conversion element having undulations. With such a structure, manufacturing cost can be reduced, and a photoelectric conversion element with high reliability and high characteristics can be provided.
 (2)ここで開示された実施形態の光電変換素子は、第1導電型非晶質半導体膜の縁部の端部が第1方向に延在するうねりを有していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (2) The photoelectric conversion element of the embodiment disclosed herein may have a undulation in which the edge of the edge of the first conductive type amorphous semiconductor film extends in the first direction. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (3)ここで開示された実施形態の光電変換素子は、第2導電型非晶質半導体膜の縁部の端部が第2方向に延在するうねりを有していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (3) The photoelectric conversion element of the embodiment disclosed herein may have a undulation in which the edge of the edge of the second conductive amorphous semiconductor film extends in the second direction. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (4)ここで開示された実施形態の光電変換素子においては、うねりの曲線度が1.03以上であることが好ましい。この場合には、光電変換素子の特性がさらに向上する傾向にある。 (4) In the photoelectric conversion element of the embodiment disclosed here, it is preferable that the degree of undulation is 1.03 or more. In this case, the characteristics of the photoelectric conversion element tend to be further improved.
 (5)ここで開示された実施形態の光電変換素子においては、うねりの曲線度が3.15以下であることが好ましい。この場合には、光電変換素子の信頼性がさらに向上する傾向にある。 (5) In the photoelectric conversion element of the embodiment disclosed herein, it is preferable that the degree of undulation is 3.15 or less. In this case, the reliability of the photoelectric conversion element tends to be further improved.
 (6)ここで開示された実施形態の光電変換素子は、半導体基板と第1導電型非晶質半導体膜との間の第1のi型非晶質半導体膜をさらに備えていてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (6) The photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous semiconductor film between the semiconductor substrate and the first conductive amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (7)ここで開示された実施形態の光電変換素子において、第1のi型非晶質半導体膜は、半導体基板および第1導電型非晶質半導体膜のそれぞれと接していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (7) In the photoelectric conversion element of the embodiment disclosed herein, the first i-type amorphous semiconductor film may be in contact with each of the semiconductor substrate and the first conductivity-type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (8)ここで開示された実施形態の光電変換素子において、半導体基板と第2導電型非晶質半導体膜との間の第2のi型非晶質半導体膜をさらに備えていてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (8) The photoelectric conversion element according to the embodiment disclosed herein may further include a second i-type amorphous semiconductor film between the semiconductor substrate and the second conductive amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (9)ここで開示された実施形態の光電変換素子において、第2のi型非晶質半導体膜は、半導体基板および第2導電型非晶質半導体膜のそれぞれと接していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (9) In the photoelectric conversion element of the embodiment disclosed herein, the second i-type amorphous semiconductor film may be in contact with each of the semiconductor substrate and the second conductivity-type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (10)ここで開示された実施形態の光電変換素子は、第1導電型非晶質半導体膜上の第1電極をさらに備えていてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (10) The photoelectric conversion element of the embodiment disclosed herein may further include a first electrode on the first conductive type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (11)ここで開示された実施形態の光電変換素子は、第2導電型非晶質半導体膜上の第2電極をさらに備えていてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を提供することができる。 (11) The photoelectric conversion element of the embodiment disclosed herein may further include a second electrode on the second conductivity type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a photoelectric conversion element having high reliability and high characteristics can be provided.
 (12)ここで開示された実施形態は、半導体基板上において第1方向に延在する第1導電型非晶質半導体膜をパターニングする工程と、半導体基板上において第2方向に延在する第2導電型非晶質半導体膜をパターニングする工程と、第2導電型非晶質半導体膜をパターニングする工程は、パターニング後の第1導電型非晶質半導体膜の縁部上に第2導電型非晶質半導体膜の縁部が位置するように第2導電型非晶質半導体膜をパターニングする工程を含み、パターニング後の第1導電型非晶質半導体膜の縁部の端部およびパターニング後の第2導電型非晶質半導体膜の縁部の端部の少なくとも一方がうねりを有している光電変換素子の製造方法である。このような構成とすることにより、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (12) In the embodiment disclosed herein, a step of patterning a first conductivity type amorphous semiconductor film extending in a first direction on a semiconductor substrate, and a step of extending in a second direction on the semiconductor substrate are described. The step of patterning the two-conductivity-type amorphous semiconductor film and the step of patterning the second-conductivity-type amorphous semiconductor film include the second conductivity-type on the edge of the patterned first-conductivity-type amorphous semiconductor film. Including a step of patterning the second conductive type amorphous semiconductor film so that the edge of the amorphous semiconductor film is located, and the edge of the edge of the first conductive type amorphous semiconductor film after patterning and after patterning This is a method for manufacturing a photoelectric conversion element in which at least one of the edge portions of the second conductivity type amorphous semiconductor film has undulations. With such a configuration, manufacturing cost can be reduced, and a highly reliable and high-performance photoelectric conversion element can be manufactured.
 (13)ここで開示された実施形態の光電変換素子の製造方法においては、第1導電型非晶質半導体膜の縁部の端部が第1方向に延在するうねりを有していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (13) In the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the edge of the edge of the first conductive type amorphous semiconductor film may have a undulation extending in the first direction. Good. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (14)ここで開示された実施形態の光電変換素子の製造方法においては、第2導電型非晶質半導体膜の縁部の端部が第2方向に延在するうねりを有していてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (14) In the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein, even if the edge of the edge of the second conductive type amorphous semiconductor film has a undulation extending in the second direction. Good. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (15)ここで開示された実施形態の光電変換素子の製造方法においては、うねりの曲線度が1.03以上であることが好ましい。この場合には、特性がさらに向上した光電変換素子を製造することができる。 (15) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, it is preferable that the degree of undulation is 1.03 or more. In this case, a photoelectric conversion element with further improved characteristics can be manufactured.
 (16)ここで開示された実施形態の光電変換素子の製造方法においては、うねりの曲線度が3.15以下であることが好ましい。この場合には、信頼性がさらに向上した光電変換素子を製造することができる。 (16) In the method for manufacturing a photoelectric conversion element of the embodiment disclosed herein, it is preferable that the degree of undulation is 3.15 or less. In this case, a photoelectric conversion element with further improved reliability can be manufactured.
 (17)ここで開示された実施形態の光電変換素子の製造方法において、第1導電型非晶質半導体膜をパターニングする工程は、エッチングレジストインク、エッチングペースト、リフトオフインクおよびレーザアブレーションからなる群から選択された少なくとも1つの方法により第1導電型非晶質半導体膜をパターニングする工程を含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (17) In the method for manufacturing a photoelectric conversion element of the embodiment disclosed herein, the step of patterning the first conductive type amorphous semiconductor film is performed from a group consisting of etching resist ink, etching paste, lift-off ink, and laser ablation. A step of patterning the first conductive type amorphous semiconductor film by at least one selected method may be included. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (18)ここで開示された実施形態の光電変換素子の製造方法において、第1導電型非晶質半導体膜をパターニングする工程は、第1導電型非晶質半導体膜をエッチングレジストインクによりパターニングする工程を含み、エッチングレジストインクによりパターニングする工程は、第1導電型非晶質半導体膜の一部上にエッチングレジストインクを設置する工程と、エッチングレジストインクを硬化する工程と、硬化させたエッチングレジストインクをマスクとして第1導電型非晶質半導体膜をエッチングする工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (18) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the first conductive type amorphous semiconductor film includes patterning the first conductive type amorphous semiconductor film with an etching resist ink. And the step of patterning with an etching resist ink includes a step of placing the etching resist ink on a part of the first conductive type amorphous semiconductor film, a step of curing the etching resist ink, and a cured etching resist And a step of etching the first conductive type amorphous semiconductor film using the ink as a mask. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (19)ここで開示された実施形態の光電変換素子の製造方法において、第1導電型非晶質半導体膜をパターニングする工程は、第1導電型非晶質半導体膜をエッチングペーストによりパターニングする工程を含み、エッチングペーストによりパターニングする工程は、第1導電型非晶質半導体膜の一部上にエッチングペーストを設置する工程と、エッチングペーストを加熱することにより第1導電型非晶質半導体膜をエッチングする工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (19) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film with an etching paste. And the step of patterning with the etching paste includes the step of placing the etching paste on a part of the first conductive type amorphous semiconductor film, and the step of heating the etching paste to form the first conductive type amorphous semiconductor film. And an etching step. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (20)ここで開示された実施形態の光電変換素子の製造方法において、第1導電型非晶質半導体膜をパターニングする工程は、第1導電型非晶質半導体膜をリフトオフインクによりパターニングする工程を含み、リフトオフインクによりパターニングする工程は、半導体基板上にリフトオフインクを設置する工程と、リフトオフインクが設置された半導体基板を覆うように第1導電型非晶質半導体膜を形成する工程と、リフトオフインクをリフトオフインク上に位置する第1導電型非晶質半導体膜とともに除去する工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (20) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film with lift-off ink. The step of patterning with lift-off ink includes a step of installing lift-off ink on a semiconductor substrate, a step of forming a first conductivity type amorphous semiconductor film so as to cover the semiconductor substrate on which the lift-off ink is installed, and And removing the lift-off ink together with the first conductive type amorphous semiconductor film located on the lift-off ink. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (21)ここで開示された実施形態の光電変換素子の製造方法において、第1導電型非晶質半導体膜をパターニングする工程は、第1導電型非晶質半導体膜をレーザアブレーションによりパターニングする工程を含み、レーザアブレーションによりパターニングする工程は、半導体基板上に第1導電型非晶質半導体膜を形成する工程と、第1導電型非晶質半導体膜にレーザ光を照射することによって第1導電型非晶質半導体膜の一部を除去する工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (21) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the first conductive type amorphous semiconductor film is a step of patterning the first conductive type amorphous semiconductor film by laser ablation. And the step of patterning by laser ablation includes a step of forming a first conductive type amorphous semiconductor film on a semiconductor substrate and a first conductive type by irradiating the first conductive type amorphous semiconductor film with laser light. And removing a part of the type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (22)ここで開示された実施形態の光電変換素子の製造方法において、第2導電型非晶質半導体膜をパターニングする工程は、エッチングレジストインク、エッチングペースト、リフトオフインクおよびレーザアブレーションからなる群から選択された少なくとも1つの方法により第2導電型非晶質半導体膜をパターニングする工程を含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (22) In the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the second conductive type amorphous semiconductor film is performed from the group consisting of etching resist ink, etching paste, lift-off ink, and laser ablation. A step of patterning the second conductive type amorphous semiconductor film by at least one selected method may be included. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (23)ここで開示された実施形態の光電変換素子の製造方法において、第2導電型非晶質半導体膜をパターニングする工程は、第2導電型非晶質半導体膜をエッチングレジストインクによりパターニングする工程を含み、エッチングレジストインクによりパターニングする工程は、第2導電型非晶質半導体膜の一部上にエッチングレジストインクを設置する工程と、エッチングレジストインクを硬化する工程と、硬化させたエッチングレジストインクをマスクとして第2導電型非晶質半導体膜をエッチングする工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (23) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the second conductive type amorphous semiconductor film includes patterning the second conductive type amorphous semiconductor film with an etching resist ink. And the step of patterning with an etching resist ink includes a step of placing the etching resist ink on a part of the second conductive type amorphous semiconductor film, a step of curing the etching resist ink, and a cured etching resist And etching the second conductive type amorphous semiconductor film using the ink as a mask. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (24)ここで開示された実施形態の光電変換素子の製造方法において、第2導電型非晶質半導体膜をパターニングする工程は、第2導電型非晶質半導体膜をエッチングペーストによりパターニングする工程を含み、エッチングペーストによりパターニングする工程は、第2導電型非晶質半導体膜の一部上にエッチングペーストを設置する工程と、エッチングペーストを加熱することにより第2導電型非晶質半導体膜をエッチングする工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (24) In the method for manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film with an etching paste. And the step of patterning with the etching paste includes a step of placing the etching paste on a part of the second conductive type amorphous semiconductor film, and a step of heating the etching paste to form the second conductive type amorphous semiconductor film. And an etching step. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (25)ここで開示された実施形態の光電変換素子の製造方法において、第2導電型非晶質半導体膜をパターニングする工程は、第2導電型非晶質半導体膜をリフトオフインクによりパターニングする工程を含み、リフトオフインクによりパターニングする工程は、半導体基板上にリフトオフインクを設置する工程と、リフトオフインクが設置された半導体基板を覆うように第2導電型非晶質半導体膜を形成する工程と、リフトオフインクをリフトオフインク上に位置する第2導電型非晶質半導体膜とともに除去する工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (25) In the method of manufacturing a photoelectric conversion element of the embodiment disclosed herein, the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film with lift-off ink. And the step of patterning with lift-off ink includes a step of installing lift-off ink on a semiconductor substrate, a step of forming a second conductivity type amorphous semiconductor film so as to cover the semiconductor substrate on which the lift-off ink is installed, and And removing the lift-off ink together with the second conductive type amorphous semiconductor film located on the lift-off ink. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 (26)ここで開示された実施形態の光電変換素子の製造方法において、第2導電型非晶質半導体膜をパターニングする工程は、第2導電型非晶質半導体膜をレーザアブレーションによりパターニングする工程を含み、レーザアブレーションによりパターニングする工程は、半導体基板上に第2導電型非晶質半導体膜を形成する工程と、第2導電型非晶質半導体膜にレーザ光を照射することによって第2導電型非晶質半導体膜の一部を除去する工程とを含んでいてもよい。この場合にも、製造コストを低減することができるとともに、高信頼性および高特性の光電変換素子を製造することができる。 (26) In the method of manufacturing a photoelectric conversion element according to the embodiment disclosed herein, the step of patterning the second conductive type amorphous semiconductor film is a step of patterning the second conductive type amorphous semiconductor film by laser ablation. And the step of patterning by laser ablation includes a step of forming a second conductive type amorphous semiconductor film on the semiconductor substrate and a second conductive type by irradiating the second conductive type amorphous semiconductor film with laser light. And removing a part of the type amorphous semiconductor film. Also in this case, the manufacturing cost can be reduced, and a highly reliable and high characteristic photoelectric conversion element can be manufactured.
 以上のように実施形態について説明を行なったが、上述の各実施形態の構成を適宜組み合わせることも当初から予定している。 Although the embodiment has been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments.
 今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
 ここで開示された実施形態は、光電変換素子および光電変換素子の製造方法に利用することができ、好適には太陽電池及び太陽電池の製造方法に利用できる可能性があり、特に好適にはヘテロ接合型バックコンタクトセルおよびヘテロ接合型バックコンタクトセルの製造方法に利用できる可能性がある。 Embodiment disclosed here can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, and may be suitably used for the manufacturing method of a solar cell and a solar cell, Especially preferably, it is hetero. There is a possibility that it can be used in a manufacturing method of a junction type back contact cell and a hetero junction type back contact cell.
 1 半導体基板、2 第1のi型非晶質半導体膜、3 第1導電型非晶質半導体膜、3a 縁部、3b 端部、4 第1のi型非晶質半導体膜、5 第2導電型非晶質半導体膜、5a 縁部、5b 端部、7 第1電極、8 第2電極、10 エッチングレジストインク、10a 硬化したエッチングレジストインク、11 エッチングペースト、11a 焼成後のエッチングペースト、12 リフトオフインク、13 レーザ光、41 第1方向、42 第2方向、51 第1導電型領域、52 第2導電型領域、111 基板、112 i型非晶質半導体層、113 i型非晶質半導体層、114 n型非晶質半導体層、115 p型非晶質半導体層、116 n側電極、116a 有機被膜、116b 金属層、116c 透明導電層、117 p側電極、117a 有機被膜、117b 金属層、117c 透明導電層、119 i型非晶質半導体層、120 n型非晶質半導体層、121 絶縁層、122 n型領域、123 p型領域、124 保護膜。 1. Semiconductor substrate, 2. First i-type amorphous semiconductor film, 3. First conductivity-type amorphous semiconductor film, 3a edge, 3b end, 4. First i-type amorphous semiconductor film, 5. Second. Conductive amorphous semiconductor film, 5a edge, 5b edge, 7 first electrode, 8 second electrode, 10 etching resist ink, 10a cured etching resist ink, 11 etching paste, 11a etching paste after baking, 12 Lift-off ink, 13 laser light, 41 1st direction, 42 2nd direction, 51 1st conductivity type region, 52 2nd conductivity type region, 111 substrate, 112 i-type amorphous semiconductor layer, 113 i-type amorphous semiconductor Layer, 114 n-type amorphous semiconductor layer, 115 p-type amorphous semiconductor layer, 116 n-side electrode, 116a organic coating, 116b metal layer, 116c transparent conductive 117 p-side electrode, 117a organic coating, 117b metal layer, 117c transparent conductive layer, 119 i-type amorphous semiconductor layer, 120 n-type amorphous semiconductor layer, 121 insulating layer, 122 n-type region, 123 p-type region 124, protective film.

Claims (6)

  1.  半導体基板と、
     前記半導体基板上において第1方向に延在する第1導電型非晶質半導体膜と、
     前記半導体基板上において第2方向に延在する第2導電型非晶質半導体膜と、を備え、
     前記第1導電型非晶質半導体膜の縁部上に前記第2導電型非晶質半導体膜の縁部が位置しており、
     前記第1導電型非晶質半導体膜の前記縁部の端部および前記第2導電型非晶質半導体膜の前記縁部の端部の少なくとも一方がうねりを有している、光電変換素子。
    A semiconductor substrate;
    A first conductive type amorphous semiconductor film extending in a first direction on the semiconductor substrate;
    A second conductivity type amorphous semiconductor film extending in a second direction on the semiconductor substrate,
    An edge of the second conductive type amorphous semiconductor film is located on an edge of the first conductive type amorphous semiconductor film;
    A photoelectric conversion element in which at least one of an end portion of the edge portion of the first conductive type amorphous semiconductor film and an end portion of the edge portion of the second conductive type amorphous semiconductor film has undulations.
  2.  前記第1導電型非晶質半導体膜の前記縁部の前記端部が前記第1方向に延在するうねりを有している、請求項1に記載の光電変換素子。 The photoelectric conversion element according to claim 1, wherein the end portion of the edge portion of the first conductive type amorphous semiconductor film has a undulation extending in the first direction.
  3.  前記第2導電型非晶質半導体膜の前記縁部の前記端部が前記第2方向に延在するうねりを有している、請求項1または請求項2に記載の光電変換素子。 3. The photoelectric conversion element according to claim 1, wherein the end portion of the edge portion of the second conductive type amorphous semiconductor film has a undulation extending in the second direction.
  4.  前記うねりの曲線度が1.03以上である、請求項1~請求項3のいずれか1項に記載の光電変換素子。 The photoelectric conversion element according to any one of claims 1 to 3, wherein the undulation curve degree is 1.03 or more.
  5.  前記うねりの曲線度が3.15以下である、請求項1~請求項4のいずれか1項に記載の光電変換素子。 The photoelectric conversion element according to any one of claims 1 to 4, wherein a curve degree of the undulation is 3.15 or less.
  6.  半導体基板上において第1方向に延在する第1導電型非晶質半導体膜をパターニングする工程と、
     前記半導体基板上において第2方向に延在する第2導電型非晶質半導体膜をパターニングする工程と、
     前記第2導電型非晶質半導体膜をパターニングする工程は、前記パターニング後の前記第1導電型非晶質半導体膜の縁部上に前記第2導電型非晶質半導体膜の縁部が位置するように前記第2導電型非晶質半導体膜をパターニングする工程を含み、
     前記パターニング後の前記第1導電型非晶質半導体膜の前記縁部の端部および前記パターニング後の前記第2導電型非晶質半導体膜の前記縁部の端部の少なくとも一方がうねりを有している、光電変換素子の製造方法。
    Patterning a first conductive type amorphous semiconductor film extending in a first direction on a semiconductor substrate;
    Patterning a second conductive amorphous semiconductor film extending in a second direction on the semiconductor substrate;
    In the step of patterning the second conductive type amorphous semiconductor film, the edge of the second conductive type amorphous semiconductor film is positioned on the edge of the patterned first conductive type amorphous semiconductor film. Patterning the second conductive type amorphous semiconductor film to include:
    At least one of the end portion of the edge portion of the first conductive type amorphous semiconductor film after the patterning and the end portion of the edge portion of the second conductive type amorphous semiconductor film after the patterning has waviness. A method for producing a photoelectric conversion element.
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