WO2016132746A1 - THIN-FILM SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, DEPOSITION APPARATUS, DEPOSITION METHOD AND GaN TEMPLATE - Google Patents

THIN-FILM SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, DEPOSITION APPARATUS, DEPOSITION METHOD AND GaN TEMPLATE Download PDF

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WO2016132746A1
WO2016132746A1 PCT/JP2016/000895 JP2016000895W WO2016132746A1 WO 2016132746 A1 WO2016132746 A1 WO 2016132746A1 JP 2016000895 W JP2016000895 W JP 2016000895W WO 2016132746 A1 WO2016132746 A1 WO 2016132746A1
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substrate
layer
buffer layer
cubic
plate surface
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PCT/JP2016/000895
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French (fr)
Japanese (ja)
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天野　浩
本田　善央
正 光成
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国立大学法人名古屋大学
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Priority to JP2017500529A priority Critical patent/JP6736005B2/en
Publication of WO2016132746A1 publication Critical patent/WO2016132746A1/en

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Definitions

  • the technical field of this specification relates to a thin film substrate, a semiconductor device, a manufacturing method, a film forming device, a film forming method, and a GaN template for forming a buffer layer having a crystal structure different from that of the substrate on the substrate.
  • a III-group nitride semiconductor represented by GaN has a high breakdown field strength and a high melting point. Therefore, group III nitride semiconductors are expected as materials for semiconductor devices for high output, high frequency, and high temperature, replacing GaAs semiconductors. Therefore, a HEMT device using a III-group nitride semiconductor has been researched and developed. In addition, Group III group nitride semiconductors are also applied to light emitting devices.
  • III group III nitride semiconductor has a hexagonal crystal structure represented by wurtzite type. For this reason, a hexagonal crystal substrate is generally used as the growth substrate.
  • An example of such a hexagonal substrate is a sapphire substrate.
  • a Si (111) substrate may be used as a growth substrate.
  • the Si (111) substrate has a structure close to a hexagonal crystal.
  • the Si substrate a large-diameter substrate can be manufactured with high quality at low cost. Therefore, it is industrially significant to grow a III-group nitride semiconductor on a Si substrate.
  • the Si (001) substrate is a cubic substrate.
  • Si atoms are arranged in a square shape. It is not easy to grow a hexagonal III-V nitride semiconductor on such a cubic Si (001) substrate. Needless to say, the crystal structures of the cubic and hexagonal crystals are greatly different.
  • Si (001) substrates are generally less expensive than Si (111) substrates. Further, Si (001) substrates having a larger diameter than Si (111) substrates are industrially produced. Therefore, it is industrially meaningful to establish a technique for growing a group III group nitride semiconductor on a Si (001) substrate.
  • the technology of this specification has been made to solve the problems of the conventional technology described above.
  • the problem is to provide a thin film substrate and a semiconductor device for forming a hexagonal buffer layer on a cubic substrate, a manufacturing method thereof, a film forming device and a film forming method, and a GaN template.
  • the thin film substrate in the first aspect includes a substrate and a buffer layer on the substrate.
  • the substrate is a cubic substrate.
  • the buffer layer is hexagonal.
  • the c-axis of the buffer layer faces the first direction at a rate of 50% or more.
  • the first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate.
  • This thin film substrate is obtained by forming a hexagonal thin film on a cubic substrate typified by a large-diameter Si (001) substrate. 50% or more of the c-axis of the buffer layer faces a specific direction over the entire plate surface of the substrate. In other words, at any position on the substrate, 50% or more of the c-axis of the buffer layer faces the specific direction. Therefore, a single crystal of a Group III nitride semiconductor can be epitaxially grown on the buffer layer.
  • the cubic substrate is a Si (001) substrate.
  • the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
  • the thin film substrate in the fourth aspect has an intermediate layer on the buffer layer.
  • the intermediate layer is hexagonal.
  • the intermediate layer has a superlattice layer.
  • the semiconductor device includes a substrate, a buffer layer on the substrate, and a group III group nitride semiconductor layer on the buffer layer.
  • the substrate is a cubic substrate.
  • the buffer layer is hexagonal.
  • the c-axis of the buffer layer faces the first direction at a rate of 50% or more.
  • the first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate.
  • the c-axis of the group III group nitride semiconductor layer is inclined within a range of 0 ° to 5 ° with respect to the first direction in both the direction perpendicular to the plate surface of the substrate and the in-plane direction.
  • the cubic substrate is a Si (001) substrate.
  • the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
  • the semiconductor device includes an intermediate layer between the buffer layer and the group III group nitride semiconductor layer.
  • the intermediate layer is hexagonal.
  • the intermediate layer has a superlattice layer.
  • the GaN template in the eleventh aspect has a substrate, a buffer layer on the substrate, and a group III nitride semiconductor layer on the buffer layer.
  • the substrate is a cubic substrate.
  • the buffer layer is hexagonal.
  • the c-axis of the buffer layer faces the first direction at a rate of 50% or more.
  • the first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate.
  • the c-axis of the group III nitride semiconductor layer is inclined within a range of 0 ° to 5 ° with respect to the first direction in both the direction perpendicular to the plate surface of the substrate and the in-plane direction.
  • the cubic substrate may be a Si (001) substrate.
  • the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
  • the thin film substrate manufacturing method includes a step of disposing a cubic substrate inside a chamber and an inclination within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate. And a step of forming a hexagonal buffer layer on the cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target. .
  • a method for manufacturing a semiconductor device comprising: arranging a cubic substrate inside a chamber; and tilting the cubic substrate within a range of 10 ° to 60 ° with respect to a direction perpendicular to a plate surface of the cubic substrate.
  • a step of disposing a target at a predetermined position, a step of forming a hexagonal buffer layer on the cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target, and a buffer layer And a step of growing a group III nitride semiconductor layer on the substrate.
  • the film forming method in the fourteenth aspect is a method of forming a thin film on a substrate.
  • a cubic substrate is placed inside a chamber, and a target is placed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate.
  • a hexagonal buffer layer is formed on the cubic substrate by sputtering.
  • the cubic substrate may be a Si (001) substrate.
  • the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
  • a film forming apparatus in a fifteenth aspect, includes a substrate support portion for supporting a substrate, a chamber for accommodating the substrate support portion, and a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate. And a target arrangement portion arranged at a position inclined so as to be relatively variable.
  • a thin film substrate and a semiconductor device for forming a hexagonal buffer layer on a cubic substrate, a manufacturing method thereof, a film forming apparatus, a film forming method, and a GaN template are provided.
  • FIG. 4 is an enlarged view of FIG. 3. It is a figure which shows the positional relationship of a board
  • FIG. 1 is a diagram showing a schematic configuration of a film forming apparatus 1000 according to this embodiment.
  • the film forming apparatus 1000 is an apparatus for forming a thin film on the substrate 110 by sputtering.
  • the film forming apparatus 1000 includes a chamber 1100, a susceptor 1200, a heater 1300, a target placement unit 1400, a target 1500, a voltage application unit 1600, and a gas supply unit (not shown).
  • the chamber 1100 is for accommodating the substrate 110 on which sputtering is performed.
  • the chamber 1100 accommodates therein a susceptor 1200, a heater 1300, a target placement unit 1400, and a target 1500.
  • the susceptor 1200 is a substrate support unit for supporting the substrate 110.
  • the heater 1300 is for heating the substrate 110 supported by the susceptor 1200.
  • the target placement unit 1400 is for placing the target 1500.
  • the target 1500 is a raw material for forming a thin film on the substrate 110 by sputtering.
  • the voltage application unit 1600 is for applying a voltage to the target 1500.
  • the chamber 1100 is grounded.
  • the voltage application unit 1600 uses a DC power supply.
  • the voltage application unit 1600 may use an AC power source or a pulse DC power source.
  • the angle formed between the direction perpendicular to the plate surface of the substrate 110 and the direction in which the target 1500 is disposed when viewed from the substrate 110 is an angle ⁇ .
  • the angle ⁇ is an angle formed by the center of the surface of the substrate 110 and the center of the surface of the target 1500.
  • the angle ⁇ is in the range of 10 ° to 60 °. That is, the target placement unit 1400 is placed at a position that is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
  • the target 1500 is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
  • the angle ⁇ is in the range of 15 ° to 55 °. More preferably, the angle ⁇ is in the range of 20 ° to 50 °. More preferably, the angle ⁇ is in the range of 25 ° to 45 °.
  • the surface of the target 1500 is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
  • the target placement unit 1400 is placed at a position and orientation in which the surface of the target 1500 is tilted within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
  • the film forming apparatus 1000 is a directional sputtering apparatus.
  • FIG. 2 is a diagram showing a substrate 110 used for film formation.
  • the substrate 110 is a Si (001) substrate.
  • the substrate 110 is a cubic substrate.
  • the substrate 110 has an orientation flat as shown in FIG. Further, in FIG. 2, a [ ⁇ 110] direction and a [110] direction are drawn.
  • an off substrate having an off angle of 15 ° or less in the [110] direction or a direction equivalent to the [110] direction may be applied.
  • the substrate 110 is placed on the susceptor 1200 inside the chamber 1100.
  • the target 1500 is positioned in the [110] direction of the substrate 110 or the direction equivalent to the [110] direction.
  • 1500 is arranged.
  • the target 1500 is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
  • the material of the target 1500 is Al.
  • about 2 to 100 sccm of N 2 gas is supplied.
  • the target 1500 is located within 30 ° in the in-plane rotation direction of the substrate 110 from the [110] direction of the substrate 110 or a direction equivalent to the [110] direction.
  • the voltage application unit 1600 applies a voltage to the target 1500. Thereby, the raw material jumps out of the target 1500. Then, the protruding raw material is scattered in a direction inclined from a direction perpendicular to the plate surface of the substrate 110. That is, when viewed from the substrate 110, the raw material is ejected from a direction inclined by an angle ⁇ from the [110] direction in a direction perpendicular to the plate surface of the substrate 110. At this time, the susceptor 1200 is not rotating. That is, the substrate 110 is not rotated with respect to the chamber 1100. Then, the protruding raw material is deposited on the substrate 110. Thereby, the buffer layer 120 is formed on the substrate 110. That is, a hexagonal AlN layer is formed on a Si (001) substrate which is a cubic substrate.
  • FIG. 3 is a diagram showing a thin film substrate 100 formed by the film forming apparatus 1000.
  • the thin film substrate 100 is a deposition target substrate on which a thin film is formed.
  • the thin film substrate 100 includes a substrate 110 and a buffer layer 120.
  • the buffer layer 120 is an AlN layer formed by sputtering.
  • the substrate 110 is a cubic substrate.
  • the buffer layer 120 is a hexagonal layer.
  • the thin film substrate 100 includes the cubic substrate 110 and the hexagonal buffer layer 120.
  • FIG. 4 is an enlarged view of FIG.
  • the c-axis of the buffer layer faces the first direction J1 over the plate surface of the substrate 110.
  • the first direction J1 is inclined by an angle ⁇ 1 with respect to the direction perpendicular to the plate surface of the substrate 110.
  • the growth direction of the buffer layer 120 is inclined by an angle ⁇ 1 with respect to the direction perpendicular to the plate surface of the substrate 110.
  • the inclination angle ⁇ ⁇ b> 1 of the growth direction of the buffer layer 120 is close to the arrangement angle ⁇ of the target 1500.
  • the angle ⁇ 1 is in the range of 10 ° to 60 °. Preferably, the angle ⁇ 1 is in the range of 15 ° to 55 °. More preferably, the angle ⁇ 1 is in the range of 20 ° to 50 °. More preferably, the angle ⁇ 1 is in the range of 25 ° to 45 °.
  • FIG. 5 is a diagram showing the positional relationship between the substrate 110 and the target 1500 in this embodiment in a polar coordinate space.
  • a direction perpendicular to the plate surface of the substrate 110 is a normal direction Z A.
  • the tilt angle from the normal direction Z A in the first direction J1 is defined as a declination angle ⁇ A
  • the in-plane rotation direction of the substrate 110 in the first direction J1 is defined as a declination angle ⁇ A.
  • a direction perpendicular to the surface of the target 1500 is defined as a normal direction Z B.
  • the target particles reach the substrate 110 from the direction of the normal direction Z B of the target 1500 or a direction close to that direction.
  • the reached target particles are crystallized so as to be thermodynamically stable. Therefore, the incident direction of the target particles is close to the growth direction of the buffer layer 120. Therefore, the first direction J1 which is the c-axis direction of the buffer layer 120 is close to the normal direction Z B of the target 1500.
  • the substrate 110 is a cubic substrate. Therefore, atoms are arranged at the lattice apexes on the plate surface of the substrate 110.
  • the buffer layer 120 is hexagonal.
  • the inclined surface of the buffer layer 120 matches the plate surface of the substrate 110.
  • a (10-13) plane of the buffer layer 120 described later is an inclined surface of the buffer layer 120.
  • atoms are arranged at the positions of the vertices of a rectangular lattice. Therefore, the atoms located at the square lattice-like vertices of the substrate 110 and the atoms located at the rectangular lattice-like vertices of the buffer layer 120 are combined. Therefore, the hexagonal buffer layer 120 can be grown on the cubic substrate 110.
  • target particles are transported toward the substrate 110 from a specific direction with respect to the substrate 110. That is, when viewed from the plate surface of the substrate 110, the raw material particles are always transported from a substantially constant direction.
  • the c-axis of the GaN layer at the first location on the substrate 110 is in the first direction J1.
  • the c-axis of the GaN layer at the second location on the substrate 110 also faces the first direction J1.
  • most of the c-axis of the AlN layer and the GaN layer to be formed are oriented in the first direction J1 over the plate surface of the substrate 110.
  • the c-axis is inclined at a specific angle ⁇ 1 (see FIG. 4) with respect to the direction perpendicular to the plate surface of the substrate 110. Further, the c-axis is directed in a specific direction within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate 110 or a direction equivalent to the [110] direction.
  • the c-axis of the GaN layer at the third location of the substrate 110 faces the second direction J2.
  • the c-axis of the GaN layer at the fourth position of the substrate 110 faces the third direction J3.
  • the second direction J2 and the third direction J3 are different directions.
  • the c-axis is directed in different directions depending on the location of the substrate 110.
  • the buffer layer 120 has a first region and a second region rotated by 30 ° in the in-plane rotation direction from the first region. That is, two regions having different crystal orientations are mixed. Therefore, a single crystal cannot be obtained. Even if an off-substrate is used, a crystal with good crystallinity cannot be obtained.
  • the thin film substrate 100 of this embodiment includes a substrate 110 and a buffer layer 120.
  • the c-axis of the buffer layer 120 faces the first direction J1 over the plate surface of the substrate 110. That is, the c-axis of the buffer layer 120 faces the first direction J1 at a rate of 95% or more.
  • the substrate 110 is not arranged in a direction equivalent to the [110] direction, the proportion of the c-axis facing the first direction J1 decreases. Even in such a case, the c-axis of the buffer layer 120 faces the first direction J1 at a rate of at least 50% or more.
  • the c-axis of the buffer layer 120 faces the first direction J1 at a rate of 50% to 100%.
  • the III-group nitride semiconductor layer can be grown with That is, the dominant direction of the c-axis in the buffer layer 120 determines the inclination of the c-axis of the III-group nitride semiconductor layer that is subsequently grown. In the group III nitride semiconductor layer grown in this way, 95% or more of the c-axis is directed in the first direction J1. That is, almost a single crystal is obtained.
  • the ratio of the c-axis facing the first direction J1 in the c-axis of the buffer layer 120 is a ratio of 50% or more and 100% or less. Preferably, it is a ratio of 65% or more and 100% or less. More preferably, the ratio is 80% or more and 100% or less. More preferably, the ratio is 90% or more and 100% or less.
  • the cubic substrate 110 in the present embodiment is a Si (001) substrate.
  • other cubic substrates can be used.
  • an MgO substrate, a TiO 2 substrate, and a SrTiO 3 substrate can be mentioned.
  • a cubic substrate such as a SiC substrate or a GaAs substrate can also be used.
  • a (110) substrate may be used.
  • the buffer layer 120 of this embodiment is an AlN layer.
  • Other buffer layers may also be used. Examples of the buffer layer include a BN layer, a ZnO layer, and a ZnS layer.
  • the manufacturing method of the thin film substrate 100 may include a first step in which the susceptor 1200 is not rotated and a second step in which the susceptor 1200 is rotated. That is, in the initial stage of film formation of the buffer layer 120, a part of the buffer layer 120 is formed with a film thickness of about 10 nm or more without rotating the susceptor 1200. At this stage, the orientation direction of the c-axis of the buffer layer 120 is determined. Thereafter, the remaining part of the buffer layer 120 is formed while the susceptor 1200 is rotated. At this stage, since the c-axis alignment direction has already been determined, the remainder of the buffer layer 120 grows according to the determined c-axis alignment direction. By using two steps in this way, the in-plane uniformity of the buffer layer 120 is improved.
  • Target Arrangement Unit The target arrangement unit 1400 of this embodiment is fixed to the chamber 1100. However, the target placement unit 1400 can change the tilt angle so that the surface of the target 1500 is relatively variable within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. It may be.
  • the angle formed by the direction perpendicular to the plate surface of the substrate 110 and the direction in which the target 1500 is disposed as viewed from the substrate 110 is inclined by an angle ⁇ . is doing. Therefore, the hexagonal buffer layer 120 can be grown on the cubic substrate 110. Therefore, for example, a group III nitride semiconductor can be grown on a large-diameter Si (001) substrate.
  • the thin film substrate 100 of the present embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a III-group nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
  • FIG. 7 is a diagram illustrating a schematic configuration of the HEMT 200 according to the second embodiment.
  • the HEMT 200 is a semiconductor element having a group III nitride semiconductor.
  • the HEMT 200 includes a substrate 110, a buffer layer 120, a base layer 230, a channel layer 240, a barrier layer 250, a source electrode S1, a drain electrode D1, and a gate electrode G1.
  • the substrate 110 is a cubic substrate. Specifically, it is a Si (001) substrate.
  • the buffer layer 120 is a hexagonal AlN layer. As described above, the hexagonal buffer layer 120 is formed on the cubic substrate 110.
  • the underlayer 230 is a GaN layer.
  • the channel layer 240 is a GaN layer.
  • the barrier layer 250 is an AlGaN layer. These are examples, and the base layer 230, the channel layer 240, and the barrier layer 250 may be other types of semiconductor layers.
  • FIG. 8 is a conceptual diagram illustrating the substrate 110, the buffer layer 120, and the base layer 230 extracted from the HEMT 200.
  • the first angle ⁇ ⁇ b> 1 is an angle formed by the direction perpendicular to the plate surface of the substrate 110 and the c-axis of the buffer layer 120.
  • the second angle ⁇ ⁇ b> 2 is an angle formed by the direction perpendicular to the plate surface of the substrate 110 and the c-axis of the base layer 230.
  • the angle ⁇ 2 is in the range of 10 ° to 60 °. Preferably, the angle ⁇ 2 is in the range of 15 ° to 55 °. More preferably, the angle ⁇ 2 is in the range of 20 ° to 50 °. More preferably, the angle ⁇ 2 is in the range of 25 ° to 45 °.
  • the direction of the c-axis of the base layer 230 is substantially the same as the direction of the c-axis of the buffer layer 120. That is, GaN grows on the buffer layer 120 whose c-axis is inclined, inheriting the crystallinity of the buffer layer 120.
  • the second angle ⁇ 2 is substantially equal to the first angle ⁇ 1.
  • the second angle ⁇ 2 is inclined by 0 ° or more and 5 ° or less with respect to the first angle ⁇ 1 in both the direction perpendicular to the plate surface of the substrate 110 and the in-plane direction.
  • the c-axis of the base layer 230 is tilted within a range of 0 ° to 5 ° with respect to both the direction perpendicular to the plate surface of the substrate 110 and the in-plane direction with respect to the c-axis direction of the buffer layer 120. is doing. Preferably, it is in the range of 0 ° to 3 °. More preferably, it is in the range of 0 ° to 1 °.
  • the c-axis of the buffer layer 120 is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate 110 or a direction equivalent to the [110] direction.
  • the surface of the foundation layer 230 that is a GaN layer is a nonpolar surface. Therefore, spontaneous polarization and piezo polarization are suppressed. Therefore, a normally-off type HEMT is easily obtained. Further, when applied to a light emitting element, wavelength shift due to polarization in the light emitting layer is suppressed. Further, separation of electron and hole wave functions due to electric field distortion is suppressed. Therefore, it is possible to suppress a decrease in luminous efficiency.
  • FIG. 9 is a graph showing the polarization in the thin film when InGaN having an In composition ratio of 20% is grown on GaN.
  • FIG. 10 is a graph showing polarization in a thin film when AlGaN having an Al composition ratio of 20% is grown on GaN.
  • the degree of polarization when the c-axis is inclined is smaller than the degree of polarization when the c-axis is not inclined. Even if the In composition ratio or Al composition ratio changes, this tendency does not change so much. Therefore, in the semiconductor device using the nonpolar plane with the c-axis inclined in this embodiment, polarization is suppressed.
  • the buffer layer 120 is formed on the substrate 110 using the film forming apparatus 1000 of the first embodiment. Thereafter, the deposited substrate 110 is taken out of the deposition apparatus 1000.
  • a group III nitride semiconductor single crystal is epitaxially grown on the buffer layer 120 using an MOCVD apparatus or the like. That is, the base layer 230 is grown on the buffer layer 120. Next, the channel layer 240 is grown on the base layer 230. Then, a barrier layer 250 is grown on the channel layer 240.
  • the source electrode S1, the drain electrode D1, and the gate electrode G1 are formed on the barrier layer 250. Then, the substrate 110 is cut out into chips. Thereby, the HEMT 200 shown in FIG. 7 is manufactured.
  • MIS HEMT The technique of the present embodiment can be applied not only to the HEMT 200 of the present embodiment but also to a MIS type HEMT or a MOS type HEMT.
  • GaN Template The technique of this embodiment can also be applied to a GaN template.
  • the structure of the GaN template in that case is the same as that shown in FIG.
  • the HEMT 200 of this embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a group III nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
  • FIG. 11 is a diagram showing a schematic configuration of a light emitting element 300 of the third embodiment.
  • the light emitting element 300 is a semiconductor element having a group III nitride semiconductor.
  • the light emitting element 300 includes a substrate 110, a buffer layer 120, an n-type contact layer 330, a light emitting layer 340, a p-type cladding layer 350, a p-type contact layer 360, an n-electrode N1, a p-electrode P1, Have
  • the substrate 110 is a cubic substrate. Specifically, it is a Si (001) substrate.
  • the buffer layer 120 is a hexagonal AlN layer. As described above, the hexagonal buffer layer 120 is formed on the cubic substrate 110.
  • the n-type contact layer 330 is a layer in contact with the n electrode N1.
  • the n-type contact layer 330 has n-type GaN.
  • the light emitting layer 340 is a layer that emits light by recombination of electrons and holes.
  • the p-type cladding layer 350 is a layer for confining electrons.
  • the p-type cladding layer 350 is a layer having a superlattice structure.
  • the p-type contact layer 360 is a layer in contact with the p-electrode P1.
  • the p-type contact layer 360 has p-type GaN.
  • Buffer Layer and GaN Layer The relationship between the buffer layer 120 and the n-type contact layer 330 in the third embodiment is the same as the relationship between the buffer layer 120 and the base layer 230 in the second embodiment. That is, the relationship shown in FIG.
  • the buffer layer 120 is formed on the substrate 110 using the film forming apparatus 1000 of the first embodiment. Thereafter, the deposited substrate 110 is taken out of the deposition apparatus 1000.
  • a group III nitride semiconductor single crystal is epitaxially grown on the buffer layer 120 using an MOCVD apparatus or the like. That is, the n-type contact layer 330 is grown on the buffer layer 120. Next, the light emitting layer 340 is grown on the n-type contact layer 330. Then, a p-type cladding layer 350 is grown on the light emitting layer 340. Then, a p-type contact layer 360 is grown on the p-type cladding layer 350.
  • Electrode forming step Then, a recess reaching from the p-type contact layer 360 to the n-type contact layer 330 is provided. Then, an n-electrode N1 is formed on the n-type contact layer 330 exposed in the recess. A p-electrode P1 is formed on the p-type contact layer 360. Further, the substrate 110 is cut out into chips. Thereby, the light emitting element 300 shown in FIG. 11 is manufactured.
  • Modified example 4-1 Semiconductor Laser Element
  • the semiconductor element according to the third embodiment shown in FIG. However, the technique of the present embodiment can be similarly applied to the semiconductor laser element.
  • the present technology can also be applied to a light receiving element.
  • the light receiving element uses the light emitting layer of the light emitting element 300 as a light absorbing layer. Examples of the light receiving element include a solar cell.
  • the HEMT 200 of this embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a group III nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
  • FIG. 12 is a view showing the structure of the thin film substrate 400 of the fourth embodiment.
  • the thin film substrate 400 includes a substrate 110, a buffer layer 120, and an intermediate layer IL.
  • the buffer layer 120 is an AlN layer formed by sputtering.
  • the substrate 110 is a cubic substrate.
  • the buffer layer 120 is a hexagonal layer.
  • the intermediate layer IL is a hexagonal layer.
  • the thin film substrate 100 includes the cubic substrate 110, the hexagonal buffer layer 120, and the hexagonal intermediate layer IL.
  • the buffer layer 120 of the fourth embodiment is the same as the buffer layer 120 of the first embodiment.
  • the intermediate layer IL of the fourth embodiment is a layer formed by the MOCVD method.
  • the intermediate layer IL is a layer for reducing lattice defects while inheriting the crystallinity of the buffer layer 120.
  • the film thickness of the intermediate layer IL is, for example, in the range of 10 nm to 100 nm.
  • the film thickness of the intermediate layer IL may be other than the above.
  • the following three types of intermediate layers can be mentioned, for example.
  • the first intermediate layer is a high temperature AlN layer.
  • the growth temperature of the high-temperature AlN layer is 950 ° C. or higher and 1100 ° C. or lower.
  • the second intermediate layer is a layer in which a low temperature AlN layer and a high temperature AlN layer are stacked. At that time, a low temperature AlN layer is formed on the buffer layer 120, and a high temperature AlN layer is formed on the low temperature AlN layer.
  • the growth temperature of the low-temperature AlN layer is 650 ° C. or higher and 800 ° C. or lower.
  • the third intermediate layer is a layer in which a high-temperature AlN layer and an AlN / GaN superlattice layer are stacked. At that time, a high-temperature AlN layer is formed on the buffer layer 120, and an AlN / GaN superlattice layer is formed on the high-temperature AlN layer.
  • the growth temperature of the AlN / GaN superlattice layer is 950 ° C. or higher and 1100 ° C. or lower.
  • the intermediate layer IL can reduce lattice defects.
  • the intermediate layer IL improves the crystallinity of the hexagonal semiconductor layer.
  • FIG. 13 is a diagram illustrating a structure of a HEMT 500 according to a modification of the fourth embodiment.
  • the HEMT 500 is a semiconductor element having a group III nitride semiconductor.
  • the HEMT 500 includes a substrate 110, a buffer layer 120, an intermediate layer IL, a base layer 230, a channel layer 240, a barrier layer 250, a source electrode S1, a drain electrode D1, and a gate electrode G1. ing.
  • the intermediate layer IL is located between the buffer layer 120 and the semiconductor layer.
  • Each layer of the HEMT 500 is the same as each layer of the HEMT 200 of the second embodiment except for the intermediate layer IL.
  • the intermediate layer IL may be any one from the first intermediate layer to the third intermediate layer of the present embodiment.
  • FIG. 14 is a diagram showing a structure of a light emitting element 600 according to a modification of the fourth embodiment.
  • the light emitting element 600 is a semiconductor element having a group III nitride semiconductor.
  • the light-emitting element 600 includes a substrate 110, a buffer layer 120, an intermediate layer IL, an n-type contact layer 330, a light-emitting layer 340, a p-type cladding layer 350, a p-type contact layer 360, an n-electrode N1, p electrode P1.
  • the intermediate layer IL is located between the buffer layer 120 and the semiconductor layer.
  • Each layer of the light emitting element 600 is the same as each layer of the light emitting element 300 of the third embodiment except for the intermediate layer IL.
  • the intermediate layer IL may be any one from the first intermediate layer to the third intermediate layer of the present embodiment.
  • the intermediate layer IL is formed by the MOCVD method.
  • other film forming methods may be used to form the intermediate layer IL.
  • HVPE method and MBE method are mentioned.
  • Experiment 1 1. Formation of GaN layer 1-1. Film Formation Conditions Using the film formation apparatus 1000, an AlN layer was formed on a Si (001) substrate. The Si (001) substrate was placed on the susceptor 1200 so that when the target was projected onto the Si (001) substrate, the target was placed in the [110] direction of the Si (001) substrate or a direction equivalent to the [110] direction. . The angle formed by the direction perpendicular to the plate surface of the Si (001) substrate and the direction in which the target is located was 36 °. The target was arranged at a position within 30 ° in the in-plane rotation direction of the Si (001) substrate from the [110] direction of the Si (001) substrate or an equivalent direction thereof.
  • the susceptor 1200 was not rotated. Therefore, the target particles are transported from the direction in which the target is located with respect to the arranged Si (001) substrate. That is, the target particles reach the Si (001) substrate from a direction close to [111].
  • an AlN layer was formed on the Si (001) substrate.
  • the substrate temperature was 450 ° C.
  • the target was Al.
  • 50 sccm of N 2 gas was supplied into the chamber 1100.
  • a voltage was applied to the target at DC 300W.
  • the internal pressure was 0.23 Pa.
  • the film formation time was 30 minutes. Thereby, an AlN layer of 80 nm was formed on the Al layer.
  • FIG. 15 is a scanning electron micrograph (SEM photograph) showing the surface of the GaN layer deposited on the Si (001) substrate. As shown in FIG. 15, anisotropy is recognized in the growth direction of the GaN layer.
  • FIG. 16 is a scanning electron micrograph (SEM photograph) showing a cross section of the GaN layer formed on the Si (001) substrate. As shown in FIG. 16, the c-axis of the GaN layer is inclined by a certain angle with respect to the plate surface of the Si (001) substrate. The angle formed by this was about 32 °.
  • FIG. 17 is an enlarged view of FIG. As shown in FIG. 17, the c-axis of the AlN layer is inclined in the sputtering direction. Further, the c-axis of the GaN layer is also inclined in the sputtering direction. The AlN layer and the GaN layer are grown in substantially the same direction. The deviation between the direction in which the AlN layer grows and the direction in which the GaN layer grows was 2 ° or less.
  • FIG. 18 is a scanning electron micrograph (SEM photograph) showing the surface of the GaN layer when the susceptor 1200 is rotated at 20 rpm. At this time, GaN layers were sparsely grown on the Si (001) substrate.
  • FIG. 19 is a graph showing the result (2 ⁇ / ⁇ ) of X-ray diffraction at an arbitrary location. As shown in FIG. 19, a peak of GaN (10-13) and a peak of Si (004) were observed. This indicates that the GaN layer formed on the Si (001) substrate has grown in the direction of the (10-13) plane.
  • FIG. 20 shows the (10-13) plane of the GaN layer.
  • FIG. 23 is a scanning electron micrograph (SEM photograph) showing a cross section of a GaN layer formed on a Si (001) substrate.
  • the first GaN layer was grown on the first AlN layer.
  • the film thickness of the first GaN layer is 1 ⁇ m.
  • a second AlN layer was grown on the first GaN layer.
  • the film thickness of the second AlN layer is about 10 nm.
  • a second GaN layer was grown on the second AlN layer.
  • the film thickness of the second GaN layer is 1 ⁇ m.
  • the surface of the second GaN layer is flat. Therefore, it is easy to form various element structures on the flat GaN layer.
  • FIG. 24 is a transmission electron micrograph (cross-sectional TEM photograph) showing a boundary surface between an AlN layer and a GaN layer formed on a Si (001) substrate.
  • the c-axis of the AlN layer does not face the first direction J1.
  • the c-axis of the AlN layer faces the first direction J1.
  • the c-axis of the AlN layer faces the first direction J1 at a rate of 50% or more.
  • the c-axis of the GaN layer faces the first direction J1 over the imaging region in FIG.
  • the information in the first direction J1 which is the dominant direction among the c-axis directions of the AlN layer as the underlying layer, is inherited.
  • the GaN layer above the AlN layer information on the c-axis direction that is not dominant in the AlN layer is hardly carried over. Therefore, if the c-axis of the AlN layer faces the first direction J1 at a rate of 50% or more, the c-axis faces the first direction J1 substantially uniformly over the plate surface of the Si (001) substrate.
  • a GaN layer is obtained. That is, it became clear that a unidirectionally oriented GaN layer was obtained.
  • a (10-13) plane GaN layer could be grown.
  • the semiconductor layer can be grown on a crystal plane corresponding to the angle ⁇ . That is, AlN particles that have reached the substrate from a specific direction grow with the c-axis inclined in a direction close to that direction. At that time, it is considered that the semiconductor layer grows while making the thermodynamically stable surface flat.
  • Experiment 2 1. Sputtering angle 1-1. Film-forming conditions The film-forming conditions are almost the same as in Experiment 1. Therefore, conditions different from those in Experiment 1 will be described.
  • the internal pressure was 0.02 Pa.
  • the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was 36 ° and 20 °.
  • FIG. 25 is a photomicrograph showing the surface of the GaN layer when the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target is 36 °. As shown in FIG. 25, the (10-13) plane of the GaN layer was observed.
  • FIG. 25A is a photograph showing a case where the growth time is 1 minute.
  • FIG. 25B shows a case where the growth time is 5 minutes.
  • FIG. 25C shows a case where the growth time is 10 minutes.
  • the c-axis of the GaN layer was inclined by 32 ° with respect to the direction perpendicular to the plate surface of the substrate.
  • FIG. 26 is a photomicrograph showing the surface of the GaN layer when the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target is 20 °. As shown in FIG. 26, the (10-15) plane of the GaN layer was observed.
  • FIG. 26A is a photograph showing a case where the growth time is 1 minute.
  • FIG. 26B shows a case where the growth time is 5 minutes.
  • FIG. 26C shows a case where the growth time is 10 minutes.
  • the c-axis of the GaN layer was inclined 20 ° with respect to the direction perpendicular to the plate surface of the substrate.
  • GaN layers growing in different plane directions were obtained. That is, the growth direction of the GaN layer can be controlled to some extent by changing the irradiation direction and arrangement of the target.
  • FIG. 27 is a diagram showing the structure of the sample of Experiment 3. Samples A, B, and C were used as samples. Samples A, B, and C respectively have the first intermediate layer, the second intermediate layer, and the third intermediate layer of the fourth embodiment.
  • Sample A is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order.
  • the intermediate layer IL is a high-temperature AlN layer having a thickness of 20 nm.
  • the thickness of the AlN layer is 45 nm.
  • the film thickness of the GaN layer is 4 ⁇ m.
  • the GaN layer is obtained by growing the (10-13) plane.
  • the AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °.
  • the intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
  • Sample B is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order.
  • the intermediate layer IL is obtained by stacking a high-temperature AlN layer having a thickness of 20 nm on a low-temperature AlN layer having a thickness of 10 nm.
  • the thickness of the AlN layer is 45 nm.
  • the film thickness of the GaN layer is 4 ⁇ m.
  • the GaN layer is obtained by growing the (10-13) plane.
  • the AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °.
  • the intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
  • Sample C is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order.
  • the intermediate layer IL is obtained by stacking 25 pairs of AlN / GaN superlattice layers on a high-temperature AlN layer having a thickness of 20 nm.
  • the thickness of the AlN layer is 45 nm.
  • the film thickness of the GaN layer is 4 ⁇ m.
  • the GaN layer is obtained by growing the (10-13) plane.
  • the AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °.
  • the intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
  • X-ray diffraction was measured for (10-13) GaN.
  • the full width at half maximum FWHM of the X-ray of GaN having the intermediate layer IL was smaller than the full width at half maximum FWHM of the X-ray of GaN having no intermediate layer IL. Further, the full width at half maximum FWHM of the X-ray of GaN having the superlattice layer as the intermediate layer IL was about half of the full width at half maximum FWHM of the GaN X-ray having no intermediate layer IL.
  • the provision of the intermediate layer IL improves the crystallinity of the GaN layer grown thereon. If a superlattice layer is used as the intermediate layer IL, the crystallinity of the GaN layer is further improved.
  • SYMBOLS 100 Thin film substrate 110 ... Substrate 120 ... Buffer layer 200 ... HEMT G1 ... Gate electrode S1 ... Source electrode D1 ... Drain electrode 300 ... Light emitting element 330 ... n-type contact layer 340 ... Light emitting layer 350 ... p-type cladding layer 360 ... p-type contact layer N1 ... n electrode P1 ... p electrode IL ... intermediate layer DESCRIPTION OF SYMBOLS 1000 ... Film-forming apparatus 1100 ... Chamber 1200 ... Susceptor 1300 ... Heater 1400 ... Target arrangement

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Abstract

The purpose of the present invention is to provide a thin-film substrate in which a hexagonal crystal buffer layer is formed on a cubic crystal substrate, a semiconductor device, a manufacturing method therefor, a deposition apparatus, a deposition method and a GaN template. This deposition method is a method that deposits a hexagonal crystal thin-film on a cubic crystal substrate. A substrate (110) is a cubic crystal Si (001) substrate. The substrate (110) is disposed on a susceptor (1200) in a chamber (1100). A target (1500) is disposed at a position that is inclined within a range of 10° to 60° with respect to a direction perpendicular to the plate surface of the substrate (110). A hexagonal crystal buffer layer (120) is deposited on the cubic crystal substrate (110) by sputtering without rotating the substrate (110) with respect to the chamber (1100).

Description

薄膜基板と半導体装置とこれらの製造方法および成膜装置および成膜方法およびＧａＮテンプレートThin film substrate, semiconductor device, manufacturing method thereof, film forming apparatus, film forming method, and GaN template
　本明細書の技術分野は、基板にその基板と結晶構造の異なるバッファ層を形成する薄膜基板と半導体装置とこれらの製造方法および成膜装置および成膜方法およびＧａＮテンプレートに関する。 The technical field of this specification relates to a thin film substrate, a semiconductor device, a manufacturing method, a film forming device, a film forming method, and a GaN template for forming a buffer layer having a crystal structure different from that of the substrate on the substrate.
　ＧａＮに代表されるIII 族窒化物半導体では、絶縁破壊電界の強度が高く、かつ融点が高い。そのため、III 族窒化物半導体は、ＧａＡｓ系半導体に代わる、高出力、高周波、高温用の半導体デバイスの材料として期待されている。そのため、III 族窒化物半導体を用いるＨＥＭＴ素子などが研究開発されている。また、III 族窒化物半導体は、発光素子にも応用されている。 A III-group nitride semiconductor represented by GaN has a high breakdown field strength and a high melting point. Therefore, group III nitride semiconductors are expected as materials for semiconductor devices for high output, high frequency, and high temperature, replacing GaAs semiconductors. Therefore, a HEMT device using a III-group nitride semiconductor has been researched and developed. In addition, Group III group nitride semiconductors are also applied to light emitting devices.
　III 族窒化物半導体は、ウルツ鉱型に代表される六方晶の結晶構造を有する。そのため、成長基板として、六方晶基板が一般的に用いられる。このような六方晶基板として、例えば、サファイア基板が挙げられる。また、特許文献１のように、成長基板として、Ｓｉ（１１１）基板が用いられることもある。ここでＳｉ（１１１）基板は、六方晶に近い構造を有している。Ｓｉ基板については、大口径基板を安価に高品質で製造することができる。そのため、Ｓｉ基板の上にIII 族窒化物半導体を成長させることは工業的に意義がある。 III group III nitride semiconductor has a hexagonal crystal structure represented by wurtzite type. For this reason, a hexagonal crystal substrate is generally used as the growth substrate. An example of such a hexagonal substrate is a sapphire substrate. Further, as in Patent Document 1, a Si (111) substrate may be used as a growth substrate. Here, the Si (111) substrate has a structure close to a hexagonal crystal. As for the Si substrate, a large-diameter substrate can be manufactured with high quality at low cost. Therefore, it is industrially significant to grow a III-group nitride semiconductor on a Si substrate.
特開２０１０－６２４８２号公報JP 2010-62482 A
　一方、Ｓｉ（００１）基板は、立方晶基板である。Ｓｉ（００１）基板の表面では、Ｓｉ原子が正方形に配列されている。このような立方晶のＳｉ（００１）基板の上に、六方晶のIII 族窒化物半導体を成長させることは決して容易ではない。いうまでもなく、立方晶と六方晶とでは、結晶構造が大きく異なっているからである。 On the other hand, the Si (001) substrate is a cubic substrate. On the surface of the Si (001) substrate, Si atoms are arranged in a square shape. It is not easy to grow a hexagonal III-V nitride semiconductor on such a cubic Si (001) substrate. Needless to say, the crystal structures of the cubic and hexagonal crystals are greatly different.
　しかし、Ｓｉ（００１）基板は、Ｓｉ（１１１）基板よりも一般的に安価である。また、Ｓｉ（１１１）基板よりも大口径のＳｉ（００１）基板が工業的に生産されている。そのため、Ｓｉ（００１）基板の上にIII 族窒化物半導体を成長させる技術を確立することは工業的に有意義である。 However, Si (001) substrates are generally less expensive than Si (111) substrates. Further, Si (001) substrates having a larger diameter than Si (111) substrates are industrially produced. Therefore, it is industrially meaningful to establish a technique for growing a group III group nitride semiconductor on a Si (001) substrate.
　本明細書の技術は、前述した従来の技術が有する問題点を解決するためになされたものである。その課題とは、立方晶基板に六方晶のバッファ層を形成する薄膜基板と半導体装置とこれらの製造方法および成膜装置および成膜方法およびＧａＮテンプレートを提供することである。 The technology of this specification has been made to solve the problems of the conventional technology described above. The problem is to provide a thin film substrate and a semiconductor device for forming a hexagonal buffer layer on a cubic substrate, a manufacturing method thereof, a film forming device and a film forming method, and a GaN template.
　第１の態様における薄膜基板は、基板と、基板の上のバッファ層と、を有する。基板は、立方晶基板である。バッファ層は、六方晶である。バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いている。第１の方向は、基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜している。 The thin film substrate in the first aspect includes a substrate and a buffer layer on the substrate. The substrate is a cubic substrate. The buffer layer is hexagonal. The c-axis of the buffer layer faces the first direction at a rate of 50% or more. The first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate.
　この薄膜基板は、大口径のＳｉ（００１）基板に代表される立方晶基板の上に六方晶の薄膜を成膜したものである。バッファ層のｃ軸の５０％以上は、基板の板面の全面にわたって特定の方向を向いている。つまり、基板上のどの位置であっても、バッファ層のｃ軸の５０％以上は、その特定の方向を向いている。そのため、このバッファ層の上にIII 族窒化物半導体の単結晶をエピタキシャル成長させることができる。 This thin film substrate is obtained by forming a hexagonal thin film on a cubic substrate typified by a large-diameter Si (001) substrate. 50% or more of the c-axis of the buffer layer faces a specific direction over the entire plate surface of the substrate. In other words, at any position on the substrate, 50% or more of the c-axis of the buffer layer faces the specific direction. Therefore, a single crystal of a Group III nitride semiconductor can be epitaxially grown on the buffer layer.
　第２の態様における薄膜基板においては、立方晶基板は、Ｓｉ（００１）基板である。第１の方向は、基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にある。 In the thin film substrate in the second aspect, the cubic substrate is a Si (001) substrate. The first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
　第３の態様における薄膜基板においては、バッファ層は、ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）である。 In the thin film substrate according to the third aspect, the buffer layer is an Al x Ga y In z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
　第４の態様における薄膜基板は、バッファ層の上の中間層を有する。中間層は、六方晶である。 The thin film substrate in the fourth aspect has an intermediate layer on the buffer layer. The intermediate layer is hexagonal.
　第５の態様における薄膜基板においては、中間層は、超格子層を有する。 In the thin film substrate according to the fifth aspect, the intermediate layer has a superlattice layer.
　第６の態様における半導体装置は、基板と、基板の上のバッファ層と、バッファ層の上のIII 族窒化物半導体層と、を有する。基板は、立方晶基板である。バッファ層は、六方晶である。バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いている。第１の方向は、基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜している。III 族窒化物半導体層のｃ軸は、基板の板面に垂直な方向および面内方向の両方について、第１の方向に対して０°以上５°以下の範囲内で傾斜している。 The semiconductor device according to the sixth aspect includes a substrate, a buffer layer on the substrate, and a group III group nitride semiconductor layer on the buffer layer. The substrate is a cubic substrate. The buffer layer is hexagonal. The c-axis of the buffer layer faces the first direction at a rate of 50% or more. The first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate. The c-axis of the group III group nitride semiconductor layer is inclined within a range of 0 ° to 5 ° with respect to the first direction in both the direction perpendicular to the plate surface of the substrate and the in-plane direction.
　第７の態様における半導体装置においては、立方晶基板は、Ｓｉ（００１）基板である。第１の方向は、基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にある。 In the semiconductor device according to the seventh aspect, the cubic substrate is a Si (001) substrate. The first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
　第８の態様における半導体装置においては、バッファ層は、ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）である。 In the semiconductor device according to the eighth aspect, the buffer layer is an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
　第９の態様における半導体装置は、バッファ層とIII 族窒化物半導体層との間に中間層を有する。中間層は、六方晶である。 The semiconductor device according to the ninth aspect includes an intermediate layer between the buffer layer and the group III group nitride semiconductor layer. The intermediate layer is hexagonal.
　第１０の態様における半導体装置においては、中間層は、超格子層を有する。 In the semiconductor device according to the tenth aspect, the intermediate layer has a superlattice layer.
　第１１の態様におけるＧａＮテンプレートは、基板と、基板の上のバッファ層と、バッファ層の上のIII 族窒化物半導体層と、を有する。基板は、立方晶基板である。バッファ層は、六方晶である。バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いている。第１の方向は、基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜している。III 族窒化物半導体層のｃ軸は、基板の板面に垂直な方向および面内方向の両方について、第１の方向に対して０°以上５°以下の範囲内で傾斜している。また、立方晶基板は、Ｓｉ（００１）基板であってもよい。この場合、第１の方向は、基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にある。また、バッファ層は、ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）であってもよい。 The GaN template in the eleventh aspect has a substrate, a buffer layer on the substrate, and a group III nitride semiconductor layer on the buffer layer. The substrate is a cubic substrate. The buffer layer is hexagonal. The c-axis of the buffer layer faces the first direction at a rate of 50% or more. The first direction is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate. The c-axis of the group III nitride semiconductor layer is inclined within a range of 0 ° to 5 ° with respect to the first direction in both the direction perpendicular to the plate surface of the substrate and the in-plane direction. Further, the cubic substrate may be a Si (001) substrate. In this case, the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction. Further, the buffer layer may be an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
　第１２の態様における薄膜基板の製造方法は、立方晶基板をチャンバーの内部に配置する工程と、立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置する工程と、立方晶基板とターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより立方晶基板の上に六方晶のバッファ層を形成する工程と、を有する。 The thin film substrate manufacturing method according to the twelfth aspect includes a step of disposing a cubic substrate inside a chamber and an inclination within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate. And a step of forming a hexagonal buffer layer on the cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target. .
　第１３の態様における半導体装置の製造方法は、立方晶基板をチャンバーの内部に配置する工程と、立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置する工程と、立方晶基板とターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより立方晶基板の上に六方晶のバッファ層を形成する工程と、バッファ層の上にIII 族窒化物半導体層を成長させる工程と、を有する。 According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: arranging a cubic substrate inside a chamber; and tilting the cubic substrate within a range of 10 ° to 60 ° with respect to a direction perpendicular to a plate surface of the cubic substrate. A step of disposing a target at a predetermined position, a step of forming a hexagonal buffer layer on the cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target, and a buffer layer And a step of growing a group III nitride semiconductor layer on the substrate.
　第１４の態様における成膜方法は、基板の上に薄膜を成膜する方法である。この方法では、立方晶基板をチャンバーの内部に配置し、立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置し、立方晶基板とターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより立方晶基板の上に六方晶のバッファ層を形成する。第８の態様から第１０の態様において、立方晶基板は、Ｓｉ（００１）基板であってもよい。この場合、第１の方向は、基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にある。また、バッファ層は、ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）であってもよい。 The film forming method in the fourteenth aspect is a method of forming a thin film on a substrate. In this method, a cubic substrate is placed inside a chamber, and a target is placed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate. While maintaining the relative positional relationship between the substrate and the target, a hexagonal buffer layer is formed on the cubic substrate by sputtering. In the eighth aspect to the tenth aspect, the cubic substrate may be a Si (001) substrate. In this case, the first direction is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction. Further, the buffer layer may be an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
　第１５の態様における成膜装置は、基板を支持するための基板支持部と、基板支持部を収容するチャンバーと、基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で相対的に可変となるように傾斜させた位置に配置されたターゲット配置部と、を有する。 In a fifteenth aspect, a film forming apparatus includes a substrate support portion for supporting a substrate, a chamber for accommodating the substrate support portion, and a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate. And a target arrangement portion arranged at a position inclined so as to be relatively variable.
　本明細書では、立方晶基板に六方晶のバッファ層を形成する薄膜基板と半導体装置とこれらの製造方法および成膜装置および成膜方法およびＧａＮテンプレートが提供されている。 In this specification, a thin film substrate and a semiconductor device for forming a hexagonal buffer layer on a cubic substrate, a manufacturing method thereof, a film forming apparatus, a film forming method, and a GaN template are provided.
第１の実施形態における成膜装置の構造を示す概略構成図である。It is a schematic block diagram which shows the structure of the film-forming apparatus in 1st Embodiment. 第１の実施形態におけるＳｉ（００１）基板の面方位を示す図である。It is a figure which shows the surface orientation of the Si (001) board | substrate in 1st Embodiment. 第１の実施形態における薄膜基板の構成を示す図である。It is a figure which shows the structure of the thin film substrate in 1st Embodiment. 図３の拡大図である。FIG. 4 is an enlarged view of FIG. 3. 基板とターゲットとの位置関係を極座標空間で示す図である。It is a figure which shows the positional relationship of a board | substrate and a target in polar coordinate space. Ｓｉ（００１）基板の上にＭＯＣＶＤ法でＧａＮ層を成膜する場合を示す図である。It is a figure which shows the case where a GaN layer is formed into a film by MOCVD method on Si (001) board | substrate. 第２の実施形態におけるＨＥＭＴ素子の構造を示す概略構成図である。It is a schematic block diagram which shows the structure of the HEMT element in 2nd Embodiment. 第１の実施形態の成膜装置でＳｉ（００１）基板の上にＧａＮ層を成膜した場合のＧａＮ層の成長方向を示す図である。It is a figure which shows the growth direction of a GaN layer at the time of forming a GaN layer on a Si (001) board | substrate with the film-forming apparatus of 1st Embodiment. ＧａＮ層の上にＩｎＧａＮ層を形成した場合の分極を示すグラフである。It is a graph which shows the polarization at the time of forming an InGaN layer on a GaN layer. ＧａＮ層の上にＡｌＧａＮ層を形成した場合の分極を示すグラフである。It is a graph which shows the polarization at the time of forming an AlGaN layer on a GaN layer. 第３の実施形態における半導体発光素子の構造を示す概略構成図である。It is a schematic block diagram which shows the structure of the semiconductor light-emitting device in 3rd Embodiment. 第４の実施形態の薄膜基板の構造を示す図である。It is a figure which shows the structure of the thin film substrate of 4th Embodiment. 第４の実施形態の変形例におけるＨＥＭＴの構造を示す図である。It is a figure which shows the structure of HEMT in the modification of 4th Embodiment. 第４の実施形態の変形例における発光素子の構造を示す図である。It is a figure which shows the structure of the light emitting element in the modification of 4th Embodiment. Ｓｉ（００１）基板の上にＧａＮ層を成長させた場合のＧａＮ層の表面を示すＳＥＭ写真である。It is a SEM photograph which shows the surface of a GaN layer at the time of growing a GaN layer on Si (001) substrate. Ｓｉ（００１）基板の上にＧａＮ層を成長させた場合のＧａＮ層の断面を示すＳＥＭ写真である。It is a SEM photograph which shows the cross section of a GaN layer at the time of growing a GaN layer on Si (001) board | substrate. Ｓｉ（００１）基板の上にＧａＮ層を成長させた場合のＧａＮ層の拡大断面を示すＳＥＭ写真である。It is a SEM photograph which shows the expanded cross section of a GaN layer at the time of growing a GaN layer on Si (001) board | substrate. Ｓｉ（００１）基板の上に基板を回転させながらＧａＮ層を成長させた場合のＧａＮ層の表面を示すＳＥＭ写真である。It is a SEM photograph which shows the surface of a GaN layer at the time of growing a GaN layer, rotating a board | substrate on a Si (001) board | substrate. Ｓｉ（００１）基板の上に成長させたＧａＮ層についてのＸ線回折における２θ／ωスキャンの結果を示すグラフである。It is a graph which shows the result of the 2 (theta) / (omega) scan in the X-ray diffraction about the GaN layer grown on the Si (001) board | substrate. ＧａＮ層の（１０－１３）面を示す図である。It is a figure which shows the (10-13) plane of a GaN layer. Ｓｉ（００１）基板の上に成長させたＧａＮ層についてのＸ線回折におけるφスキャンの結果を示すグラフ（その１）である。It is a graph (the 1) which shows the result of (phi) scan in the X-ray diffraction about the GaN layer grown on the Si (001) board | substrate. Ｓｉ（００１）基板の上に成長させたＧａＮ層についてのＸ線回折におけるφスキャンの結果を示すグラフ（その２）である。It is a graph (the 2) which shows the result of the (phi) scan in the X-ray diffraction about the GaN layer grown on the Si (001) board | substrate. Ｓｉ（００１）基板の上に平坦なＧａＮ層を成長させた場合を示すＳＥＭ写真である。It is a SEM photograph which shows the case where a flat GaN layer is grown on a Si (001) substrate. Ｓｉ（００１）基板の上に成膜したＡｌＮ層およびＧａＮ層の境界面を示す断面ＴＥＭ写真である。It is a cross-sectional TEM photograph which shows the boundary surface of the AlN layer and GaN layer which were formed into a film on Si (001) board | substrate. 基板の板面に垂直な方向とターゲットの表面に垂直な方向との間のなす角を３６°とした場合におけるＧａＮ層の表面を示す顕微鏡写真である。It is a microscope picture which shows the surface of a GaN layer in case the angle made between the direction perpendicular | vertical to the plate surface of a board | substrate and the direction perpendicular | vertical to the surface of a target is 36 degrees. 基板の板面に垂直な方向とターゲットの表面に垂直な方向との間のなす角を２０°とした場合におけるＧａＮ層の表面を示す顕微鏡写真である。It is a microscope picture which shows the surface of a GaN layer in case the angle made between the direction perpendicular | vertical to the board surface of a board | substrate and the direction perpendicular | vertical to the surface of a target is 20 degrees. 実験３のサンプルの構造を示す図である。It is a figure which shows the structure of the sample of Experiment 3.
　以下、具体的な実施形態について、薄膜基板と半導体装置とこれらの製造方法および成膜装置および成膜方法およびＧａＮテンプレートを例に挙げて図を参照しつつ説明する。なお、図面中の各層の厚みの比率は、実際の比率を反映したものではない。 Hereinafter, specific embodiments will be described with reference to the drawings, taking a thin film substrate, a semiconductor device, a manufacturing method thereof, a film forming apparatus, a film forming method, and a GaN template as examples. In addition, the ratio of the thickness of each layer in the drawing does not reflect the actual ratio.
（第１の実施形態）
　第１の実施形態について説明する。 (First embodiment)
A first embodiment will be described.
１．成膜装置
１－１．成膜装置の構成
　図１は、本実施形態の成膜装置１０００の概略構成を示す図である。成膜装置１０００は、スパッタリングにより基板１１０の上に薄膜を成膜するための装置である。成膜装置１０００は、チャンバー１１００と、サセプター１２００と、ヒーター１３００と、ターゲット配置部１４００と、ターゲット１５００と、電圧印加部１６００と、ガス供給部（図示せず）と、を有する。 1. Film forming apparatus 1-1. Configuration of Film Forming Apparatus FIG. 1 is a diagram showing a schematic configuration of a film forming apparatus 1000 according to this embodiment. The film forming apparatus 1000 is an apparatus for forming a thin film on the substrate 110 by sputtering. The film forming apparatus 1000 includes a chamber 1100, a susceptor 1200, a heater 1300, a target placement unit 1400, a target 1500, a voltage application unit 1600, and a gas supply unit (not shown).
　チャンバー１１００は、スパッタリングを実施する基板１１０を収容するためのものである。また、チャンバー１１００は、サセプター１２００と、ヒーター１３００と、ターゲット配置部１４００と、ターゲット１５００と、を内部に収容している。サセプター１２００は、基板１１０を支持するための基板支持部である。ヒーター１３００は、サセプター１２００に支持される基板１１０を加熱するためのものである。ターゲット配置部１４００は、ターゲット１５００を配置するためのものである。ターゲット１５００は、スパッタリングにより基板１１０に薄膜を成膜するための原材料である。 The chamber 1100 is for accommodating the substrate 110 on which sputtering is performed. The chamber 1100 accommodates therein a susceptor 1200, a heater 1300, a target placement unit 1400, and a target 1500. The susceptor 1200 is a substrate support unit for supporting the substrate 110. The heater 1300 is for heating the substrate 110 supported by the susceptor 1200. The target placement unit 1400 is for placing the target 1500. The target 1500 is a raw material for forming a thin film on the substrate 110 by sputtering.
　電圧印加部１６００は、ターゲット１５００に電圧を印加するためのものである。ここで、チャンバー１１００は、接地されている。電圧印加部１６００は、直流電源を用いるものである。しかし、電圧印加部１６００は、交流電源あるいはパルスＤＣ電源を用いるものであってもよい。 The voltage application unit 1600 is for applying a voltage to the target 1500. Here, the chamber 1100 is grounded. The voltage application unit 1600 uses a DC power supply. However, the voltage application unit 1600 may use an AC power source or a pulse DC power source.
１－２．ターゲットの配置
　基板１１０の板面に垂直な方向と、基板１１０からみてターゲット１５００の配置されている方向とのなす角の角度は、角度θである。ここで、角度θは、基板１１０の表面の中心と、ターゲット１５００の表面の中心と、がなす角の角度である。角度θは、１０°以上６０°以下の範囲内である。つまり、ターゲット配置部１４００は、基板１１０の板面に垂直な方向に対して、１０°以上６０°以下の範囲内で傾斜させた位置に配置されている。もちろん、ターゲット１５００は、基板１１０の板面に垂直な方向に対して、１０°以上６０°以下の範囲内で傾斜させた位置に配置されている。好ましくは、角度θは、１５°以上５５°以下の範囲内である。より好ましくは、角度θは、２０°以上５０°以下の範囲内である。さらに好ましくは、角度θは、２５°以上４５°以下の範囲内である。 1-2. Target Arrangement The angle formed between the direction perpendicular to the plate surface of the substrate 110 and the direction in which the target 1500 is disposed when viewed from the substrate 110 is an angle θ. Here, the angle θ is an angle formed by the center of the surface of the substrate 110 and the center of the surface of the target 1500. The angle θ is in the range of 10 ° to 60 °. That is, the target placement unit 1400 is placed at a position that is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. Of course, the target 1500 is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. Preferably, the angle θ is in the range of 15 ° to 55 °. More preferably, the angle θ is in the range of 20 ° to 50 °. More preferably, the angle θ is in the range of 25 ° to 45 °.
　ターゲット１５００の表面は、基板１１０の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜している。また、ターゲット配置部１４００は、ターゲット１５００の表面が、基板１１０の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜する位置および向きで配置されている。 The surface of the target 1500 is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. In addition, the target placement unit 1400 is placed at a position and orientation in which the surface of the target 1500 is tilted within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110.
　したがって、この成膜装置１０００を用いると、特定の角度θの方向からターゲット粒子が基板１１０に向かって輸送される。また、基板１１０については回転させない。このように、成膜装置１０００は、指向性スパッタリング装置である。 Therefore, when this film forming apparatus 1000 is used, the target particles are transported toward the substrate 110 from the direction of the specific angle θ. Further, the substrate 110 is not rotated. Thus, the film forming apparatus 1000 is a directional sputtering apparatus.
２．成膜装置における成膜方法
２－１．用いる基板
　図２は、成膜に用いる基板１１０を示す図である。基板１１０は、Ｓｉ（００１）基板である。ここで、基板１１０は、立方晶基板である。基板１１０は、図２に示すようにオリエンテーションフラットを有する。また、図２には、［－１１０］方向と、［１１０］方向と、が描かれている。なお、基板１１０として、［１１０］方向または［１１０］方向と等価な方向に１５°以内のオフ角をつけたオフ基板を適用してもよい。 2. 2. Film forming method in film forming apparatus 2-1. 2. Substrate used FIG. 2 is a diagram showing a substrate 110 used for film formation. The substrate 110 is a Si (001) substrate. Here, the substrate 110 is a cubic substrate. The substrate 110 has an orientation flat as shown in FIG. Further, in FIG. 2, a [−110] direction and a [110] direction are drawn. As the substrate 110, an off substrate having an off angle of 15 ° or less in the [110] direction or a direction equivalent to the [110] direction may be applied.
２－２．成膜方法
　まず、チャンバー１１００の内部のサセプター１２００に基板１１０を配置する。この際、図１に示すように、ターゲット１５００を基板１１０の板面に射影した場合に、ターゲット１５００が基板１１０の［１１０］方向もしくは［１１０］方向に等価な方向に位置するように、ターゲット１５００を配置する。このとき、ターゲット１５００は、基板１１０の板面に垂直な方向に対して、１０°以上６０°以下の範囲内で傾斜させた位置に配置されている。ここで、ターゲット１５００の材質は、Ａｌである。また、Ｎ2 ガスを１０～１００ｓｃｃｍ程度供給する。なお、ターゲット１５００は、基板１１０の［１１０］方向または［１１０］方向と等価な方向から基板１１０の面内回転方向で３０°以内に位置する。 2-2. Film Forming Method First, the substrate 110 is placed on the susceptor 1200 inside the chamber 1100. At this time, as shown in FIG. 1, when the target 1500 is projected onto the plate surface of the substrate 110, the target 1500 is positioned in the [110] direction of the substrate 110 or the direction equivalent to the [110] direction. 1500 is arranged. At this time, the target 1500 is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. Here, the material of the target 1500 is Al. Further, about 2 to 100 sccm of N 2 gas is supplied. The target 1500 is located within 30 ° in the in-plane rotation direction of the substrate 110 from the [110] direction of the substrate 110 or a direction equivalent to the [110] direction.
　次に、電圧印加部１６００がターゲット１５００に電圧を印加する。これにより、ターゲット１５００から原材料が飛び出す。そして、飛び出した原材料は、基板１１０の板面に垂直な方向から傾斜する向きに飛散する。つまり、基板１１０からみると、［１１０］方向から基板１１０の板面に垂直な方向に角度θ程度だけ傾斜した方向から、原材料が飛び出してくる。このとき、サセプター１２００は、回転していない。つまり、基板１１０をチャンバー１１００に対して回転させない。そして、飛び出した原材料は、基板１１０に堆積する。これにより、基板１１０にバッファ層１２０が成膜される。つまり、立方晶基板であるＳｉ（００１）基板の上に六方晶のＡｌＮ層が成膜される。 Next, the voltage application unit 1600 applies a voltage to the target 1500. Thereby, the raw material jumps out of the target 1500. Then, the protruding raw material is scattered in a direction inclined from a direction perpendicular to the plate surface of the substrate 110. That is, when viewed from the substrate 110, the raw material is ejected from a direction inclined by an angle θ from the [110] direction in a direction perpendicular to the plate surface of the substrate 110. At this time, the susceptor 1200 is not rotating. That is, the substrate 110 is not rotated with respect to the chamber 1100. Then, the protruding raw material is deposited on the substrate 110. Thereby, the buffer layer 120 is formed on the substrate 110. That is, a hexagonal AlN layer is formed on a Si (001) substrate which is a cubic substrate.
３．成膜された薄膜基板
　図３は、成膜装置１０００により成膜された薄膜基板１００を示す図である。薄膜基板１００とは、薄膜を成膜された被成膜基板である。薄膜基板１００は、基板１１０と、バッファ層１２０と、を有している。バッファ層１２０は、スパッタリングにより成膜されたＡｌＮ層である。ここで、基板１１０は、立方晶基板である。一方、バッファ層１２０は、六方晶の層である。このように、薄膜基板１００は、立方晶の基板１１０と、六方晶のバッファ層１２０と、を有している。 3. FIG. 3 is a diagram showing a thin film substrate 100 formed by the film forming apparatus 1000. The thin film substrate 100 is a deposition target substrate on which a thin film is formed. The thin film substrate 100 includes a substrate 110 and a buffer layer 120. The buffer layer 120 is an AlN layer formed by sputtering. Here, the substrate 110 is a cubic substrate. On the other hand, the buffer layer 120 is a hexagonal layer. As described above, the thin film substrate 100 includes the cubic substrate 110 and the hexagonal buffer layer 120.
　図４は、図３を拡大した図である。図４に示すように、バッファ層のｃ軸は、基板１１０の板面にわたって第１の方向Ｊ１を向いている。そして、第１の方向Ｊ１は、基板１１０の板面に垂直な方向に対して角度θ１だけ傾斜している。バッファ層１２０の成長方向は、基板１１０の板面に垂直な方向に対して角度θ１だけ傾斜している。ここで、バッファ層１２０の成長方向の傾きの角度θ１は、ターゲット１５００の配置角度θと近い。 FIG. 4 is an enlarged view of FIG. As shown in FIG. 4, the c-axis of the buffer layer faces the first direction J1 over the plate surface of the substrate 110. The first direction J1 is inclined by an angle θ1 with respect to the direction perpendicular to the plate surface of the substrate 110. The growth direction of the buffer layer 120 is inclined by an angle θ1 with respect to the direction perpendicular to the plate surface of the substrate 110. Here, the inclination angle θ <b> 1 of the growth direction of the buffer layer 120 is close to the arrangement angle θ of the target 1500.
　角度θ１は、１０°以上６０°以下の範囲内である。好ましくは、角度θ１は、１５°以上５５°以下の範囲内である。より好ましくは、角度θ１は、２０°以上５０°以下の範囲内である。さらに好ましくは、角度θ１は、２５°以上４５°以下の範囲内である。 The angle θ1 is in the range of 10 ° to 60 °. Preferably, the angle θ1 is in the range of 15 ° to 55 °. More preferably, the angle θ1 is in the range of 20 ° to 50 °. More preferably, the angle θ1 is in the range of 25 ° to 45 °.
４．結晶構造と結晶成長
　図５は、本実施形態における基板１１０とターゲット１５００との間の位置関係を極座標空間で示す図である。基板１１０の板面に垂直な方向は、法線方向ＺA である。第１の方向Ｊ１における法線方向ＺA からの傾斜角を偏角θA 、第１の方向Ｊ１における基板１１０の面内回転方向を偏角φA 、と定義する。また、ターゲット１５００の表面に垂直な方向を法線方向ＺB と定義する。 4). Crystal Structure and Crystal Growth FIG. 5 is a diagram showing the positional relationship between the substrate 110 and the target 1500 in this embodiment in a polar coordinate space. A direction perpendicular to the plate surface of the substrate 110 is a normal direction Z A. The tilt angle from the normal direction Z A in the first direction J1 is defined as a declination angle θ A , and the in-plane rotation direction of the substrate 110 in the first direction J1 is defined as a declination angle φ A. A direction perpendicular to the surface of the target 1500 is defined as a normal direction Z B.
　本実施形態では、ターゲット粒子は、ターゲット１５００の法線方向ＺB の向きもしくはその方向に近い向きから基板１１０に到達する。そして、到達したターゲット粒子は、熱力学的に安定となるように結晶化する。そのため、ターゲット粒子の入射方向は、バッファ層１２０の成長方向と近い。そのため、バッファ層１２０のｃ軸の方向である第１の方向Ｊ１は、ターゲット１５００の法線方向ＺB に近い。 In the present embodiment, the target particles reach the substrate 110 from the direction of the normal direction Z B of the target 1500 or a direction close to that direction. The reached target particles are crystallized so as to be thermodynamically stable. Therefore, the incident direction of the target particles is close to the growth direction of the buffer layer 120. Therefore, the first direction J1 which is the c-axis direction of the buffer layer 120 is close to the normal direction Z B of the target 1500.
　ここで、基板１１０は、立方晶基板である。そのため、基板１１０の板面には、原子が格子状の頂点に配置されている。これに対して、バッファ層１２０は、六方晶である。ただし、バッファ層１２０の傾斜面が、基板１１０の板面と適合する。例えば、後述するバッファ層１２０の（１０－１３）面は、バッファ層１２０の傾斜面である。そして、バッファ層１２０の（１０－１３）面では、原子が長方形の格子状の頂点の位置に配置されている。したがって、基板１１０の正方形の格子状の頂点に位置する原子と、バッファ層１２０の長方形の格子状の頂点に位置する原子とが、結合する。よって、立方晶の基板１１０の上に六方晶のバッファ層１２０を成長させることができるのである。 Here, the substrate 110 is a cubic substrate. Therefore, atoms are arranged at the lattice apexes on the plate surface of the substrate 110. In contrast, the buffer layer 120 is hexagonal. However, the inclined surface of the buffer layer 120 matches the plate surface of the substrate 110. For example, a (10-13) plane of the buffer layer 120 described later is an inclined surface of the buffer layer 120. On the (10-13) plane of the buffer layer 120, atoms are arranged at the positions of the vertices of a rectangular lattice. Therefore, the atoms located at the square lattice-like vertices of the substrate 110 and the atoms located at the rectangular lattice-like vertices of the buffer layer 120 are combined. Therefore, the hexagonal buffer layer 120 can be grown on the cubic substrate 110.
５．従来の成膜方法との比較
５－１．本実施形態の成膜方法
　本実施形態では、基板１１０に対して、特定の方向からターゲット粒子を基板１１０に向けて輸送する。つまり、基板１１０の板面からみると、常にほぼ一定の方向から原料粒子が輸送される。その結果、図４に示すように、成膜された基板１１０の上では、基板１１０の上の第１の箇所におけるＧａＮ層のｃ軸は、第１の方向Ｊ１を向いている。また、基板１１０の上の第２の箇所におけるＧａＮ層のｃ軸も、第１の方向Ｊ１を向いている。このように、成膜されるＡｌＮ層およびＧａＮ層のｃ軸のほとんどは、基板１１０の板面にわたって第１の方向Ｊ１を向いている。つまり、ｃ軸は、基板１１０の板面に垂直な方向に対して、ある特定の角度θ１（図４参照）で傾いているのである。また、ｃ軸は、基板１１０の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲の特定の方向を向いている。 5. Comparison with conventional film formation method 5-1. In the present embodiment, target particles are transported toward the substrate 110 from a specific direction with respect to the substrate 110. That is, when viewed from the plate surface of the substrate 110, the raw material particles are always transported from a substantially constant direction. As a result, as shown in FIG. 4, on the deposited substrate 110, the c-axis of the GaN layer at the first location on the substrate 110 is in the first direction J1. In addition, the c-axis of the GaN layer at the second location on the substrate 110 also faces the first direction J1. As described above, most of the c-axis of the AlN layer and the GaN layer to be formed are oriented in the first direction J1 over the plate surface of the substrate 110. That is, the c-axis is inclined at a specific angle θ1 (see FIG. 4) with respect to the direction perpendicular to the plate surface of the substrate 110. Further, the c-axis is directed in a specific direction within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate 110 or a direction equivalent to the [110] direction.
５－２．従来の成膜方法
　従来のＭＯＣＶＤ法を用いて、立方晶の基板の上に六方晶のバッファ層を成膜しようと試みたと仮定する。その場合には、種々の方向から原料粒子が輸送される。その結果、ある箇所では、例えば、［１１０］方向にｃ軸が傾く。別の箇所では、例えば、［－１１０］方向にｃ軸が傾く。また、［１－１０］方向もしくは［－１－１０］方向にｃ軸が傾く場合がある。このように、基板上の位置によってｃ軸の傾く向きが異なっている。 5-2. Conventional Film Formation Method Assume that an attempt is made to form a hexagonal buffer layer on a cubic substrate using a conventional MOCVD method. In that case, the raw material particles are transported from various directions. As a result, at a certain point, for example, the c-axis is inclined in the [110] direction. In another place, for example, the c-axis is inclined in the [−110] direction. In addition, the c-axis may be inclined in the [1-10] direction or the [-1-10] direction. Thus, the direction in which the c-axis is inclined differs depending on the position on the substrate.
　図６に示すように、低温成膜された基板１１０上のＧａＮでは、基板１１０の第３の箇所におけるＧａＮ層のｃ軸は、第２の方向Ｊ２を向いている。また、基板１１０の第４の箇所におけるＧａＮ層のｃ軸は、第３の方向Ｊ３を向いている。もちろん、第２の方向Ｊ２と第３の方向Ｊ３とは異なる方向である。このように、基板１１０の場所によって、ｃ軸は別々の方向を向いている。 As shown in FIG. 6, in the GaN on the substrate 110 formed at a low temperature, the c-axis of the GaN layer at the third location of the substrate 110 faces the second direction J2. In addition, the c-axis of the GaN layer at the fourth position of the substrate 110 faces the third direction J3. Of course, the second direction J2 and the third direction J3 are different directions. As described above, the c-axis is directed in different directions depending on the location of the substrate 110.
　高温で成膜した場合にはｃ軸は傾かない。しかし、バッファ層１２０は、第１の領域と、第１の領域から面内回転方向に３０°回転した第２の領域と、を有することとなる。つまり、結晶方位の異なる２つの領域が混在することとなる。したがって、単結晶は得られない。また、オフ基板を用いたとしても、結晶性の良い結晶は得られない。 When the film is formed at high temperature, the c-axis does not tilt. However, the buffer layer 120 has a first region and a second region rotated by 30 ° in the in-plane rotation direction from the first region. That is, two regions having different crystal orientations are mixed. Therefore, a single crystal cannot be obtained. Even if an off-substrate is used, a crystal with good crystallinity cannot be obtained.
　なお、何らかの理由により、特定の方向が支配的になる可能性がないわけではない。しかし、基板１１０の板面にわたって一様にｃ軸が傾斜するＧａＮ層を成長させることは、非常に困難である。つまり、再現性が悪い。 Note that for some reason, a particular direction is not without possibility. However, it is very difficult to grow a GaN layer in which the c-axis is uniformly inclined over the plate surface of the substrate 110. That is, the reproducibility is poor.
６．変形例
６－１．ｃ軸の傾き
　本実施形態の薄膜基板１００は、基板１１０と、バッファ層１２０と、を有する。バッファ層１２０のｃ軸は、基板１１０の板面にわたって第１の方向Ｊ１を向いている。つまり、バッファ層１２０のｃ軸は、９５％以上の割合で第１の方向Ｊ１を向いている。しかし、基板１１０を［１１０］方向に等価な方向に配置しなかった場合には、第１の方向Ｊ１を向いているｃ軸の割合は低下する。その場合であっても、バッファ層１２０のｃ軸は、少なくとも５０％以上の割合で第１の方向Ｊ１を向いている。このように、バッファ層１２０のｃ軸は、５０％以上１００％以下の割合で第１の方向Ｊ１を向いている。 6). Modification 6-1. Inclination of c-axis The thin film substrate 100 of this embodiment includes a substrate 110 and a buffer layer 120. The c-axis of the buffer layer 120 faces the first direction J1 over the plate surface of the substrate 110. That is, the c-axis of the buffer layer 120 faces the first direction J1 at a rate of 95% or more. However, if the substrate 110 is not arranged in a direction equivalent to the [110] direction, the proportion of the c-axis facing the first direction J1 decreases. Even in such a case, the c-axis of the buffer layer 120 faces the first direction J1 at a rate of at least 50% or more. As described above, the c-axis of the buffer layer 120 faces the first direction J1 at a rate of 50% to 100%.
　このように、バッファ層１２０のｃ軸が、５０％以上の割合で第１の方向Ｊ１を向いていれば、III 族窒化物半導体層のｃ軸のほとんどが第１の方向Ｊ１を向いた状態でIII 族窒化物半導体層を成長させることができる。つまり、バッファ層１２０におけるｃ軸の支配的な向きが、その後に成長させるIII 族窒化物半導体層のｃ軸の傾きを決定づけるのである。このように成長させたIII 族窒化物半導体層では、ｃ軸の９５％以上は、第１の方向Ｊ１を向いている。つまり、ほとんど単結晶が得られる。もちろん、バッファ層１２０のｃ軸のうち第１の方向Ｊ１を向いている割合が多いほど、その上に成長させるIII 族窒化物半導体層の結晶性はよい。 Thus, if the c-axis of the buffer layer 120 is oriented in the first direction J1 at a rate of 50% or more, most of the c-axis of the III-group nitride semiconductor layer is oriented in the first direction J1. The III-group nitride semiconductor layer can be grown with That is, the dominant direction of the c-axis in the buffer layer 120 determines the inclination of the c-axis of the III-group nitride semiconductor layer that is subsequently grown. In the group III nitride semiconductor layer grown in this way, 95% or more of the c-axis is directed in the first direction J1. That is, almost a single crystal is obtained. Of course, the higher the ratio of the c-axis of the buffer layer 120 facing the first direction J1, the better the crystallinity of the III-group nitride semiconductor layer grown thereon.
　よって、バッファ層１２０のｃ軸のうち第１の方向Ｊ１を向いているｃ軸の割合は、５０％以上１００％以下の割合である。好ましくは、６５％以上１００％以下の割合である。より好ましくは、８０％以上１００％以下の割合である。さらに好ましくは、９０％以上１００％以下の割合である。 Therefore, the ratio of the c-axis facing the first direction J1 in the c-axis of the buffer layer 120 is a ratio of 50% or more and 100% or less. Preferably, it is a ratio of 65% or more and 100% or less. More preferably, the ratio is 80% or more and 100% or less. More preferably, the ratio is 90% or more and 100% or less.
６－２．基板の種類
　本実施形態における立方晶の基板１１０は、Ｓｉ（００１）基板である。しかし、その他の立方晶基板を用いることもできる。例えば、ＭｇＯ基板と、ＴｉＯ2 基板と、ＳｒＴｉＯ3 基板と、が挙げられる。また、ＳｉＣ基板、ＧａＡｓ基板、等の立方晶基板を用いることもできる。また、（００１）基板以外に、（１１０）基板を用いてもよい。 6-2. Types of Substrate The cubic substrate 110 in the present embodiment is a Si (001) substrate. However, other cubic substrates can be used. For example, an MgO substrate, a TiO 2 substrate, and a SrTiO 3 substrate can be mentioned. A cubic substrate such as a SiC substrate or a GaAs substrate can also be used. In addition to the (001) substrate, a (110) substrate may be used.
６－３．バッファ層の種類
　本実施形態のバッファ層１２０は、ＡｌＮ層である。しかし、ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）を用いてもよい。また、その他のバッファ層を用いてもよい。バッファ層として、例えば、ＢＮ層と、ＺｎＯ層と、ＺｎＳ層と、が挙げられる。 6-3. Type of buffer layer The buffer layer 120 of this embodiment is an AlN layer. However, an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1) may be used. Other buffer layers may also be used. Examples of the buffer layer include a BN layer, a ZnO layer, and a ZnS layer.
６－４．サセプターの回転（その１）
　本実施形態では、サセプター１２００を回転させない。しかし、基板１１０およびターゲット１５００の位置関係を保持した状態で、サセプター１２００およびターゲット１５００の両方を回転させてもよい。 6-4. Rotation of susceptor (part 1)
In this embodiment, the susceptor 1200 is not rotated. However, both the susceptor 1200 and the target 1500 may be rotated while the positional relationship between the substrate 110 and the target 1500 is maintained.
６－５．サセプターの回転（その２）
　本実施形態の薄膜基板１００の製造方法は、サセプター１２００を回転させない第１の工程と、サセプター１２００を回転させる第２の工程と、を有していてもよい。つまり、バッファ層１２０の成膜初期段階では、サセプター１２００を回転させずに約１０ｎｍ以上の膜厚でバッファ層１２０の一部を成膜する。この段階では、バッファ層１２０のｃ軸の配向方向が決定されている。そして、この後、サセプター１２００を回転させながらバッファ層１２０の残部を成膜する。この段階では、既にｃ軸の配向方向が決定されているので、その決定されたｃ軸の配向方向に従ってバッファ層１２０の残部は成長する。このように２段階にすることにより、バッファ層１２０の基板面内均一性が向上する。 6-5. Rotation of susceptor (part 2)
The manufacturing method of the thin film substrate 100 according to the present embodiment may include a first step in which the susceptor 1200 is not rotated and a second step in which the susceptor 1200 is rotated. That is, in the initial stage of film formation of the buffer layer 120, a part of the buffer layer 120 is formed with a film thickness of about 10 nm or more without rotating the susceptor 1200. At this stage, the orientation direction of the c-axis of the buffer layer 120 is determined. Thereafter, the remaining part of the buffer layer 120 is formed while the susceptor 1200 is rotated. At this stage, since the c-axis alignment direction has already been determined, the remainder of the buffer layer 120 grows according to the determined c-axis alignment direction. By using two steps in this way, the in-plane uniformity of the buffer layer 120 is improved.
６－６．ターゲット配置部
　本実施形態のターゲット配置部１４００は、チャンバー１１００に固定されている。しかし、ターゲット配置部１４００は、ターゲット１５００の表面が、基板１１０の板面に垂直な方向に対して１０°以上６０°以下の範囲内で相対的に可変となるように傾斜角を変更できるようになっていてもよい。 6-6. Target Arrangement Unit The target arrangement unit 1400 of this embodiment is fixed to the chamber 1100. However, the target placement unit 1400 can change the tilt angle so that the surface of the target 1500 is relatively variable within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate 110. It may be.
６－７．組み合わせ
　上記の変形例を自由に組み合わせてもよい。 6-7. Combination The above modification examples may be freely combined.
７．本実施形態のまとめ
　本実施形態の成膜装置１０００では、基板１１０の板面に垂直な方向と、基板１１０からみてターゲット１５００の配置されている方向とのなす角の角度が、角度θだけ傾斜している。そのため、立方晶である基板１１０の上に六方晶のバッファ層１２０を成長させることができる。したがって、例えば、大口径のＳｉ（００１）基板の上にIII 族窒化物半導体を成長させることができる。 7). Summary of this embodiment In the film forming apparatus 1000 of this embodiment, the angle formed by the direction perpendicular to the plate surface of the substrate 110 and the direction in which the target 1500 is disposed as viewed from the substrate 110 is inclined by an angle θ. is doing. Therefore, the hexagonal buffer layer 120 can be grown on the cubic substrate 110. Therefore, for example, a group III nitride semiconductor can be grown on a large-diameter Si (001) substrate.
　本実施形態の薄膜基板１００は、立方晶の基板１１０と、その基板１１０の上に成長させた六方晶のバッファ層１２０と、を有している。そのため、安価で大口径のＳｉ（００１）基板の上にIII 族窒化物半導体を成長させることができる。 The thin film substrate 100 of the present embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a III-group nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
（第２の実施形態）
　第２の実施形態について説明する。 (Second Embodiment)
A second embodiment will be described.
１．ＨＥＭＴ
　図７は、第２の実施形態のＨＥＭＴ２００の概略構成を示す図である。ＨＥＭＴ２００は、III 族窒化物半導体を有する半導体素子である。ＨＥＭＴ２００は、基板１１０と、バッファ層１２０と、下地層２３０と、チャネル層２４０と、バリア層２５０と、ソース電極Ｓ１と、ドレイン電極Ｄ１と、ゲート電極Ｇ１と、を有している。 1. HEMT
FIG. 7 is a diagram illustrating a schematic configuration of the HEMT 200 according to the second embodiment. The HEMT 200 is a semiconductor element having a group III nitride semiconductor. The HEMT 200 includes a substrate 110, a buffer layer 120, a base layer 230, a channel layer 240, a barrier layer 250, a source electrode S1, a drain electrode D1, and a gate electrode G1.
　基板１１０は、立方晶基板である。具体的には、Ｓｉ（００１）基板である。バッファ層１２０は、六方晶のＡｌＮ層である。このように、立方晶の基板１１０の上に六方晶のバッファ層１２０が形成されている。また、下地層２３０は、ＧａＮ層である。チャネル層２４０は、ＧａＮ層である。バリア層２５０は、ＡｌＧａＮ層である。これらは例示であり、下地層２３０と、チャネル層２４０と、バリア層２５０とは、これ以外の種類の半導体層であってもよい。 The substrate 110 is a cubic substrate. Specifically, it is a Si (001) substrate. The buffer layer 120 is a hexagonal AlN layer. As described above, the hexagonal buffer layer 120 is formed on the cubic substrate 110. The underlayer 230 is a GaN layer. The channel layer 240 is a GaN layer. The barrier layer 250 is an AlGaN layer. These are examples, and the base layer 230, the channel layer 240, and the barrier layer 250 may be other types of semiconductor layers.
２．バッファ層およびＧａＮ層
　図８は、ＨＥＭＴ２００から基板１１０とバッファ層１２０と下地層２３０とを抜き出して描いた概念図である。ここで、第１の角度θ１は、基板１１０の板面に垂直な方向と、バッファ層１２０のｃ軸と、がなす角の角度である。第２の角度θ２は、基板１１０の板面に垂直な方向と、下地層２３０のｃ軸と、がなす角の角度である。 2. Buffer Layer and GaN Layer FIG. 8 is a conceptual diagram illustrating the substrate 110, the buffer layer 120, and the base layer 230 extracted from the HEMT 200. Here, the first angle θ <b> 1 is an angle formed by the direction perpendicular to the plate surface of the substrate 110 and the c-axis of the buffer layer 120. The second angle θ <b> 2 is an angle formed by the direction perpendicular to the plate surface of the substrate 110 and the c-axis of the base layer 230.
　角度θ２は、１０°以上６０°以下の範囲内である。好ましくは、角度θ２は、１５°以上５５°以下の範囲内である。より好ましくは、角度θ２は、２０°以上５０°以下の範囲内である。さらに好ましくは、角度θ２は、２５°以上４５°以下の範囲内である。 The angle θ2 is in the range of 10 ° to 60 °. Preferably, the angle θ2 is in the range of 15 ° to 55 °. More preferably, the angle θ2 is in the range of 20 ° to 50 °. More preferably, the angle θ2 is in the range of 25 ° to 45 °.
　図８に示すように、下地層２３０のｃ軸の向きは、バッファ層１２０のｃ軸の向きとほぼ同じ向きである。つまり、ｃ軸が傾斜しているバッファ層１２０の上には、そのバッファ層１２０の結晶性を受け継いで、ＧａＮが成長する。ここで、第２の角度θ２は、第１の角度θ１にほぼ等しい。第２の角度θ２は、基板１１０の板面に垂直な方向および面内方向の両方について、第１の角度θ１に対して０°以上５°以下だけ傾斜している。つまり、下地層２３０のｃ軸は、バッファ層１２０のｃ軸の方向に対して、基板１１０の板面に垂直な方向および面内方向の両方について、０°以上５°以下の範囲内で傾斜している。好ましくは、０°以上３°以下の範囲内である。より好ましくは、０°以上１°以下の範囲内である。 As shown in FIG. 8, the direction of the c-axis of the base layer 230 is substantially the same as the direction of the c-axis of the buffer layer 120. That is, GaN grows on the buffer layer 120 whose c-axis is inclined, inheriting the crystallinity of the buffer layer 120. Here, the second angle θ2 is substantially equal to the first angle θ1. The second angle θ2 is inclined by 0 ° or more and 5 ° or less with respect to the first angle θ1 in both the direction perpendicular to the plate surface of the substrate 110 and the in-plane direction. That is, the c-axis of the base layer 230 is tilted within a range of 0 ° to 5 ° with respect to both the direction perpendicular to the plate surface of the substrate 110 and the in-plane direction with respect to the c-axis direction of the buffer layer 120. is doing. Preferably, it is in the range of 0 ° to 3 °. More preferably, it is in the range of 0 ° to 1 °.
３．本実施形態の効果
　バッファ層１２０のｃ軸は、基板１１０の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にある。この場合、ＧａＮ層である下地層２３０の表面は非極性面となる。そのため、自発分極とピエゾ分極が抑制される。したがって、ノーマリオフタイプのＨＥＭＴが得られやすい。また、発光素子に適用する場合には、発光層内の分極による波長シフトが抑制される。また、電界の歪みによる電子および正孔の波動関数の分離が抑制される。したがって、発光効率の低下を抑制することができる。 3. Effect of this Embodiment The c-axis of the buffer layer 120 is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction of the plate surface of the substrate 110 or a direction equivalent to the [110] direction. In this case, the surface of the foundation layer 230 that is a GaN layer is a nonpolar surface. Therefore, spontaneous polarization and piezo polarization are suppressed. Therefore, a normally-off type HEMT is easily obtained. Further, when applied to a light emitting element, wavelength shift due to polarization in the light emitting layer is suppressed. Further, separation of electron and hole wave functions due to electric field distortion is suppressed. Therefore, it is possible to suppress a decrease in luminous efficiency.
　図９は、Ｉｎ組成比が２０％のＩｎＧａＮをＧａＮ上に成長させた場合の薄膜中の分極を示すグラフである。図１０は、Ａｌ組成比が２０％のＡｌＧａＮをＧａＮ上に成長させた場合の薄膜中の分極を示すグラフである。図９および図１０に示すように、ｃ軸を傾斜させた場合の分極の度合いは、ｃ軸を傾斜させない場合の分極の度合いよりも小さい。Ｉｎ組成比やＡｌ組成比が変化しても、この傾向はそれほど変わらない。したがって、本実施形態のｃ軸が傾斜した非極性面を用いる半導体装置では、分極が抑制される。 FIG. 9 is a graph showing the polarization in the thin film when InGaN having an In composition ratio of 20% is grown on GaN. FIG. 10 is a graph showing polarization in a thin film when AlGaN having an Al composition ratio of 20% is grown on GaN. As shown in FIGS. 9 and 10, the degree of polarization when the c-axis is inclined is smaller than the degree of polarization when the c-axis is not inclined. Even if the In composition ratio or Al composition ratio changes, this tendency does not change so much. Therefore, in the semiconductor device using the nonpolar plane with the c-axis inclined in this embodiment, polarization is suppressed.
４．ＨＥＭＴの製造方法
４－１．バッファ層形成工程
　第１の実施形態の成膜装置１０００を用いて、基板１１０の上にバッファ層１２０を形成する。その後、成膜した基板１１０を成膜装置１０００から取り出す。 4). 4. Manufacturing method of HEMT 4-1. Buffer Layer Forming Step The buffer layer 120 is formed on the substrate 110 using the film forming apparatus 1000 of the first embodiment. Thereafter, the deposited substrate 110 is taken out of the deposition apparatus 1000.
４－２．半導体層形成工程
　その後、ＭＯＣＶＤ装置等を用いて、バッファ層１２０の上にIII 族窒化物半導体の単結晶をエピタキシャル成長させる。つまり、バッファ層１２０の上に下地層２３０を成長させる。次に、下地層２３０の上にチャネル層２４０を成長させる。そして、チャネル層２４０の上にバリア層２５０を成長させる。 4-2. Semiconductor Layer Formation Step Thereafter, a group III nitride semiconductor single crystal is epitaxially grown on the buffer layer 120 using an MOCVD apparatus or the like. That is, the base layer 230 is grown on the buffer layer 120. Next, the channel layer 240 is grown on the base layer 230. Then, a barrier layer 250 is grown on the channel layer 240.
４－３．電極形成工程
　そして、バリア層２５０の上に、ソース電極Ｓ１と、ドレイン電極Ｄ１と、ゲート電極Ｇ１と、を形成する。そして、基板１１０を切り出してチップ化する。これにより、図７に示すＨＥＭＴ２００が製造される。 4-3. Electrode Forming Step Then, the source electrode S1, the drain electrode D1, and the gate electrode G1 are formed on the barrier layer 250. Then, the substrate 110 is cut out into chips. Thereby, the HEMT 200 shown in FIG. 7 is manufactured.
５．変形例
５－１．ＭＩＳ型ＨＥＭＴ
　本実施形態のＨＥＭＴ２００に限らず、ＭＩＳ型ＨＥＭＴもしくはＭＯＳ型ＨＥＭＴにも本実施形態の技術を適用することができる。 5. Modified example 5-1. MIS HEMT
The technique of the present embodiment can be applied not only to the HEMT 200 of the present embodiment but also to a MIS type HEMT or a MOS type HEMT.
５－２．縦型素子
　また、その他の縦型の半導体素子についても、本実施形態の技術を適用することができる。 5-2. Vertical Element The technology of the present embodiment can also be applied to other vertical semiconductor elements.
５－３．ＧａＮテンプレート
　また、本実施形態の技術は、ＧａＮテンプレートにも適用することができる。その場合のＧａＮテンプレートの構造は、図８に示すものと同様である。 5-3. GaN Template The technique of this embodiment can also be applied to a GaN template. The structure of the GaN template in that case is the same as that shown in FIG.
５－４．組み合わせ
　上記の変形例を第１の実施形態およびその変形例と自由に組み合わせてもよい。 5-4. Combination The above modification may be freely combined with the first embodiment and its modification.
６．本実施形態のまとめ
　本実施形態のＨＥＭＴ２００は、立方晶の基板１１０と、その基板１１０の上に成長させた六方晶のバッファ層１２０と、を有している。そのため、安価で大口径のＳｉ（００１）基板の上にIII 族窒化物半導体を成長させることができる。 6). Summary of this Embodiment The HEMT 200 of this embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a group III nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
（第３の実施形態）
　第３の実施形態について説明する。 (Third embodiment)
A third embodiment will be described.
１．半導体発光素子
　図１１は、第３の実施形態の発光素子３００の概略構成を示す図である。発光素子３００は、III 族窒化物半導体を有する半導体素子である。発光素子３００は、基板１１０と、バッファ層１２０と、ｎ型コンタクト層３３０と、発光層３４０と、ｐ型クラッド層３５０と、ｐ型コンタクト層３６０と、ｎ電極Ｎ１と、ｐ電極Ｐ１と、を有する。 1. Semiconductor Light Emitting Element FIG. 11 is a diagram showing a schematic configuration of a light emitting element 300 of the third embodiment. The light emitting element 300 is a semiconductor element having a group III nitride semiconductor. The light emitting element 300 includes a substrate 110, a buffer layer 120, an n-type contact layer 330, a light emitting layer 340, a p-type cladding layer 350, a p-type contact layer 360, an n-electrode N1, a p-electrode P1, Have
　基板１１０は、立方晶基板である。具体的には、Ｓｉ（００１）基板である。バッファ層１２０は、六方晶のＡｌＮ層である。このように、立方晶の基板１１０の上に六方晶のバッファ層１２０が形成されている。 The substrate 110 is a cubic substrate. Specifically, it is a Si (001) substrate. The buffer layer 120 is a hexagonal AlN layer. As described above, the hexagonal buffer layer 120 is formed on the cubic substrate 110.
　ｎ型コンタクト層３３０は、ｎ電極Ｎ１と接触する層である。ｎ型コンタクト層３３０は、ｎ型ＧａＮを有している。発光層３４０は、電子と正孔とが再結合して発光する層である。ｐ型クラッド層３５０は、電子を閉じ込めておくための層である。ｐ型クラッド層３５０は、超格子構造を備える層である。ｐ型コンタクト層３６０は、ｐ電極Ｐ１と接触する層である。ｐ型コンタクト層３６０は、ｐ型ＧａＮを有している。これらは、例示であり、これ以外の半導体層を有していてもよい。 The n-type contact layer 330 is a layer in contact with the n electrode N1. The n-type contact layer 330 has n-type GaN. The light emitting layer 340 is a layer that emits light by recombination of electrons and holes. The p-type cladding layer 350 is a layer for confining electrons. The p-type cladding layer 350 is a layer having a superlattice structure. The p-type contact layer 360 is a layer in contact with the p-electrode P1. The p-type contact layer 360 has p-type GaN. These are merely examples, and other semiconductor layers may be included.
２．バッファ層およびＧａＮ層
　第３の実施形態におけるバッファ層１２０とｎ型コンタクト層３３０との関係は、第２の実施形態のバッファ層１２０と下地層２３０との関係と同様である。つまり、図８に示す関係が、発光素子３００においても成り立つ。 2. Buffer Layer and GaN Layer The relationship between the buffer layer 120 and the n-type contact layer 330 in the third embodiment is the same as the relationship between the buffer layer 120 and the base layer 230 in the second embodiment. That is, the relationship shown in FIG.
３．半導体発光素子の製造方法
３－１．バッファ層形成工程
　第１の実施形態の成膜装置１０００を用いて、基板１１０の上にバッファ層１２０を形成する。その後、成膜した基板１１０を成膜装置１０００から取り出す。 3. Manufacturing method of semiconductor light emitting device 3-1. Buffer Layer Forming Step The buffer layer 120 is formed on the substrate 110 using the film forming apparatus 1000 of the first embodiment. Thereafter, the deposited substrate 110 is taken out of the deposition apparatus 1000.
３－２．半導体層形成工程
　その後、ＭＯＣＶＤ装置等を用いて、バッファ層１２０の上にIII 族窒化物半導体の単結晶をエピタキシャル成長させる。つまり、バッファ層１２０の上にｎ型コンタクト層３３０を成長させる。次に、ｎ型コンタクト層３３０の上に発光層３４０を成長させる。そして、発光層３４０の上にｐ型クラッド層３５０を成長させる。そして、ｐ型クラッド層３５０の上にｐ型コンタクト層３６０を成長させる。 3-2. Semiconductor Layer Formation Step Thereafter, a group III nitride semiconductor single crystal is epitaxially grown on the buffer layer 120 using an MOCVD apparatus or the like. That is, the n-type contact layer 330 is grown on the buffer layer 120. Next, the light emitting layer 340 is grown on the n-type contact layer 330. Then, a p-type cladding layer 350 is grown on the light emitting layer 340. Then, a p-type contact layer 360 is grown on the p-type cladding layer 350.
３－３．電極形成工程
　そして、ｐ型コンタクト層３６０からｎ型コンタクト層３３０まで達する凹部を設ける。そして、その凹部に露出しているｎ型コンタクト層３３０の上にｎ電極Ｎ１を形成する。また、ｐ型コンタクト層３６０の上にｐ電極Ｐ１を形成する。また、基板１１０を切り出してチップ化する。これにより、図１１に示す発光素子３００が製造される。 3-3. Electrode forming step Then, a recess reaching from the p-type contact layer 360 to the n-type contact layer 330 is provided. Then, an n-electrode N1 is formed on the n-type contact layer 330 exposed in the recess. A p-electrode P1 is formed on the p-type contact layer 360. Further, the substrate 110 is cut out into chips. Thereby, the light emitting element 300 shown in FIG. 11 is manufactured.
４．変形例
４－１．半導体レーザー素子
　図１１に示す第３の実施形態の半導体素子は、発光素子３００である。しかし、半導体レーザー素子に対しても、同様に、本実施形態の技術を適用することができる。 4). Modified example 4-1. Semiconductor Laser Element The semiconductor element according to the third embodiment shown in FIG. However, the technique of the present embodiment can be similarly applied to the semiconductor laser element.
４－２．受光素子
　また、本技術は、受光素子にも適用することができる。受光素子は、発光素子３００の発光層を光吸収層として用いる。受光素子として、例えば、太陽電池が挙げられる。 4-2. Light Receiving Element The present technology can also be applied to a light receiving element. The light receiving element uses the light emitting layer of the light emitting element 300 as a light absorbing layer. Examples of the light receiving element include a solar cell.
４－３．組み合わせ
　上記の変形例を第１の実施形態およびその変形例と自由に組み合わせてもよい。 4-3. Combination The above modification may be freely combined with the first embodiment and its modification.
５．本実施形態のまとめ
　本実施形態のＨＥＭＴ２００は、立方晶の基板１１０と、その基板１１０の上に成長させた六方晶のバッファ層１２０と、を有している。そのため、安価で大口径のＳｉ（００１）基板の上にIII 族窒化物半導体を成長させることができる。 5. Summary of this Embodiment The HEMT 200 of this embodiment includes a cubic substrate 110 and a hexagonal buffer layer 120 grown on the substrate 110. Therefore, a group III nitride semiconductor can be grown on an inexpensive and large-diameter Si (001) substrate.
（第４の実施形態）
　第４の実施形態について説明する。 (Fourth embodiment)
A fourth embodiment will be described.
１．薄膜基板
　図１２は、第４の実施形態の薄膜基板４００の構造を示す図である。薄膜基板４００は、基板１１０と、バッファ層１２０と、中間層ＩＬと、を有している。バッファ層１２０は、スパッタリングにより成膜されたＡｌＮ層である。ここで、基板１１０は、立方晶基板である。一方、バッファ層１２０は、六方晶の層である。また、中間層ＩＬは、六方晶の層である。このように、薄膜基板１００は、立方晶の基板１１０と、六方晶のバッファ層１２０と、六方晶の中間層ＩＬと、を有している。第４の実施形態のバッファ層１２０は、第１の実施形態のバッファ層１２０と同様である。 1. Thin Film Substrate FIG. 12 is a view showing the structure of the thin film substrate 400 of the fourth embodiment. The thin film substrate 400 includes a substrate 110, a buffer layer 120, and an intermediate layer IL. The buffer layer 120 is an AlN layer formed by sputtering. Here, the substrate 110 is a cubic substrate. On the other hand, the buffer layer 120 is a hexagonal layer. The intermediate layer IL is a hexagonal layer. As described above, the thin film substrate 100 includes the cubic substrate 110, the hexagonal buffer layer 120, and the hexagonal intermediate layer IL. The buffer layer 120 of the fourth embodiment is the same as the buffer layer 120 of the first embodiment.
２．中間層
　ここで、中間層ＩＬについて説明する。第４の実施形態の中間層ＩＬは、ＭＯＣＶＤ法により成膜された層である。中間層ＩＬは、バッファ層１２０の結晶性を受け継ぎつつ、格子欠陥を低減させるための層である。中間層ＩＬの膜厚は、例えば、１０ｎｍ以上１００ｎｍ以下の範囲内である。中間層ＩＬの膜厚は上記以外であってもよい。そして、中間層ＩＬとして、例えば、次の３種類の中間層を挙げることができる。 2. Intermediate Layer Here, the intermediate layer IL will be described. The intermediate layer IL of the fourth embodiment is a layer formed by the MOCVD method. The intermediate layer IL is a layer for reducing lattice defects while inheriting the crystallinity of the buffer layer 120. The film thickness of the intermediate layer IL is, for example, in the range of 10 nm to 100 nm. The film thickness of the intermediate layer IL may be other than the above. And as intermediate layer IL, the following three types of intermediate layers can be mentioned, for example.
２－１．第１の中間層
　第１の中間層は、高温ＡｌＮ層である。高温ＡｌＮ層の成長温度は、９５０℃以上１１００℃以下である。 2-1. First intermediate layer The first intermediate layer is a high temperature AlN layer. The growth temperature of the high-temperature AlN layer is 950 ° C. or higher and 1100 ° C. or lower.
２－２．第２の中間層
　第２の中間層は、低温ＡｌＮ層と高温ＡｌＮ層とを積層した層である。その際に、バッファ層１２０の上に低温ＡｌＮ層を形成し、低温ＡｌＮ層の上に高温ＡｌＮ層を形成する。低温ＡｌＮ層の成長温度は、６５０℃以上８００℃以下である。 2-2. Second Intermediate Layer The second intermediate layer is a layer in which a low temperature AlN layer and a high temperature AlN layer are stacked. At that time, a low temperature AlN layer is formed on the buffer layer 120, and a high temperature AlN layer is formed on the low temperature AlN layer. The growth temperature of the low-temperature AlN layer is 650 ° C. or higher and 800 ° C. or lower.
２－３．第３の中間層
　第３の中間層は、高温ＡｌＮ層とＡｌＮ／ＧａＮ超格子層とを積層した層である。その際に、バッファ層１２０の上に高温ＡｌＮ層を形成し、高温ＡｌＮ層の上にＡｌＮ／ＧａＮ超格子層を形成する。ＡｌＮ／ＧａＮ超格子層の成長温度は、９５０℃以上１１００℃以下である。 2-3. Third Intermediate Layer The third intermediate layer is a layer in which a high-temperature AlN layer and an AlN / GaN superlattice layer are stacked. At that time, a high-temperature AlN layer is formed on the buffer layer 120, and an AlN / GaN superlattice layer is formed on the high-temperature AlN layer. The growth temperature of the AlN / GaN superlattice layer is 950 ° C. or higher and 1100 ° C. or lower.
３．本実施形態の効果
　中間層ＩＬは、格子欠陥を低減させることができる。そして、中間層ＩＬより上層に六方晶の半導体層を成長させる場合に、中間層ＩＬは、その六方晶の半導体層の結晶性を向上させる。 3. Effects of this Embodiment The intermediate layer IL can reduce lattice defects. When a hexagonal semiconductor layer is grown above the intermediate layer IL, the intermediate layer IL improves the crystallinity of the hexagonal semiconductor layer.
４．変形例
４－１．ＨＥＭＴ
　図１３は、第４の実施形態の変形例におけるＨＥＭＴ５００の構造を示す図である。ＨＥＭＴ５００は、III 族窒化物半導体を有する半導体素子である。ＨＥＭＴ５００は、基板１１０と、バッファ層１２０と、中間層ＩＬと、下地層２３０と、チャネル層２４０と、バリア層２５０と、ソース電極Ｓ１と、ドレイン電極Ｄ１と、ゲート電極Ｇ１と、を有している。中間層ＩＬは、バッファ層１２０と半導体層との間に位置している。 4). Modified example 4-1. HEMT
FIG. 13 is a diagram illustrating a structure of a HEMT 500 according to a modification of the fourth embodiment. The HEMT 500 is a semiconductor element having a group III nitride semiconductor. The HEMT 500 includes a substrate 110, a buffer layer 120, an intermediate layer IL, a base layer 230, a channel layer 240, a barrier layer 250, a source electrode S1, a drain electrode D1, and a gate electrode G1. ing. The intermediate layer IL is located between the buffer layer 120 and the semiconductor layer.
　ＨＥＭＴ５００の各層は、中間層ＩＬを除いて第２の実施形態のＨＥＭＴ２００の各層と同じである。中間層ＩＬは、本実施形態の第１の中間層から第３の中間層までのいずれかであればよい。 Each layer of the HEMT 500 is the same as each layer of the HEMT 200 of the second embodiment except for the intermediate layer IL. The intermediate layer IL may be any one from the first intermediate layer to the third intermediate layer of the present embodiment.
４－２．半導体発光素子
　図１４は、第４の実施形態の変形例における発光素子６００の構造を示す図である。発光素子６００は、III 族窒化物半導体を有する半導体素子である。発光素子６００は、基板１１０と、バッファ層１２０と、中間層ＩＬと、ｎ型コンタクト層３３０と、発光層３４０と、ｐ型クラッド層３５０と、ｐ型コンタクト層３６０と、ｎ電極Ｎ１と、ｐ電極Ｐ１と、を有する。中間層ＩＬは、バッファ層１２０と半導体層との間に位置している。 4-2. Semiconductor Light Emitting Element FIG. 14 is a diagram showing a structure of a light emitting element 600 according to a modification of the fourth embodiment. The light emitting element 600 is a semiconductor element having a group III nitride semiconductor. The light-emitting element 600 includes a substrate 110, a buffer layer 120, an intermediate layer IL, an n-type contact layer 330, a light-emitting layer 340, a p-type cladding layer 350, a p-type contact layer 360, an n-electrode N1, p electrode P1. The intermediate layer IL is located between the buffer layer 120 and the semiconductor layer.
　発光素子６００の各層は、中間層ＩＬを除いて第３の実施形態の発光素子３００の各層と同じである。中間層ＩＬは、本実施形態の第１の中間層から第３の中間層までのいずれかであればよい。 Each layer of the light emitting element 600 is the same as each layer of the light emitting element 300 of the third embodiment except for the intermediate layer IL. The intermediate layer IL may be any one from the first intermediate layer to the third intermediate layer of the present embodiment.
４－３．中間層の成膜方法
　本実施形態では、中間層ＩＬをＭＯＣＶＤ法により成膜する。しかし、中間層ＩＬを成膜するためにその他の成膜方法を用いてもよい。例えば、ＨＶＰＥ法、ＭＢＥ法が挙げられる。 4-3. In the present embodiment, the intermediate layer IL is formed by the MOCVD method. However, other film forming methods may be used to form the intermediate layer IL. For example, HVPE method and MBE method are mentioned.
Ａ．実験１
１．ＧａＮ層の成膜
１－１．成膜条件
　成膜装置１０００を用いて、Ｓｉ（００１）基板にＡｌＮ層を成膜した。ターゲットをＳｉ（００１）基板に射影すると、Ｓｉ（００１）基板の［１１０］方向または［１１０］方向と等価な方向にターゲットが配置されるように、Ｓｉ（００１）基板をサセプター１２００に配置した。Ｓｉ（００１）基板の板面に垂直な方向と、ターゲットの位置する方向と、のなす角の角度は、３６°であった。なお、ターゲットは、Ｓｉ（００１）基板の［１１０］方向もしくはその等価な方向からＳｉ（００１）基板の面内回転方向で３０°以内の位置に配置した。 A. Experiment 1
1. 1. Formation of GaN layer 1-1. Film Formation Conditions Using the film formation apparatus 1000, an AlN layer was formed on a Si (001) substrate. The Si (001) substrate was placed on the susceptor 1200 so that when the target was projected onto the Si (001) substrate, the target was placed in the [110] direction of the Si (001) substrate or a direction equivalent to the [110] direction. . The angle formed by the direction perpendicular to the plate surface of the Si (001) substrate and the direction in which the target is located was 36 °. The target was arranged at a position within 30 ° in the in-plane rotation direction of the Si (001) substrate from the [110] direction of the Si (001) substrate or an equivalent direction thereof.
　また、サセプター１２００については、回転させなかった。そのため、配置したＳｉ（００１）基板に対して、ターゲットの位置する方向から、ターゲット粒子が輸送されることとなる。つまり、ターゲット粒子は、［１１１］に近い方向からＳｉ（００１）基板に到達することとなる。 Also, the susceptor 1200 was not rotated. Therefore, the target particles are transported from the direction in which the target is located with respect to the arranged Si (001) substrate. That is, the target particles reach the Si (001) substrate from a direction close to [111].
　そして、Ｓｉ（００１）基板の上にＡｌＮ層を成膜した。基板温度は、４５０℃であった。ターゲットは、Ａｌであった。そして、５０ｓｃｃｍのＮ2 ガスをチャンバー１１００の内部に供給した。ここで、ＤＣ３００Ｗでターゲットに電圧を印加した。内圧は、０．２３Ｐａであった。成膜時間は、３０分であった。これにより、Ａｌ層の上に８０ｎｍのＡｌＮ層を成膜した。 Then, an AlN layer was formed on the Si (001) substrate. The substrate temperature was 450 ° C. The target was Al. Then, 50 sccm of N 2 gas was supplied into the chamber 1100. Here, a voltage was applied to the target at DC 300W. The internal pressure was 0.23 Pa. The film formation time was 30 minutes. Thereby, an AlN layer of 80 nm was formed on the Al layer.
　次に、ＭＯＣＶＤ装置を用いて、ＡｌＮ層の上にＧａＮ層を成長させた。 Next, a GaN layer was grown on the AlN layer using an MOCVD apparatus.
１－２．成膜結果
　図１５は、Ｓｉ（００１）基板に成膜したＧａＮ層の表面を示す走査型電子顕微鏡写真（ＳＥＭ写真）である。図１５に示すように、ＧａＮ層の成長方向に異方性が認められる。 1-2. Deposition Result FIG. 15 is a scanning electron micrograph (SEM photograph) showing the surface of the GaN layer deposited on the Si (001) substrate. As shown in FIG. 15, anisotropy is recognized in the growth direction of the GaN layer.
　図１６は、Ｓｉ（００１）基板に成膜したＧａＮ層の断面を示す走査型電子顕微鏡写真（ＳＥＭ写真）である。図１６に示すように、ＧａＮ層のｃ軸は、Ｓｉ（００１）基板の板面に対して一定の角度だけ傾斜している。このなす角の角度は、約３２°であった。 FIG. 16 is a scanning electron micrograph (SEM photograph) showing a cross section of the GaN layer formed on the Si (001) substrate. As shown in FIG. 16, the c-axis of the GaN layer is inclined by a certain angle with respect to the plate surface of the Si (001) substrate. The angle formed by this was about 32 °.
　図１７は、図１６を拡大した拡大図である。図１７に示すように、ＡｌＮ層のｃ軸は、スパッタリングの方向に傾斜している。また、ＧａＮ層のｃ軸も、スパッタリングの方向に傾斜している。そして、ＡｌＮ層とＧａＮ層とは、ほぼ同じ方向に成長している。ＡｌＮ層が成長する方向と、ＧａＮ層が成長する方向と、の間の方向のずれは、２°以下であった。 FIG. 17 is an enlarged view of FIG. As shown in FIG. 17, the c-axis of the AlN layer is inclined in the sputtering direction. Further, the c-axis of the GaN layer is also inclined in the sputtering direction. The AlN layer and the GaN layer are grown in substantially the same direction. The deviation between the direction in which the AlN layer grows and the direction in which the GaN layer grows was 2 ° or less.
　図１８は、サセプター１２００を２０ｒｐｍで回転させたときのＧａＮ層の表面を示す走査型電子顕微鏡写真（ＳＥＭ写真）である。このときには、Ｓｉ（００１）基板にまばらにＧａＮ層が成長した。 FIG. 18 is a scanning electron micrograph (SEM photograph) showing the surface of the GaN layer when the susceptor 1200 is rotated at 20 rpm. At this time, GaN layers were sparsely grown on the Si (001) substrate.
２．ＧａＮ層の配向
２－１．Ｘ線回折
　図１９は、任意の箇所でのＸ線回折の結果（２θ／ω）を示すグラフである。図１９に示すように、ＧａＮ（１０－１３）のピークと、Ｓｉ（００４）のピークと、が観測された。これは、Ｓｉ（００１）基板の上に成膜したＧａＮ層が、（１０－１３）面の方向に成長したことを示している。 2. Orientation of GaN layer 2-1. X-Ray Diffraction FIG. 19 is a graph showing the result (2θ / ω) of X-ray diffraction at an arbitrary location. As shown in FIG. 19, a peak of GaN (10-13) and a peak of Si (004) were observed. This indicates that the GaN layer formed on the Si (001) substrate has grown in the direction of the (10-13) plane.
　また、図１９では、ＧａＮ（１０－１３）のピークと、Ｓｉ（００４）のピークと、を除くピークが観測されていない。これは、ＧａＮ層が、Ｓｉ（００１）基板の全表面にわたって一様な膜を成膜されたものであることを示している。 Further, in FIG. 19, no peaks other than the peak of GaN (10-13) and the peak of Si (004) are observed. This indicates that the GaN layer is formed by forming a uniform film over the entire surface of the Si (001) substrate.
　図２０は、ＧａＮ層の（１０－１３）面を示す図である。 FIG. 20 shows the (10-13) plane of the GaN layer.
　図２１は、Ｘ線回折の結果（φスキャン）を示すグラフである。図２１に示すように、Ｘ＝３１．６°のときに、ＧａＮ（０００２）のピークがφ＝１８０°の位置に観測された。 FIG. 21 is a graph showing the result of X-ray diffraction (φ scan). As shown in FIG. 21, when X = 31.6 °, a peak of GaN (0002) was observed at a position of φ = 180 °.
　図２２は、Ｘ線回折の結果（φスキャン）を示すグラフである。図２２に示すように、Ｘ＝５４．６°のときに、Ｓｉ｛１１１｝のピークがφ＝９０°、１８０°、２７０°の位置に観測された。 FIG. 22 is a graph showing the result of X-ray diffraction (φ scan). As shown in FIG. 22, when X = 54.6 °, a peak of Si {111} was observed at positions of φ = 90 °, 180 °, and 270 °.
　このように、ＧａＮ（０００１）面から３１．６°だけ傾斜しているＧａＮ（１０－１３）面が、成長したことが確認された。 Thus, it was confirmed that the GaN (10-13) plane inclined by 31.6 ° from the GaN (0001) plane grew.
２－２．平坦性
　図２３は、Ｓｉ（００１）基板に成膜したＧａＮ層の断面を示す走査型電子顕微鏡写真（ＳＥＭ写真）である。図２３では、第１のＡｌＮ層の上に第１のＧａＮ層を成長させた。第１のＧａＮ層の膜厚は１μｍである。そして、第１のＧａＮ層の上に第２のＡｌＮ層を成長させた。第２のＡｌＮ層の膜厚は１０ｎｍ程度である。そして、第２のＡｌＮ層の上に第２のＧａＮ層を成長させた。第２のＧａＮ層の膜厚は１μｍである。 2-2. Flatness FIG. 23 is a scanning electron micrograph (SEM photograph) showing a cross section of a GaN layer formed on a Si (001) substrate. In FIG. 23, the first GaN layer was grown on the first AlN layer. The film thickness of the first GaN layer is 1 μm. Then, a second AlN layer was grown on the first GaN layer. The film thickness of the second AlN layer is about 10 nm. Then, a second GaN layer was grown on the second AlN layer. The film thickness of the second GaN layer is 1 μm.
　図２３に示すように、第２のＧａＮ層の表面は、平坦である。したがって、この平坦なＧａＮ層の上に種々の素子構造を形成することは容易である。 As shown in FIG. 23, the surface of the second GaN layer is flat. Therefore, it is easy to form various element structures on the flat GaN layer.
２－３．第１の方向を向いているｃ軸の割合
　図２４は、Ｓｉ（００１）基板の上に成膜したＡｌＮ層およびＧａＮ層の境界面を示す透過型電子顕微鏡写真（断面ＴＥＭ写真）である。図２４中の破線で囲んだ領域では、ＡｌＮ層のｃ軸が第１の方向Ｊ１を向いていない。破線で囲まれていない領域では、ＡｌＮ層のｃ軸が第１の方向Ｊ１を向いている。このように図２４中では、ＡｌＮ層のｃ軸は、５０％以上の割合で第１の方向Ｊ１を向いている。 2-3. Ratio of c-axis facing first direction FIG. 24 is a transmission electron micrograph (cross-sectional TEM photograph) showing a boundary surface between an AlN layer and a GaN layer formed on a Si (001) substrate. In the region surrounded by the broken line in FIG. 24, the c-axis of the AlN layer does not face the first direction J1. In the region not surrounded by the broken line, the c-axis of the AlN layer faces the first direction J1. As described above, in FIG. 24, the c-axis of the AlN layer faces the first direction J1 at a rate of 50% or more.
　一方、ＡｌＮ層の上のＧａＮ層では、図２４中の撮像領域にわたってＧａＮ層のｃ軸は第１の方向Ｊ１を向いている。ＡｌＮ層の上のＧａＮ層では、下地層であるＡｌＮ層のｃ軸の方向のうち、支配的な方向である第１の方向Ｊ１の情報を引き継いでいる。そして、ＡｌＮ層の上のＧａＮ層では、ＡｌＮ層で支配的でないｃ軸の方向の情報はほとんど引き継がれない。したがって、ＡｌＮ層のｃ軸が、５０％以上の割合で第１の方向Ｊ１を向いていれば、Ｓｉ（００１）基板の板面にわたってほぼ一様にｃ軸が第１の方向Ｊ１を向いているＧａＮ層が得られる。つまり、単一配向のＧａＮ層が得られることが明らかとなった。 On the other hand, in the GaN layer on the AlN layer, the c-axis of the GaN layer faces the first direction J1 over the imaging region in FIG. In the GaN layer above the AlN layer, the information in the first direction J1, which is the dominant direction among the c-axis directions of the AlN layer as the underlying layer, is inherited. In the GaN layer above the AlN layer, information on the c-axis direction that is not dominant in the AlN layer is hardly carried over. Therefore, if the c-axis of the AlN layer faces the first direction J1 at a rate of 50% or more, the c-axis faces the first direction J1 substantially uniformly over the plate surface of the Si (001) substrate. A GaN layer is obtained. That is, it became clear that a unidirectionally oriented GaN layer was obtained.
３．考察
　これは、ＡｌＮ層のｃ軸が第１の方向Ｊ１を向いている場合において、Ｓｉ（００１）基板の法線方向の結晶面が熱力学的に安定であるため、ＧａＮ層の初期核が優先的に形成されたためであると考えられる。図２４中において、第１の方向Ｊ１を向いているときの基板の法線方向の結晶面は、それ以外の方向を向いているときに発現する結晶面よりも熱力学的に安定であると考えられる。つまり、（１）ＡｌＮ層のｃ軸の支配的な方向およびその割合と、（２）ＡｌＮ層におけるｃ軸の方向を受け継いだとした場合の結晶面の熱力学的安定性と、がその上のＧａＮ層の結晶を決定づけると考えられる。 3. Consideration This is because when the c-axis of the AlN layer is in the first direction J1, the crystal plane in the normal direction of the Si (001) substrate is thermodynamically stable, so that the initial nucleus of the GaN layer is This is probably because it was formed with priority. In FIG. 24, the crystal plane in the normal direction of the substrate when facing the first direction J1 is more thermodynamically stable than the crystal plane appearing when facing the other direction. Conceivable. That is, (1) the dominant direction and ratio of the c-axis of the AlN layer, and (2) the thermodynamic stability of the crystal plane when the c-axis direction in the AlN layer is inherited. This is considered to determine the crystal of the GaN layer.
　本実験では、（１０－１３）面のＧａＮ層を成長させることができた。しかし、ターゲットを配置する角度θを変えれば、その角度θに応じた結晶面で半導体層を成長させることができると考えられる。つまり、ある特定の方向から基板に到達したＡｌＮ粒子は、その方向に近い向きにｃ軸を傾斜させた状態で成長する。その際に、熱力学的に安定な面を平坦面としつつ半導体層は成長すると考えられる。 In this experiment, a (10-13) plane GaN layer could be grown. However, it is considered that if the angle θ at which the target is disposed is changed, the semiconductor layer can be grown on a crystal plane corresponding to the angle θ. That is, AlN particles that have reached the substrate from a specific direction grow with the c-axis inclined in a direction close to that direction. At that time, it is considered that the semiconductor layer grows while making the thermodynamically stable surface flat.
Ｂ．実験２
１．スパッタリングの角度
１－１．成膜条件
　成膜条件は、実験１とほぼ同じである。そのため、実験１と異なる条件について説明する。内圧は、０．０２Ｐａであった。基板の板面に垂直な方向と、ターゲットの表面に垂直な方向と、の間のなす角を３６°と、２０°と、の２通りを実施した。 B. Experiment 2
1. Sputtering angle 1-1. Film-forming conditions The film-forming conditions are almost the same as in Experiment 1. Therefore, conditions different from those in Experiment 1 will be described. The internal pressure was 0.02 Pa. The angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was 36 ° and 20 °.
１－２．実験結果
　図２５は、基板の板面に垂直な方向とターゲットの表面に垂直な方向との間のなす角を３６°とした場合におけるＧａＮ層の表面を示す顕微鏡写真である。図２５に示すように、ＧａＮ層の（１０－１３）面が観測された。図２５（ａ）は、成長時間が１分の場合を示す写真である。図２５（ｂ）は、成長時間が５分の場合を示す図である。図２５（ｃ）は、成長時間が１０分の場合を示す図である。 1-2. Experimental Results FIG. 25 is a photomicrograph showing the surface of the GaN layer when the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target is 36 °. As shown in FIG. 25, the (10-13) plane of the GaN layer was observed. FIG. 25A is a photograph showing a case where the growth time is 1 minute. FIG. 25B shows a case where the growth time is 5 minutes. FIG. 25C shows a case where the growth time is 10 minutes.
　図２５（ｃ）に示すように、ＧａＮ層のｃ軸は、基板の板面に垂直な方向に対して３２°傾斜していた。 As shown in FIG. 25 (c), the c-axis of the GaN layer was inclined by 32 ° with respect to the direction perpendicular to the plate surface of the substrate.
　図２６は、基板の板面に垂直な方向とターゲットの表面に垂直な方向との間のなす角を２０°とした場合におけるＧａＮ層の表面を示す顕微鏡写真である。図２６に示すように、ＧａＮ層の（１０－１５）面が観測された。図２６（ａ）は、成長時間が１分の場合を示す写真である。図２６（ｂ）は、成長時間が５分の場合を示す図である。図２６（ｃ）は、成長時間が１０分の場合を示す図である。 FIG. 26 is a photomicrograph showing the surface of the GaN layer when the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target is 20 °. As shown in FIG. 26, the (10-15) plane of the GaN layer was observed. FIG. 26A is a photograph showing a case where the growth time is 1 minute. FIG. 26B shows a case where the growth time is 5 minutes. FIG. 26C shows a case where the growth time is 10 minutes.
　図２６（ｃ）に示すように、ＧａＮ層のｃ軸は、基板の板面に垂直な方向に対して２０°傾斜していた。 As shown in FIG. 26 (c), the c-axis of the GaN layer was inclined 20 ° with respect to the direction perpendicular to the plate surface of the substrate.
　このように、基板の板面に垂直な方向と、ターゲットの表面に垂直な方向と、の間のなす角を異なる値に設定することにより、異なる面方向に成長するＧａＮ層が得られた。つまり、ターゲットの照射方向および配置を変えることにより、ＧａＮ層の成長方向をある程度制御することができる。 Thus, by setting the angles formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target to different values, GaN layers growing in different plane directions were obtained. That is, the growth direction of the GaN layer can be controlled to some extent by changing the irradiation direction and arrangement of the target.
Ｃ．実験３
１．中間層
１－１．サンプルの製作
　図２７は、実験３のサンプルの構造を示す図である。サンプルとしてサンプルＡ、Ｂ、Ｃを用いた。サンプルＡ、Ｂ、Ｃは、それぞれ、第４の実施形態の第１の中間層、第２の中間層、第３の中間層を有する。 C. Experiment 3
1. Intermediate layer 1-1. Production of Sample FIG. 27 is a diagram showing the structure of the sample of Experiment 3. Samples A, B, and C were used as samples. Samples A, B, and C respectively have the first intermediate layer, the second intermediate layer, and the third intermediate layer of the fourth embodiment.
　サンプルＡは、Ｓｉ（００１）基板と、ＡｌＮ層と、中間層ＩＬと、ＧａＮ層と、をこの順序で積層したものである。中間層ＩＬは、膜厚２０ｎｍの高温ＡｌＮ層である。ＡｌＮ層の膜厚は４５ｎｍである。ＧａＮ層の膜厚は４μｍである。ＧａＮ層は、（１０－１３）面を成長させたものである。ＡｌＮ層は、スパッタリングにより成膜した。その際に、基板の板面に垂直な方向と、ターゲットの表面に垂直な方向と、の間のなす角を３６°とした。中間層ＩＬおよびＧａＮ層は、通常のＭＯＣＶＤ法により成膜した。 Sample A is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order. The intermediate layer IL is a high-temperature AlN layer having a thickness of 20 nm. The thickness of the AlN layer is 45 nm. The film thickness of the GaN layer is 4 μm. The GaN layer is obtained by growing the (10-13) plane. The AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °. The intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
　サンプルＢは、Ｓｉ（００１）基板と、ＡｌＮ層と、中間層ＩＬと、ＧａＮ層と、をこの順序で積層したものである。中間層ＩＬは、膜厚１０ｎｍの低温ＡｌＮ層の上に膜厚２０ｎｍの高温ＡｌＮ層を積層したものである。ＡｌＮ層の膜厚は４５ｎｍである。ＧａＮ層の膜厚は４μｍである。ＧａＮ層は、（１０－１３）面を成長させたものである。ＡｌＮ層は、スパッタリングにより成膜した。その際に、基板の板面に垂直な方向と、ターゲットの表面に垂直な方向と、の間のなす角を３６°とした。中間層ＩＬおよびＧａＮ層は、通常のＭＯＣＶＤ法により成膜した。 Sample B is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order. The intermediate layer IL is obtained by stacking a high-temperature AlN layer having a thickness of 20 nm on a low-temperature AlN layer having a thickness of 10 nm. The thickness of the AlN layer is 45 nm. The film thickness of the GaN layer is 4 μm. The GaN layer is obtained by growing the (10-13) plane. The AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °. The intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
　サンプルＣは、Ｓｉ（００１）基板と、ＡｌＮ層と、中間層ＩＬと、ＧａＮ層と、をこの順序で積層したものである。中間層ＩＬは、膜厚２０ｎｍの高温ＡｌＮ層の上に２５ペアのＡｌＮ／ＧａＮ超格子層を積層したものである。ＡｌＮ層の膜厚は４５ｎｍである。ＧａＮ層の膜厚は４μｍである。ＧａＮ層は、（１０－１３）面を成長させたものである。ＡｌＮ層は、スパッタリングにより成膜した。その際に、基板の板面に垂直な方向と、ターゲットの表面に垂直な方向と、の間のなす角を３６°とした。中間層ＩＬおよびＧａＮ層は、通常のＭＯＣＶＤ法により成膜した。 Sample C is obtained by laminating a Si (001) substrate, an AlN layer, an intermediate layer IL, and a GaN layer in this order. The intermediate layer IL is obtained by stacking 25 pairs of AlN / GaN superlattice layers on a high-temperature AlN layer having a thickness of 20 nm. The thickness of the AlN layer is 45 nm. The film thickness of the GaN layer is 4 μm. The GaN layer is obtained by growing the (10-13) plane. The AlN layer was formed by sputtering. At that time, the angle formed between the direction perpendicular to the plate surface of the substrate and the direction perpendicular to the surface of the target was set to 36 °. The intermediate layer IL and the GaN layer were formed by a normal MOCVD method.
１－２．Ｘ線回折
　（１０－１３）ＧａＮについてＸ線回折を測定した。中間層ＩＬを有するＧａＮのＸ線の半値全幅ＦＷＨＭは、中間層ＩＬを有さないＧａＮのＸ線の半値全幅ＦＷＨＭよりも小さかった。また、中間層ＩＬとして超格子層を有するＧａＮのＸ線の半値全幅ＦＷＨＭは、中間層ＩＬを有さないＧａＮのＸ線の半値全幅ＦＷＨＭの半分程度であった。 1-2. X-ray diffraction X-ray diffraction was measured for (10-13) GaN. The full width at half maximum FWHM of the X-ray of GaN having the intermediate layer IL was smaller than the full width at half maximum FWHM of the X-ray of GaN having no intermediate layer IL. Further, the full width at half maximum FWHM of the X-ray of GaN having the superlattice layer as the intermediate layer IL was about half of the full width at half maximum FWHM of the GaN X-ray having no intermediate layer IL.
　したがって、中間層ＩＬを設けることにより、その上に成長させるＧａＮ層の結晶性が向上する。そして、中間層ＩＬとして超格子層を用いると、ＧａＮ層の結晶性はより向上する。 Therefore, the provision of the intermediate layer IL improves the crystallinity of the GaN layer grown thereon. If a superlattice layer is used as the intermediate layer IL, the crystallinity of the GaN layer is further improved.
１００…薄膜基板
１１０…基板
１２０…バッファ層
２００…ＨＥＭＴ
Ｇ１…ゲート電極
Ｓ１…ソース電極
Ｄ１…ドレイン電極
３００…発光素子
３３０…ｎ型コンタクト層
３４０…発光層
３５０…ｐ型クラッド層
３６０…ｐ型コンタクト層
Ｎ１…ｎ電極
Ｐ１…ｐ電極
ＩＬ…中間層
１０００…成膜装置
１１００…チャンバー
１２００…サセプター
１３００…ヒーター
１４００…ターゲット配置部
１５００…ターゲット
１６００…電圧印加部 DESCRIPTION OF SYMBOLS 100 ... Thin film substrate 110 ... Substrate 120 ... Buffer layer 200 ... HEMT
G1 ... Gate electrode S1 ... Source electrode D1 ... Drain electrode 300 ... Light emitting element 330 ... n-type contact layer 340 ... Light emitting layer 350 ... p-type cladding layer 360 ... p-type contact layer N1 ... n electrode P1 ... p electrode IL ... intermediate layer DESCRIPTION OF SYMBOLS 1000 ... Film-forming apparatus 1100 ... Chamber 1200 ... Susceptor 1300 ... Heater 1400 ... Target arrangement | positioning part 1500 ... Target 1600 ... Voltage application part

Claims (15)

  1. 基板と、
    前記基板の上のバッファ層と、
    を有する薄膜基板において、
    　前記基板は、立方晶基板であり、
    　前記バッファ層は、六方晶であり、
    　前記バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いており、
    　前記第１の方向は、
    　　前記基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜していること
    を特徴とする薄膜基板。     A substrate,
    A buffer layer on the substrate;
    In a thin film substrate having
    The substrate is a cubic substrate;
    The buffer layer is hexagonal;
    The c-axis of the buffer layer faces the first direction at a rate of 50% or more,
    The first direction is:
    A thin film substrate, which is inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate.
  2. 請求項１に記載の薄膜基板において、
    　前記立方晶基板は、
    　　Ｓｉ（００１）基板であり、
    　前記第１の方向は、
    　　前記基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にあること
    を特徴とする薄膜基板。     The thin film substrate according to claim 1,
    The cubic substrate is
    Si (001) substrate,
    The first direction is:
    A thin-film substrate having an in-plane rotation direction of 30 ° or less with respect to the [110] direction of the plate surface of the substrate or a direction equivalent to the [110] direction.
  3. 請求項１または請求項２に記載の薄膜基板において、
    　前記バッファ層は、
    　　ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）であること
    を特徴とする薄膜基板。     The thin film substrate according to claim 1 or 2,
    The buffer layer is
    A thin film substrate comprising an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
  4. 請求項１から請求項３までのいずれか１項に記載の薄膜基板において、
    　前記バッファ層の上の中間層を有し、
    　前記中間層は、六方晶であること
    を特徴とする薄膜基板。     In the thin film substrate according to any one of claims 1 to 3,
    Having an intermediate layer above the buffer layer;
    The intermediate layer is a hexagonal crystal substrate.
  5. 請求項４に記載の薄膜基板において、
    　前記中間層は、超格子層を有すること
    を特徴とする薄膜基板。     The thin film substrate according to claim 4,
    The intermediate layer includes a superlattice layer.
  6. 基板と、
    前記基板の上のバッファ層と、
    前記バッファ層の上のIII 族窒化物半導体層と、
    を有する半導体装置において、
    　前記基板は、立方晶基板であり、
    　前記バッファ層は、六方晶であり、
    　前記バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いており、
    　前記第１の方向は、
    　　前記基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜しており、
    　前記III 族窒化物半導体層のｃ軸は、
    　　前記基板の板面に垂直な方向および面内方向の両方について、前記第１の方向に対して０°以上５°以下の範囲内で傾斜していること
    を特徴とする半導体装置。     A substrate,
    A buffer layer on the substrate;
    A group III nitride semiconductor layer on the buffer layer;
    In a semiconductor device having
    The substrate is a cubic substrate;
    The buffer layer is hexagonal;
    The c-axis of the buffer layer faces the first direction at a rate of 50% or more,
    The first direction is:
    Inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate,
    The c-axis of the group III nitride semiconductor layer is
    The semiconductor device, wherein both the direction perpendicular to the plate surface of the substrate and the in-plane direction are inclined within a range of 0 ° to 5 ° with respect to the first direction.
  7. 請求項６に記載の半導体装置において、
    　前記立方晶基板は、
    　　Ｓｉ（００１）基板であり、
    　前記第１の方向は、
    　　前記基板の板面の［１１０］方向または［１１０］方向と等価な方向に対して面内回転方向で３０°以下の範囲内にあること
    を特徴とする半導体装置。     The semiconductor device according to claim 6.
    The cubic substrate is
    Si (001) substrate,
    The first direction is:
    A semiconductor device characterized in that it is within a range of 30 ° or less in the in-plane rotation direction with respect to the [110] direction or the direction equivalent to the [110] direction of the plate surface of the substrate.
  8. 請求項６または請求項７に記載の半導体装置において、
    　前記バッファ層は、
    　　ＡｌX ＧａY ＩｎZ Ｎ層（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｚ≦１、Ｘ＋Ｙ＋Ｚ＝１）であること
    を特徴とする半導体装置。     The semiconductor device according to claim 6 or 7,
    The buffer layer is
    A semiconductor device characterized by being an Al X Ga Y In Z N layer (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, X + Y + Z = 1).
  9. 請求項６から請求項８までのいずれか１項に記載の半導体装置において、
    　前記バッファ層と前記III 族窒化物半導体層との間に中間層を有し、
    　前記中間層は、六方晶であること
    を特徴とする半導体装置。     The semiconductor device according to any one of claims 6 to 8,
    Having an intermediate layer between the buffer layer and the group III nitride semiconductor layer;
    The semiconductor device, wherein the intermediate layer is a hexagonal crystal.
  10. 請求項９に記載の半導体装置において、
    　前記中間層は、超格子層を有すること
    を特徴とする半導体装置。     The semiconductor device according to claim 9.
    The semiconductor device, wherein the intermediate layer has a superlattice layer.
  11. 基板と、
    前記基板の上のバッファ層と、
    前記バッファ層の上のIII 族窒化物半導体層と、
    を有するＧａＮテンプレートにおいて、
    　前記基板は、立方晶基板であり、
    　前記バッファ層は、六方晶であり、
    　前記バッファ層のｃ軸は、５０％以上の割合で第１の方向を向いており、
    　前記第１の方向は、
    　　前記基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜しており、
    　前記III 族窒化物半導体層のｃ軸は、
    　　前記基板の板面に垂直な方向および面内方向の両方について、前記第１の方向に対して０°以上５°以下の範囲内で傾斜していること
    を特徴とするＧａＮテンプレート。     A substrate,
    A buffer layer on the substrate;
    A group III nitride semiconductor layer on the buffer layer;
    In a GaN template having
    The substrate is a cubic substrate;
    The buffer layer is hexagonal;
    The c-axis of the buffer layer faces the first direction at a rate of 50% or more,
    The first direction is:
    Inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate,
    The c-axis of the group III nitride semiconductor layer is
    A GaN template, wherein both the direction perpendicular to the plate surface of the substrate and the in-plane direction are inclined with respect to the first direction within a range of 0 ° to 5 °.
  12. 薄膜基板の製造方法において、
    　立方晶基板をチャンバーの内部に配置し、
    　前記立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置し、
    　前記立方晶基板と前記ターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより前記立方晶基板の上に六方晶のバッファ層を形成すること
    を特徴とする薄膜基板の製造方法。     In the method of manufacturing a thin film substrate,
    Place the cubic substrate inside the chamber,
    A target is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate,
    A method of manufacturing a thin film substrate, comprising forming a hexagonal buffer layer on the cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target.
  13. 半導体装置の製造方法において、
    　立方晶基板をチャンバーの内部に配置し、
    　前記立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置し、
    　前記立方晶基板と前記ターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより前記立方晶基板の上に六方晶のバッファ層を形成し、
    　前記バッファ層の上にIII 族窒化物半導体層を成長させること
    を特徴とする半導体装置の製造方法。     In a method for manufacturing a semiconductor device,
    Place the cubic substrate inside the chamber,
    A target is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate,
    In a state where the relative positional relationship between the cubic substrate and the target is maintained, a hexagonal buffer layer is formed on the cubic substrate by sputtering,
    A method of manufacturing a semiconductor device, comprising growing a group III nitride semiconductor layer on the buffer layer.
  14. 基板の上に薄膜を成膜する成膜方法において、
    　立方晶基板をチャンバーの内部に配置し、
    　前記立方晶基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で傾斜させた位置にターゲットを配置し、
    　前記立方晶基板と前記ターゲットとの間の相対的位置関係を保持した状態で、スパッタリングにより前記立方晶基板の上に六方晶のバッファ層を形成すること
    を特徴とする成膜方法。     In a film forming method for forming a thin film on a substrate,
    Place the cubic substrate inside the chamber,
    A target is disposed at a position inclined within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the cubic substrate,
    A film forming method, wherein a hexagonal buffer layer is formed on a cubic substrate by sputtering while maintaining a relative positional relationship between the cubic substrate and the target.
  15. 基板を支持するための基板支持部と、
    前記基板支持部を収容するチャンバーと、
    前記基板の板面に垂直な方向に対して１０°以上６０°以下の範囲内で相対的に可変となるように傾斜させた位置に配置されたターゲット配置部と、
    を有すること
    を特徴とする成膜装置。     A substrate support for supporting the substrate;
    A chamber for housing the substrate support;
    A target placement portion disposed at a position inclined so as to be relatively variable within a range of 10 ° to 60 ° with respect to a direction perpendicular to the plate surface of the substrate;
    A film forming apparatus comprising:
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WO2019123763A1 (en) * 2017-12-19 2019-06-27 株式会社Sumco Method for producing group iii nitride semiconductor substrate
CN111527587B (en) * 2017-12-19 2023-11-21 胜高股份有限公司 Method for producing group III nitride semiconductor substrate
WO2019225112A1 (en) * 2018-05-23 2019-11-28 株式会社Sumco Group iii nitride semiconductor substrate and method of producing same
KR20210003229A (en) * 2018-05-23 2021-01-11 가부시키가이샤 사무코 Group III nitride semiconductor substrate and manufacturing method thereof
CN112470260A (en) * 2018-05-23 2021-03-09 胜高股份有限公司 Group III nitride semiconductor substrate and method for producing same
JPWO2019225112A1 (en) * 2018-05-23 2021-05-27 株式会社Sumco Group III nitride semiconductor substrate and its manufacturing method
US20210210340A1 (en) * 2018-05-23 2021-07-08 Sumco Corporation Group iii nitride semiconductor substrate and manufacturing method thereof
KR102513206B1 (en) * 2018-05-23 2023-03-23 가부시키가이샤 사무코 Manufacturing method of group III nitride semiconductor substrate
CN112470260B (en) * 2018-05-23 2024-05-14 胜高股份有限公司 Group III nitride semiconductor substrate and method for manufacturing same

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