WO2016121523A1

WO2016121523A1 - Solid-state image pickup element and control method, and electronic equipment

Info

Publication number: WO2016121523A1
Application number: PCT/JP2016/051082
Authority: WO
Inventors: 裕治源代
Original assignee: ソニー株式会社
Priority date: 2015-01-30
Filing date: 2016-01-15
Publication date: 2016-08-04

Abstract

The present disclosure relates to a solid-state image pickup element and control method, and electronic equipment that make it possible to sufficiently shorten the stabilization time of a ramp signal. An ADC performs A/D conversion on a pixel signal of a pixel. A ramp generation unit generates a ramp signal, and outputs the ramp signal to a plurality of ADCs individually. A ramp line extends from the ramp generation unit. A plurality of A/D conversion units are individually connected in parallel to the ramp line. A current source is connected to the far end of the ramp line from the ramp generation unit and capable of being switched on and off. The present disclosure is applicable to, for example, a CMOS image sensor or the like.

Description

Solid-state imaging device, control method, and electronic apparatus

The present disclosure relates to a solid-state imaging device, a control method, and an electronic device, and more particularly, to a solid-state imaging device, a control method, and an electronic device that can sufficiently shorten a ramp signal settling time.

Single slope column ADC (SS-ADC) is widely used in CMOS (Complementary Metal-Oxide Semiconductor) image sensors. In this SS-ADC, a comparator is arranged for each column, and in each comparator, the voltage of the pixel signal supplied from the pixel is compared with the voltage of the ramp signal common to all the comparators. . Since the time until the comparison result is inverted differs depending on the voltage of the pixel signal, the digital value can be obtained by counting the time.

A ramp generator that generates a ramp signal used in such an SS-ADC and supplies it to all the comparators via the ramp line needs to drive a large number of capacitive loads distributed throughout the ramp line. . Therefore, the waveform becomes dull at the start of ramp signal generation, and a large settling time is required until a constant slew rate is reached. In addition, the settling time and the settling level are different between a position (near end) near the lamp generating portion of the lamp line and a position far from the lamp generating portion (far end).

In SS-ADC, if the ramp signal is not settled, A / D conversion cannot be performed correctly, so the delay in settling leads to an increase in A / D conversion time. In addition, an increase in the ramp signal settling time causes the operating range of the ramp signal to be narrowed.

Therefore, assuming that the capacitive load of the lamp wire is concentrated at a predetermined location, the current flowing from the capacitive load after the ramp signal is settled is forcibly extracted immediately after the start of the ramp signal generation. It has been devised to shorten the signal settling time (see, for example, Patent Document 1).

JP 2011-259407 A

However, in practice, since the capacitive load of the lamp line is distributed over the entire lamp line, in the invention described in Patent Document 1, the voltage distribution of the lamp signal in the lamp line changes, and the change is The ramp signal will not settle until it settles. Therefore, the settling time of the ramp signal cannot be shortened sufficiently.

The present disclosure has been made in view of such a situation, and makes it possible to sufficiently shorten the ramp signal settling time.

A solid-state imaging device according to the first aspect of the present disclosure includes a plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels, a ramp signal, and a plurality of A / D conversion units. A ramp generator that outputs to each, a ramp line that is connected to each of the plurality of A / D converters from the ramp generator, and is connected to a far end of the ramp line from the ramp generator And a first current source that can be turned on and off.

In the first aspect of the present disclosure, a plurality of A / D conversion units that perform A / D conversion on a pixel signal of a pixel, and a ramp signal are generated and output to each of the plurality of A / D conversion units A ramp generator that is connected to each of the plurality of A / D converters in parallel from the ramp generator, and an on / off connected to a far end of the ramp line from the ramp generator. A possible first current source is provided.

A control method according to a second aspect of the present disclosure includes a plurality of A / D conversion units that perform A / D conversion on a pixel signal of a pixel, a ramp signal, and each of the plurality of A / D conversion units Connected to the far end of the ramp line from the ramp generation unit, the ramp line that is output from the ramp generation unit, the lamp line is connected to each of the plurality of A / D conversion units in parallel, A control device for controlling a solid-state imaging device including a first current source that can be turned on / off, when the voltage of the lamp line transits from a predetermined voltage to another predetermined voltage, the control device controls the solid-state imaging device only for a predetermined period. 1 is a control method including a step of turning on or off one current source.

In the second aspect of the present disclosure, a plurality of A / D conversion units that perform A / D conversion on a pixel signal of a pixel, and a ramp signal are generated and output to each of the plurality of A / D conversion units A ramp generator that is connected to each of the plurality of A / D converters in parallel from the ramp generator, and an on / off connected to a far end of the ramp line from the ramp generator. When the voltage of the lamp line of the solid-state imaging device including the first current source that can be changed from a predetermined voltage to another predetermined voltage, the first current source is turned on or off for a predetermined period. To be.

An electronic apparatus according to a third aspect of the present disclosure includes a plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels, a ramp signal, and each of the plurality of A / D conversion units. Connected to the far end of the ramp line from the ramp generation unit, the ramp line that is output from the ramp generation unit, the lamp line is connected to each of the plurality of A / D conversion units in parallel, And a first current source that can be turned on and off.

In the third aspect of the present disclosure, a plurality of A / D conversion units that perform A / D conversion on a pixel signal of a pixel, and a ramp signal are generated and output to each of the plurality of A / D conversion units A ramp generator that is connected to each of the plurality of A / D converters in parallel from the ramp generator, and an on / off connected to a far end of the ramp line from the ramp generator. A possible first current source is provided.

According to the first and third aspects of the present disclosure, imaging can be performed. According to the first aspect of the present disclosure, it is possible to sufficiently shorten the ramp signal settling time.

Moreover, according to the second aspect of the present disclosure, the solid-state imaging device can be controlled. According to the second aspect of the present disclosure, the solid-state imaging device can be controlled so as to sufficiently shorten the ramp signal settling time.

It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure which shows the outline of a structure of 1st Embodiment of the CMOS image sensor as a solid-state image sensor to which this indication is applied. It is a figure which shows the 1st detailed structural example of the column process part of FIG. It is an image figure explaining control of the control part at the time of a ramp signal production | generation. It is a graph which shows the voltage waveform example of the simulation result of the ramp signal at the time of the production | generation of the ramp signal of a CMOS image sensor in which two current sources are not connected to the lamp line. It is a graph which shows the voltage waveform example of the simulation result of the ramp signal at the time of the production | generation of the ramp signal of the CMOS image sensor by which only one current source is connected to a lamp line. 2 is a graph illustrating an example of a voltage waveform of a simulation result of a ramp signal when the ramp signal is generated by the CMOS image sensor of FIG. 1. FIG. 7 is a graph obtained by enlarging a voltage waveform in the vicinity of the start of ramp signal generation in the graphs of FIGS. 4 and 6. It is an image figure explaining control of the control part at the time of return from P phase offset. 2 is a graph showing a voltage waveform example of a simulation result of a ramp signal when two current sources are not connected to a ramp line and a return from a P-phase offset of the CMOS image sensor of FIG. 1. It is a figure which shows the 2nd detailed structural example of the column process part of FIG. It is a figure which shows the 3rd detailed structural example of the column process part of FIG. It is a figure which shows the structural example of 2nd Embodiment of the CMOS image sensor as a solid-state image sensor to which this indication is applied. It is a figure which shows the structural example of the A / D process part of FIG. It is a block diagram showing an example of composition of an embodiment of an imaging device as electronic equipment to which this indication is applied.

Hereinafter, modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1st Embodiment: Solid-state image sensor (FIGS. 1 to 11)
2. Second Embodiment: Solid-State Image Sensor (FIGS. 12 and 13)
3. Third Embodiment: Electronic Device (FIG. 14)

<First embodiment>
(Configuration example of the first embodiment of the CMOS image sensor)
FIG. 1 is a diagram illustrating an outline of the configuration of a first embodiment of a CMOS image sensor as a solid-state imaging device to which the present disclosure is applied.

The CMOS image sensor 10 includes a pixel region 11, a pixel driving line 12, a vertical signal line 13, a vertical driving unit 14, a column processing unit 15, a horizontal driving unit 17, a signal processing unit 18, and the like, which are not shown in a semiconductor substrate such as a silicon substrate. It is formed on a substrate (chip).

In the pixel region 11 of the CMOS image sensor 10, pixels 11 </ b> A having photoelectric conversion elements that generate and store charges corresponding to the amount of incident light are two-dimensionally arranged in a matrix to perform imaging. In the pixel region 11, pixel drive lines 12 are formed for each row with respect to the matrix-like pixels 11A, and vertical signal lines 13 are formed for each column.

The vertical drive unit 14 includes a shift register, an address decoder, and the like, and drives each pixel 11A in the pixel area 11 in units of rows. One end of the pixel drive line 12 is connected to an output end (not shown) corresponding to each row of the vertical drive unit 14. Although a specific configuration of the vertical driving unit 14 is not illustrated, the vertical driving unit 14 has two scanning systems, a reading scanning system and a sweeping scanning system.

The readout scanning system sequentially selects each row so that pixel signals obtained as a result of imaging by each pixel 11A are sequentially read in units of rows, and outputs a selection signal or the like from an output terminal connected to the pixel drive line 12 of the selected row. . As a result, the pixels 11 </ b> A in the row selected by the readout scanning system read out the electrical signals of the charges accumulated in the photoelectric conversion elements as pixel signals and supply them to the vertical signal lines 13.

The sweep scanning system sweeps (resets) unnecessary charges from the photoelectric conversion elements, and resets from the output terminal connected to the pixel drive line 12 of each row prior to the scanning of the readout system by the time of the shutter speed. Output a signal. By the scanning by the sweep-out scanning system, so-called electronic shutter operation is sequentially performed for each row. Here, the electronic shutter operation refers to an operation in which the charge of the photoelectric conversion element is discarded and exposure is newly started (charge accumulation is started).

The column processing unit 15 is an SS-ADC, and includes a ramp generation unit 15A, an ADC (Analog Digital Converter) 15B for each column of the pixels 11A in the pixel region 11, and the like.

The ramp generation unit 15A is a DAC (Digital Analog Converter), for example, and generates a ramp signal and outputs it to each ADC 15B.

The ADC 15B includes a comparator 31 and a counter latch 32.

The ADC 15B first performs A / D conversion on the reset level signal (P phase) output from the pixel 11A in the selected row of the corresponding column through the vertical signal line 13, and then, from the pixel 11A to the vertical signal line 13 A / D conversion is performed on the pixel signal (D-phase) output through. The ADC 15B performs correlated double sampling by subtracting the P-phase digital data from the D-phase digital data obtained as a result of the A / D conversion.

Specifically, the comparator 31 of the ADC 15B first compares the ramp signal generated by the ramp generator 15A with the reset level signal. The counter latch 32 counts the comparison time of the comparator 31 until the comparison result is switched, and holds the count result as digital data after A / D conversion of the reset level signal.

Next, the comparator 31 compares the ramp signal with the pixel signal. The counter latch 32 subtracts the comparison time of the comparator 31 until the comparison result is switched from the digital data of the held reset level signal. In other words, the counter latch 32 sets the count result of the comparison time of the comparator 31 until the comparison result is switched as digital data after A / D conversion of the pixel signal, and subtracts it from the digital data of the reset level signal. The counter latch 32 holds the subtraction result as a correlated double sampling result.

The horizontal drive unit 17 includes a shift register, an address decoder, and the like, and selects the ADC 15B of the column processing unit 15 in order. By the selective scanning by the horizontal driving unit 17, the correlated double sampling results held by the counter latches 32 of the column processing unit 15 are sequentially output to the signal processing unit 18.

The signal processing unit 18 performs various signal processing such as addition processing on the correlated double sampling result output from the counter latch 32. The signal processing unit 18 outputs digital data of the pixel signal after signal processing.

(First detailed configuration example of the column processing unit)
FIG. 2 is a diagram illustrating a first detailed configuration example of the column processing unit 15 of FIG.

As shown in FIG. 2, the ramp generator 15A includes a ramp signal generating current source 51 and a resistor 52. The ramp generation unit 15A generates a ramp signal by controlling the current flowing through the resistor 52 using the ramp signal generation current source 51 according to the control of the control unit 63.

Specifically, the ramp signal generation current source 51 of the ramp generation unit 15 _{</ b>} A is connected to a power supply, and supplies the current of the current value I _ramp set by the control unit 63 to the resistor 52. Resistor 52 is the resistance of the resistance value R _o, electric current supplied from the ramp signal generator for the current source 51 to GND. The current value I _ramp is set so as to gradually decrease from a predetermined value, for example, when the ramp signal is generated. As a result, the voltage at the contact point P between the ramp signal generating current source 51 and the resistor 52 becomes a voltage having a ramp waveform that gradually decreases.

The lamp generator 15A outputs the ramp signal at the contact point P between the ramp signal generating current source 51 and the resistor 52 to all the ADCs 15B via the ramp line (output wiring) 60.

The lamp wire 60 connects the contact P and the current source 61 (first current source). That is, the ramp line 60 exits from the ramp generator 15A. Further, the current source 61 is connected to a position Q of an end portion (far end) opposite to the end portion (near end) connected to the contact P of the lamp wire 60.

The current source 61 switches the operation of whether or not to pass a DC current having a preset current value _Ife between the lamp line 60 and GND according to the control of the control unit 63. The current source 61 is configured to be turned on / off using a current mirror circuit or the like. The current value I _fe is positive in the direction of flowing into the lamp line 60. Therefore, when the current value I _fe is negative, direct current flows out from the lamp line 60.

Each ADC 15B is connected to the ramp line 60 in parallel. A current source 62 (second current source) is connected to a position (near-end side position) R between the ADC 15B and the contact P connected to the lamp line 60 at a position closest to the contact P of the lamp line 60. Is done.

The current source 62 switches the operation of whether or not to pass a DC current having a preset current value _Ine between the lamp line 60 and the power source according to the control of the control unit 63. The current source 62 is configured to be turned on / off using a current mirror circuit or the like. The direction in which the current value I _ne flows into the lamp line 60 is positive. Therefore, when the current value _Ine is negative, the direct current flows out from the lamp line.

The controller 63 controls the ramp signal generating current source 51, the current source 61, and the current source 62. Specifically, the control unit 63 sets the current value I _ramp of the _ramp signal generating current source 51. In addition, the control unit 63 controls on and off of the operations of the current source 61 and the current source 62.

As described above, in the CMOS image sensor 10, the current source 61 is connected to the ramp generator 15A of the lamp line 60 at the position Q farthest from the ADC 15B farthest from the ADC 15B, and the current source 61 is positioned at the position R closer to the ADC 15B closest to the lamp generator 15A. 62 is connected.

The current value I _fe and the current value _Ine are determined based on characteristics unique to the lamp line 60, such as the wiring resistance and parasitic capacitance of the lamp line 60, and the resistance value _Ro , for example, unique to the lamp line 60. This is a value that minimizes the settling time (optimizes the settling characteristic inherent to the ramp line 60). Specifically, the current value I _fe and the current value I _ne during ramp signal generation, wiring resistance and parasitic capacitance of the lamp line 60, is determined based such as the resistance value R _o, proportional to the slew rate of the ramp signal The value to be The current value I _fe (current value I _ne ) at the time of recovery from the P-phase offset is a value unique to the lamp line 60 determined based on the wiring resistance, parasitic capacitance, resistance value _Ro, etc. of the lamp line 60. And the coefficient determined by the period during which the current source 61 (current source 62) is off is multiplied by the transition potential difference of the lamp line 60.

Here, it is assumed that the current source 61 is connected to the position Q of the lamp line 60 that is the farthest from the ADC 15B to the ramp generating unit 15A, but the connecting position of the current source 61 is the ADC 15B that is the farthest from the ramp generating unit 15A. If it is near, it may be a little away. Similarly, the connection position of the current source 62 may be slightly away from the ADC 15B as long as it is in the vicinity of the ADC 15B closest to the lamp generating unit 15A.

Further, the current source 62 may be incorporated in the lamp generator 15A. Further, the CMOS image sensor 10 may include only one of the current source 61 and the current source 62.

(Explanation of control of the control unit at the time of ramp signal generation)
FIG. 3 is an image diagram for explaining the control of the control unit 63 of FIG. 2 when generating a ramp signal.

In the graph of FIG. 3, the horizontal axis represents time, and the vertical axis represents the current value. The thick solid line, the alternate long and short dash line, and the thin solid line represent the current value I _ramp , the current value of the current source 62, and the current value of the current source 61, respectively.

In the example of FIG. 3, at time t ₁ , the control unit 63 starts to gradually reduce the current value I _ramp from the predetermined value I _{ramp, max} . Thereby, the generation of the ramp signal is started. At time t _2, the when the current value I _'ramp becomes 0, the control unit 63 ends the reduction of the current value _{I' ramp.} Thereby, the generation of the ramp signal is completed.

In this case, the control unit 63 turns on the current source 61 from the time t ₁ that is the start time of the ramp signal generation to the time t ₂ that is the end time of the ramp signal generation, and turns the current source 62 on. Turn off. As a result, the current value of the current source 62 changes from a preset positive current value _Ine at the on time to a current value 0 at the off time. That is, there is no current flowing into the lamp line 60 from the current source 62 when the current source 62 is turned on. As described above, when the current value of the current source 62 changes in the minus direction, that is, in the direction of drawing from the lamp line 60, the voltage at the contact P changes in the minus direction.

Further, the current value of the current source 61 changes from the current value 0 at the off time to the negative current value I _fe that is set at the on time in advance. That is, current is drawn from the lamp line 60 to the current source 61. As described above, when the current value of the current source 61 changes in the minus direction, that is, in the direction of drawing from the lamp line 60, the voltage at the contact P changes in the minus direction.

At time t ₂ , the control unit 63 turns off the current source 61 and turns on the current source 62. As a result, the current value of the current source 62 returns from the current value 0 at the off time to the positive current value _Ine at the on time.

The current value of the current source 61 returns from the negative current value _Ife when the current source 61 is on to the current value 0 when it is off.

Here, in order to make the final ramp signal voltage higher than GND, the current is supplied from the current source 62 to the resistor 52 before the start of the generation of the ramp signal. Good. In this case, the current source 62 is connected to GND, and the current value _Ine is a negative value. Then, from time t ₁ to time t ₂ , the current source 62 is turned on, and current is drawn from the lamp line 60 to the current source 62.

Similarly, here, the current is not supplied from the current source 61 to the resistor 52 before the start of the ramp signal generation. For example, the ramp generator 15A is configured by a DAC in which an output resistor is connected to GND. When the final ramp signal voltage is GND, a current may be supplied. In this case, the current source 61 is connected to the power source, and the current value _Ife is a positive value. Then, the current source 61 is turned off from the time t ₁ to the time t ₂ , and the current flowing into the lamp line 60 when the current source 61 is turned on disappears.

The factor of the effect of reducing the settling time of the ramp signal is the amount of change in current due to the on / off of the current source 61 and the current source 62. Therefore, the current value of the current source 61 and the current value of the current source 62 are the time t _1. Any value can be used as long as the current changes from the ramp line 60 in the direction from which the current is drawn from the time t ₂ to the time t ₂ .

(Explanation of effect when generating ramp signal of the present disclosure)
FIG. 4 is a graph showing a voltage waveform example of a simulation result of a ramp signal when generating a ramp signal of a CMOS image sensor in which the current source 61 and the current source 62 are not connected to the ramp line 60. FIG. 5 is a graph showing an example of a voltage waveform of a simulation result of a ramp signal when generating a ramp signal of a CMOS image sensor in which only the current source 62 is connected to the lamp line 60.

Further, FIG. 6 is a graph showing an example of a voltage waveform of a simulation result of the ramp signal when the ramp signal of the CMOS image sensor 10 is generated, and FIG. 7 is a start of generation of the ramp signal of the graphs of FIGS. 4 and 6. It is the graph which expanded the voltage waveform near the hour.

4 to 7, the horizontal axis represents time, and the vertical axis represents the voltage of the ramp signal. 4 to 6, the solid line represents the waveform of the ramp signal near the position R of the ramp line 60, the rough dotted line represents the waveform of the ramp signal near the position Q, and the fine dotted line represents the position R and the position. The waveform of the ramp signal near the middle of Q is shown. In FIG. 7, a thin solid line, a thin coarse dotted line, and a thin fine dotted line are a solid line, a coarse dotted line, and a fine dotted line near the start of ramp signal generation in FIG. 4, respectively, and are a thick solid line, a thick coarse dotted line, and a thick dotted line. The fine dotted lines are a solid line, a rough dotted line, and a fine dotted line near the start of ramp signal generation in FIG.

In the simulations of FIGS. 4 to 6, the total load capacitance C of the lamp line 60 is set to 500 pF, the total wiring resistance R is set to 200Ω, and approximated by a 100-stage RC ladder. Therefore, the time constant τ (= RC) of the ramp line 60 is 100 ns. The resistance value R _o of the resistor 52 was 100Ω, and the slew rate k of the ramp signal was 500 kV / s.

The wiring length is not necessary as a simulation parameter, and the waveform of the ramp signal is determined by the total load capacitance C and the total wiring resistance R of the lamp line 60. Note that the total load capacitance C includes not only the actual load but also the parasitic capacitance.

In the simulation as described above, in the CMOS image sensor in which the current source 61 and the current source 62 are not connected to the lamp line 60, as shown in FIGS. 4 and 7, the ramp signal near the position Q far from the lamp generator 15A is settled. The time T ₁ becomes 200 ns or more.

As shown in FIG. 4, in the vicinity of the intermediate position distant position Q near and position R and position Q from the ramp generator 15A, at the start of the generation of the ramp signal (2.0 × 10- ⁷ seconds after the start of the simulation), lamp The signal voltage change starts with a delay. Therefore, the ramp signal settling time T ₁ is longer than the ramp signal settling time T ₁ ′ in the vicinity of the position R close to the ramp generating unit 15A.

On the other hand, in the CMOS image sensor in which only the current source 62 is connected to the lamp line 60, a current value I _ne is -200Myuei, when the current source 62 is turned off at the time of generation of the ramp signal, as shown in FIG. 5 The settling time T ₂ of the ramp signal in the vicinity of the position Q far from the ramp generating unit 15A is 100 ns to 200 ns, which is shorter than the settling time T ₁ .

The current value I _ne of −200 μA is the value described in Japanese Patent Application Laid-Open No. 2011-259407. However, when the current value I _ne is −200 μA, current flows from the lamp line 60 after settling. . The absolute value of the current value I _ne that minimizes the settling time is greater than 200 μA. In this case, the voltage waveform of the ramp signal near the position between the position R and the position Q is linear, and the voltage waveform of the ramp signal near the position R and the voltage waveform of the ramp signal near the position Q are the position R And the voltage waveform of the ramp signal in the vicinity of the intermediate position between the position Q and the position close to the vertical symmetry.

4 and 5, only the voltage waveform of the ramp signal in the vicinity of the position R, in the vicinity of the position Q, and in the vicinity of the intermediate position between the position R and the position Q is illustrated, but the voltage waveform in the other positions is illustrated. , Between the voltage waveform near position R and the voltage waveform near position Q.

In the CMOS image sensor 10, a current value I _fe is -121Myuei, the current value I _ne -141μA, when the current source 61 when generating the ramp signal is turned on, the current source 62 is turned off, FIGS. 6 and As shown in FIG. 7, the settling time T ₃ of the ramp signal near the position R, the position Q, and the position between the position R and the position Q of the ramp line 60 is significantly shorter than the settling time T _1. 10ns or less.

That is, in the simulation of FIG. 6, the current is drawn from the ramp line 60 by the current source 61 and the current is drawn from the ramp line 60 by the current source 62. Thereby, the delay of the voltage change of the ramp signal near the position Q far from the lamp generator 15A and near the middle between the position R and the position Q is further shortened. In addition, since the voltage of the ramp signal at each position converges immediately, the voltage waveform does not shift back. Accordingly, the ramp signal settling time T ₃ is shorter than the settling time T ₂ .

Further, as shown in FIGS. 6 and 7, the voltage waveforms of the ramp signals near the position R near the lamp generating unit 15A and the position near the position Q are almost overlapped. Furthermore, the voltage of the ramp signal near the intermediate position between the position R and the position Q is the highest, which is ideal.

Further, as shown in FIGS. 6 and 7, in the CMOS image sensor 10, the current source 61 and the current source 62 provide both the current source 61 and the current source 62 with a potential difference in the ramp line 60 after settling. Compared to a CMOS image sensor that does not, it is roughly 1/4 size. This increases the voltage range (P-phase margin) of the ramp signal that can be used for P-phase A / D conversion.

In the graph of FIG. 6, only the voltage waveform of the ramp signal in the vicinity of the position R, in the vicinity of the position Q, and in the vicinity of the intermediate position between the position R and the position Q is illustrated. It exists between the voltage waveform near and near position Q and the voltage waveform near the position between position R and position Q.

As described above, in the CMOS image sensor 10 including both the current source 61 and the current source 62, since the ramp signals at all positions in the ramp line 60 converge immediately, there is no need to perform control for changing the current value over time. The settling time of the ramp signal can be sufficiently shortened. That is, the settling of the ramp signal can be sufficiently accelerated only by turning on / off the current source 61 and the current source 62.

Further, since the delay of the voltage change of the ramp signal near the position Q far from the ramp generating unit 15A and near the intermediate position between the position R and the position Q is shortened, the voltage at the end of the generation of the ramp signal is expressed in FIG. Compared to FIG. In addition, the operation start voltage of the ramp signal increases due to the shortening of the settling time. Accordingly, the operating range of the ramp signal is increased.

Even when only the current source 61 is connected to the lamp line 60, the effect of sufficiently shortening the ramp signal settling time can be obtained as in the case where both the current source 61 and the current source 62 are connected. The effect is smaller than when both are connected.

(Explanation of the control of the control unit when returning from the P-phase offset)
FIG. 8 is an image diagram for explaining the control of the control unit 63 in FIG. 2 when returning from the P-phase offset.

In the graph of FIG. 8, the horizontal axis represents time, and the vertical axis represents the current value. A thick solid line and a thin solid line represent the current value I _ramp and the current value of the current source 61, respectively.

In the ADC 15B of the CMOS image sensor 10, when a reset level signal is input from each pixel 11A of the selected row, the comparator 31 is in auto-zero operation. When returning from the P-phase offset, the ramp generator 15A needs to transition the voltage of the ramp signal from the voltage at the time of auto zero to the voltage at the start of ramp signal generation (at the time of step response).

Therefore, as shown in FIG. 8, at time t _{11 when} the recovery from the P-phase offset is started, the control unit 63 increases the current value I _ramp of the _ramp signal generating current source 51 to a predetermined value I _{ramp, start} . . At this time, the control unit 63 is also so turned off current source 61 for a predetermined finite time period T _w, to generate a step current. This shortens the settling time when returning from the P-phase offset.

It should be noted that ON / OFF of the current source 61 when returning from the P-phase offset differs depending on the voltage of the ramp signal during auto zero. When the voltage of the ramp signal decreases when returning from the P-phase offset, the current source 61 is turned on for a finite period T _w when returning from the P-phase offset, and current flows out from the ramp line 70. Further, when returning from the P-phase offset, the current source 61 may be connected to a power supply instead of GND. In this case, the current source 61 is turned on / off in the reverse manner when connected to the GND.

Also, in general, the more finite period T _w is long, but only a small current value I _fe, acceleration degree of settling time decreases. Therefore, the finite period T _w is determined in consideration of this trade-off. Although only the current source 61 is described here, only the current source 62 may be used, or both the current source 61 and the current source 62 may be used.

(Description of the effect at the time of return from P phase offset of this indication)
FIG. 9 illustrates a CMOS image sensor in which the current source 61 and the current source 62 are not connected to the lamp line 60, and a CMOS image sensor 10 in which the current source 61 and the current source 62 are connected to the lamp line 60. It is a graph which shows the voltage waveform example of the simulation result of the ramp signal at the time of a return.

In FIG. 9, the horizontal axis represents time, and the vertical axis represents the voltage of the ramp signal. In FIG. 9, a thin solid line, a thin coarse dotted line, and a thin fine dotted line indicate a position near the position R, a position Q, and a position Q when the current source 61 and the current source 62 are not connected to the lamp line 60, respectively. And the waveform of the ramp signal in the vicinity of the middle position between R and R.

In addition, a thick solid line, a thick coarse dotted line, and a thick fine dotted line represent the waveform of the ramp signal near the position R, near the position Q, and between the position Q and the position R of the ramp line 60 of the CMOS image sensor 10, respectively. .

In the simulation of FIG. 9, similar to the case of FIGS. 4 to 6, the total load capacitance C of the lamp line 60 is set to 500 pF, the total wiring resistance R is set to 200Ω, and approximation is performed with a 100-stage RC ladder. The resistance value R _o of the resistor 52 was 100Ω. Furthermore, the voltage of the ramp signal at auto zero was set to 0.9V, and the voltage at the start of the ramp signal generation was set to 1.0V. That is, the voltage change V _step when returning from the P-phase offset is 0.1V.

As shown in FIG. 9, when the current source 61 and the current source 62 are not connected to the ramp line 60, the settling time T ₁₁ of the ramp signal near the position R is from 300 ns, which is three times the time constant 100 ns of the ramp line 60. long. Position Q and the position settling time of the intermediate position and near the position Q near the ramp signal R is integer longer than constant-time T _11.

On the other hand, in the CMOS image sensor 10, a current value I _fe is 51.7Myuei, when a finite time period T _w is 200 ns, as shown in FIG. 9, near the position Q, near the position R, and the position Q to the position R settling time T ₁₂ of the ramp signal near the middle position is shorter 200ns about than the settling time T _11.

That is, near the position Q, near the position R, and the voltage waveform of the ramp signal near an intermediate position of the position Q and the position R, the time of restoration starts from P-phase offset (1.0 × 10- ⁷ seconds after the start of the simulation), The current source 61 and the current source 62 are substantially the same regardless of the presence or absence. However, the CMOS image sensor 10 having a current source 61 and current source 62, then rapidly approaches the 1.0 V, and after a finite time period T _w, reaches approximately 1.0 V. In the voltage waveform of the ramp signal at a position Q far from the ramp generator 15A, overshoot occurs due to the current of the current source 61, but immediately after the current source 61 is turned on, it is set to 1.0V.

Although not shown, the vicinity of the position Q, near the position R, and the voltage waveform of the position Q and the position ramp signal location other than near the middle position of the R, like the these positions, after a finite time period T _w It reaches about 1.0V.

As described above, in the CMOS image sensor 10, not only the settling acceleration at the time of generating the ramp signal but also the settling acceleration at the time of returning from the P-phase offset (step) only by changing the control of the current source 61 by the control unit 63. Speeding up the settling). That is, the CMOS image sensor 10 can shorten the settling time at the time of generating the ramp signal or returning from the P-phase offset only by switching the current source 62 on / off.

As a result, the frame rate of the captured image can be improved. In addition, even if the time constant of the lamp line 60 is large, the settling time is in an allowable range, so that the width of the lamp line 60 can be reduced.

Further, the CMOS image sensor 10 can further shorten the settling time by using not only the current source 61 but also the current source 62.

Furthermore, even when the position of the current source 61 is deviated from the position Q or when the current value of the current source 61 varies, the effect is only diminished and no sudden failure occurs. Therefore, this technique is a robust technique.

Further, the acceleration of the settling time, since the resistance value R ₀ of the resistor 52 is less dependent, it is possible to increase the resistance value R _0. As a result, the power consumption of the lamp generator 15A can be reduced. In general, since the ratio of the power consumption of the lamp generation unit 15A to the power consumption of the entire CMOS image sensor 10 is large, the effect of reducing the power consumption of the lamp generation unit 15A is large.

Furthermore, the CMOS image sensor 10 can suppress an increase in power consumption because it is not necessary to pass a current unnecessarily in order to generate a ramp signal as compared with a case where a DAC is connected to the position R and the position Q. . Further, since the voltage driving unit is only the ramp generating unit 15A, the output of the DAC does not batt unlike the case where the DAC is connected to the position R and the position Q.

(Second detailed configuration example of the column processing unit)
FIG. 10 is a diagram illustrating a second detailed configuration example of the column processing unit 15 in FIG.

10, the same reference numerals are given to the same components as those in FIG. 2. The overlapping description will be omitted as appropriate.

The configuration of the column processing unit 15 in FIG. 10 is different from the configuration in FIG. 2 in that a step power source 81 is provided instead of the current source 62 and a control unit 82 is provided instead of the control unit 63. The configuration in FIG. 10 is obtained by transforming the current drive of the contact P in the configuration in FIG. 2 into a voltage drive using Thevenin's theorem.

Specifically, in the ramp generator 15A of FIG. 10, a step power supply 81 is connected between the resistor 52 and GND. The step power supply 81 is, for example, a resistor that generates a voltage V _ne and is short-circuited when a ramp signal is generated according to the control of the control unit 82. Further, the step power supply 81 inserts a resistor for a predetermined finite period (turns the short switch off) when returning from the P-phase offset according to the control of the control unit 82. As a result, the voltage of the ramp signal at the contact P changes in the negative direction.

The control unit 82 controls the ramp signal generating current source 51, the current source 61, and the step power source 81. Specifically, the control unit 82 sets the current value I _ramp of the _ramp signal generating current source 51 as in the control unit 63 of FIG. The control unit 82 controls the operation of the current source 61 on and off as with the control unit 63. Further, control unit 82 controls step power supply 81 to be short-circuited during a predetermined finite period when the ramp signal is generated and when the phase signal is restored from the P-phase offset.

As described above, in the lamp generating unit 15A of FIG. 10, the step power supply 81 is driven by the voltage during the predetermined finite period at the time of generating the ramp signal and returning from the P-phase offset. The voltage of the ramp signal is changed in the negative direction. If the resistance R _o of the resistor 52 is zero, but can not perform the current driving, it is possible to sufficiently shorten the settling time of the ramp signal by the voltage driving.

(Third detailed configuration example of the column processing unit)
FIG. 11 is a diagram illustrating a third detailed configuration example of the column processing unit 15 in FIG. 1.

11, the same components as those in FIG. 10 are denoted by the same reference numerals. The overlapping description will be omitted as appropriate.

11 differs from the configuration of FIG. 10 in that an operational amplifier 101 and a resistor 102 are provided instead of the resistor 52, and a power supply 103 is provided.

As described above, when the voltage is driven by the step power supply 81, the settling time of the ramp signal can be sufficiently shortened even when the resistance value _Ro is 0. Therefore, the column processing unit 15 in FIG. A ramp signal is generated using the operational amplifier 101 and the resistor 102 instead of the resistor 52.

Specifically, in the ramp generator 15A of FIG. 11, the other end of the ramp signal generating current source 51, one end of which is connected to the power source, is connected to the inverting input terminal of the operational amplifier 101 and one end of the resistor 102 having the resistance value _Rf. Connected. The output terminal of the operational amplifier 101 and the other end of the resistor 102 are connected to the lamp line 60, respectively. The non-inverting input terminal of the operational amplifier 101 is connected to one end of the step power supply 81, and the other end of the step power supply 81 is connected to the power supply 103 having the voltage V _ped .

When the ramp signal is generated, the controller 82 sets the current value I _ramp of the ramp signal generating current source 51 so as to gradually increase from a predetermined value. As a result, the voltage of the ramp signal output from the output terminal of the operational amplifier 101 to the ramp line 60 becomes a voltage having a ramp waveform that gradually decreases.

When the ramp signal is generated by the operational amplifier 101 as in the ramp generator 15A of FIG. 11, the output resistance of the operational amplifier 101 is very small. Therefore, even if a current flows into the lamp line 60 from the capacitive load of the lamp line 60, the lamp signal instantaneously settles on the side of the lamp line 60 close to the lamp generator 15A. Therefore, it is meaningless to draw the current on the side close to the lamp generator 15A as in the invention of Patent Document 1. However, since the settling time of the ramp signal is determined according to the time constant of the ramp line 60 on the side far from the ramp generating unit 15A, the settling time is relatively long.

Since the column processing unit 15 of FIG. 11 includes the current source 61, the settling time of the ramp signal far from the ramp generation unit 15A can be sufficiently shortened. In addition, since the column processing unit 15 of FIG. 11 includes not only the current source 61 but also the step power supply 81, the settling time of the ramp signal can be further shortened.

Note that, instead of providing the step power supply 81, a step current may be supplied to the resistor 102. In addition, when the impedance of the lamp generating unit 15A is small, the column processing unit 15 of FIG. 11 including the step power supply 81 instead of the current source 62 is more desirable than the column processing unit 15 of FIG.

<Second Embodiment>
(Configuration example of the second embodiment of the CMOS image sensor)
FIG. 12 is a diagram illustrating a configuration example of a second embodiment of a CMOS image sensor as a solid-state imaging device to which the present disclosure is applied.

12, the same reference numerals are given to the same components as those in FIG. 1. The overlapping description will be omitted as appropriate.

The CMOS image sensor 120 in FIG. 12 is configured by stacking three semiconductor substrates 121 to 123.

The pixel region 11 is provided on the semiconductor substrate 121, the A / D processing unit 141 is provided on the semiconductor substrate 122, and the circuit unit 142 is provided on the semiconductor substrate 123. The A / D processing unit 141 is provided for each pixel group including one or more pixels 11A in the pixel region 11, and the ADC 15B and the ramp generation unit 15A perform A / D conversion on the pixel signal of each pixel in the pixel group. Etc. The circuit unit 142 includes the vertical drive unit 14 in FIG. 1, a horizontal drive unit that sequentially selects the ADC 15 </ b> B of each pixel in the selected row, and the signal processing unit 18.

Like the CMOS image sensor 120, a CMOS image sensor in which the ADC and the pixel region are provided on different semiconductor substrates and the ADC is two-dimensionally arranged for each pixel is, for example, K. Kiyoyama, Y. Ohara, K.-W. Lee, Y. Yang, T. Fukushima, T. Tanaka, and M. Koyanagi, “A parallel ADC for high-speed CMOS image processing system with 3D structure” IEEE International Conference on 3D System Integration, pp. 1--4, Sep. , 2009.

(Configuration example of A / D processing unit)
FIG. 13 is a diagram illustrating a configuration example of the A / D processing unit 141 in FIG.

13, the same components as those in FIG. 2 are denoted by the same reference numerals. The overlapping description will be omitted as appropriate.

As shown in FIG. 13, in the A / D processing unit 141, the ADC 15B is arranged in a matrix corresponding to the pixel group. The ramp line 161 is two-dimensionally (mesh) arranged in a region corresponding to the pixel region 11 and is connected to the contact P of the ramp generation unit 15A. In the example of FIG. 13, the ramp line 161 includes a ramp line 161A provided for each row of the ADC 15B and a ramp line 161B provided for each column. The ramp line 161A may be provided for each of a plurality of rows, and the ramp line 161B may be provided for each of a plurality of columns.

The lamp line 161A and the lamp line 161B exit from the contact point P of the lamp generating unit 15A. A plurality of ADCs 15B in the corresponding row are connected in parallel to the ramp line 161A, and a plurality of ADCs 15B in the corresponding column are connected in parallel to the ramp line 161B.

Current sources

162, 164, and 165 (first current source) are connected to the far ends of the

lamp lines

161A and 161B.

Further, a current source 163 (second current source) is connected to a position between the ADC 15B in the column closest to the lamp generating unit 15A of each lamp line 161A and the contact P.

The A / D processing unit 141 is also provided with a control unit 166. The control unit 166 sets the current value I _ramp of the _ramp signal generating current source 51, similarly to the control unit 63 of FIG. The control unit 166 controls on / off of the operation of the current sources 162 to 165.

The control method of the current source 162, the current source 164, and the current source 165 is the same as the control method of the current source 61, and the control method of the current source 163 is the same as the control method of the current source 62. That is, the current value I _{2 of} the current source 162, the current value I _{1 of} the current source 163, the current value I ₃ of the current source 164, and the current during a predetermined finite period when the ramp signal is generated and returned from the P-phase offset The current value I ₄ of the source 165 changes in the direction of drawing from the lamp line 60 or the direction of flowing in.

As described above, in the CMOS image sensor 120, the ADCs 15B are arranged in a matrix, so that the comparator 31 of the ADC 15B serving as the load of the ramp generation unit 15A spreads two-dimensionally. In addition, since the ADC 15B is provided for each of the one or more pixels 11A, the number of the comparators 31 in the A / D processing unit 141 generally increases by one digit or more as compared with the column processing unit 15.

For example, when 2000 pixels 11A are arranged in the vertical direction and 4000 pixels are arranged in the horizontal direction, the number of comparators 31 in the column processing unit 15 is 4000. On the other hand, when the ADC 15B of the A / D processing unit 141 is provided for each 10 × 10 pixel 11A, the number of the comparators 31 of the A / D processing unit 141 is 80000 (= 200 × 400). This is 20 times that of the column processing unit 15.

Since the number of comparators 31 in the A / D processing unit 141 varies depending on the number of pixels 11A corresponding to one ADC 15B, the number of comparators 31 when provided for each pixel 11A greater than 10 × 10 is Less. However, when the ADC 15B is arranged corresponding not only to the column of the pixel 11A but also to the row, the number of ADCs 15B basically increases as compared with the case where the ADC 15B is arranged corresponding to only the column. The number of 31 also increases.

Even in such a case, since the A / D processing unit 141 is provided with the current sources 162 to 165, the settling time of the ramp signal can be sufficiently shortened.

In the example of FIG. 13, the current sources 162 to 165 are arranged at the four corners of the lamp line 161 arranged two-dimensionally, but the current is at a position far from the contact point P on the lamp line 161A or the lamp line 161B. If a source is provided, the number and position of the current sources are not limited to this. Further, the position of the ramp generator 15A is not limited to the example of FIG.

For example, the lamp generator 15A and the current sources 162 to 165 may be arranged at the center of the lamp line 161A or the lamp line 161B. Further, the current source 162 and the current source 164 may not be provided.

<Third Embodiment>
(Configuration example of one embodiment of imaging device)
FIG. 14 is a block diagram illustrating a configuration example of an embodiment of an imaging apparatus as an electronic apparatus to which the present disclosure is applied.

14 is a video camera, a digital still camera, or the like. The imaging apparatus 1000 includes a lens group 1001, a solid-state imaging device 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus line 1009.

The lens group 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 1002. The solid-state image sensor 1002 includes the CMOS image sensor 10 or the CMOS image sensor 120 described above. The solid-state imaging device 1002 converts the amount of incident light imaged on the imaging surface by the lens group 1001 into an electrical signal in units of pixels and supplies the electrical signal to the DSP circuit 1003 as a pixel signal.

The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state imaging device 1002, supplies the image signal after the image processing to the frame memory 1004 in units of frames, and temporarily stores them.

The display unit 1005 includes, for example, a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on a pixel signal in a frame unit temporarily stored in the frame memory 1004.

The recording unit 1006 includes a DVD (Digital Versatile Disk), a flash memory, and the like, and reads and records pixel signals in units of frames temporarily stored in the frame memory 1004.

The operation unit 1007 issues operation commands for various functions of the imaging apparatus 1000 under operation by the user. The power supply unit 1008 appropriately supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

An electronic device to which the present technology is applied may be a device that uses a CMOS image sensor for an image capturing unit (photoelectric conversion unit). In addition to the imaging device 1000, a portable terminal device having an imaging function, and a CMOS image for an image reading unit. There are copiers that use sensors.

In addition, the effect described in this specification is an illustration to the last, and is not limited, There may exist another effect.

The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present disclosure.

For example, in the first and second embodiments, a mechanism for correcting a difference in settling time due to manufacturing variation may be provided. Further, the ramp generator 15A of the second embodiment may be the ramp generator 15A of FIG. 10 or FIG.

In the first and second embodiments, when the ramp signal is generated, the current value I _ramp may be set to gradually increase from a predetermined value. As a result, the voltage at the contact point P between the ramp signal generating current source 51 and the resistor 52 becomes a voltage having a ramp waveform that gradually increases. In this case, the current value of the current source 61 changes in the direction of flowing into the ramp line 60 when the ramp signal is generated and returned from the P-phase offset.

Further, the present disclosure can have the following configurations.

(1)
A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels;
A ramp generator that generates a ramp signal and outputs the ramp signal to each of the plurality of A / D converters;
A ramp line connected in parallel to each of the plurality of A / D conversion units from the ramp generation unit,
A solid-state imaging device comprising: a first current source capable of being turned on / off connected to a far end of the lamp line from the lamp generating unit.
(2)
The current value of the first current source is determined according to the slew rate of the ramp signal, and is configured to optimize the settling characteristic specific to the lamp line. The solid according to (1) Image sensor.
(3)
The solid-state imaging device according to (1) or (2), further including: a second current source that can be turned on / off at a near end of the ramp line from the ramp generation unit.
(4)
When the voltage of the ramp line transits from a predetermined voltage to another predetermined voltage, either the first current source or the second current source or the first current for a predetermined period only. The solid-state imaging device according to (3), wherein a target current source that is both a source and the second current source is configured to be turned on or off.
(5)
The current value of the target current source is determined according to an ON period of the target current source and a voltage transition amount of the ramp line, and is configured to optimize a settling characteristic unique to the ramp line. (4) The solid-state image sensor as described.
(6)
A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels, a ramp generation unit that generates a ramp signal and outputs it to each of the plurality of A / D conversion units, and the ramp generation unit A ramp line connected in parallel to each of the plurality of A / D converters, and a first current source that can be turned on / off connected to a far end of the ramp line from the ramp generation unit. A control device for controlling the solid-state image sensor,
A control method comprising: turning on or off the first current source only for a predetermined period when the voltage of the ramp line transits from a predetermined voltage to another predetermined voltage.
(7)
A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels;
A ramp generator that generates a ramp signal and outputs the ramp signal to each of the plurality of A / D converters;
A ramp line connected in parallel to each of the plurality of A / D conversion units from the ramp generation unit,
An electronic device comprising: a first current source capable of being turned on / off connected to a far end of the lamp line from the lamp generating unit.

10 CMOS image sensor, 11A pixel, 15A lamp generation unit, 15B ADC, 51 current source for lamp signal generation, 52 resistance, 60 ramp lines, 61 current source, 62 current source, 63 control unit, 81 step power supply, 101 operational amplifier, 121,122 semiconductor substrate, 1000 imaging device

Claims

A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels;
A ramp generator that generates a ramp signal and outputs the ramp signal to each of the plurality of A / D converters;
A ramp line connected in parallel to each of the plurality of A / D conversion units from the ramp generation unit,
A solid-state imaging device comprising: a first current source capable of being turned on / off connected to a far end of the lamp line from the lamp generating unit.
The solid-state imaging according to claim 1, wherein the current value of the first current source is determined in accordance with a slew rate of the ramp signal, and is a value that optimizes a settling characteristic specific to the ramp line. element.
The solid-state imaging device according to claim 1, further comprising a second current source that can be turned on and off at a near end of the ramp line from the ramp generation unit.
When the voltage of the ramp line transits from a predetermined voltage to another predetermined voltage, either the first current source or the second current source or the first current for a predetermined period only. The solid-state imaging device according to claim 3, wherein a target current source that is both a source and the second current source is configured to be turned on or off.
The current value of the target current source is determined according to an ON period of the target current source and a voltage transition amount of the ramp line, and is configured to optimize a settling characteristic specific to the ramp line. Item 5. The solid-state imaging device according to Item 4.
A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels, a ramp generation unit that generates a ramp signal and outputs it to each of the plurality of A / D conversion units, and the ramp generation unit A ramp line connected in parallel to each of the plurality of A / D converters, and a first current source that can be turned on / off connected to a far end of the ramp line from the ramp generation unit. A control device for controlling the solid-state image sensor,
A control method comprising: turning on or off the first current source only for a predetermined period when the voltage of the ramp line transits from a predetermined voltage to another predetermined voltage.
A plurality of A / D conversion units that perform A / D conversion on pixel signals of pixels;
A ramp generator that generates a ramp signal and outputs the ramp signal to each of the plurality of A / D converters;
A ramp line connected in parallel to each of the plurality of A / D conversion units from the ramp generation unit,
An electronic device comprising: a first current source capable of being turned on / off connected to a far end of the lamp line from the lamp generating unit.