WO2016117338A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2016117338A1
WO2016117338A1 PCT/JP2016/000269 JP2016000269W WO2016117338A1 WO 2016117338 A1 WO2016117338 A1 WO 2016117338A1 JP 2016000269 W JP2016000269 W JP 2016000269W WO 2016117338 A1 WO2016117338 A1 WO 2016117338A1
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Prior art keywords
layer
gate
voltage
electrode
gate electrode
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PCT/JP2016/000269
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French (fr)
Japanese (ja)
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剛志 井上
岩村　剛宏
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株式会社デンソー
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present disclosure relates to a semiconductor device in which a semiconductor switching element having an insulated gate structure and a free wheel diode element (hereinafter referred to as an FWD element) are formed on a common semiconductor substrate.
  • a semiconductor switching element having an insulated gate structure and a free wheel diode element hereinafter referred to as an FWD element
  • Patent Document 1 a semiconductor device in which a semiconductor switching element having an insulated gate structure and an FWD element are formed on a common semiconductor substrate has been proposed (see, for example, Patent Document 1).
  • a P-type base layer is formed on the front surface side of the semiconductor substrate constituting the N ⁇ -type drift layer, and a P + -type collector layer and an N + -type are formed on the rear surface side of the semiconductor substrate.
  • the cathode layer is formed.
  • a plurality of trenches reaching the drift layer through the base layer are formed, and a gate electrode is embedded in the trench through a gate insulating film.
  • An N + -type emitter region is formed in the surface layer portion of the base layer so as to be in contact with the trench.
  • a first electrode electrically connected to the base layer and the emitter region is formed on the front surface side of the semiconductor substrate, and a second electrode electrically connected to the collector layer and the cathode layer is formed on the back surface side of the semiconductor substrate. Is formed. As described above, the semiconductor switching element is formed on the semiconductor substrate.
  • an FWD element having a PN junction is formed on the semiconductor substrate by the N-type drift layer and the cathode layer and the P-type base layer.
  • a power conversion device such as an inverter device or a converter device may be configured using a plurality of the semiconductor devices.
  • a gate drive voltage based on a PWM signal generated by a microcomputer or the like is applied to the gate electrode of each semiconductor device, but the gate drive voltage using the PWM signal waveform as it is has a large conduction loss.
  • the gate drive voltage using the PWM signal waveform as it is has a large conduction loss.
  • This disclosure is intended to provide a semiconductor device capable of reducing conduction loss.
  • a semiconductor device includes a semiconductor substrate including a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a surface layer portion of the base layer.
  • a first conductivity type emitter region formed away from the drift layer with the base layer interposed therebetween and having a higher impurity concentration than the drift layer, and a plurality of gates disposed in a surface layer portion of the base layer
  • an inversion layer that connects between the emitter region and the drift layer is formed in a portion of the base layer that is located on the opposite side of the gate electrode with the gate insulating film interposed therebetween.
  • a semiconductor switching element that allows a current to flow between the first electrode and the second electrode and has a PN junction formed by the base layer and the drift layer, and the first electrode and the second electrode
  • a free-wheeling diode element that allows current to flow between the electrodes is provided.
  • An independent gate driving voltage is applied to the plurality of gate electrodes by connecting some of the gate electrodes and the remaining gate electrodes to different gate terminals.
  • the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer.
  • the gate driving voltage at which an inversion layer connecting the emitter region and the drift layer is formed in a portion is defined as a first voltage.
  • the gate driving voltage in which the inversion layer that connects the emitter region and the drift layer is not formed in a part is defined as a second voltage.
  • the semiconductor device described above when the operation of the semiconductor device is unclear, the first voltage is applied to a part of the gate electrodes so that the part in contact with the gate insulating film where the part of the gate electrodes is disposed An inversion layer is formed. Further, when the second voltage is applied to the remaining gate electrode, an inversion layer that connects the emitter region and the drift layer is not formed in a portion in contact with the gate insulating film in which the remaining gate electrode is disposed. For this reason, when the semiconductor device is operating as a semiconductor switching element, the conduction loss of the semiconductor switching element can be reduced by the inversion layer formed along the gate insulating film in which a part of the gate electrode is disposed. When operating as an element, an inversion layer is not formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed, so that conduction loss in the FWD element can be reduced.
  • a semiconductor device in another aspect of the present disclosure, includes a semiconductor substrate including a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a surface layer portion of the base layer.
  • a first conductivity type emitter region that is formed away from the drift layer with the base layer interposed therebetween and has a higher impurity concentration than the drift layer, and a plurality of layers disposed in a surface layer portion of the base layer
  • a conductivity type collector layer ; a first conductivity type cathode layer formed in contact with the drift layer and spaced apart from the base layer, and having a higher impurity concentration than the drift layer; and the base layer Having a first electrode pre said emitter region and electrically connected, and a second electrode connected said collector layer and the said cathode layer and electrically.
  • an inversion layer that connects between the emitter region and the drift layer is formed in a portion of the base layer that is located on the opposite side of the gate electrode with the gate insulating film interposed therebetween.
  • a semiconductor switching element that allows a current to flow between the first electrode and the second electrode, and has a PN junction formed by the base layer and the drift layer, and the first electrode and the second electrode
  • a free-wheeling diode element that allows current to flow between the electrodes.
  • An independent gate driving voltage is applied to the plurality of gate electrodes by connecting some of the gate electrodes and the remaining gate electrodes to different gate terminals.
  • the threshold voltage of the insulated gate structure having the partial gate electrode is different from the threshold voltage of the insulated gate structure having the remaining gate electrode.
  • the emitter region and the part of the base layer in contact with the gate insulating film where the part of the gate electrode is disposed An inversion layer that connects the drift layer is formed, and a portion of the base layer that is in contact with the gate insulating film where the remaining gate electrode is disposed extends from the drift layer side to an intermediate position toward the emitter region.
  • the gate driving voltage for forming the inversion layer is defined as a first voltage.
  • the gate drive voltage in which the inversion layer that connects the emitter region and the drift layer is not formed in a part is defined as a second voltage.
  • the first voltage is applied to a part of the gate electrodes, and the gate insulating film on which the part of the gate electrodes is disposed
  • the inversion layer is formed in the contact portion, and the inversion layer is not formed in the portion in contact with the gate insulating film in which the remaining gate electrode is disposed by applying the second voltage to the remaining gate electrode.
  • the inversion layer When operating as an element, the inversion layer is not formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed, so that the conduction loss of the FWD element can be reduced.
  • an inversion layer is formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed from the drift layer side to a midway position toward the emitter region. For this reason, when the semiconductor device is operating as a semiconductor switching element, the conduction loss of the semiconductor switching element can be reduced as compared with the case where the second voltage is applied to the remaining gate electrode.
  • the semiconductor device operates as an FWD element
  • an inversion layer that connects the emitter region and the drift layer is formed along the gate insulating film in which the remaining gate electrode is disposed on the remaining gate electrode. Compared with the case where a voltage is applied, the conduction loss of the FWD element can be reduced.
  • FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 2 is a circuit diagram when a power conversion device is configured using the semiconductor device shown in FIG.
  • FIG. 3A is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an IGBT element.
  • FIG. 3B is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an FWD element.
  • FIG. 3C is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the operation of the semiconductor device is unknown.
  • FIG. 3A is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an IGBT element.
  • FIG. 3B is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an FWD element.
  • FIG. 3C is a timing chart showing gate drive voltages applied to the first and second
  • FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 5A is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an FWD element.
  • FIG. 5B is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the operation of the semiconductor device is unknown.
  • the semiconductor device 1 of the present embodiment includes a so-called reverse conducting IGBT (RC-IGBT) having an IGBT element 2 and an FWD element 3 as semiconductor switching elements.
  • the FWD element 3 is formed on an N ⁇ -type common semiconductor substrate 10 that functions as the drift layer 11.
  • a P-type base layer 12 is formed on the drift layer 11 (on the one surface 10a side of the semiconductor substrate 10).
  • a plurality of trenches 13 a and 13 b are formed so as to penetrate the base layer 12 and reach the drift layer 11, and the base layer 12 is separated into a plurality by the trenches 13 a and 13 b.
  • the trenches 13a and 13b are formed at equal intervals along one direction (the depth direction in the drawing in FIG. 2) of the surface directions of the one surface 10a of the semiconductor substrate 10. Further, one surface 10 a of the semiconductor substrate 10 is configured by one surface of the base layer 12 opposite to the drift layer 11.
  • a gate insulating film 14 formed so as to cover the wall surfaces of the respective trenches 13a and 13b, and a gate electrode 15a formed of polysilicon or the like formed on the gate insulating film 14 , 15b.
  • a trench gate structure is configured.
  • the gate electrodes 15a and 15b formed in the trenches 13a and 13b are connected to gate terminals G1 and G2 in which a part of the gate electrodes 15a and the remaining gate electrode 15b are different. . That is, different gate drive voltages are applied to some of the gate electrodes 15a and the remaining gate electrodes 15b.
  • a part of the gate electrodes is referred to as a first gate electrode 15a
  • the remaining gate electrode is referred to as a second gate electrode 15b
  • a trench in which the first gate electrode 15a is disposed is referred to as a first trench 13a and a second gate electrode.
  • the trench in which the gate electrode 15b is disposed will be described as the second trench 13b.
  • first trench 13a and the second trench 13b are perpendicular to the extending direction of the first and second trenches 13a and 13b (FIG. 1).
  • Two second trenches 13b are formed between the first trenches 13a in the left-right direction of the middle sheet).
  • an N + -type emitter region 16 and a P + -type contact region 17 sandwiched between the emitter regions 16 are formed.
  • the emitter region 16 is configured to have a higher impurity concentration than the drift layer 11, is terminated in the base layer 12, and is in contact with the side surfaces of the first and second trenches 13a and 13b.
  • the contact region 17 has a higher impurity concentration than the base layer 12, and is formed so as to terminate in the base layer 12, similarly to the emitter region 16.
  • the emitter region 16 is formed on the side surfaces of the first and second trenches 13a and 13b along the longitudinal direction of the first and second trenches 13a and 13b in the region between the first and second trenches 13a and 13b. It extends in the shape of a rod so as to be in contact with the first and second trenches 13a and 13b, and terminates inside the tip.
  • the contact region 17 is sandwiched between the two emitter regions 16 and extends in a rod shape along the longitudinal direction of the first and second trenches 13a and 13b (that is, the emitter region 16). In the present embodiment, the contact region 17 is formed deeper than the emitter region 16 with respect to the one surface 10a of the semiconductor substrate 10.
  • an interlayer insulating film 18 made of BPSG or the like is formed on the base layer 12 (one surface 10a of the semiconductor substrate 10).
  • a contact hole 18 a is formed in the interlayer insulating film 18 to expose a part of the emitter region 16 and the contact region 17.
  • a first electrode 19 is formed on the interlayer insulating film 18.
  • the first electrode 19 is electrically connected to the emitter region 16 and the contact region 17 through the contact hole 18a. That is, the first electrode 19 functions as an emitter electrode in the IGBT element 2 and also functions as an anode element in the FWD element 3.
  • a P-type collector layer 20 and an N-type cathode layer 21 are formed on the drift layer 11 opposite to the base layer 12 side (the other surface 10b side of the semiconductor substrate 10). That is, the IGBT element 2 and the FWD element 3 are basically partitioned depending on whether the layer formed on the other surface 10 b side of the semiconductor substrate 10 is the collector layer 20 or the cathode layer 21.
  • a second electrode 22 is formed on the collector layer 20 and the cathode layer 21 (the other surface 10b of the semiconductor substrate 10).
  • the second electrode 22 functions as a collector electrode in the IGBT element 2 and functions as a cathode electrode in the FWD element 3.
  • the FWD element 3 having a PN junction with the base layer 12 and the contact region 17 as an anode and the drift layer 11 and the cathode layer 21 as a cathode is configured as described above.
  • the N type, the N + type, and the N ⁇ type correspond to the first conductivity type of the present disclosure
  • the P type and the P + type correspond to the second conductivity type of the present disclosure.
  • the semiconductor device 1 is applied to a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor or the like to boost and step down a DC voltage
  • a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor or the like to boost and step down a DC voltage
  • the power conversion apparatus includes a high-potential-side DC power supply line 31 and a low-potential-side DC power supply line (ground) 32.
  • the semiconductor devices 1A and 1B are connected in series with an output terminal Nt connected to a load between the high potential side DC power supply line 31 and the low potential side DC power supply line 32 so as to constitute a half-bridge circuit. Is arranged.
  • the semiconductor devices 1A and 1B are both the semiconductor device 1 shown in FIG. 1 described above.
  • the semiconductor device 1A basically has the above-described configuration, but the semiconductor device 1A includes the main element Ma having the IGBT element 2aM and the FWD element 3aM, and the IGBT element 2aS and the FWD element 3aS. In addition, a sense element Sa is formed which passes a minute current proportional to the current flowing through the main element Ma.
  • the semiconductor device 1B basically has the above-described configuration, but the semiconductor device 1B includes the main element Mb having the IGBT element 2bM and the FWD element 3bM, and the IGBT element 2bS and the FWD element 3bS.
  • a sense element Sb that allows a minute current proportional to the current flowing in the main element Mb to be formed is formed.
  • the gate drive voltages VGH1, VGH2, VGL1, and VGL2 are applied to the first and second gate electrodes 15a and 15b in the semiconductor devices 1A and 1B, respectively.
  • Sense resistors 4a and 4b are connected between the terminals S1 and S2 connected to the main elements Ma and Mb and the sense elements Sa and Sb in the semiconductor devices 1A and 1B, respectively.
  • the sense resistors 4a and 4b constitute a current detection device together with current detection units 45a and 45b described later.
  • the power conversion device includes a microcomputer 41.
  • the microcomputer 41 includes a PWM signal generation unit 42 that generates PWM signals FH and FL on the high side and low side of the half bridge circuit, a storage device (not shown), peripheral devices, and the like.
  • the PWM signals FH and FL are input to the drive ICs 44a and 44b via the photocouplers 43a and 43b, respectively.
  • the drive IC 44a includes a current detection unit 45a, a gate voltage control unit 46a, a first drive circuit 47a, and a second drive circuit 48a, and operates by being supplied with a power supply voltage VDDA (for example, 15V).
  • the drive IC 44b includes a current detection unit 45b, a gate voltage control unit 46b, a first drive circuit 47b, and a second drive circuit 48b, and operates when a power supply voltage VDDB (for example, 15 V) is supplied. It has a configuration.
  • the drive ICs 44a and 44b are provided separately for the high-side semiconductor device 1A and the low-side semiconductor device 1B, respectively. Therefore, the drive ICs 44a and 44b only need to have a withstand voltage corresponding to the power supply voltages VDDA and VDDB (that is, withstand voltage according to the gate drive voltage).
  • the current detection unit 45b detects the magnitude and polarity of the current flowing through the semiconductor device 1B based on the sense voltage VSL generated in the sense resistor 4b, and outputs the detection result to the gate voltage control unit 46b.
  • the gate voltage control unit 46b determines the state of the semiconductor device 1B based on the detection result input from the current detection unit 45b and a threshold current Is described later. Specifically, the gate voltage control unit 46b is configured so that the semiconductor device 1B operates as (a) the IGBT element 2, (b) operates as the FWD element 3, and (c) the IGBT element 2 and the FWD element. It is determined which of the three operations is unknown or in which state.
  • the first gate drive signal VGL1 to be applied to the first gate electrode 15a through the first drive circuit 47b is generated, and the second gate through the second drive circuit 48b.
  • a second gate drive signal VGL2 to be applied to the electrode 15b is generated.
  • the gate voltage control unit 46b is configured to generate a plurality of gate drive voltages VGL1 and VGL2 according to the state of the semiconductor device 1B.
  • the present embodiment is configured to generate four types of second gate drive voltages VGL2.
  • the operation of the semiconductor device 1B is unclear when the current flowing through the semiconductor device 1B is very small and the detection result detected by the current detection unit 45b is smaller than the current threshold Is, for example, the semiconductor device Occurs when switching between 1A and semiconductor device 1B is switched.
  • a threshold setting circuit 49b is externally attached to the drive IC 44b.
  • This threshold value setting circuit 49b is configured with a floating potential equal to the emitter potential of the semiconductor device 1B (the ground potential because the semiconductor device 1B is on the low potential side) as a reference potential, and is defined by dividing the voltage VDDB with resistors R1 and R2. A voltage Vml is generated. Then, the gate voltage control unit 46b determines the threshold current Is when compared with the current flowing through the semiconductor device 1B using the specified voltage Vm1.
  • a switching signal Sk is input to the drive IC 44b (gate voltage control unit 46b).
  • the gate voltage control unit 46b is configured to generate a plurality of gate drive voltages VGL1 and VGL2 according to the state of the semiconductor device 1B as described above. It is possible to determine whether to generate (apply) a gate drive voltage.
  • the configuration of the drive IC 44a is the same as that of the drive IC 44b.
  • the first and second gate drive voltages VGL1 and VGL2 applied to the first and second gate electrodes 15a and 15b of the semiconductor device 1B are shown in FIGS. This will be described with reference to 3C.
  • the gate voltage control unit 46b determines that (a) the semiconductor device 1B operates as the IGBT element 2, it determines that (b) the semiconductor device 1B operates as the FWD element 3.
  • the first and second gate drive voltages VGH1 and VGH2 applied to the high-side semiconductor device 1A are basically the same as the first and second gate drive voltages VGL1 and VGL2 applied to the low-side semiconductor device 1B. Is the same.
  • the waveform of the gate drive voltage VGL1 is the same as that of the PWM signal FL.
  • the high-level gate driving voltage is such that an inversion layer that connects the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 that is in contact with the first and second trenches 13a and 13b. Voltage.
  • the low-level gate drive voltage is a voltage at which an inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in a portion of the base layer 12 in contact with the first and second trenches 13a and 13b. Yes, in this embodiment, it is set to 0V.
  • the high-level gate drive voltage corresponds to the first voltage of the present disclosure
  • the low-level gate drive voltage corresponds to the second voltage of the present disclosure.
  • the low level voltage is assumed to be 0 V. However, the low level voltage is applied to the emitter region 16 and the drift layer 11 in the portion of the base layer 12 that is in contact with the first and second trenches 13a and 13b. Any voltage may be used as long as the inversion layer connecting the two is not formed. That is, any voltage lower than the threshold voltage Vth of the insulated gate structure having the first and second gate electrodes 15a and 15b may be used.
  • one of the second gate drive voltages VGL2a and VGL2b is applied to the second gate electrode 15b according to the switching signal Sk.
  • the second gate drive voltage VGL2a is a signal having the same waveform as the first gate drive voltage VGL1a.
  • the second gate drive voltage VGL2b is a signal that is at a high level from time T1 before time T2 and is a negative voltage from time T1 to time T3.
  • the first and second gates One of the first and second gate drive voltages VGL1a, VGL1b, VGL2a, and VGL2b is applied to the electrodes 15a and 15b in accordance with the switching signal Sk.
  • the first and second gate drive voltages VGL1a and VGL2a are low level signals.
  • the first and second gate drive voltages VGL1b and VGL2b are signals that are at a low level from time T4 to a high level from time T4 to time T5.
  • the time point T4 is a time point before the recovery current starts to flow through the semiconductor device 1B.
  • any one of the first and second gate drive voltages VGL1a, VGL1b, VGL2a, and VGL2b is applied to the first and second gate electrodes 15a and 15b, an inversion layer is not formed in the base layer 12.
  • An increase in the forward voltage of the FWD element 3 can be suppressed, and conduction loss in the FWD element 3 can be reduced.
  • first and second gate drive voltages VGL1b and VGL2b are applied to the first and second gate electrodes 15a and 15b, an inversion layer is formed in the base layer 12, thereby causing the FWD from the time T4 to the time T5. Holes accumulated in the element 3 can be reduced. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
  • the same gate drive voltage is applied to the first and second gate electrodes 15a and 15b.
  • the first gate drive voltage VGL1a is applied to the first gate electrode 15a
  • the second The second gate drive voltage VGL2b may be applied to the gate electrode 15b.
  • one of the second gate drive voltages VGL2a to VGL2d is input to the second gate electrode 15b according to the switching signal Sk.
  • the gate drive voltage VGL2a is a low level signal.
  • the gate drive voltage VGL2b is a low level until time T6, and is a negative voltage from time T6 to time T8 before the gate drive signal VGL1 falls to low level at time T7.
  • the gate drive voltage VGL2c is a signal that is at a low level from time T9 and is at a high level from time T9 to time T10. Note that time T9 is a time before the recovery current starts flowing when the semiconductor device 1B operates as the FWD element 3.
  • the gate drive voltage VGL2d is a combination of the gate drive voltage VGL2b and the gate drive voltage VGL2c.
  • the recovery loss can be reduced, and the semiconductor device 1B operates as the IGBT element 2. In this case, the switching loss can be reduced.
  • the first gate electrode 15a and the second gate electrode 15b are provided, and independent gate drive voltages VGL1 and VGL2 are applied to the first and second gate electrodes 15a and 15b. I have to.
  • a high level gate drive voltage VGL1 is applied to the first gate electrode 15a, and a low level gate drive voltage VGL2 is applied to the second gate electrode 15b.
  • the first gate drive voltage VGL1 which is a high level signal is applied to the first gate electrode 15a, whereby the first gate electrode 15a has a first level. Since the inversion layer is formed in the vicinity of the gate electrode 15a, the conduction loss in the IGBT element 2 can be reduced.
  • the second gate drive voltage VGL2 that is at a low level is applied to the second gate electrode 15b, whereby the second gate electrode 15b in the base layer 12 is applied. Since no inversion layer is formed in the vicinity, the conduction loss in the FWD element 3 can be reduced.
  • the second gate electrode 15b when the operation of the semiconductor device 1 is unknown, the second gate electrode 15b has a gate drive voltage VGL2b that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level.
  • VGL2d can also be applied (see FIG. 3C). For this reason, when the gate drive voltages VGL2b and VGL2d are applied, a part of holes accumulated in the drift layer 11 can be extracted in advance through the accumulation layer, and switching loss can be reduced.
  • the second gate electrode 15b has a gate drive signal that is at a high level from the point before the recovery current starts flowing when the semiconductor device 1 operates as the FWD element 3.
  • VGL2c and VGL2d can also be applied (see FIG. 3C). For this reason, when the gate drive signals VGL2c and VGL2d are applied, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
  • the second gate electrode 15b has a gate drive voltage VGL2b that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level. It can be applied (see FIG. 3A). For this reason, when the gate drive voltage VGL2b is applied, the switching loss can be reduced.
  • the gate drive signal VGL2b that is at a high level from the time before the recovery current starts flowing can be applied to the second gate electrode 15b. (See FIG. 3B). For this reason, when the gate drive signal VGL2b is applied, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
  • the depth of the emitter region 16 in contact with the first trench 13a is made deeper than the depth of the emitter region 16 in contact with the second trench 13b.
  • the semiconductor device 1 of the present embodiment since a current flows in the thickness direction of the semiconductor substrate 10, the length between the emitter region 16 and the drift layer 11 along the current flow direction in the base layer 12.
  • the portion located on the opposite side of the first gate electrode 15a with the gate insulating film 14 interposed therebetween is shorter than the portion located on the opposite side of the second gate electrode 15b with the gate insulating film 14 interposed therebetween. That is, each emitter region 16 is formed so that the peak concentration positions of the emitter region 16 in contact with the first trench 13a and the emitter region 16 in contact with the second trench 13b are different.
  • the threshold voltage Vth of the gate insulating structure having the first gate electrode 15a is different from the threshold voltage Vth of the gate insulating structure having the second gate electrode 15b.
  • the threshold voltage Vth of the insulated gate structure having the second gate electrode 15b is The threshold voltage Vth of the insulated gate structure having one gate electrode 15a is set higher.
  • the threshold voltage Vth of the insulated gate structure in this embodiment forms an inversion layer that connects the emitter region 16 and the drift layer 11 when a gate drive voltage is applied to the first and second gate electrodes 15a and 15b. This is the minimum voltage required to
  • the above is the configuration of the semiconductor device 1 in the present embodiment.
  • the first and second gate drive voltages VGL1 and VGL2 applied to the gate electrodes 15a and 15b of the semiconductor device 1B on the low side when such a semiconductor device 1 is applied to the power conversion device of FIG. This will be described with reference to FIGS. 3A, 5A, and 5B.
  • the gate voltage control unit 46b determines that (a) the semiconductor device 1B operates as the IGBT element 2, it determines that (b) the semiconductor device 1B operates as the FWD element 3.
  • the first and second gate drive voltages VGH1 and VGH2 applied to the high-side semiconductor device 1A are basically the same as the first and second gate drive voltages VGL1 and VGL2 applied to the low-side semiconductor device 1B. Is the same.
  • the threshold voltage Vth of the insulated gate structure having the second gate electrode 15b is higher than the threshold voltage Vth of the insulated gate structure having the first gate electrode 15a.
  • the high-level gate drive voltage is applied to the first and second gate electrodes 15a and 15b, and the emitter region 16 is only applied to the portion of the base layer 12 that is in contact with the first trench 13a.
  • an inversion layer that connects the drift layer 11 is formed, and the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in a portion in contact with the second trench 13b.
  • the inversion layer that does not connect the emitter region 16 and the drift layer 11 to the portion of the base layer 12 in contact with the second trench 13b. is formed. More specifically, an inversion layer is formed from the portion on the drift layer 11 side in the portion in contact with the second trench 13 b in the base layer 12 to the middle position toward the emitter region 16. For this reason, since the second gate drive voltages VGL2a and VGL2b are applied to the second gate electrode 15b, an inversion layer is formed in the portion on the drift layer 11 side in the portion in contact with the second trench 13b.
  • the conduction loss in the IGBT element 2 can be reduced by applying a high level signal also to the second gate electrode 15b.
  • the first and second gate drive voltages VGL1a and VGL2a are signals that are at a high level until time T11 and are at a low level from time T11, and the semiconductor device 1B operates as the IGBT element 2.
  • This signal is similar to the first gate drive voltage VGL1 applied to the first gate electrode 15a. That is, the waveforms of the first and second gate drive voltages VGL1a and VGL2a in FIG. 5A are the same as that of the PWM signal FL.
  • the emitter region 16 is formed in a portion of the base layer 12 in contact with the first trench 13a.
  • the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in the portion in contact with the second trench 13b. Therefore, a gate driving voltage is applied to the first and second gate electrodes 15a and 15b so that an inversion layer connecting the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 in contact with the first trench 13a.
  • the conduction loss in the FWD element 3 can be reduced.
  • the waveforms of the first and second gate drive voltages VGL1a and VGL2a are the same as that of the PWM signal FL, the control of the gate voltage control unit 46b can be simplified.
  • the first and second gate drive voltages VGL1b and VGL2b are low level signals.
  • the first and second gate drive voltages VGL1c and VGL2c are low level signals until time T12.
  • the first gate drive voltage VGL1c is a signal that is at a high level from time T12 to time T13
  • the second gate drive voltage VGL2c is a signal that is at a high level from time T12 to time T14.
  • the time point T12 is a time point before the recovery current starts to flow through the semiconductor device 1B. The reason why the first gate drive voltage VGL1c becomes high level at time T13 before time T14 after it becomes high level from time T12 is to suppress a short circuit.
  • the first and second gate drive voltages VGL1b, VGL2b, VGL1c, and VGL2c are applied to the first and second gate electrodes 15a and 15b, an inversion layer is not formed in the base layer 12, so that the FWD element 3 As a result, the forward voltage can be suppressed from increasing, and the conduction loss of the FWD element 3 can be reduced.
  • first and second gate drive voltages VGL1c and VGL2c are applied to the first and second gate electrodes 15a and 15b.
  • the second gate drive voltage VGL2c is applied to the second gate electrode 15b. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
  • the period from time T12 to time T14 in FIG. 5A is longer than the period from time T4 to time T5 in FIG. 3B.
  • the inversion layer connects the emitter region 16 and the drift layer 11 to the portion of the base layer 12 in contact with the second trench 13b even when the second gate drive voltage VGL2c of high level is applied to the second gate electrode 15b.
  • VGL2c of high level is applied to the second gate electrode 15b.
  • a high level signal can be applied for a long time before the recovery current starts to flow, and the recovery loss can be further reduced.
  • the first and second gate drive voltages VGL1d and VGL2d are combinations of the first and second gate drive voltages VGL1a and VGL2a and the first and second gate drive voltages VGL1c and 2c. For this reason, the recovery loss can be reduced while reducing the conduction loss in the FWD element 3.
  • the first and second gate drive voltages VGL1d and VGL2d are low in the period from the time T11 to the time T12, but are set to the high level in the period from the time T11 to the time T12. It may be.
  • the same gate drive voltage is applied to the first and second gate electrodes 15a and 15b.
  • the first gate drive voltage VGL1a is applied to the first gate electrode 15a
  • the second The second gate drive voltage VGL2b may be applied to the gate electrode 15b.
  • one of the second gate drive voltages VGL2a to VGL2h is input to the second gate electrode 15b according to the switching signal Sk.
  • the second gate drive voltage VGL2a is the same signal as the first gate drive voltage VGL1a.
  • the second gate drive voltage VGL2b is a signal that is at a high level until time T14 and is a negative voltage from time T14 to time T16 before the gate drive signal VGL1 falls to a low level at time T15.
  • the gate drive voltage VGL2c is a signal that is at a high level from time T15, and is at a high level from time T17 to time T18 after falling to a low level at time T15.
  • the time T17 is a time before the recovery current starts flowing when the semiconductor device 1B operates as the FWD element 3.
  • the semiconductor device 1B when the second gate drive voltages VGL2a to VGL2c are applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, the second of the base layers 12 Since the inversion layer is also formed in the portion in contact with the trench 13b, the conduction loss in the IGBT element 2 can be reduced. Further, when the semiconductor device 1B operates as the FWD element 3, an inversion layer that does not connect the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 that is in contact with the second trench 13b. The conduction loss in the FWD element 3 can be reduced as compared with the case where a gate drive voltage for forming an inversion layer connecting the emitter region 16 and the drift layer 11 is applied to the second gate electrode 15b.
  • the semiconductor device 1B when the second gate drive voltage VGL2c is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, it is accumulated in the drift layer 11 from time T14 to time T16. Since some of the holes can be extracted in advance through the storage layer, switching loss can be reduced.
  • the semiconductor device 1B When the second gate drive voltage VGL2c is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the FWD element 3, it is accumulated in the FWD element 3 from time T17 to time T18. Can reduce the number of holes. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
  • the gate drive voltage VGL2d is a combination of the gate drive voltage VGL2c and the gate drive voltage VGL2d. For this reason, when the gate drive voltage VGL2d is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, the conduction loss and the recovery loss of the FWD element 3 can be reduced. When 1B is operating as the IGBT element 2, switching loss can be reduced.
  • the gate drive voltage VGL2e is a low level signal.
  • the gate drive voltage VGL2f is a low level gate drive signal until time T14, and is a signal that becomes a negative voltage from time T14 to time T16 before the gate drive signal VGL1 falls to low level at time T15.
  • the gate drive voltage VGL2g is a signal that is at a low level from time T17 and is at a high level from time T17 to time T18.
  • the gate drive voltages VGL2e to VGL2g are applied to the second gate electrode 15b, if the semiconductor device 1B is operating as the FWD element 3, the second trench 13b in the base layer 12 is used. Since the inversion layer is not formed in the portion in contact with the FWD element 3, the conduction loss in the FWD element 3 can be reduced.
  • the semiconductor device 1B when the second gate drive voltage VGL2f is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, it is accumulated in the drift layer 11 from time T14 to time T16. Since some of the holes can be extracted in advance through the storage layer, switching loss can be reduced.
  • the semiconductor device 1B When the second gate drive voltage VGL2g is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the FWD element 3, it is accumulated in the FWD element 3 from time T17 to time T18. Can reduce the number of holes. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
  • the gate drive voltage VGL2h is a combination of the gate drive voltage VGL2f and the gate drive voltage VGL2g. Therefore, when the gate drive voltage VGL2h is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, the conduction loss and the recovery loss of the FWD element 3 can be reduced, and the semiconductor device When 1B is operating as the IGBT element 2, switching loss can be reduced.
  • the threshold voltage Vt of the insulated gate structure having the second gate electrode 15b is set higher than the threshold voltage Vt of the insulated gate structure having the first gate electrode 15a.
  • a high level voltage is applied to the first and second gate electrodes 15a and 15b, an inversion layer that connects the emitter region 16 and the drift layer 11 to a portion of the base layer 12 that is in contact with the first trench 13a.
  • the inversion layer is formed in a portion of the base layer 12 that is in contact with the second trench 13 b from the drift layer 11 side to the middle of the emitter region 16.
  • the semiconductor device 1 becomes the IGBT element 2.
  • the conduction loss in the IGBT element 2 can be reduced.
  • the semiconductor device 1 operates as the FWD element 3, compared with a case where a gate driving voltage is applied to form an inversion layer that connects the emitter region 16 and the drift layer 11 to the second gate electrode 15 b.
  • the conduction loss of the FWD element 3 can be reduced.
  • the semiconductor device 1 When the operation of the semiconductor device 1 is unknown, when the low-level gate drive voltages VGL2e to 2h are applied to the second gate electrode 15b (see FIG. 5B), the semiconductor device 1 operates as the FWD element 3. Can further reduce the conduction loss in the FWD element 3.
  • the second gate electrode 15b has a gate drive voltage that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level.
  • VGL2b, VGL2d, VGL2f, and VGL2h can be applied (see FIG. 5B).
  • the gate drive voltages VGL2b, VGL2d, VGL2f, and VGL2h are applied to the second gate electrode 15b, a part of the holes accumulated in the drift layer 11 is passed through the accumulation layer in advance. Can be pulled out and switching loss can be reduced.
  • the second gate electrode 15b has a gate drive signal that is at a high level from the point before the recovery current starts flowing when the semiconductor device 1 operates as the FWD element 3.
  • VGL2c, VGL2d, VGL2g, and VGL2h can be applied (see FIG. 5B). Therefore, when the gate drive signals VGL2c, VGL2d, VGL2g, and VGL2h are applied to the second gate electrode 15b, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
  • the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed even when a high level signal is applied to the second gate electrode 15b, the high level period can be extended. For this reason, recovery loss can be further reduced.
  • the first conductivity type is N type and the second conductivity type is P type.
  • the first conductivity type is P type
  • the second conductivity type is N type. You can also.
  • the first trench 13a and the second trench 13b are perpendicular to the extending direction of the first and second trenches 13a and 13b (see FIG.
  • the first and second gate electrodes 15a and 15b are arranged in such a manner that the two second trenches 13b are arranged between the first trenches 13a. The manner can be changed as appropriate.
  • the semiconductor device 1 that flows current in the thickness direction of the semiconductor substrate 10 has been described as an example.
  • the present disclosure is applied to the semiconductor device 1 that flows current in the plane direction of the semiconductor substrate 10.
  • the first and second gate electrodes 15a and 15b are not arranged in the first and second trenches 13a and 13b, but are formed on a so-called planar type semiconductor device 1B arranged on the one surface 10a of the semiconductor substrate 10. The disclosure can also be applied.
  • the structure for making the threshold voltage of the gate insulating structure having the first gate electrode 15a different from the threshold voltage of the gate insulating structure having the second gate electrode 15b can be changed as appropriate.
  • the gradient of the impurity concentration is made in the base layer 12, and the impurity concentration of the portion in contact with the second trench 13b in the base layer 12 is higher than the impurity concentration of the portion in contact with the first trench 13a. It may be made to become.

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Abstract

A semiconductor device, having a semiconductor substrate (10) that includes a drift layer (11), a base layer (12) on the drift layer, an emitter region (16) on the surface layer part of the base layer, a plurality of gate electrodes (15a, 15b) on the surface layer part of the base layer with a plurality of gate insulation films (14) interposed therebetween, a cathode layer (21) and a collector layer (20) in contact with the drift layer, a first electrode (19) connected to the base layer and the emitter region, and a second electrode (22) connected to the collector layer and the cathode layer. The gate driving voltage at which an inversion layer is formed is defined as a first voltage, and the gate driving voltage at which no inversion layer is formed is defined as a second voltage. When it is not possible to distinguish between a semiconductor switching element and an FWD operation on the basis of the current flowing in the semiconductor substrate, the first voltage is applied to some of the gate electrodes and the second voltage is applied to the remainder of the gate electrodes.

Description

半導体装置Semiconductor device 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１５年１月２１日に出願された日本特許出願番号２０１５－９６５２号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese Patent Application No. 2015-9652 filed on January 21, 2015, the contents of which are incorporated herein by reference.
　本開示は、絶縁ゲート構造を有する半導体スイッチング素子とフリーホイールダイオード素子（以下、ＦＷＤ素子という）とが共通の半導体基板に形成された半導体装置に関するものである。 The present disclosure relates to a semiconductor device in which a semiconductor switching element having an insulated gate structure and a free wheel diode element (hereinafter referred to as an FWD element) are formed on a common semiconductor substrate.
　従来より、絶縁ゲート構造を有する半導体スイッチング素子とＦＷＤ素子とが共通の半導体基板に形成された半導体装置が提案されている（例えば、特許文献１参照）。 Conventionally, a semiconductor device in which a semiconductor switching element having an insulated gate structure and an FWD element are formed on a common semiconductor substrate has been proposed (see, for example, Patent Document 1).
　具体的には、この半導体装置では、Ｎ－型のドリフト層を構成する半導体基板の表面側にＰ型のベース層が形成され、半導体基板の裏面側にＰ＋型のコレクタ層およびＮ＋型のカソード層が形成されている。そして、ベース層を貫通してドリフト層に達する複数のトレンチが形成され、トレンチ内には、ゲート絶縁膜を介してゲート電極が埋め込まれている。また、ベース層の表層部には、トレンチと接するようにＮ＋型のエミッタ領域が形成されている。さらに、半導体基板の表面側にはベース層およびエミッタ領域と電気的に接続される第１電極が形成され、半導体基板の裏面側にはコレクタ層およびカソード層と電気的に接続される第２電極が形成されている。以上のようにして、半導体基板に半導体スイッチング素子が形成されている。 Specifically, in this semiconductor device, a P-type base layer is formed on the front surface side of the semiconductor substrate constituting the N − -type drift layer, and a P + -type collector layer and an N + -type are formed on the rear surface side of the semiconductor substrate. The cathode layer is formed. A plurality of trenches reaching the drift layer through the base layer are formed, and a gate electrode is embedded in the trench through a gate insulating film. An N + -type emitter region is formed in the surface layer portion of the base layer so as to be in contact with the trench. Further, a first electrode electrically connected to the base layer and the emitter region is formed on the front surface side of the semiconductor substrate, and a second electrode electrically connected to the collector layer and the cathode layer is formed on the back surface side of the semiconductor substrate. Is formed. As described above, the semiconductor switching element is formed on the semiconductor substrate.
　また、このような構成とされていることにより、半導体基板には、Ｎ型のドリフト層およびカソード層とＰ型のベース層とによってＰＮ接合を有するＦＷＤ素子が形成されている。 Also, with such a configuration, an FWD element having a PN junction is formed on the semiconductor substrate by the N-type drift layer and the cathode layer and the P-type base layer.
　ところで、上記半導体装置を複数用いてインバータ装置やコンバータ装置等の電力変換装置を構成することがある。この場合、通常、各半導体装置のゲート電極には、マイコン等で生成されたＰＷＭ信号に基づいたゲート駆動電圧が印加されるが、ＰＷＭ信号の波形をそのまま用いたゲート駆動電圧では導通損失が大きくなる場合がある。 Incidentally, a power conversion device such as an inverter device or a converter device may be configured using a plurality of the semiconductor devices. In this case, normally, a gate drive voltage based on a PWM signal generated by a microcomputer or the like is applied to the gate electrode of each semiconductor device, but the gate drive voltage using the PWM signal waveform as it is has a large conduction loss. There is a case.
特開２０１１－１４６５５５号公報JP2011-146555A
　本開示は、導通損失を低減できる半導体装置を提供することを目的とする。 This disclosure is intended to provide a semiconductor device capable of reducing conduction loss.
　本開示のある態様において、半導体装置は、第１導電型のドリフト層を含む半導体基板と、前記ドリフト層上に形成された第２導電型のベース層と、前記ベース層の表層部であって、前記ベース層を挟んで前記ドリフト層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のエミッタ領域と、前記ベース層の表層部に配置された複数のゲート絶縁膜と、前記ゲート絶縁膜上に配置された複数のゲート電極と、前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第２導電型のコレクタ層と、前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のカソード層と、前記ベース層および前記エミッタ領域と電気的に接続される第１電極と、前記コレクタ層および前記カソード層と電気的に接続される第２電極と、を有する。半導体装置は、前記ベース層のうち、前記ゲート絶縁膜を挟んで前記ゲート電極と反対側に位置する部分に前記エミッタ領域と前記ドリフト層との間を繋ぐ反転層を形成し、当該反転層を介して前記第１電極と前記第２電極との間に電流を流す半導体スイッチング素子を備えていると共に、前記ベース層と前記ドリフト層とによるＰＮ接合を有し、前記第１電極と前記第２電極との間に電流を流すフリーホイールダイオード素子を備えている。前記複数のゲート電極は、一部のゲート電極と残部のゲート電極とが異なるゲート端子に接続されることによって独立したゲート駆動電圧が印加されるようになっている。前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成される前記ゲート駆動電圧を第１電圧と定義する。前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されない前記ゲート駆動電圧を第２電圧と定義する。前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記一部のゲート電極には前記第１電圧が印加され、前記残部のゲート電極には前記第２電圧が印加される。 In one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate including a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a surface layer portion of the base layer. A first conductivity type emitter region formed away from the drift layer with the base layer interposed therebetween and having a higher impurity concentration than the drift layer, and a plurality of gates disposed in a surface layer portion of the base layer An insulating film, a plurality of gate electrodes disposed on the gate insulating film, and a second conductivity formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer A collector layer of a type, a cathode layer of a first conductivity type formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer; and the base layer Having a first electrode pre said emitter region and electrically connected, and a second electrode connected said collector layer and the said cathode layer and electrically. In the semiconductor device, an inversion layer that connects between the emitter region and the drift layer is formed in a portion of the base layer that is located on the opposite side of the gate electrode with the gate insulating film interposed therebetween. And a semiconductor switching element that allows a current to flow between the first electrode and the second electrode, and has a PN junction formed by the base layer and the drift layer, and the first electrode and the second electrode A free-wheeling diode element that allows current to flow between the electrodes is provided. An independent gate driving voltage is applied to the plurality of gate electrodes by connecting some of the gate electrodes and the remaining gate electrodes to different gate terminals. When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate driving voltage at which an inversion layer connecting the emitter region and the drift layer is formed in a portion is defined as a first voltage. When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate drive voltage in which the inversion layer that connects the emitter region and the drift layer is not formed in a part is defined as a second voltage. When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the first voltage is applied to the partial gate electrodes, and the remaining gate electrodes The second voltage is applied to.
　上記の半導体装置によれば、半導体装置の作動が不明である場合、一部のゲート電極に第１電圧が印加されることによって当該一部のゲート電極が配置されるゲート絶縁膜と接する部分に反転層が形成される。また、残部のゲート電極に第２電圧が印加されることによって当該残部のゲート電極が配置されるゲート絶縁膜と接する部分に、エミッタ領域とドリフト層とを繋ぐ反転層が形成されない。このため、半導体装置が半導体スイッチング素子として作動している場合には、一部のゲート電極が配置されるゲート絶縁膜に沿って形成される反転層によって半導体スイッチング素子の導通損失を低減でき、ＦＷＤ素子として作動している場合には残部のゲート電極が配置されるゲート絶縁膜の近傍に反転層が形成されないため、ＦＷＤ素子における導通損失を低減できる。 According to the semiconductor device described above, when the operation of the semiconductor device is unclear, the first voltage is applied to a part of the gate electrodes so that the part in contact with the gate insulating film where the part of the gate electrodes is disposed An inversion layer is formed. Further, when the second voltage is applied to the remaining gate electrode, an inversion layer that connects the emitter region and the drift layer is not formed in a portion in contact with the gate insulating film in which the remaining gate electrode is disposed. For this reason, when the semiconductor device is operating as a semiconductor switching element, the conduction loss of the semiconductor switching element can be reduced by the inversion layer formed along the gate insulating film in which a part of the gate electrode is disposed. When operating as an element, an inversion layer is not formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed, so that conduction loss in the FWD element can be reduced.
　本開示の他の態様において、半導体装置は、第１導電型のドリフト層を含む半導体基板と、前記ドリフト層上に形成された第２導電型のベース層と、前記ベース層の表層部であって、前記ベース層を挟んで前記ドリフト層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のエミッタ領域と、前記ベース層の表層部に配置された複数のゲート絶縁膜と、前記ゲート絶縁膜上に配置された複数のゲート電極と、前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第２導電型のコレクタ層と、前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のカソード層と、前記ベース層および前記エミッタ領域と電気的に接続される第１電極と、前記コレクタ層および前記カソード層と電気的に接続される第２電極と、を有する。半導体装置は、前記ベース層のうち、前記ゲート絶縁膜を挟んで前記ゲート電極と反対側に位置する部分に前記エミッタ領域と前記ドリフト層との間を繋ぐ反転層を形成し、当該反転層を介して前記第１電極と前記第２電極との間に電流を流す半導体スイッチング素子を備えていると共に、前記ベース層と前記ドリフト層とによるＰＮ接合を有し、前記第１電極と前記第２電極との間に電流を流すフリーホイールダイオード素子を備えている。前記複数のゲート電極は、一部のゲート電極と残部のゲート電極とが異なるゲート端子に接続されることによって独立したゲート駆動電圧が印加されるようになっている。前記一部のゲート電極を有する絶縁ゲート構造の閾値電圧と前記残部のゲート電極を有する絶縁ゲート構造の閾値電圧とが異なっている。前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されると共に、前記ベース層のうちの前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記ドリフト層側から前記エミッタ領域に向かう途中位置まで反転層が形成される前記ゲート駆動電圧を第１電圧と定義する。前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されない前記ゲート駆動電圧を第２電圧と定義する。前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記一部のゲート電極には前記第１電圧が印加され、前記残部のゲート電極には、前記第１電圧または前記第２電圧のいずれか一方が印加される。 In another aspect of the present disclosure, a semiconductor device includes a semiconductor substrate including a first conductivity type drift layer, a second conductivity type base layer formed on the drift layer, and a surface layer portion of the base layer. A first conductivity type emitter region that is formed away from the drift layer with the base layer interposed therebetween and has a higher impurity concentration than the drift layer, and a plurality of layers disposed in a surface layer portion of the base layer A gate insulating film; a plurality of gate electrodes disposed on the gate insulating film; and a second impurity layer formed in contact with the drift layer and spaced apart from the base layer, and having a higher impurity concentration than the drift layer. A conductivity type collector layer; a first conductivity type cathode layer formed in contact with the drift layer and spaced apart from the base layer, and having a higher impurity concentration than the drift layer; and the base layer Having a first electrode pre said emitter region and electrically connected, and a second electrode connected said collector layer and the said cathode layer and electrically. In the semiconductor device, an inversion layer that connects between the emitter region and the drift layer is formed in a portion of the base layer that is located on the opposite side of the gate electrode with the gate insulating film interposed therebetween. And a semiconductor switching element that allows a current to flow between the first electrode and the second electrode, and has a PN junction formed by the base layer and the drift layer, and the first electrode and the second electrode A free-wheeling diode element that allows current to flow between the electrodes is provided. An independent gate driving voltage is applied to the plurality of gate electrodes by connecting some of the gate electrodes and the remaining gate electrodes to different gate terminals. The threshold voltage of the insulated gate structure having the partial gate electrode is different from the threshold voltage of the insulated gate structure having the remaining gate electrode. When a gate driving voltage is applied to the part of the gate electrode and the remaining part of the gate electrode, the emitter region and the part of the base layer in contact with the gate insulating film where the part of the gate electrode is disposed An inversion layer that connects the drift layer is formed, and a portion of the base layer that is in contact with the gate insulating film where the remaining gate electrode is disposed extends from the drift layer side to an intermediate position toward the emitter region. The gate driving voltage for forming the inversion layer is defined as a first voltage. When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate drive voltage in which the inversion layer that connects the emitter region and the drift layer is not formed in a part is defined as a second voltage. When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the first voltage is applied to the partial gate electrodes, and the remaining gate electrodes One of the first voltage and the second voltage is applied to.
　上記の半導体装置によれば、第一の態様に記載の半導体装置と同様に、一部のゲート電極に第１電圧が印加されることによって当該一部のゲート電極が配置されるゲート絶縁膜と接する部分に反転層が形成されると共に、残部のゲート電極に第２電圧が印加されることによって当該残部のゲート電極が配置されるゲート絶縁膜と接する部分に反転層が形成されない。このため、半導体装置が半導体スイッチング素子として作動している場合には、一部のゲート電極が配置されるゲート絶縁膜に沿って形成される反転層によって半導体スイッチング素子の導通損失を低減でき、ＦＷＤ素子として作動している場合には残部のゲート電極が配置されるゲート絶縁膜の近傍に反転層が形成されないため、ＦＷＤ素子の導通損失を低減できる。また、残部のゲート電極に第１電圧が印加された場合、当該残部のゲート電極が配置されるゲート絶縁膜近傍には、ドリフト層側からエミッタ領域に向かう途中位置まで反転層が形成される。このため、半導体装置が半導体スイッチング素子として作動している場合には、残部のゲート電極に第２電圧が印加される場合より半導体スイッチング素子の導通損失を低減できる。また、半導体装置がＦＷＤ素子として作動している場合には、残部のゲート電極に当該残部のゲート電極が配置されるゲート絶縁膜に沿ってエミッタ領域とドリフト層とを繋ぐ反転層が形成される電圧が印加される場合と比較して、ＦＷＤ素子の導通損失を低減できる。 According to the above semiconductor device, as in the semiconductor device described in the first aspect, the first voltage is applied to a part of the gate electrodes, and the gate insulating film on which the part of the gate electrodes is disposed The inversion layer is formed in the contact portion, and the inversion layer is not formed in the portion in contact with the gate insulating film in which the remaining gate electrode is disposed by applying the second voltage to the remaining gate electrode. For this reason, when the semiconductor device is operating as a semiconductor switching element, the conduction loss of the semiconductor switching element can be reduced by the inversion layer formed along the gate insulating film in which a part of the gate electrode is disposed. When operating as an element, the inversion layer is not formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed, so that the conduction loss of the FWD element can be reduced. In addition, when the first voltage is applied to the remaining gate electrode, an inversion layer is formed in the vicinity of the gate insulating film where the remaining gate electrode is disposed from the drift layer side to a midway position toward the emitter region. For this reason, when the semiconductor device is operating as a semiconductor switching element, the conduction loss of the semiconductor switching element can be reduced as compared with the case where the second voltage is applied to the remaining gate electrode. Further, when the semiconductor device operates as an FWD element, an inversion layer that connects the emitter region and the drift layer is formed along the gate insulating film in which the remaining gate electrode is disposed on the remaining gate electrode. Compared with the case where a voltage is applied, the conduction loss of the FWD element can be reduced.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図１は、本開示の第１実施形態における半導体装置の断面図であり、 図２は、図１に示す半導体装置を用いて電力変換装置を構成した際の回路図であり、 図３Ａは、半導体装置がＩＧＢＴ素子として作動している際の第１、第２ゲート電極に印加されるゲート駆動電圧を示すタイミングチャートであり、 図３Ｂは、半導体装置がＦＷＤ素子として作動している際の第１、第２ゲート電極に印加されるゲート駆動電圧を示すタイミングチャートであり、 図３Ｃは、半導体装置の作動が不明である際の第１、第２ゲート電極に印加されるゲート駆動電圧を示すタイミングチャートであり、 図４は、本開示の第２実施形態における半導体装置の断面図であり、 図５Ａは、半導体装置がＦＷＤ素子として作動している際の第１、第２ゲート電極に印加されるゲート駆動電圧を示すタイミングチャートであり、 図５Ｂは、半導体装置の作動が不明である際の第１、第２ゲート電極に印加されるゲート駆動電圧を示すタイミングチャートである。 The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present disclosure. FIG. 2 is a circuit diagram when a power conversion device is configured using the semiconductor device shown in FIG. FIG. 3A is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an IGBT element. FIG. 3B is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an FWD element. FIG. 3C is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the operation of the semiconductor device is unknown. FIG. 4 is a cross-sectional view of the semiconductor device according to the second embodiment of the present disclosure. FIG. 5A is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the semiconductor device operates as an FWD element. FIG. 5B is a timing chart showing gate drive voltages applied to the first and second gate electrodes when the operation of the semiconductor device is unknown.
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.
　（第１実施形態）
　本開示の第１実施形態について図面を参照しつつ説明する。まず、図１を参照しつつ本実施形態の半導体装置１の構成について説明する。 (First embodiment)
A first embodiment of the present disclosure will be described with reference to the drawings. First, the configuration of the semiconductor device 1 of the present embodiment will be described with reference to FIG.
　本実施形態の半導体装置１は、図１に示されるように、半導体スイッチング素子としてのＩＧＢＴ素子２およびＦＷＤ素子３を有するいわゆる逆導通型ＩＧＢＴ（ＲＣ－ＩＧＢＴ）を備えるものであり、ＩＧＢＴ素子２およびＦＷＤ素子３は、ドリフト層１１として機能するＮ－型の共通の半導体基板１０に形成されている。 As shown in FIG. 1, the semiconductor device 1 of the present embodiment includes a so-called reverse conducting IGBT (RC-IGBT) having an IGBT element 2 and an FWD element 3 as semiconductor switching elements. The FWD element 3 is formed on an N − -type common semiconductor substrate 10 that functions as the drift layer 11.
　具体的には、ドリフト層１１上（半導体基板１０の一面１０ａ側）にＰ型のベース層１２が形成されている。そして、ベース層１２を貫通してドリフト層１１に達するように複数のトレンチ１３ａ、１３ｂが形成され、このトレンチ１３ａ、１３ｂによってベース層１２が複数個に分離されている。 Specifically, a P-type base layer 12 is formed on the drift layer 11 (on the one surface 10a side of the semiconductor substrate 10). A plurality of trenches 13 a and 13 b are formed so as to penetrate the base layer 12 and reach the drift layer 11, and the base layer 12 is separated into a plurality by the trenches 13 a and 13 b.
　なお、各トレンチ１３ａ、１３ｂは、半導体基板１０の一面１０ａの面方向のうちの一方向（図２中紙面奥行き方向）に沿って等間隔に形成されている。また、半導体基板１０の一面１０ａは、ベース層１２のうちのドリフト層１１と反対側の一面にて構成されている。 The trenches 13a and 13b are formed at equal intervals along one direction (the depth direction in the drawing in FIG. 2) of the surface directions of the one surface 10a of the semiconductor substrate 10. Further, one surface 10 a of the semiconductor substrate 10 is configured by one surface of the base layer 12 opposite to the drift layer 11.
　そして、各トレンチ１３ａ、１３ｂ内は、各トレンチ１３ａ、１３ｂの壁面を覆うように形成されたゲート絶縁膜１４と、このゲート絶縁膜１４上に形成されたポリシリコン等により構成されるゲート電極１５ａ、１５ｂとにより埋め込まれている。これにより、トレンチゲート構造が構成されている。 In each of the trenches 13a and 13b, a gate insulating film 14 formed so as to cover the wall surfaces of the respective trenches 13a and 13b, and a gate electrode 15a formed of polysilicon or the like formed on the gate insulating film 14 , 15b. Thereby, a trench gate structure is configured.
　ここで、本実施形態では、各トレンチ１３ａ、１３ｂ内に形成されたゲート電極１５ａ、１５ｂは、一部のゲート電極１５ａと残部のゲート電極１５ｂとが異なるゲート端子Ｇ１、Ｇ２に接続されている。つまり、一部のゲート電極１５ａと残部のゲート電極１５ｂとは、互いに異なるゲート駆動電圧が印加されるようになっている。以下では、一部のゲート電極を第１ゲート電極１５ａとすると共に、残部のゲート電極を第２ゲート電極１５ｂとし、第１ゲート電極１５ａが配置されるトレンチを第１トレンチ１３ａとすると共に第２ゲート電極１５ｂが配置されるトレンチを第２トレンチ１３ｂとして説明する。なお、本実施形態では、第１トレンチ１３ａおよび第２トレンチ１３ｂ（第１ゲート電極１５ａおよび第２ゲート電極１５ｂ）は、第１、第２トレンチ１３ａ、１３ｂの延設方向と垂直方向（図１中紙面左右方向）において、第１トレンチ１３ａの間に２つの第２トレンチ１３ｂが配置されるように形成されている。 Here, in this embodiment, the gate electrodes 15a and 15b formed in the trenches 13a and 13b are connected to gate terminals G1 and G2 in which a part of the gate electrodes 15a and the remaining gate electrode 15b are different. . That is, different gate drive voltages are applied to some of the gate electrodes 15a and the remaining gate electrodes 15b. In the following, a part of the gate electrodes is referred to as a first gate electrode 15a, the remaining gate electrode is referred to as a second gate electrode 15b, and a trench in which the first gate electrode 15a is disposed is referred to as a first trench 13a and a second gate electrode. The trench in which the gate electrode 15b is disposed will be described as the second trench 13b. In the present embodiment, the first trench 13a and the second trench 13b (first gate electrode 15a and second gate electrode 15b) are perpendicular to the extending direction of the first and second trenches 13a and 13b (FIG. 1). Two second trenches 13b are formed between the first trenches 13a in the left-right direction of the middle sheet).
　ベース層１２の表層部には、Ｎ＋型のエミッタ領域１６と、エミッタ領域１６に挟まれるＰ＋型のコンタクト領域１７とが形成されている。 In the surface layer portion of the base layer 12, an N + -type emitter region 16 and a P + -type contact region 17 sandwiched between the emitter regions 16 are formed.
　エミッタ領域１６は、ドリフト層１１よりも高不純物濃度で構成され、ベース層１２内において終端し、かつ、第１、第２トレンチ１３ａ、１３ｂの側面に接するように形成されている。一方、コンタクト領域１７は、ベース層１２よりも高不純物濃度で構成され、エミッタ領域１６と同様に、ベース層１２内において終端するように形成されている。 The emitter region 16 is configured to have a higher impurity concentration than the drift layer 11, is terminated in the base layer 12, and is in contact with the side surfaces of the first and second trenches 13a and 13b. On the other hand, the contact region 17 has a higher impurity concentration than the base layer 12, and is formed so as to terminate in the base layer 12, similarly to the emitter region 16.
　より詳しくは、エミッタ領域１６は、第１、第２トレンチ１３ａ、１３ｂ間の領域において、第１、第２トレンチ１３ａ、１３ｂの長手方向に沿って第１、第２トレンチ１３ａ、１３ｂの側面に接するように棒状に延設され、第１、第２トレンチ１３ａ、１３ｂの先端よりも内側で終端する構造とされている。また、コンタクト領域１７は、２つのエミッタ領域１６に挟まれて第１、第２トレンチ１３ａ、１３ｂの長手方向（つまりエミッタ領域１６）に沿って棒状に延設されている。なお、本実施形態のコンタクト領域１７は、半導体基板１０の一面１０ａを基準としてエミッタ領域１６よりも深く形成されている。 More specifically, the emitter region 16 is formed on the side surfaces of the first and second trenches 13a and 13b along the longitudinal direction of the first and second trenches 13a and 13b in the region between the first and second trenches 13a and 13b. It extends in the shape of a rod so as to be in contact with the first and second trenches 13a and 13b, and terminates inside the tip. The contact region 17 is sandwiched between the two emitter regions 16 and extends in a rod shape along the longitudinal direction of the first and second trenches 13a and 13b (that is, the emitter region 16). In the present embodiment, the contact region 17 is formed deeper than the emitter region 16 with respect to the one surface 10a of the semiconductor substrate 10.
　また、図１に示されるように、ベース層１２（半導体基板１０の一面１０ａ）上にはＢＰＳＧ等で構成される層間絶縁膜１８が形成されている。そして、層間絶縁膜１８には、エミッタ領域１６の一部およびコンタクト領域１７を露出させるコンタクトホール１８ａが形成されている。 Further, as shown in FIG. 1, an interlayer insulating film 18 made of BPSG or the like is formed on the base layer 12 (one surface 10a of the semiconductor substrate 10). A contact hole 18 a is formed in the interlayer insulating film 18 to expose a part of the emitter region 16 and the contact region 17.
　層間絶縁膜１８上には第１電極１９が形成されている。そして、この第１電極１９は、コンタクトホール１８ａを介してエミッタ領域１６およびコンタクト領域１７と電気的に接続されている。つまり、第１電極１９は、ＩＧＢＴ素子２におけるエミッタ電極として機能すると共にＦＷＤ素子３におけるアノード素子として機能する。 A first electrode 19 is formed on the interlayer insulating film 18. The first electrode 19 is electrically connected to the emitter region 16 and the contact region 17 through the contact hole 18a. That is, the first electrode 19 functions as an emitter electrode in the IGBT element 2 and also functions as an anode element in the FWD element 3.
　ドリフト層１１のうちのベース層１２側と反対側（半導体基板１０の他面１０ｂ側）には、Ｐ型のコレクタ層２０およびＮ型のカソード層２１が形成されている。つまり、ＩＧＢＴ素子２とＦＷＤ素子３とは、半導体基板１０の他面１０ｂ側に形成される層がコレクタ層２０であるかカソード層２１であるかによって基本的に区画されている。 A P-type collector layer 20 and an N-type cathode layer 21 are formed on the drift layer 11 opposite to the base layer 12 side (the other surface 10b side of the semiconductor substrate 10). That is, the IGBT element 2 and the FWD element 3 are basically partitioned depending on whether the layer formed on the other surface 10 b side of the semiconductor substrate 10 is the collector layer 20 or the cathode layer 21.
　コレクタ層２０およびカソード層２１上（半導体基板１０の他面１０ｂ）には第２電極２２が形成されている。この第２電極２２は、ＩＧＢＴ素子２においてはコレクタ電極として機能し、ＦＷＤ素子３においてはカソード電極として機能する。 A second electrode 22 is formed on the collector layer 20 and the cathode layer 21 (the other surface 10b of the semiconductor substrate 10). The second electrode 22 functions as a collector electrode in the IGBT element 2 and functions as a cathode electrode in the FWD element 3.
　そして、上記のように構成されていることにより、ベース層１２およびコンタクト領域１７をアノードとし、ドリフト層１１、カソード層２１をカソードとしてＰＮ接合を有するＦＷＤ素子３が構成されている。 The FWD element 3 having a PN junction with the base layer 12 and the contact region 17 as an anode and the drift layer 11 and the cathode layer 21 as a cathode is configured as described above.
　以上が本実施形成における半導体装置１の基本的な構成である。なお、本実施形態では、Ｎ型、Ｎ＋型、Ｎ－型が本開示の第１導電型に相当し、Ｐ型、Ｐ＋型が本開示の第２導電型に相当している。 The above is the basic configuration of the semiconductor device 1 in this embodiment. In the present embodiment, the N type, the N + type, and the N − type correspond to the first conductivity type of the present disclosure, and the P type and the P + type correspond to the second conductivity type of the present disclosure.
　次に、上記半導体装置１をモータ等の誘導性負荷を駆動するインバータ装置や、インダクタ等を備えて直流電圧を昇圧および降圧するコンバータ装置等の電力変換装置に適用した例について説明する。まず、電力変換装置の構成について説明する。 Next, an example in which the semiconductor device 1 is applied to a power conversion device such as an inverter device that drives an inductive load such as a motor, or a converter device that includes an inductor or the like to boost and step down a DC voltage will be described. First, the configuration of the power conversion device will be described.
　図２に示されるように、電力変換装置は、高電位側の直流電源線３１と低電位側の直流電源線（グランド）３２とを有している。そして、ハーフブリッジ回路を構成するように、高電位側の直流電源線３１と低電位側の直流電源線３２との間に負荷と接続された出力端子Ｎｔを挟んで半導体装置１Ａ、１Ｂが直列に配置されている。なお、半導体装置１Ａ、１Ｂは、共に上記で説明した図１に示す半導体装置１である。 As shown in FIG. 2, the power conversion apparatus includes a high-potential-side DC power supply line 31 and a low-potential-side DC power supply line (ground) 32. The semiconductor devices 1A and 1B are connected in series with an output terminal Nt connected to a load between the high potential side DC power supply line 31 and the low potential side DC power supply line 32 so as to constitute a half-bridge circuit. Is arranged. The semiconductor devices 1A and 1B are both the semiconductor device 1 shown in FIG. 1 described above.
　ここで、半導体装置１Ａは、基本的には上記構成であるが、半導体装置１Ａ内には、上記ＩＧＢＴ素子２ａＭおよびＦＷＤ素子３ａＭを有するメイン素子Ｍａと、上記ＩＧＢＴ素子２ａＳおよびＦＷＤ素子３ａＳを有し、メイン素子Ｍａに流れる電流に比例した微小な電流を流すセンス素子Ｓａとが形成されている。同様に、半導体装置１Ｂは、基本的には上記構成であるが、半導体装置１Ｂ内には、上記ＩＧＢＴ素子２ｂＭおよびＦＷＤ素子３ｂＭを有するメイン素子Ｍｂと、上記ＩＧＢＴ素子２ｂＳおよびＦＷＤ素子３ｂＳを有し、メイン素子Ｍｂに流れる電流に比例した微小な電流を流すセンス素子Ｓｂとが形成されている。そして、半導体装置１Ａ、１Ｂにおける第１、第２ゲート電極１５ａ、１５ｂには、それぞれゲート駆動電圧ＶＧＨ１、ＶＧＨ２、ＶＧＬ１、ＶＧＬ２が印加されるようになっている。 Here, the semiconductor device 1A basically has the above-described configuration, but the semiconductor device 1A includes the main element Ma having the IGBT element 2aM and the FWD element 3aM, and the IGBT element 2aS and the FWD element 3aS. In addition, a sense element Sa is formed which passes a minute current proportional to the current flowing through the main element Ma. Similarly, the semiconductor device 1B basically has the above-described configuration, but the semiconductor device 1B includes the main element Mb having the IGBT element 2bM and the FWD element 3bM, and the IGBT element 2bS and the FWD element 3bS. In addition, a sense element Sb that allows a minute current proportional to the current flowing in the main element Mb to be formed is formed. The gate drive voltages VGH1, VGH2, VGL1, and VGL2 are applied to the first and second gate electrodes 15a and 15b in the semiconductor devices 1A and 1B, respectively.
　そして、半導体装置１Ａ、１Ｂにおけるメイン素子Ｍａ、Ｍｂおよびセンス素子Ｓａ、Ｓｂと接続される端子Ｓ１、Ｓ２の間には、それぞれセンス抵抗４ａ、４ｂが接続されている。このセンス抵抗４ａ、４ｂは、後述する電流検出部４５ａ、４５ｂと共に電流検出装置を構成するものである。 Sense resistors 4a and 4b are connected between the terminals S1 and S2 connected to the main elements Ma and Mb and the sense elements Sa and Sb in the semiconductor devices 1A and 1B, respectively. The sense resistors 4a and 4b constitute a current detection device together with current detection units 45a and 45b described later.
　また、電力変換装置は、マイクロコンピュータ４１を備えている。このマイクロコンピュータ４１は、ハーフブリッジ回路のハイサイド側およびローサイード側のＰＷＭ信号ＦＨ、ＦＬを生成するＰＷＭ信号生成部４２や、図示しない記憶装置、周辺機器等によって構成されている。そして、ＰＷＭ信号ＦＨ、ＦＬは、それぞれフォトカプラ４３ａ、４３ｂを介して駆動ＩＣ４４ａ、４４ｂに入力される。 Further, the power conversion device includes a microcomputer 41. The microcomputer 41 includes a PWM signal generation unit 42 that generates PWM signals FH and FL on the high side and low side of the half bridge circuit, a storage device (not shown), peripheral devices, and the like. The PWM signals FH and FL are input to the drive ICs 44a and 44b via the photocouplers 43a and 43b, respectively.
　駆動ＩＣ４４ａは、電流検出部４５ａ、ゲート電圧制御部４６ａ、第１ドライブ回路４７ａ、第２ドライブ回路４８ａを備えており、電源電圧ＶＤＤＡ（例えば、１５Ｖ）が供給されることで作動する構成となっている。同様に、駆動ＩＣ４４ｂは、電流検出部４５ｂ、ゲート電圧制御部４６ｂ、第１ドライブ回路４７ｂ、第２ドライブ回路４８ｂを備えており、電源電圧ＶＤＤＢ（例えば、１５Ｖ）が供給されることで作動する構成となっている。なお、本実施形態では、駆動ＩＣ４４ａ、４４ｂは、それぞれハイサイド側の半導体装置１Ａおよびローサイド側の半導体装置１Ｂに対して別々に備えられている。このため、駆動ＩＣ４４ａ、４４ｂは、各電源電圧ＶＤＤＡ、ＶＤＤＢに応じた耐圧（すなわちゲート駆動電圧に応じた耐圧）とされていればよい。 The drive IC 44a includes a current detection unit 45a, a gate voltage control unit 46a, a first drive circuit 47a, and a second drive circuit 48a, and operates by being supplied with a power supply voltage VDDA (for example, 15V). ing. Similarly, the drive IC 44b includes a current detection unit 45b, a gate voltage control unit 46b, a first drive circuit 47b, and a second drive circuit 48b, and operates when a power supply voltage VDDB (for example, 15 V) is supplied. It has a configuration. In the present embodiment, the drive ICs 44a and 44b are provided separately for the high-side semiconductor device 1A and the low-side semiconductor device 1B, respectively. Therefore, the drive ICs 44a and 44b only need to have a withstand voltage corresponding to the power supply voltages VDDA and VDDB (that is, withstand voltage according to the gate drive voltage).
　次に、本実施形態の駆動ＩＣ４４ａ、４４ｂの具体的な構成について説明する。なお、以下では駆動ＩＣ４４ｂについて説明するが、駆動ＩＣ４４ａと駆動ＩＣ４４ｂは同様の構成とされているため、駆動ＩＣ４４ａも同様である。 Next, a specific configuration of the drive ICs 44a and 44b of this embodiment will be described. Although the drive IC 44b will be described below, since the drive IC 44a and the drive IC 44b have the same configuration, the drive IC 44a is also the same.
　電流検出部４５ｂは、センス抵抗４ｂに生じるセンス電圧ＶＳＬに基づいて、半導体装置１Ｂに流れる電流の大きさおよび極性を検出し、検出結果をゲート電圧制御部４６ｂに出力する。 The current detection unit 45b detects the magnitude and polarity of the current flowing through the semiconductor device 1B based on the sense voltage VSL generated in the sense resistor 4b, and outputs the detection result to the gate voltage control unit 46b.
　ゲート電圧制御部４６ｂは、電流検出部４５ｂから入力される検出結果および後述する閾値電流Ｉｓに基づき、半導体装置１Ｂの状態を判定する。具体的には、ゲート電圧制御部４６ｂは、半導体装置１Ｂが、（ａ）ＩＧＢＴ素子２として作動している、（ｂ）ＦＷＤ素子３として作動している、（ｃ）ＩＧＢＴ素子２およびＦＷＤ素子３のいずれの作動か不明であるか、いずれの状態であるかを判定する。 The gate voltage control unit 46b determines the state of the semiconductor device 1B based on the detection result input from the current detection unit 45b and a threshold current Is described later. Specifically, the gate voltage control unit 46b is configured so that the semiconductor device 1B operates as (a) the IGBT element 2, (b) operates as the FWD element 3, and (c) the IGBT element 2 and the FWD element. It is determined which of the three operations is unknown or in which state.
　そして、当該判定結果およびＰＷＭ信号ＦＬに基づき、第１ドライブ回路４７ｂを介して第１ゲート電極１５ａに印加する第１ゲート駆動信号ＶＧＬ１を生成すると共に、第２ドライブ回路４８ｂを介して第２ゲート電極１５ｂに印加する第２ゲート駆動信号ＶＧＬ２を生成する。 Based on the determination result and the PWM signal FL, the first gate drive signal VGL1 to be applied to the first gate electrode 15a through the first drive circuit 47b is generated, and the second gate through the second drive circuit 48b. A second gate drive signal VGL2 to be applied to the electrode 15b is generated.
　なお、具体的には後述するが、ゲート電圧制御部４６ｂは、半導体装置１Ｂの状態に応じて複数のゲート駆動電圧ＶＧＬ１、ＶＧＬ２を生成できるように構成されている。例えば、半導体装置１Ｂの作動が不明であると判定した場合、本実施形態では、４種類の第２ゲート駆動電圧ＶＧＬ２を生成できるように構成されている。また、半導体装置１Ｂの作動が不明であるとは、半導体装置１Ｂに流れる電流が微小であって電流検出部４５ｂで検出された検出結果が電流閾値Ｉｓより小さくなる場合であり、例えば、半導体装置１Ａと半導体装置１Ｂとのスイッチングが切り替えられるときに発生する。 Although specifically described later, the gate voltage control unit 46b is configured to generate a plurality of gate drive voltages VGL1 and VGL2 according to the state of the semiconductor device 1B. For example, when it is determined that the operation of the semiconductor device 1B is unknown, the present embodiment is configured to generate four types of second gate drive voltages VGL2. Further, the operation of the semiconductor device 1B is unclear when the current flowing through the semiconductor device 1B is very small and the detection result detected by the current detection unit 45b is smaller than the current threshold Is, for example, the semiconductor device Occurs when switching between 1A and semiconductor device 1B is switched.
　また、駆動ＩＣ４４ｂには、閾値設定回路４９ｂが外付けされている。この閾値設定回路４９ｂは、半導体装置１Ｂのエミッタ電位に等しいフローティング電位（半導体装置１Ｂは低電位側なのでグランド電位）を基準電位として構成されており、電圧ＶＤＤＢを抵抗Ｒ１、Ｒ２で分圧して規定電圧Ｖｍｌを生成する。そして、ゲート電圧制御部４６ｂは、この規定電圧Ｖｍ１を用いて半導体装置１Ｂに流れる電流と比較する際の閾値電流Ｉｓを決定する。 Further, a threshold setting circuit 49b is externally attached to the drive IC 44b. This threshold value setting circuit 49b is configured with a floating potential equal to the emitter potential of the semiconductor device 1B (the ground potential because the semiconductor device 1B is on the low potential side) as a reference potential, and is defined by dividing the voltage VDDB with resistors R1 and R2. A voltage Vml is generated. Then, the gate voltage control unit 46b determines the threshold current Is when compared with the current flowing through the semiconductor device 1B using the specified voltage Vm1.
　さらに、駆動ＩＣ４４ｂ（ゲート電圧制御部４６ｂ）には、切替信号Ｓｋが入力されるようになっている。本実施形態では、ゲート電圧制御部４６ｂは、上記のように半導体装置１Ｂの状態に応じて複数のゲート駆動電圧ＶＧＬ１、ＶＧＬ２を生成することができるよう構成されており、切替信号Ｓｋによっていずれのゲート駆動電圧を生成するのか（印加するのか）を決定できるようになっている。 Furthermore, a switching signal Sk is input to the drive IC 44b (gate voltage control unit 46b). In the present embodiment, the gate voltage control unit 46b is configured to generate a plurality of gate drive voltages VGL1 and VGL2 according to the state of the semiconductor device 1B as described above. It is possible to determine whether to generate (apply) a gate drive voltage.
　以上が本実施形態の基本的な電力変換装置の構成である。なお、上記のように、駆動ＩＣ４４ａの構成は、駆動ＩＣ４４ｂと同様である。 The above is the basic configuration of the power converter of this embodiment. As described above, the configuration of the drive IC 44a is the same as that of the drive IC 44b.
　次に、電力変換装置におけるローサイド側の半導体装置１Ｂにおいて、当該半導体装置１Ｂの第１、第２ゲート電極１５ａ、１５ｂに印加される第１、第２ゲート駆動電圧ＶＧＬ１、ＶＧＬ２について図３Ａ～図３Ｃを参照しつつ説明する。なお、以下では、ゲート電圧制御部４６ｂが、（ａ）半導体装置１ＢがＩＧＢＴ素子２として作動していると判定した場合、（ｂ）半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合、（ｃ）半導体装置１Ｂの作動が不明であると判定した場合について、それぞれ説明する。また、ハイサイド側の半導体装置１Ａに印加される第１、第２ゲート駆動電圧ＶＧＨ１、ＶＧＨ２は、ローサイド側の半導体装置１Ｂに印加される第１、第２ゲート駆動電圧ＶＧＬ１、ＶＧＬ２と基本的には同様である。 Next, in the semiconductor device 1B on the low side in the power converter, the first and second gate drive voltages VGL1 and VGL2 applied to the first and second gate electrodes 15a and 15b of the semiconductor device 1B are shown in FIGS. This will be described with reference to 3C. In the following description, when the gate voltage control unit 46b determines that (a) the semiconductor device 1B operates as the IGBT element 2, it determines that (b) the semiconductor device 1B operates as the FWD element 3. In the case, (c) the case where it is determined that the operation of the semiconductor device 1B is unknown will be described. The first and second gate drive voltages VGH1 and VGH2 applied to the high-side semiconductor device 1A are basically the same as the first and second gate drive voltages VGL1 and VGL2 applied to the low-side semiconductor device 1B. Is the same.
　（ａ）半導体装置１ＢがＩＧＢＴ素子２として作動していると判定した場合
　半導体素装置１ＢがＩＧＢＴ素子２として作動していると判定した場合、図３Ａに示されるように、第１ゲート電極１５ａには時点Ｔ２までハイレベルであり、時点Ｔ２からローレベルとなるゲート駆動電圧ＶＧＬ１が印加される。 (A) When it is determined that the semiconductor device 1B is operating as the IGBT element 2, when it is determined that the semiconductor device 1B is operating as the IGBT element 2, as shown in FIG. 3A, the first gate electrode 15a Is applied with the gate drive voltage VGL1 which is at the high level until the time T2, and becomes the low level from the time T2.
　なお、ゲート駆動電圧ＶＧＬ１の波形は、ＰＷＭ信号ＦＬと同じ波形である。また、本実施形態において、ハイレベルのゲート駆動電圧とは、ベース層１２のうちの第１、第２トレンチ１３ａ、１３ｂと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成される電圧のことである。反対に、ローレベルのゲート駆動電圧とは、ベース層１２のうちの第１、第２トレンチ１３ａ、１３ｂと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されない電圧のことであり、本実施形態では０Ｖとされている。そして、本実施形態では、ハイレベルのゲート駆動電圧が本開示の第１電圧に相当し、ローレベルのゲート駆動電圧が本開示の第２電圧に相当している。 Note that the waveform of the gate drive voltage VGL1 is the same as that of the PWM signal FL. In the present embodiment, the high-level gate driving voltage is such that an inversion layer that connects the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 that is in contact with the first and second trenches 13a and 13b. Voltage. On the other hand, the low-level gate drive voltage is a voltage at which an inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in a portion of the base layer 12 in contact with the first and second trenches 13a and 13b. Yes, in this embodiment, it is set to 0V. In the present embodiment, the high-level gate drive voltage corresponds to the first voltage of the present disclosure, and the low-level gate drive voltage corresponds to the second voltage of the present disclosure.
　なお、本実施形態では、ローレベルの電圧を０Ｖとして説明するが、ローレベルの電圧はベース層１２のうちの第１、第２トレンチ１３ａ、１３ｂと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されない電圧であればよい。つまり、第１、第２ゲート電極１５ａ、１５ｂを有する絶縁ゲート構造の閾値電圧Ｖｔｈ未満の電圧であればよい。 In this embodiment, the low level voltage is assumed to be 0 V. However, the low level voltage is applied to the emitter region 16 and the drift layer 11 in the portion of the base layer 12 that is in contact with the first and second trenches 13a and 13b. Any voltage may be used as long as the inversion layer connecting the two is not formed. That is, any voltage lower than the threshold voltage Vth of the insulated gate structure having the first and second gate electrodes 15a and 15b may be used.
　また、第２ゲート電極１５ｂには、切替信号Ｓｋに応じて、第２ゲート駆動電圧ＶＧＬ２ａ、ＶＧＬ２ｂのいずれか一方が印加される。具体的には、第２ゲート駆動電圧ＶＧＬ２ａは、第１ゲート駆動電圧ＶＧＬ１ａと同じ波形の信号である。第２ゲート駆動電圧ＶＧＬ２ｂは、時点Ｔ２以前の時点Ｔ１までハイレベルであり、時点Ｔ１から時点Ｔ３まで負電圧となる信号である。 Also, one of the second gate drive voltages VGL2a and VGL2b is applied to the second gate electrode 15b according to the switching signal Sk. Specifically, the second gate drive voltage VGL2a is a signal having the same waveform as the first gate drive voltage VGL1a. The second gate drive voltage VGL2b is a signal that is at a high level from time T1 before time T2 and is a negative voltage from time T1 to time T3.
　このため、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｂが印加されるようにした場合には、時点Ｔ１までベース層１２のうちの第２トレンチ１３ｂと接する部分に形成されていた反転層が消滅すると共に反転層が形成されていた領域にＰ＋型の蓄積層が形成される。したがって、時点Ｔ１から時点Ｔ２においてドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができ、スイッチング速度を速くすることができる。つまり、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｂが印加されるようにした場合には、スイッチング損失を低減できる。 Therefore, when the second gate drive voltage VGL2b is applied to the second gate electrode 15b, the inversion layer formed in the portion of the base layer 12 in contact with the second trench 13b until the time T1 is A P + -type accumulation layer is formed in the region where the inversion layer has been formed while disappearing. Therefore, part of the holes accumulated in the drift layer 11 from the time T1 to the time T2 can be extracted in advance through the accumulation layer, and the switching speed can be increased. That is, when the second gate drive voltage VGL2b is applied to the second gate electrode 15b, the switching loss can be reduced.
　（ｂ）半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合
　半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合、図３Ｂに示されるように、第１、第２ゲート電極１５ａ、１５ｂには、切替信号Ｓｋに応じて、第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ１ｂ、ＶＧＬ２ａ、ＶＧＬ２ｂのいずれか一方が印加される。具体的には、第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａは、ローレベルの信号である。また、第１、第２ゲート駆動電圧ＶＧＬ１ｂ、ＶＧＬ２ｂは、時点Ｔ４までがローレベルであり、時点Ｔ４から時点Ｔ５までハイレベルとなる信号である。なお、時点Ｔ４は、半導体装置１Ｂにリカバリ電流が流れ始める前の時点である。 (B) When it is determined that the semiconductor device 1B is operating as the FWD element 3, when it is determined that the semiconductor device 1B is operating as the FWD element 3, as shown in FIG. 3B, the first and second gates One of the first and second gate drive voltages VGL1a, VGL1b, VGL2a, and VGL2b is applied to the electrodes 15a and 15b in accordance with the switching signal Sk. Specifically, the first and second gate drive voltages VGL1a and VGL2a are low level signals. The first and second gate drive voltages VGL1b and VGL2b are signals that are at a low level from time T4 to a high level from time T4 to time T5. The time point T4 is a time point before the recovery current starts to flow through the semiconductor device 1B.
　このため、第１、第２ゲート電極１５ａ、１５ｂに第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ１ｂ、ＶＧＬ２ａ、ＶＧＬ２ｂのいずれかが印加されることにより、ベース層１２に反転層が形成されないため、ＦＷＤ素子３の順方向電圧が高くなることを抑制でき、ＦＷＤ素子３における導通損失を低減できる。 For this reason, since any one of the first and second gate drive voltages VGL1a, VGL1b, VGL2a, and VGL2b is applied to the first and second gate electrodes 15a and 15b, an inversion layer is not formed in the base layer 12. An increase in the forward voltage of the FWD element 3 can be suppressed, and conduction loss in the FWD element 3 can be reduced.
　また、第１、第２ゲート電極１５ａ、１５ｂに第１、第２ゲート駆動電圧ＶＧＬ１ｂ、ＶＧＬ２ｂが印加されることにより、ベース層１２に反転層が形成されることによって時点Ｔ４から時点Ｔ５においてＦＷＤ素子３に蓄積されるホールを減少できる。このため、リカバリ電流の低減を図ることができ、リカバリ損失を低減できる。 Further, when the first and second gate drive voltages VGL1b and VGL2b are applied to the first and second gate electrodes 15a and 15b, an inversion layer is formed in the base layer 12, thereby causing the FWD from the time T4 to the time T5. Holes accumulated in the element 3 can be reduced. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
　なお、上記では、第１、第２ゲート電極１５ａ、１５ｂに同じゲート駆動電圧が印加される例を説明したが、例えば、第１ゲート電極１５ａに第１ゲート駆動電圧ＶＧＬ１ａが印加され、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｂが印加されるようにしてもよい。 In the above description, the same gate drive voltage is applied to the first and second gate electrodes 15a and 15b. However, for example, the first gate drive voltage VGL1a is applied to the first gate electrode 15a, and the second The second gate drive voltage VGL2b may be applied to the gate electrode 15b.
　（ｃ）半導体装置１Ｂの作動が判定できない場合
　半導体装置１Ｂに流れる電流が微小であって電流閾値Ｉｓ未満の場合、半導体装置１ＢがＩＧＢＴ素子２として作動しているかＦＷＤ素子３として作動しているかが判定できない。このため、図３Ｃに示されるように、第１ゲート電極１５ａには、時点Ｔ７までハイレベルであり、時点Ｔ７からローレベルとなるゲート駆動電圧ＶＧＬ１が印加される。これにより、半導体装置１ＢがＩＧＢＴ素子２として作動している場合には、第１トレンチ１３ａと接する部分に反転層が形成されるため、ＩＧＢＴ素子２における導通損失（オン電圧）を低減できる。なお、このゲート駆動電圧ＶＧＬ１の波形は、ＰＷＭ信号ＦＬと同じ波形である。 (C) When the operation of the semiconductor device 1B cannot be determined If the current flowing through the semiconductor device 1B is very small and less than the current threshold Is, whether the semiconductor device 1B is operating as the IGBT element 2 or the FWD element 3 Cannot be determined. Therefore, as shown in FIG. 3C, the gate drive voltage VGL1 that is at the high level until the time T7 and becomes the low level from the time T7 is applied to the first gate electrode 15a. Thereby, when the semiconductor device 1B is operating as the IGBT element 2, an inversion layer is formed in a portion in contact with the first trench 13a, so that the conduction loss (ON voltage) in the IGBT element 2 can be reduced. The waveform of the gate drive voltage VGL1 is the same as that of the PWM signal FL.
　一方、第２ゲート電極１５ｂには、切替信号Ｓｋに応じて、第２ゲート駆動電圧ＶＧＬ２ａ～ＶＧＬ２ｄのいずれかが入力される。 On the other hand, one of the second gate drive voltages VGL2a to VGL2d is input to the second gate electrode 15b according to the switching signal Sk.
　具体的には、ゲート駆動電圧ＶＧＬ２ａは、ローレベルの信号である。ゲート駆動電圧ＶＧＬ２ｂは、時点Ｔ６までローレベルであり、ゲート駆動信号ＶＧＬ１が時点Ｔ７でローレベルに立ち下がる前の時点Ｔ６から時点Ｔ８までが負電圧となる信号である。ゲート駆動電圧ＶＧＬ２ｃは、時点Ｔ９までローレベルであり、時点Ｔ９から時点Ｔ１０までハイレベルとなる信号である。なお、時点Ｔ９は、半導体装置１ＢがＦＷＤ素子３として作動していた場合にリカバリ電流が流れ始める前の時点である。ゲート駆動電圧ＶＧＬ２ｄは、ゲート駆動電圧ＶＧＬ２ｂおよびゲート駆動電圧ＶＧＬ２ｃを組み合わせたものである。 Specifically, the gate drive voltage VGL2a is a low level signal. The gate drive voltage VGL2b is a low level until time T6, and is a negative voltage from time T6 to time T8 before the gate drive signal VGL1 falls to low level at time T7. The gate drive voltage VGL2c is a signal that is at a low level from time T9 and is at a high level from time T9 to time T10. Note that time T9 is a time before the recovery current starts flowing when the semiconductor device 1B operates as the FWD element 3. The gate drive voltage VGL2d is a combination of the gate drive voltage VGL2b and the gate drive voltage VGL2c.
　このため、第２ゲート電極１５ａにゲート駆動電圧ＶＧＬ２ａ～２ｄが印加されると、半導体装置１ＢがＦＷＤ素子３として作動している場合には、ベース層１２のうちの第２トレンチ１３ｂと接する部分に反転層が形成されないため、ＦＷＤ素子３における導通損失を低減できる。 Therefore, when the gate drive voltages VGL2a to 2d are applied to the second gate electrode 15a, when the semiconductor device 1B operates as the FWD element 3, a portion of the base layer 12 that is in contact with the second trench 13b Therefore, the conduction loss in the FWD element 3 can be reduced.
　また、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｂが印加されると、半導体装置１ＢがＩＧＢＴ素子２として作動している場合には、時点Ｔ６から時点Ｔ８においてドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができるため、スイッチング損失を低減できる。 In addition, when the gate drive voltage VGL2b is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the IGBT element 2, holes accumulated in the drift layer 11 from the time T6 to the time T8 are stored. Can be extracted in advance through the storage layer, so that switching loss can be reduced.
　そして、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｃが印加されると、半導体装置１ＢがＦＷＤ素子３として作動している場合には、時点Ｔ９から時点Ｔ１０においてＦＷＤ素子３に蓄積されるホールを減少できる。したがって、リカバリ損失を低減できる。 When the gate drive voltage VGL2c is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, holes accumulated in the FWD element 3 from time T9 to time T10 are reduced. it can. Therefore, recovery loss can be reduced.
　また、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｄが印加されると、半導体装置１ＢがＦＷＤ素子３として作動している場合には、リカバリ損失を低減でき、半導体装置１ＢがＩＧＢＴ素子２として作動している場合にはスイッチング損失を低減できる。 In addition, when the gate drive voltage VGL2d is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, the recovery loss can be reduced, and the semiconductor device 1B operates as the IGBT element 2. In this case, the switching loss can be reduced.
　以上説明したように、本実施形態では、第１ゲート電極１５ａと第２ゲート電極１５ｂとを備え、第１、第２ゲート電極１５ａ、１５ｂに独立したゲート駆動電圧ＶＧＬ１、ＶＧＬ２が印加されるようにしている。 As described above, in the present embodiment, the first gate electrode 15a and the second gate electrode 15b are provided, and independent gate drive voltages VGL1 and VGL2 are applied to the first and second gate electrodes 15a and 15b. I have to.
　そして、半導体装置１の作動が不明である場合、第１ゲート電極１５ａにハイレベルのゲート駆動電圧ＶＧＬ１を印加し、第２ゲート電極１５ｂにローベルのゲート駆動電圧ＶＧＬ２を印加するようにしている。このため、半導体装置１がＩＧＢＴ素子２として作動している場合には、ハイレベルの信号である第１ゲート駆動電圧ＶＧＬ１が第１ゲート電極１５ａに印加されるによってベース層１２のうちの第１ゲート電極１５ａ近傍に反転層が形成されるため、ＩＧＢＴ素子２における導通損失を低減できる。また、半導体装置１がＦＷＤ素子３として作動している場合には、ローレベルである第２ゲート駆動電圧ＶＧＬ２が第２ゲート電極１５ｂ印加されることによってベース層１２のうちの第２ゲート電極１５ｂ近傍に反転層が形成されないため、ＦＷＤ素子３における導通損失を低減できる。 When the operation of the semiconductor device 1 is unknown, a high level gate drive voltage VGL1 is applied to the first gate electrode 15a, and a low level gate drive voltage VGL2 is applied to the second gate electrode 15b. For this reason, when the semiconductor device 1 operates as the IGBT element 2, the first gate drive voltage VGL1 which is a high level signal is applied to the first gate electrode 15a, whereby the first gate electrode 15a has a first level. Since the inversion layer is formed in the vicinity of the gate electrode 15a, the conduction loss in the IGBT element 2 can be reduced. When the semiconductor device 1 operates as the FWD element 3, the second gate drive voltage VGL2 that is at a low level is applied to the second gate electrode 15b, whereby the second gate electrode 15b in the base layer 12 is applied. Since no inversion layer is formed in the vicinity, the conduction loss in the FWD element 3 can be reduced.
　そして、本実施形態では、半導体装置１の作動が不明な場合、第２ゲート電極１５ｂには、第１ゲート駆動電圧ＶＧＬ１がハイレベルからローレベルに立ち下がる前後において負電圧となるゲート駆動電圧ＶＧＬ２ｂ、ＶＧＬ２ｄも印加できるようになっている（図３Ｃ参照）。このため、当該ゲート駆動電圧ＶＧＬ２ｂ、ＶＧＬ２ｄを印加した場合には、ドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができ、スイッチング損失を低減できる。 In the present embodiment, when the operation of the semiconductor device 1 is unknown, the second gate electrode 15b has a gate drive voltage VGL2b that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level. VGL2d can also be applied (see FIG. 3C). For this reason, when the gate drive voltages VGL2b and VGL2d are applied, a part of holes accumulated in the drift layer 11 can be extracted in advance through the accumulation layer, and switching loss can be reduced.
　また、半導体装置１の作動が不明な場合、第２ゲート電極１５ｂには、半導体装置１がＦＷＤ素子３として作動していた場合にリカバリ電流が流れ始める前の時点からハイレベルとなるゲート駆動信号ＶＧＬ２ｃ、ＶＧＬ２ｄも印加できるようになっている（図３Ｃ参照）。このため、当該ゲート駆動信号ＶＧＬ２ｃ、ＶＧＬ２ｄを印加した場合には、ＦＷＤ素子３に蓄積されるホールを減少でき、リカバリ損失を低減できる。 When the operation of the semiconductor device 1 is unknown, the second gate electrode 15b has a gate drive signal that is at a high level from the point before the recovery current starts flowing when the semiconductor device 1 operates as the FWD element 3. VGL2c and VGL2d can also be applied (see FIG. 3C). For this reason, when the gate drive signals VGL2c and VGL2d are applied, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
　さらに、半導体装置１がＩＧＢＴ素子２として作動している場合、第２ゲート電極１５ｂには、第１ゲート駆動電圧ＶＧＬ１がハイレベルからローレベルに立ち下がる前後において負電圧となるゲート駆動電圧ＶＧＬ２ｂが印加できるようになっている（図３Ａ参照）。このため、当該ゲート駆動電圧ＶＧＬ２ｂを印加した場合には、スイッチング損失を低減できる。 Further, when the semiconductor device 1 operates as the IGBT element 2, the second gate electrode 15b has a gate drive voltage VGL2b that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level. It can be applied (see FIG. 3A). For this reason, when the gate drive voltage VGL2b is applied, the switching loss can be reduced.
　同様に、半導体装置１がＦＷＤ素子３として作動している場合、第２ゲート電極１５ｂには、リカバリ電流が流れ始める前の時点からハイレベルとなるゲート駆動信号ＶＧＬ２ｂが印加できるようになっている（図３Ｂ参照）。このため、当該ゲート駆動信号ＶＧＬ２ｂを印加した場合には、ＦＷＤ素子３に蓄積されるホールを減少でき、リカバリ損失を低減できる。 Similarly, when the semiconductor device 1 operates as the FWD element 3, the gate drive signal VGL2b that is at a high level from the time before the recovery current starts flowing can be applied to the second gate electrode 15b. (See FIG. 3B). For this reason, when the gate drive signal VGL2b is applied, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
　（第２実施形態）
　本開示の第２実施形態について説明する。本実施形態は、第１実施形態に対してゲート絶縁構造の閾値電圧Ｖｔｈを変更するためにエミッタ領域１６の深さを変更したものであり、その他に関しては第１実施形態と同様であるため、ここでは説明を省略する。 (Second Embodiment)
A second embodiment of the present disclosure will be described. In the present embodiment, the depth of the emitter region 16 is changed in order to change the threshold voltage Vth of the gate insulating structure with respect to the first embodiment, and the others are the same as in the first embodiment. The description is omitted here.
　本実施形態では、図４に示されるように、第１トレンチ１３ａと接するエミッタ領域１６の深さは、第２トレンチ１３ｂと接するエミッタ領域１６の深さより深くされている。言い換えると、本実施形態の半導体装置１では、半導体基板１０の厚さ方向に電流が流れるため、ベース層１２のうちの電流の流れ方向に沿ったエミッタ領域１６とドリフト層１１との間の長さは、ゲート絶縁膜１４を挟んで第１ゲート電極１５ａと反対側に位置する部分の方がゲート絶縁膜１４を挟んで第２ゲート電極１５ｂと反対側に位置する部分より短くされている。つまり、第１トレンチ１３ａと接するエミッタ領域１６と、第２トレンチ１３ｂと接するエミッタ領域１６とのピーク濃度の位置が異なるように、各エミッタ領域１６が形成されている。 In this embodiment, as shown in FIG. 4, the depth of the emitter region 16 in contact with the first trench 13a is made deeper than the depth of the emitter region 16 in contact with the second trench 13b. In other words, in the semiconductor device 1 of the present embodiment, since a current flows in the thickness direction of the semiconductor substrate 10, the length between the emitter region 16 and the drift layer 11 along the current flow direction in the base layer 12. The portion located on the opposite side of the first gate electrode 15a with the gate insulating film 14 interposed therebetween is shorter than the portion located on the opposite side of the second gate electrode 15b with the gate insulating film 14 interposed therebetween. That is, each emitter region 16 is formed so that the peak concentration positions of the emitter region 16 in contact with the first trench 13a and the emitter region 16 in contact with the second trench 13b are different.
　すなわち、第１ゲート電極１５ａを有するゲート絶縁構造の閾値電圧Ｖｔｈと第２ゲート電極１５ｂを有するゲート絶縁構造の閾値電圧Ｖｔｈとが異なるようにしている。具体的には、第２トレンチ１３ｂと接するエミッタ領域１６は、第１トレンチ１３ａと接するエミッタ領域１６より浅く形成されているため、第２ゲート電極１５ｂを有する絶縁ゲート構造の閾値電圧Ｖｔｈは、第１ゲート電極１５ａを有する絶縁ゲート構造の閾値電圧Ｖｔｈより高くされている。なお、本実施形態における絶縁ゲート構造の閾値電圧Ｖｔｈとは、第１、第２ゲート電極１５ａ、１５ｂにゲート駆動電圧が印加された際、エミッタ領域１６とドリフト層１１とを繋ぐ反転層を形成するために必要な最小電圧のことである。 That is, the threshold voltage Vth of the gate insulating structure having the first gate electrode 15a is different from the threshold voltage Vth of the gate insulating structure having the second gate electrode 15b. Specifically, since the emitter region 16 in contact with the second trench 13b is formed shallower than the emitter region 16 in contact with the first trench 13a, the threshold voltage Vth of the insulated gate structure having the second gate electrode 15b is The threshold voltage Vth of the insulated gate structure having one gate electrode 15a is set higher. Note that the threshold voltage Vth of the insulated gate structure in this embodiment forms an inversion layer that connects the emitter region 16 and the drift layer 11 when a gate drive voltage is applied to the first and second gate electrodes 15a and 15b. This is the minimum voltage required to
　以上が本実施形態における半導体装置１の構成である。次に、このような半導体装置１を上記図２の電力変換装置に適用した場合におけるローサイド側の半導体装置１Ｂのゲート電極１５ａ、１５ｂに印加される第１、第２ゲート駆動電圧ＶＧＬ１、ＶＧＬ２について図３Ａ、図５Ａ、図５Ｂを参照しつつ説明する。なお、以下では、ゲート電圧制御部４６ｂが、（ａ）半導体装置１ＢがＩＧＢＴ素子２として作動していると判定した場合、（ｂ）半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合、（ｃ）半導体装置１Ｂの作動が不明であると判定した場合について、それぞれ説明する。また、ハイサイド側の半導体装置１Ａに印加される第１、第２ゲート駆動電圧ＶＧＨ１、ＶＧＨ２は、ローサイド側の半導体装置１Ｂに印加される第１、第２ゲート駆動電圧ＶＧＬ１、ＶＧＬ２と基本的には同様である。 The above is the configuration of the semiconductor device 1 in the present embodiment. Next, regarding the first and second gate drive voltages VGL1 and VGL2 applied to the gate electrodes 15a and 15b of the semiconductor device 1B on the low side when such a semiconductor device 1 is applied to the power conversion device of FIG. This will be described with reference to FIGS. 3A, 5A, and 5B. In the following description, when the gate voltage control unit 46b determines that (a) the semiconductor device 1B operates as the IGBT element 2, it determines that (b) the semiconductor device 1B operates as the FWD element 3. In the case, (c) the case where it is determined that the operation of the semiconductor device 1B is unknown will be described. The first and second gate drive voltages VGH1 and VGH2 applied to the high-side semiconductor device 1A are basically the same as the first and second gate drive voltages VGL1 and VGL2 applied to the low-side semiconductor device 1B. Is the same.
　（ａ）半導体装置１ＢがＩＧＢＴ素子２として作動していると判定した場合
　半導体素装置１ＢがＩＧＢＴ素子２として作動していると判定した場合には、第１、第２ゲート電極１５ａ、１５ｂには、上記図３Ａを用いて説明した第１、第２ゲート駆動電圧ＶＧＬ１、ＶＧＬ２ａ、ＶＧＬ２ｂがそれぞれ印加される。このため、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｂが印加されるようにした場合には、上記と同様に、スイッチング損失を低減できる。 (A) When it is determined that the semiconductor device 1B operates as the IGBT element 2, When it is determined that the semiconductor device 1B operates as the IGBT element 2, the first and second gate electrodes 15a and 15b Are applied with the first and second gate drive voltages VGL1, VGL2a, and VGL2b described with reference to FIG. 3A. Therefore, when the second gate drive voltage VGL2b is applied to the second gate electrode 15b, the switching loss can be reduced as described above.
　ここで、本実施形態では、上記のように、第２ゲート電極１５ｂを有する絶縁ゲート構造の閾値電圧Ｖｔｈは、第１ゲート電極１５ａを有する絶縁ゲート構造の閾値電圧Ｖｔｈより高くされている。そして、本実施形態において、ハイレベルのゲート駆動電圧とは、第１、第２ゲート電極１５ａ、１５ｂに印加された際、ベース層１２のうちの第１トレンチ１３ａと接する部分にのみエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成され、第２トレンチ１３ｂと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されない電圧のことである。なお、第２ゲート電極１５ｂにハイレベルのゲート駆動電圧が印加された場合には、ベース層１２のうちの第２トレンチ１３ｂと接する部分に、エミッタ領域１６とドリフト層１１とを繋がない反転層が形成される。詳述すると、ベース層１２における第２トレンチ１３ｂと接する部分のうちのドリフト層１１側の部分からエミッタ領域１６に向かう途中位置までの反転層が形成される。このため、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ａ、ＶＧＬ２ｂが印加されることにより、第２トレンチ１３ｂと接する部分のうちのドリフト層１１側の部分に反転層が形成されるため、第２ゲート電極１５ｂにローレベルのゲート駆動電圧が印加される場合と比較して、当該反転層によってドリフト層１１に蓄積されているホールが抜け出ることを抑制できる。したがって、第２ゲート電極１５ｂにもハイレベルの信号を印加することにより、ＩＧＢＴ素子２における導通損失を低減できる。 Here, in the present embodiment, as described above, the threshold voltage Vth of the insulated gate structure having the second gate electrode 15b is higher than the threshold voltage Vth of the insulated gate structure having the first gate electrode 15a. In the present embodiment, the high-level gate drive voltage is applied to the first and second gate electrodes 15a and 15b, and the emitter region 16 is only applied to the portion of the base layer 12 that is in contact with the first trench 13a. And an inversion layer that connects the drift layer 11 is formed, and the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in a portion in contact with the second trench 13b. When a high-level gate drive voltage is applied to the second gate electrode 15b, the inversion layer that does not connect the emitter region 16 and the drift layer 11 to the portion of the base layer 12 in contact with the second trench 13b. Is formed. More specifically, an inversion layer is formed from the portion on the drift layer 11 side in the portion in contact with the second trench 13 b in the base layer 12 to the middle position toward the emitter region 16. For this reason, since the second gate drive voltages VGL2a and VGL2b are applied to the second gate electrode 15b, an inversion layer is formed in the portion on the drift layer 11 side in the portion in contact with the second trench 13b. Compared with the case where a low-level gate driving voltage is applied to the two-gate electrode 15b, it is possible to suppress the holes accumulated in the drift layer 11 from being escaped by the inversion layer. Therefore, the conduction loss in the IGBT element 2 can be reduced by applying a high level signal also to the second gate electrode 15b.
　（ｂ）半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合
　半導体装置１ＢがＦＷＤ素子３として作動していると判定した場合、図５Ａに示されるように、第１、第２ゲート電極１５ａ、１５ｂには、切替信号Ｓｋに応じて、第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａ～ＶＧＬ１ｄ、ＶＧＬ２ｄのいずれかが印加される。 (B) When it is determined that the semiconductor device 1B operates as the FWD element 3, when it is determined that the semiconductor device 1B operates as the FWD element 3, as shown in FIG. 5A, the first and second gates One of the first and second gate drive voltages VGL1a, VGL2a to VGL1d, and VGL2d is applied to the electrodes 15a and 15b in accordance with the switching signal Sk.
　具体的には、第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａは、時点Ｔ１１までハイレベルであって、時点Ｔ１１からローレベルとなる信号であり、半導体装置１ＢがＩＧＢＴ素子２として作動している際に第１ゲート電極１５ａに印加される第１ゲート駆動電圧ＶＧＬ１と同様の信号である。つまり、図５Ａ中の第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａの波形は、ＰＷＭ信号ＦＬと同じ波形である。 Specifically, the first and second gate drive voltages VGL1a and VGL2a are signals that are at a high level until time T11 and are at a low level from time T11, and the semiconductor device 1B operates as the IGBT element 2. This signal is similar to the first gate drive voltage VGL1 applied to the first gate electrode 15a. That is, the waveforms of the first and second gate drive voltages VGL1a and VGL2a in FIG. 5A are the same as that of the PWM signal FL.
　このため、第１、第２ゲート電極１５ａ、１５ｂに第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２が印加される場合には、ベース層１２のうちの第１トレンチ１３ａと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されるが、第２トレンチ１３ｂと接する部分にはエミッタ領域１６とドリフト層１１とを繋ぐ反転層は形成されない。したがって、第１、第２ゲート電極１５ａ、１５ｂにベース層１２のうちの第１トレンチ１３ａと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されるゲート駆動電圧が印加された場合と比較して、ＦＷＤ素子３における導通損失を低減できる。また、この第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａの波形は、ＰＷＭ信号ＦＬと同じ波形であるため、ゲート電圧制御部４６ｂの制御を簡略化できる。 For this reason, when the first and second gate drive voltages VGL1a and VGL2 are applied to the first and second gate electrodes 15a and 15b, the emitter region 16 is formed in a portion of the base layer 12 in contact with the first trench 13a. However, the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed in the portion in contact with the second trench 13b. Therefore, a gate driving voltage is applied to the first and second gate electrodes 15a and 15b so that an inversion layer connecting the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 in contact with the first trench 13a. Compared with the case, the conduction loss in the FWD element 3 can be reduced. Further, since the waveforms of the first and second gate drive voltages VGL1a and VGL2a are the same as that of the PWM signal FL, the control of the gate voltage control unit 46b can be simplified.
　第１、第２ゲート駆動電圧ＶＧＬ１ｂ、ＶＧＬ２ｂは、ローレベルの信号である。 The first and second gate drive voltages VGL1b and VGL2b are low level signals.
　第１、第２ゲート駆動電圧ＶＧＬ１ｃ、ＶＧＬ２ｃは、時点Ｔ１２までがローレベルの信号である。そして、第１ゲート駆動電圧ＶＧＬ１ｃは、時点Ｔ１２から時点Ｔ１３までハイレベルとなる信号であり、第２ゲート駆動電圧ＶＧＬ２ｃは、時点Ｔ１２から時点Ｔ１４までハイレベルとなる信号である。なお、時点Ｔ１２は、半導体装置１Ｂにリカバリ電流が流れ始める前の時点である。また、第１ゲート駆動電圧ＶＧＬ１ｃが時点Ｔ１２からハイレベルとなった後、時点Ｔ１４以前の時点Ｔ１３でローレベルとなるのは、短絡を抑制するためである。 The first and second gate drive voltages VGL1c and VGL2c are low level signals until time T12. The first gate drive voltage VGL1c is a signal that is at a high level from time T12 to time T13, and the second gate drive voltage VGL2c is a signal that is at a high level from time T12 to time T14. The time point T12 is a time point before the recovery current starts to flow through the semiconductor device 1B. The reason why the first gate drive voltage VGL1c becomes high level at time T13 before time T14 after it becomes high level from time T12 is to suppress a short circuit.
　このため、第１、第２ゲート電極１５ａ、１５ｂに第１、第２ゲート駆動電圧ＶＧＬ１ｂ、ＶＧＬ２ｂ、ＶＧＬ１ｃ、ＶＧＬ２ｃが印加されることにより、ベース層１２に反転層が形成されないため、ＦＷＤ素子３の順方向電圧が高くなることを抑制でき、ＦＷＤ素子３の導通損失を低減できる。 For this reason, since the first and second gate drive voltages VGL1b, VGL2b, VGL1c, and VGL2c are applied to the first and second gate electrodes 15a and 15b, an inversion layer is not formed in the base layer 12, so that the FWD element 3 As a result, the forward voltage can be suppressed from increasing, and the conduction loss of the FWD element 3 can be reduced.
　また、第１、第２ゲート電極１５ａ、１５ｂに第１、第２ゲート駆動電圧ＶＧＬ１ｃ、ＶＧＬ２ｃが印加されることにより、時点Ｔ１２から時点Ｔ１３においてＦＷＤ素子３に蓄積されるホールを減少できる。さらに、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｃが印加されることにより、時点Ｔ１４までＦＷＤ素子３に蓄積されるホールを減少できる。このため、リカバリ電流の低減を図ることができ、リカバリ損失を低減できる。 Further, by applying the first and second gate drive voltages VGL1c and VGL2c to the first and second gate electrodes 15a and 15b, holes accumulated in the FWD element 3 from time T12 to time T13 can be reduced. Furthermore, by applying the second gate drive voltage VGL2c to the second gate electrode 15b, holes accumulated in the FWD element 3 can be reduced until time T14. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
　なお、図５Ａ中の時点Ｔ１２から時点Ｔ１４の期間は上記図３Ｂの時点Ｔ４から時点Ｔ５の期間より長くされている。これは、第２ゲート電極１５ｂにハイレベルの第２ゲート駆動電圧ＶＧＬ２ｃが印加されても、ベース層１２のうちの第２トレンチ１３ｂと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されないためである。つまり、本実施形態の半導体装置１Ｂでは、リカバリ電流が流れ始める前から長期間ハイレベルの信号を印加することができ、リカバリ損失をさらに低減できる。 Note that the period from time T12 to time T14 in FIG. 5A is longer than the period from time T4 to time T5 in FIG. 3B. This is because the inversion layer connects the emitter region 16 and the drift layer 11 to the portion of the base layer 12 in contact with the second trench 13b even when the second gate drive voltage VGL2c of high level is applied to the second gate electrode 15b. This is because is not formed. That is, in the semiconductor device 1B of the present embodiment, a high level signal can be applied for a long time before the recovery current starts to flow, and the recovery loss can be further reduced.
　第１、第２ゲート駆動電圧ＶＧＬ１ｄ、ＶＧＬ２ｄは、第１、第２ゲート駆動電圧ＶＧＬ１ａ、ＶＧＬ２ａと第１、第２ゲート駆動電圧ＶＧＬ１ｃ、２ｃとを組み合わせたものである。このため、ＦＷＤ素子３における導通損失を低減しつつ、リカバリ損失も低減できる。 The first and second gate drive voltages VGL1d and VGL2d are combinations of the first and second gate drive voltages VGL1a and VGL2a and the first and second gate drive voltages VGL1c and 2c. For this reason, the recovery loss can be reduced while reducing the conduction loss in the FWD element 3.
　なお、図５Ａでは、第１、第２ゲート駆動電圧ＶＧＬ１ｄ、ＶＧＬ２ｄは、時点Ｔ１１から時点Ｔ１２の期間においてローレベルであるものを示しているが、時点Ｔ１１から時点Ｔ１２の期間においてハイレベルとされていてもよい。また、上記では、第１、第２ゲート電極１５ａ、１５ｂに同じゲート駆動電圧が印加される例を説明したが、例えば、第１ゲート電極１５ａに第１ゲート駆動電圧ＶＧＬ１ａが印加され、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｂが印加されるようにしてもよい。 In FIG. 5A, the first and second gate drive voltages VGL1d and VGL2d are low in the period from the time T11 to the time T12, but are set to the high level in the period from the time T11 to the time T12. It may be. In the above description, the same gate drive voltage is applied to the first and second gate electrodes 15a and 15b. However, for example, the first gate drive voltage VGL1a is applied to the first gate electrode 15a, and the second The second gate drive voltage VGL2b may be applied to the gate electrode 15b.
　（ｃ）半導体装置１Ｂの作動が不明であると判定した場合
　半導体装置１Ｂに流れる電流が微小であるために半導体装置１Ｂの作動が不明であると判定した場合、図５Ｂに示されるように、第１ゲート電極１５ａには、時点Ｔ１５までハイレベルであり、時点Ｔ１５からローレベルとなるゲート駆動電圧ＶＧＬ１が印加される。これにより、半導体装置１ＢがＩＧＢＴ素子２として作動している場合には、第１トレンチ１３ａと接する部分に反転層が形成されるため、ＩＧＢＴ素子２における導通損失を低減できる。このゲート駆動電圧ＶＧＬ１の波形は、ＰＷＭ信号ＦＬと同じ波形である。 (C) When it is determined that the operation of the semiconductor device 1B is unknown When the operation of the semiconductor device 1B is determined to be unknown because the current flowing through the semiconductor device 1B is very small, as shown in FIG. 5B, The first gate electrode 15a is applied with a gate drive voltage VGL1 that is at a high level until time T15 and is at a low level from time T15. Thereby, when the semiconductor device 1B operates as the IGBT element 2, an inversion layer is formed in a portion in contact with the first trench 13a, so that conduction loss in the IGBT element 2 can be reduced. The waveform of the gate drive voltage VGL1 is the same as that of the PWM signal FL.
　一方、第２ゲート電極１５ｂには、切替信号Ｓｋに応じて、第２ゲート駆動電圧ＶＧＬ２ａ～ＶＧＬ２ｈのいずれかが入力される。 On the other hand, one of the second gate drive voltages VGL2a to VGL2h is input to the second gate electrode 15b according to the switching signal Sk.
　第２ゲート駆動電圧ＶＧＬ２ａは、第１ゲート駆動電圧ＶＧＬ１ａと同様の信号である。　第２ゲート駆動電圧ＶＧＬ２ｂは、時点Ｔ１４までハイレベルであり、ゲート駆動信号ＶＧＬ１が時点Ｔ１５でローレベルに立ち下がる前の時点Ｔ１４から時点Ｔ１６まで負電圧となる信号である。ゲート駆動電圧ＶＧＬ２ｃは、時点Ｔ１５までハイレベルであり、時点Ｔ１５でローレベルに立ち下がった後、時点Ｔ１７から時点Ｔ１８までハイレベルとなる信号である。なお、時点Ｔ１７は、半導体装置１ＢがＦＷＤ素子３として作動していた場合にリカバリ電流が流れ始める前の時点である。 The second gate drive voltage VGL2a is the same signal as the first gate drive voltage VGL1a. The second gate drive voltage VGL2b is a signal that is at a high level until time T14 and is a negative voltage from time T14 to time T16 before the gate drive signal VGL1 falls to a low level at time T15. The gate drive voltage VGL2c is a signal that is at a high level from time T15, and is at a high level from time T17 to time T18 after falling to a low level at time T15. The time T17 is a time before the recovery current starts flowing when the semiconductor device 1B operates as the FWD element 3.
　このため、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ａ～ＶＧＬ２ｃが印加されるようにした場合には、半導体装置１ＢがＩＧＢＴ素子２として作動していると、ベース層１２のうちの第２トレンチ１３ｂと接する部分にも反転層が形成されるため、ＩＧＢＴ素子２における導通損失を低減できる。また、半導体装置１ＢがＦＷＤ素子３として作動していると、ベース層１２のうちの第２トレンチ１３ｂと接する部分にはエミッタ領域１６とドリフト層１１とを繋がない反転層が形成されるため、第２ゲート電極１５ｂにエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されるゲート駆動電圧を印加した場合と比較して、ＦＷＤ素子３における導通損失を低減できる。 Therefore, when the second gate drive voltages VGL2a to VGL2c are applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, the second of the base layers 12 Since the inversion layer is also formed in the portion in contact with the trench 13b, the conduction loss in the IGBT element 2 can be reduced. Further, when the semiconductor device 1B operates as the FWD element 3, an inversion layer that does not connect the emitter region 16 and the drift layer 11 is formed in a portion of the base layer 12 that is in contact with the second trench 13b. The conduction loss in the FWD element 3 can be reduced as compared with the case where a gate drive voltage for forming an inversion layer connecting the emitter region 16 and the drift layer 11 is applied to the second gate electrode 15b.
　また、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｃが印加されるようにした場合には、半導体装置１ＢがＩＧＢＴ素子２として作動していると時点Ｔ１４から時点Ｔ１６においてドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができるため、スイッチング損失を低減できる。 Further, when the second gate drive voltage VGL2c is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, it is accumulated in the drift layer 11 from time T14 to time T16. Since some of the holes can be extracted in advance through the storage layer, switching loss can be reduced.
　そして、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｃが印加されるようにした場合には、半導体装置１ＢがＦＷＤ素子３として作動していると時点Ｔ１７から時点Ｔ１８においてＦＷＤ素子３に蓄積されるホールを減少できる。このため、リカバリ電流の低減を図ることができ、リカバリ損失を低減できる。 When the second gate drive voltage VGL2c is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the FWD element 3, it is accumulated in the FWD element 3 from time T17 to time T18. Can reduce the number of holes. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
　ゲート駆動電圧ＶＧＬ２ｄは、ゲート駆動電圧ＶＧＬ２ｃおよびゲート駆動電圧ＶＧＬ２ｄを組み合わせたものである。このため、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｄが印加されると、半導体装置１ＢがＦＷＤ素子３として作動している場合には、ＦＷＤ素子３の導通損失およびリカバリ損失を低減でき、半導体装置１ＢがＩＧＢＴ素子２として作動している場合にはスイッチング損失を低減できる。 The gate drive voltage VGL2d is a combination of the gate drive voltage VGL2c and the gate drive voltage VGL2d. For this reason, when the gate drive voltage VGL2d is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, the conduction loss and the recovery loss of the FWD element 3 can be reduced. When 1B is operating as the IGBT element 2, switching loss can be reduced.
　ゲート駆動電圧ＶＧＬ２ｅは、ローレベルの信号である。ゲート駆動電圧ＶＧＬ２ｆは、時点Ｔ１４までローレベルのゲート駆動信号であり、ゲート駆動信号ＶＧＬ１が時点Ｔ１５でローレベルに立ち下がる前の時点Ｔ１４から時点Ｔ１６まで負電圧となる信号である。ゲート駆動電圧ＶＧＬ２ｇは、時点Ｔ１７までローレベルであり、時点Ｔ１７から時点Ｔ１８までハイレベルとなる信号である。 The gate drive voltage VGL2e is a low level signal. The gate drive voltage VGL2f is a low level gate drive signal until time T14, and is a signal that becomes a negative voltage from time T14 to time T16 before the gate drive signal VGL1 falls to low level at time T15. The gate drive voltage VGL2g is a signal that is at a low level from time T17 and is at a high level from time T17 to time T18.
　このため、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｅ～ＶＧＬ２ｇが印加されるようにした場合には、半導体装置１ＢがＦＷＤ素子３として作動していると、ベース層１２のうちの第２トレンチ１３ｂと接する部分に反転層が形成されないため、ＦＷＤ素子３における導通損失を低減できる。 Therefore, when the gate drive voltages VGL2e to VGL2g are applied to the second gate electrode 15b, if the semiconductor device 1B is operating as the FWD element 3, the second trench 13b in the base layer 12 is used. Since the inversion layer is not formed in the portion in contact with the FWD element 3, the conduction loss in the FWD element 3 can be reduced.
　また、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｆが印加されるようにした場合には、半導体装置１ＢがＩＧＢＴ素子２として作動していると時点Ｔ１４から時点Ｔ１６においてドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができるため、スイッチング損失を低減できる。 Further, when the second gate drive voltage VGL2f is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the IGBT element 2, it is accumulated in the drift layer 11 from time T14 to time T16. Since some of the holes can be extracted in advance through the storage layer, switching loss can be reduced.
　そして、第２ゲート電極１５ｂに第２ゲート駆動電圧ＶＧＬ２ｇが印加されるようにした場合には、半導体装置１ＢがＦＷＤ素子３として作動していると時点Ｔ１７から時点Ｔ１８においてＦＷＤ素子３に蓄積されるホールを減少できる。このため、リカバリ電流の低減を図ることができ、リカバリ損失を低減できる。 When the second gate drive voltage VGL2g is applied to the second gate electrode 15b, if the semiconductor device 1B operates as the FWD element 3, it is accumulated in the FWD element 3 from time T17 to time T18. Can reduce the number of holes. Therefore, the recovery current can be reduced and the recovery loss can be reduced.
　ゲート駆動電圧ＶＧＬ２ｈは、ゲート駆動電圧ＶＧＬ２ｆおよびゲート駆動電圧ＶＧＬ２ｇを組み合わせたものである。このため、第２ゲート電極１５ｂにゲート駆動電圧ＶＧＬ２ｈが印加されると、半導体装置１ＢがＦＷＤ素子３として作動している場合には、ＦＷＤ素子３の導通損失およびリカバリ損失を低減でき、半導体装置１ＢがＩＧＢＴ素子２として作動している場合にはスイッチング損失を低減できる。 The gate drive voltage VGL2h is a combination of the gate drive voltage VGL2f and the gate drive voltage VGL2g. Therefore, when the gate drive voltage VGL2h is applied to the second gate electrode 15b, when the semiconductor device 1B operates as the FWD element 3, the conduction loss and the recovery loss of the FWD element 3 can be reduced, and the semiconductor device When 1B is operating as the IGBT element 2, switching loss can be reduced.
　以上説明したように、本実施形態では、第２ゲート電極１５ｂを有する絶縁ゲート構造の閾値電圧Ｖｔが第１ゲート電極１５ａを有する絶縁ゲート構造の閾値電圧Ｖｔより高くなるようにしている。そして、第１、第２ゲート電極１５ａ、１５ｂにハイレベルの電圧が印加された際、ベース層１２のうちの第１トレンチ１３ａと接する部分にエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成され、ベース層１２のうちの第２トレンチ１３ｂと接する部分にドリフト層１１側からエミッタ領域１６に向かう途中位置まで反転層が形成されるようにしている。 As described above, in this embodiment, the threshold voltage Vt of the insulated gate structure having the second gate electrode 15b is set higher than the threshold voltage Vt of the insulated gate structure having the first gate electrode 15a. When a high level voltage is applied to the first and second gate electrodes 15a and 15b, an inversion layer that connects the emitter region 16 and the drift layer 11 to a portion of the base layer 12 that is in contact with the first trench 13a. The inversion layer is formed in a portion of the base layer 12 that is in contact with the second trench 13 b from the drift layer 11 side to the middle of the emitter region 16.
　このため、半導体装置１の作動が不明な場合、第１、第２ゲート電極１５ａ、１５ｂにハイレベルのゲート駆動電圧ＶＧＬ２ａ～２ｄを印加すると（図５Ｂ参照）、半導体装置１がＩＧＢＴ素子２として作動している場合には、ＩＧＢＴ素子２における導通損失を低減できる。また、半導体装置１がＦＷＤ素子３として作動している場合には、第２ゲート電極１５ｂにエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されるゲート駆動電圧を印加した場合と比較して、ＦＷＤ素子３の導通損失を低減できる。 Therefore, when the operation of the semiconductor device 1 is unclear, when the high-level gate drive voltages VGL2a to 2d are applied to the first and second gate electrodes 15a and 15b (see FIG. 5B), the semiconductor device 1 becomes the IGBT element 2. When operating, the conduction loss in the IGBT element 2 can be reduced. Further, when the semiconductor device 1 operates as the FWD element 3, compared with a case where a gate driving voltage is applied to form an inversion layer that connects the emitter region 16 and the drift layer 11 to the second gate electrode 15 b. Thus, the conduction loss of the FWD element 3 can be reduced.
　また、半導体装置１の作動が不明な場合、第２ゲート電極１５ｂにローレベルのゲート駆動電圧ＶＧＬ２ｅ～２ｈを印加すると（図５Ｂ参照）、半導体装置１がＦＷＤ素子３として作動している場合には、さらにＦＷＤ素子３における導通損失を低減できる。 When the operation of the semiconductor device 1 is unknown, when the low-level gate drive voltages VGL2e to 2h are applied to the second gate electrode 15b (see FIG. 5B), the semiconductor device 1 operates as the FWD element 3. Can further reduce the conduction loss in the FWD element 3.
　さらに、本実施形態においても、半導体装置１の作動が不明な場合、第２ゲート電極１５ｂには、第１ゲート駆動電圧ＶＧＬ１がハイレベルからローレベルに立ち下がる前後において負電圧となるゲート駆動電圧ＶＧＬ２ｂ、ＶＧＬ２ｄ、ＶＧＬ２ｆ、ＶＧＬ２ｈが印加できるようになっている（図５Ｂ参照）。このため、第２ゲート電極１５ｂに当該ゲート駆動電圧ＶＧＬ２ｂ、ＶＧＬ２ｄ、ＶＧＬ２ｆ、ＶＧＬ２ｈが印加されるようにした場合には、ドリフト層１１に蓄積されている正孔の一部を予め蓄積層を介して引き抜くことができ、スイッチング損失を低減できる。 Furthermore, also in this embodiment, when the operation of the semiconductor device 1 is unknown, the second gate electrode 15b has a gate drive voltage that becomes a negative voltage before and after the first gate drive voltage VGL1 falls from the high level to the low level. VGL2b, VGL2d, VGL2f, and VGL2h can be applied (see FIG. 5B). For this reason, when the gate drive voltages VGL2b, VGL2d, VGL2f, and VGL2h are applied to the second gate electrode 15b, a part of the holes accumulated in the drift layer 11 is passed through the accumulation layer in advance. Can be pulled out and switching loss can be reduced.
　また、半導体装置１の作動が不明な場合、第２ゲート電極１５ｂには、半導体装置１がＦＷＤ素子３として作動していた場合にリカバリ電流が流れ始める前の時点からハイレベルとなるゲート駆動信号ＶＧＬ２ｃ、ＶＧＬ２ｄ、ＶＧＬ２ｇ、ＶＧＬ２ｈが印加できるようになっている（図５Ｂ参照）。このため、第２ゲート電極１５ｂに当該ゲート駆動信号ＶＧＬ２ｃ、ＶＧＬ２ｄ、ＶＧＬ２ｇ、ＶＧＬ２ｈが印加されるようにした場合には、ＦＷＤ素子３に蓄積されるホールを減少でき、リカバリ損失を低減できる。 When the operation of the semiconductor device 1 is unknown, the second gate electrode 15b has a gate drive signal that is at a high level from the point before the recovery current starts flowing when the semiconductor device 1 operates as the FWD element 3. VGL2c, VGL2d, VGL2g, and VGL2h can be applied (see FIG. 5B). Therefore, when the gate drive signals VGL2c, VGL2d, VGL2g, and VGL2h are applied to the second gate electrode 15b, holes accumulated in the FWD element 3 can be reduced, and recovery loss can be reduced.
　そして、本実施形態では、第２ゲート電極１５ｂにハイレベルの信号を印加してもエミッタ領域１６とドリフト層１１とを繋ぐ反転層が形成されないため、ハイレベルの期間を長くすることができる。このため、リカバリ損失をさらに低減できる。 In this embodiment, since the inversion layer that connects the emitter region 16 and the drift layer 11 is not formed even when a high level signal is applied to the second gate electrode 15b, the high level period can be extended. For this reason, recovery loss can be further reduced.
　（他の実施形態）
　例えば、上記各実施形態では、第１導電型をＮ型とし、第２導電型をＰ型とした例について説明したが、第１導電型をＰ型とし、第２導電型をＮ型とすることもできる。 (Other embodiments)
For example, in each of the above embodiments, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type is P type, and the second conductivity type is N type. You can also.
　また、上記各実施形態では、第１トレンチ１３ａおよび第２トレンチ１３ｂ（第１ゲート電極１５ａおよび第２ゲート電極１５ｂ）は、第１、第２トレンチ１３ａ、１３ｂの延設方向と垂直方向（図１中紙面左右方向）において、第１トレンチ１３ａの間に２つの第２トレンチ１３ｂが配置されるように形成されているものを説明したが、第１、第２ゲート電極１５ａ、１５ｂの配置の仕方は適宜変更可能である。 In each of the above embodiments, the first trench 13a and the second trench 13b (the first gate electrode 15a and the second gate electrode 15b) are perpendicular to the extending direction of the first and second trenches 13a and 13b (see FIG. In the description, the first and second gate electrodes 15a and 15b are arranged in such a manner that the two second trenches 13b are arranged between the first trenches 13a. The manner can be changed as appropriate.
　そして、上記各実施形態では、半導体基板１０の厚さ方向に電流を流す半導体装置１を例に挙げて説明したが、半導体基板１０の平面方向に電流を流す半導体装置１に本開示を適用することもできる。そして、第１、第２ゲート電極１５ａ、１５ｂは、第１、第２トレンチ１３ａ、１３ｂに配置されておらず、半導体基板１０の一面１０ａ上に配置されるいわゆるプレーナ型の半導体装置１Ｂに本開示を適用することもできる。 In each of the above embodiments, the semiconductor device 1 that flows current in the thickness direction of the semiconductor substrate 10 has been described as an example. However, the present disclosure is applied to the semiconductor device 1 that flows current in the plane direction of the semiconductor substrate 10. You can also. The first and second gate electrodes 15a and 15b are not arranged in the first and second trenches 13a and 13b, but are formed on a so-called planar type semiconductor device 1B arranged on the one surface 10a of the semiconductor substrate 10. The disclosure can also be applied.
　また、上記第２実施形態において、第１ゲート電極１５ａを有するゲート絶縁構造の閾値電圧と第２ゲート電極１５ｂを有するゲート絶縁構造の閾値電圧とを異ならせるための構造は、適宜変更可能である。特に図示しないが、例えば、ベース層１２内において不純物濃度の勾配ができるようにし、ベース層１２のうちの第２トレンチ１３ｂに接する部分の不純物濃度が第１トレンチ１３ａに接する部分の不純物濃度より高くなるようにしてもよい。 In the second embodiment, the structure for making the threshold voltage of the gate insulating structure having the first gate electrode 15a different from the threshold voltage of the gate insulating structure having the second gate electrode 15b can be changed as appropriate. . Although not particularly illustrated, for example, the gradient of the impurity concentration is made in the base layer 12, and the impurity concentration of the portion in contact with the second trench 13b in the base layer 12 is higher than the impurity concentration of the portion in contact with the first trench 13a. It may be made to become.
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (6)

  1. 　第１導電型のドリフト層（１１）を含む半導体基板（１０）と、
    　前記ドリフト層上に形成された第２導電型のベース層（１２）と、
    　前記ベース層の表層部であって、前記ベース層を挟んで前記ドリフト層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のエミッタ領域（１６）と、
    　前記ベース層の表層部に配置された複数のゲート絶縁膜（１４）と、
    　前記ゲート絶縁膜上に配置された複数のゲート電極（１５ａ、１５ｂ）と、
    　前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第２導電型のコレクタ層（２０）と、
    　前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のカソード層（２１）と、
    　前記ベース層および前記エミッタ領域と電気的に接続される第１電極（１９）と、
    　前記コレクタ層および前記カソード層と電気的に接続される第２電極（２２）と、を有し、
    　前記ベース層のうち、前記ゲート絶縁膜を挟んで前記ゲート電極と反対側に位置する部分に前記エミッタ領域と前記ドリフト層との間を繋ぐ反転層を形成し、当該反転層を介して前記第１電極と前記第２電極との間に電流を流す半導体スイッチング素子（２）を備えていると共に、
    　前記ベース層と前記ドリフト層とによるＰＮ接合を有し、前記第１電極と前記第２電極との間に電流を流すフリーホイールダイオード素子（３）を備えている半導体装置において、
    　前記複数のゲート電極は、一部のゲート電極（１５ａ）と残部のゲート電極（１５ｂ）とが異なるゲート端子（Ｇ１、Ｇ２）に接続されることによって独立したゲート駆動電圧が印加されるようになっており、
    　前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成される前記ゲート駆動電圧を第１電圧と定義し、
    　前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されない前記ゲート駆動電圧を第２電圧と定義し、
    　前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記一部のゲート電極には前記第１電圧が印加され、前記残部のゲート電極には前記第２電圧が印加される半導体装置。     A semiconductor substrate (10) including a drift layer (11) of a first conductivity type;
    A second conductivity type base layer (12) formed on the drift layer;
    A first conductivity type emitter region (16), which is a surface layer portion of the base layer, is formed apart from the drift layer with the base layer interposed therebetween, and has a higher impurity concentration than the drift layer;
    A plurality of gate insulating films (14) disposed in a surface layer portion of the base layer;
    A plurality of gate electrodes (15a, 15b) disposed on the gate insulating film;
    A second conductivity type collector layer (20) formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer;
    A cathode layer (21) of the first conductivity type formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer;
    A first electrode (19) electrically connected to the base layer and the emitter region;
    A second electrode (22) electrically connected to the collector layer and the cathode layer;
    An inversion layer that connects the emitter region and the drift layer is formed in a portion of the base layer that is opposite to the gate electrode with the gate insulating film interposed therebetween, and the first layer is interposed through the inversion layer. A semiconductor switching element (2) for passing a current between one electrode and the second electrode;
    In a semiconductor device having a PN junction formed by the base layer and the drift layer, and including a free wheel diode element (3) for passing a current between the first electrode and the second electrode,
    The plurality of gate electrodes are applied with independent gate driving voltages by connecting some of the gate electrodes (15a) and the remaining gate electrodes (15b) to different gate terminals (G1, G2). And
    When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate driving voltage at which an inversion layer connecting the emitter region and the drift layer is formed in a part is defined as a first voltage,
    When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate driving voltage in which an inversion layer connecting the emitter region and the drift layer is not formed in a part is defined as a second voltage,
    When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the first voltage is applied to the partial gate electrodes, and the remaining gate electrodes A semiconductor device to which the second voltage is applied.
  2. 　第１導電型のドリフト層（１１）を含む半導体基板（１０）と、
    　前記ドリフト層上に形成された第２導電型のベース層（１２）と、
    　前記ベース層の表層部であって、前記ベース層を挟んで前記ドリフト層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のエミッタ領域（１６）と、
    　前記ベース層の表層部に配置された複数のゲート絶縁膜（１４）と、
    　前記ゲート絶縁膜上に配置された複数のゲート電極（１５ａ、１５ｂ）と、
    　前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第２導電型のコレクタ層（２０）と、
    　前記ドリフト層と接触すると共に前記ベース層から離間して形成され、前記ドリフト層よりも高不純物濃度とされた第１導電型のカソード層（２１）と、
    　前記ベース層および前記エミッタ領域と電気的に接続される第１電極（１９）と、
    　前記コレクタ層および前記カソード層と電気的に接続される第２電極（２２）と、を有し、
    　前記ベース層のうち、前記ゲート絶縁膜を挟んで前記ゲート電極と反対側に位置する部分に前記エミッタ領域と前記ドリフト層との間を繋ぐ反転層を形成し、当該反転層を介して前記第１電極と前記第２電極との間に電流を流す半導体スイッチング素子（２）を備えていると共に、
    　前記ベース層と前記ドリフト層とによるＰＮ接合を有し、前記第１電極と前記第２電極との間に電流を流すフリーホイールダイオード素子（３）を備えている半導体装置において、
    　前記複数のゲート電極は、一部のゲート電極（１５ａ）と残部のゲート電極（１５ｂ）とが異なるゲート端子（Ｇ１、Ｇ２）に接続されることによって独立したゲート駆動電圧が印加されるようになっており、
    　前記一部のゲート電極を有する絶縁ゲート構造の閾値電圧と前記残部のゲート電極を有する絶縁ゲート構造の閾値電圧とが異なっており、
    　前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されると共に、前記ベース層のうちの前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記ドリフト層側から前記エミッタ領域に向かう途中位置まで反転層が形成される前記ゲート駆動電圧を第１電圧と定義し、
    　前記一部のゲート電極および前記残部のゲート電極にゲート駆動電圧が印加された際、前記ベース層のうちの前記一部のゲート電極および前記残部のゲート電極が配置される前記ゲート絶縁膜と接する部分に前記エミッタ領域と前記ドリフト層とを繋ぐ反転層が形成されない前記ゲート駆動電圧を第２電圧と定義し、
    　前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記一部のゲート電極には前記第１電圧が印加され、前記残部のゲート電極には、前記第１電圧または前記第２電圧のいずれか一方が印加される半導体装置。     A semiconductor substrate (10) including a drift layer (11) of a first conductivity type;
    A second conductivity type base layer (12) formed on the drift layer;
    A first conductivity type emitter region (16), which is a surface layer portion of the base layer, is formed apart from the drift layer with the base layer interposed therebetween, and has a higher impurity concentration than the drift layer;
    A plurality of gate insulating films (14) disposed in a surface layer portion of the base layer;
    A plurality of gate electrodes (15a, 15b) disposed on the gate insulating film;
    A second conductivity type collector layer (20) formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer;
    A cathode layer (21) of the first conductivity type formed in contact with the drift layer and spaced apart from the base layer and having a higher impurity concentration than the drift layer;
    A first electrode (19) electrically connected to the base layer and the emitter region;
    A second electrode (22) electrically connected to the collector layer and the cathode layer;
    An inversion layer that connects the emitter region and the drift layer is formed in a portion of the base layer that is opposite to the gate electrode with the gate insulating film interposed therebetween, and the first layer is interposed through the inversion layer. A semiconductor switching element (2) for passing a current between one electrode and the second electrode;
    In a semiconductor device having a PN junction formed by the base layer and the drift layer, and including a free wheel diode element (3) for passing a current between the first electrode and the second electrode,
    The plurality of gate electrodes are applied with independent gate driving voltages by connecting some of the gate electrodes (15a) and the remaining gate electrodes (15b) to different gate terminals (G1, G2). And
    The threshold voltage of the insulated gate structure having the partial gate electrode is different from the threshold voltage of the insulated gate structure having the remaining gate electrode,
    When a gate driving voltage is applied to the part of the gate electrode and the remaining part of the gate electrode, the emitter region and the part of the base layer in contact with the gate insulating film where the part of the gate electrode is disposed An inversion layer connecting the drift layer is formed, and a portion of the base layer that is in contact with the gate insulating film where the remaining gate electrode is disposed is located on the way to the emitter region from the drift layer side. The gate drive voltage at which the inversion layer is formed is defined as a first voltage,
    When a gate driving voltage is applied to the partial gate electrode and the remaining gate electrode, the gate insulating film is in contact with the partial gate electrode and the remaining gate electrode of the base layer. The gate driving voltage in which an inversion layer connecting the emitter region and the drift layer is not formed in a part is defined as a second voltage,
    When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the first voltage is applied to the partial gate electrodes, and the remaining gate electrodes A semiconductor device to which either the first voltage or the second voltage is applied.
  3. 　前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記残部のゲート電極には、前記一部のゲート電極に印加されるゲート駆動電圧が前記第１電圧から第２電圧に切り替わる所定期間前から、前記ベース層に前記反転層が形成される電圧の極性と反対の極性となる電圧が印加される請求項１または２に記載の半導体装置。 When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the remaining gate electrode has a gate drive voltage applied to the part of the gate electrodes. 3. The semiconductor according to claim 1, wherein a voltage having a polarity opposite to a polarity of a voltage at which the inversion layer is formed is applied to the base layer from a predetermined period before switching from the first voltage to the second voltage. apparatus.
  4. 　前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動か前記フリーホイールダイオード素子の作動かを判定できない際、前記残部のゲート電極には、前記一部のゲート電極に印加されるゲート駆動電圧が前記第１電圧から第２電圧に切り替わった後、前記フリーホイールダイオード素子として作動していた際にリカバリ電流が流れ始める前に前記第１電圧が印加される請求項１ないし３のいずれか１つに記載の半導体装置。 When the operation of the semiconductor switching element or the operation of the free wheel diode element cannot be determined based on the current flowing through the semiconductor substrate, the remaining gate electrode has a gate drive voltage applied to the part of the gate electrodes. The first voltage is applied before the recovery current starts to flow when operating as the freewheeling diode element after switching from the first voltage to the second voltage. The semiconductor device described in one.
  5. 　前記半導体基板に流れる電流に基づいて前記半導体スイッチング素子の作動であると判定した際、前記残部のゲート電極には、前記一部のゲート電極に印加されるゲート駆動電圧が前記第１電圧から第２電圧に切り替わる所定期間前から、前記ベース層に前記反転層が形成される電圧の極性と反対の極性となる電圧が印加される請求項１ないし４のいずれか１つに記載の半導体装置。 When it is determined that the operation of the semiconductor switching element is based on the current flowing through the semiconductor substrate, the remaining gate electrode has a gate drive voltage applied to the partial gate electrode from the first voltage to the first voltage. 5. The semiconductor device according to claim 1, wherein a voltage having a polarity opposite to a polarity of a voltage at which the inversion layer is formed is applied to the base layer from a predetermined period before switching to two voltages.
  6. 　前記半導体基板に流れる電流に基づいて前記フリーホイールダイオード素子の作動であると判定した際、前記一部のゲート電極および残部のゲート電極の少なくともいずれか一方には、リカバリ電流が流れ始める前に前記第１電圧が印加される請求項１ないし５のいずれか１つに記載の半導体装置。
          When it is determined that the operation of the freewheeling diode element is based on the current flowing through the semiconductor substrate, at least one of the partial gate electrode and the remaining gate electrode before the recovery current starts flowing. The semiconductor device according to claim 1, wherein the first voltage is applied.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110678988A (en) * 2017-05-29 2020-01-10 株式会社日立功率半导体 Semiconductor device with a plurality of semiconductor chips
CN111416598A (en) * 2019-01-04 2020-07-14 株式会社东芝 Control circuit, semiconductor device, and circuit device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6414090B2 (en) 2016-01-27 2018-10-31 株式会社デンソー Semiconductor device
JP6952483B2 (en) * 2017-04-06 2021-10-20 三菱電機株式会社 Semiconductor devices, semiconductor device manufacturing methods, and power converters
JP6753951B2 (en) * 2017-06-06 2020-09-09 三菱電機株式会社 Semiconductor devices and power converters
JP7353891B2 (en) * 2019-09-20 2023-10-02 株式会社東芝 Semiconductor devices and semiconductor circuits
JP7352443B2 (en) 2019-11-01 2023-09-28 株式会社東芝 Control method for semiconductor devices
JP7319601B2 (en) 2019-11-01 2023-08-02 株式会社東芝 semiconductor equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008072848A (en) * 2006-09-14 2008-03-27 Mitsubishi Electric Corp Semiconductor device
JP2009268336A (en) * 2007-09-05 2009-11-12 Denso Corp Semiconductor device
JP2014063960A (en) * 2012-09-24 2014-04-10 Denso Corp Semiconductor device
JP2014171356A (en) * 2013-03-05 2014-09-18 Denso Corp Drive control device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4840482B2 (en) * 2008-10-14 2011-12-21 株式会社デンソー Semiconductor device
JP5229288B2 (en) * 2010-09-20 2013-07-03 株式会社デンソー Semiconductor device and control method thereof
JP5696713B2 (en) * 2012-11-06 2015-04-08 株式会社デンソー Semiconductor device and inspection method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008072848A (en) * 2006-09-14 2008-03-27 Mitsubishi Electric Corp Semiconductor device
JP2009268336A (en) * 2007-09-05 2009-11-12 Denso Corp Semiconductor device
JP2014063960A (en) * 2012-09-24 2014-04-10 Denso Corp Semiconductor device
JP2014171356A (en) * 2013-03-05 2014-09-18 Denso Corp Drive control device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110678988A (en) * 2017-05-29 2020-01-10 株式会社日立功率半导体 Semiconductor device with a plurality of semiconductor chips
EP3633733A4 (en) * 2017-05-29 2021-03-03 Hitachi Power Semiconductor Device, Ltd. Semiconductor device
CN110678988B (en) * 2017-05-29 2023-02-24 株式会社日立功率半导体 Semiconductor device with a plurality of semiconductor chips
CN111416598A (en) * 2019-01-04 2020-07-14 株式会社东芝 Control circuit, semiconductor device, and circuit device

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