WO2016108577A1 - 이중화 제어 시스템 - Google Patents
이중화 제어 시스템 Download PDFInfo
- Publication number
- WO2016108577A1 WO2016108577A1 PCT/KR2015/014405 KR2015014405W WO2016108577A1 WO 2016108577 A1 WO2016108577 A1 WO 2016108577A1 KR 2015014405 W KR2015014405 W KR 2015014405W WO 2016108577 A1 WO2016108577 A1 WO 2016108577A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- control data
- controller
- controllers
- buffers
- control
- Prior art date
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
- G05B19/0425—Safety, monitoring
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
- Y04S20/222—Demand response systems, e.g. load shedding, peak shaving
Definitions
- the present invention relates to a redundancy control system, and more particularly, to check whether there is control data output from each controller during the same clock period, and to determine whether or not a failure of the controller depends on a result of checking whether there is a failure.
- the present invention relates to a redundant control system for controlling to continue to operate as a non-controller.
- HVDC High Voltage Direct Current
- the controller In order to operate the HVDC system stably, the controller should be configured in a redundant manner so that the trouble of the controller does not cause a problem in the system.
- the auxiliary controller is switched and operated when a failure of the main controller occurs, but it takes a certain time when the standby controller is switched.
- control data transmitted from the controller may not be transmitted to the lower module, or control data previously transmitted may be used.
- the present invention has been proposed to solve the problems of the prior art, and checks whether the control data output from the first and second controllers exist for the same clock period, and from the check result whether the first and second controllers are faulty or not. It is an object of the present invention to provide a redundant control system for determining and controlling a controller having no failure among the first and second controllers.
- the clock generation unit for generating a clock at a predetermined period; A first buffer for storing control data output from the first controller; A second buffer for storing control data output from the second controller; First and second state monitors verifying whether there is control data of the first and second controllers stored in the first and second buffers during the same clock period among clocks supplied by the clock generator; A switching unit which is switched to transmit control data of any one of the control data of the first and second controllers stored in the first and second buffers to a lower module; And determining whether the first and second controllers are faulty based on a result of checking whether the control data exists in the first and second controllers output from the first and second state monitors, and controlling the switching unit according to the determination result.
- a control unit includes.
- control unit switches to a buffer in which the control data exists when the control data exists only in one of the first and second buffers as a result of checking whether the control data of the first and second controllers exist. Control the switching unit so as to.
- both the first controller and the second controller is in a normal operating state It determines that it is and maintains the previous switching state of the said switch part.
- the first and second state monitors confirm the existence of control data of the first and second controllers stored in the first and second buffers a predetermined number of times during the same clock period, and from the confirmation result. If control data does not exist in all of the preset times, it is determined that a failure occurs in a controller in which the control data does not exist.
- the present invention it is possible to switch in a short time, it is possible to prevent the malfunction of the HVDC system due to the wrong control data for the time required for the transfer determination.
- FIG. 1 is a block diagram showing a connection state of a redundant control system according to an embodiment of the present invention.
- FIG. 1 is a block diagram illustrating a connection state of a redundant control system according to an exemplary embodiment of the present invention.
- the first and second controllers 10 and 20 are configured to perform the same function, and in normal operation, both controllers operate in an active state.
- the first and second controllers 10 and 20 respectively output the same control data at the same time, and the output control data is transmitted to the redundant control system 30.
- the redundancy control system 30 implements redundancy of the first and second controllers 10 and 20 by using control data of each of the first and second controllers 10 and 20.
- the redundancy control system 30 includes a clock generator 301, a first buffer 302, a second buffer 303, a first state monitor 304, a second state monitor 305, The control unit 306 and the switching unit 307 is included.
- the clock generator 301 generates a clock at a predetermined cycle.
- the generated clock is supplied to the first and second state monitors 304 and 305 and the controller 301.
- the first buffer 302 stores control data output from the first controller 10
- the second buffer 303 stores control data output from the second controller 20.
- the control data output from the first and second controllers 10 and 20 is finally transferred to the lower module 40.
- the first state monitor 304 determines whether the control data stored in the first buffer 302 is present during the same clock period among the clocks supplied by the clock generation unit 301. The presence of control data stored in the second buffer 303 is checked.
- the first and second controllers 10 and 20 operate to send control data in synchronization with the same clock. Therefore, in the normal case, the control data sent from the first and second controllers 10 and 20 at the same clock should be present in the first and second buffers 302 and 303 simultaneously.
- the controller 306 checks whether the control data exists in the first and second controllers 10 and 20 and outputs from the first and second state monitors 304 and 305. , 20) to determine if there is a failure. For example, it is confirmed that control data of the first controller 10 exists in the first buffer 10, but that control data of the second controller 20 does not exist in the second buffer 20. If it is confirmed, since the second controller 20 cannot send control data, the controller 306 determines that the second controller 20 has a failure.
- control unit ( 306 determines that a failure occurs in the first controller 20.
- the switching unit 307 is switched by the control of the control unit 306 when a failure occurs in any one of the first and second controllers 10 and 20. For example, when it is determined that the failure of the second controller 20 has occurred, the first controller 10 is switched to the first controller 10 to maintain the operation state. If, on the contrary, the failure of the first controller 10 occurs, the second controller 20 is switched to the second controller 20 so that the second controller 20 continues to operate.
- the control data is transmitted to the lower module 40 by maintaining the operation state of the other controller.
- the controller 306 may control the first controller and the second controller 10. , 20 are all determined to be in a normal operating state to maintain the previous switching state of the switching unit 307. This is because both the first and second controllers 10 and 20 operate normally, regardless of the operation of the switching unit 307, the control data from both the first and second controllers 10 and 20 is transferred to the lower module ( 40) can be delivered.
- control unit 306 does not have control data in the first and second buffers 302 and 303 a predetermined number of times during the same clock period when the control data of the first and second controllers 10 and 20 are checked. If not, it may be determined that a failure has occurred in a controller in which the control data does not exist.
- the first and second state monitors 304 and 305 are configured to control the control data of the first and second controllers 10 and 20 stored in the first and second buffers 302 and 303 a predetermined number of times during the same clock period. If the existence of the control data does not exist in all of the predetermined number of times from the check result, it may be determined that a failure occurs in the controller in which the control data does not exist.
- the predetermined number of times refers to the number of times of checking the existence of control data during the same clock period, and may be set at least once.
- the first and second controllers 10 and 20 maintain an active state, and output control data to the first and second buffers 302 and 303, respectively.
- the first and second state monitors 304 and 305 store the first and second controllers stored in the first and second buffers 302 and 303 during the clock period supplied by the clock generator 301.
- the first and second state monitors 304 and 305 transmit the confirmation result to the control unit 306, and the control unit 306 is sent from the first and second state monitors 304 and 305.
- the failure of the first and second controllers 10 and 20 is determined using the result of the check.
- control unit 306 determines that the control data
- the switching unit 307 is operated to maintain normal operation of the existing controller.
- control unit 306 maintains the previous switching state of the switching unit 307 in order to maintain the state of the first and second controllers 10 and 20.
- the present invention enables the identification of a controller that has a failure by using the presence or absence of control data without using separate signal lines (communication lines) for checking the states of the first and second controllers.
- the first and second controllers always operate in an active state, so that even if a failure occurs in any one controller, the controller can maintain a normal operating state. It is not efficient.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Hardware Redundancy (AREA)
Abstract
Description
Claims (4)
- 기설정된 주기로 클럭을 발생시키는 클럭생성부;제1제어기로부터 출력되는 제어 데이터를 저장하는 제1버퍼;제2제어기로부터 출력되는 제어 데이터를 저장하는 제2버퍼;상기 클럭생성부에 의해 공급되는 클럭 중 동일한 클럭 주기 동안 상기 제1 및 제2버퍼에 각각 저장된 상기 제1 및 제2제어기의 제어 데이터의 존재여부를 확인하는 제1 및 제2상태감시기;상기 제1 및 제2버퍼에 저장된 상기 제1 및 제2제어기의 제어 데이터 중 어느 하나의 제어 데이터를 하위모듈에 전송하도록 스위칭되는 스위칭부; 및상기 제1 및 제2상태감시기로부터 출력된 상기 제1 및 제2제어기의 제어 데이터 존재여부 확인결과로부터 상기 제1 및 제2제어기의 장애 여부를 판단하고, 상기 판단결과에 따라 상기 스위칭부를 제어하는 제어부; 를 포함하는 것을 특징으로 하는 이중화 제어 시스템.
- 제 1항에 있어서,상기 제어부는 상기 제1 및 제2 제어기의 제어 데이터의 존재여부 확인결과, 상기 제어 데이터가 상기 제1 및 제2 버퍼 중 어느 하나에만 존재하는 경우 상기 제어 데이터가 존재하는 버퍼로 스위칭되도록 상기 스위칭부를 제어하는 것을 특징으로 하는 이중화 제어 시스템.
- 제 1항에 있어서,상기 제어부는 상기 제1 및 제2 제어기의 제어 데이터의 존재여부 확인결과, 상기 제1 및 제2 버퍼에 모두 제어 데이터가 존재할 경우 상기 제1제어기 및 제2제어기가 모두 정상 작동 상태인 것으로 판단하여 상기 스위칭부의 이전 스위칭 상태를 그대로 유지하도록 하는 것을 특징으로 하는 이중화 제어 시스템.
- 제 1항에 있어서,상기 제1 및 제2상태감시기는 동일한 클럭 주기 동안 기설정된 횟수만큼 상기 제1 및 제2 버퍼에 저장된 상기 제1 및 제2 제어기의 제어 데이터의 존재를 확인하고, 상기 확인결과로부터 상기 기설정된 횟수 모두 제어 데이터가 존재하지 않을 경우 상기 제어 데이터가 존재하지 않는 제어기에 장애가 발생한 것으로 판단하는 것을 특징으로 하는 이중화 제어 시스템.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/539,468 US20170351249A1 (en) | 2014-12-29 | 2015-12-29 | Redundant control system |
BR112017013818-2A BR112017013818A2 (pt) | 2014-12-29 | 2015-12-29 | sistema de controle redundante |
EP15875671.8A EP3242171A4 (en) | 2014-12-29 | 2015-12-29 | Redundant control system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2014-0192751 | 2014-12-29 | ||
KR1020140192751A KR101764680B1 (ko) | 2014-12-29 | 2014-12-29 | 이중화 제어 시스템 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016108577A1 true WO2016108577A1 (ko) | 2016-07-07 |
Family
ID=56284634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2015/014405 WO2016108577A1 (ko) | 2014-12-29 | 2015-12-29 | 이중화 제어 시스템 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20170351249A1 (ko) |
EP (1) | EP3242171A4 (ko) |
KR (1) | KR101764680B1 (ko) |
BR (1) | BR112017013818A2 (ko) |
WO (1) | WO2016108577A1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101704787B1 (ko) * | 2014-12-31 | 2017-02-22 | 주식회사 효성 | 제어기의 이중화 시스템 |
WO2019100227A1 (zh) * | 2017-11-22 | 2019-05-31 | 贵州智慧能源科技有限公司 | 控制系统及保护装置 |
JP7077644B2 (ja) * | 2018-02-09 | 2022-05-31 | 横河電機株式会社 | 制御システム、診断装置、診断方法、および診断プログラム |
Citations (5)
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KR19980075016A (ko) * | 1997-03-28 | 1998-11-05 | 이종수 | 통신포트단자의 이중화장치 |
KR100205031B1 (ko) * | 1996-09-23 | 1999-06-15 | 이계철 | 이중화 제어시스템의 동기제어 장치 |
KR20030073788A (ko) * | 2002-03-13 | 2003-09-19 | 한국전기연구원 | 계층적 제어 시스템에서의 이중화 제어방법 및 그 장치 |
KR20120020867A (ko) * | 2010-08-31 | 2012-03-08 | 주식회사 포스코아이씨티 | 이중화 구조를 갖는 제어기 및 그 운용 방법 |
KR20130115776A (ko) * | 2012-04-13 | 2013-10-22 | 엘에스산전 주식회사 | Hvdc 시스템의 이중화 제어장치 |
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US6233702B1 (en) * | 1992-12-17 | 2001-05-15 | Compaq Computer Corporation | Self-checked, lock step processor pairs |
US5903717A (en) * | 1997-04-02 | 1999-05-11 | General Dynamics Information Systems, Inc. | Fault tolerant computer system |
DE102005037242A1 (de) * | 2004-10-25 | 2007-02-15 | Robert Bosch Gmbh | Verfahren und Vorrichtung zur Umschaltung und zum Signalvergleich bei einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten |
JP4074304B2 (ja) * | 2004-11-18 | 2008-04-09 | 日本電信電話株式会社 | パケット転送方法及びパケット転送装置 |
JPWO2011068177A1 (ja) * | 2009-12-02 | 2013-04-18 | 日本電気株式会社 | 二重化計算システム及び二重化計算方法 |
US9367438B2 (en) * | 2011-04-21 | 2016-06-14 | Renesas Electronics Corporation | Semiconductor integrated circuit and method for operating same |
EP2787401B1 (en) * | 2013-04-04 | 2016-11-09 | ABB Schweiz AG | Method and apparatus for controlling a physical unit in an automation system |
-
2014
- 2014-12-29 KR KR1020140192751A patent/KR101764680B1/ko active IP Right Grant
-
2015
- 2015-12-29 WO PCT/KR2015/014405 patent/WO2016108577A1/ko active Application Filing
- 2015-12-29 BR BR112017013818-2A patent/BR112017013818A2/pt not_active Application Discontinuation
- 2015-12-29 EP EP15875671.8A patent/EP3242171A4/en not_active Withdrawn
- 2015-12-29 US US15/539,468 patent/US20170351249A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100205031B1 (ko) * | 1996-09-23 | 1999-06-15 | 이계철 | 이중화 제어시스템의 동기제어 장치 |
KR19980075016A (ko) * | 1997-03-28 | 1998-11-05 | 이종수 | 통신포트단자의 이중화장치 |
KR20030073788A (ko) * | 2002-03-13 | 2003-09-19 | 한국전기연구원 | 계층적 제어 시스템에서의 이중화 제어방법 및 그 장치 |
KR20120020867A (ko) * | 2010-08-31 | 2012-03-08 | 주식회사 포스코아이씨티 | 이중화 구조를 갖는 제어기 및 그 운용 방법 |
KR20130115776A (ko) * | 2012-04-13 | 2013-10-22 | 엘에스산전 주식회사 | Hvdc 시스템의 이중화 제어장치 |
Non-Patent Citations (1)
Title |
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See also references of EP3242171A4 * |
Also Published As
Publication number | Publication date |
---|---|
KR20160080025A (ko) | 2016-07-07 |
EP3242171A4 (en) | 2018-09-05 |
BR112017013818A2 (pt) | 2018-02-27 |
EP3242171A1 (en) | 2017-11-08 |
US20170351249A1 (en) | 2017-12-07 |
KR101764680B1 (ko) | 2017-08-03 |
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