WO2016107496A1 - 处理视频帧的方法、视频处理芯片以及运动估计和运动补偿memc芯片 - Google Patents

处理视频帧的方法、视频处理芯片以及运动估计和运动补偿memc芯片 Download PDF

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Publication number
WO2016107496A1
WO2016107496A1 PCT/CN2015/098760 CN2015098760W WO2016107496A1 WO 2016107496 A1 WO2016107496 A1 WO 2016107496A1 CN 2015098760 W CN2015098760 W CN 2015098760W WO 2016107496 A1 WO2016107496 A1 WO 2016107496A1
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Prior art keywords
frame
resolution
video
chip
frame rate
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PCT/CN2015/098760
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English (en)
French (fr)
Inventor
谭丽娟
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华为技术有限公司
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Priority to EP15875174.3A priority Critical patent/EP3232669B1/en
Publication of WO2016107496A1 publication Critical patent/WO2016107496A1/zh
Priority to US15/640,658 priority patent/US10536730B2/en

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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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    • H04N21/43635—HDMI

Definitions

  • the present invention relates to multimedia technologies, and in particular, to a method for processing a video frame, a video processing chip, and a MEMC chip.
  • the terminal device generally includes video processing. a chip, a MEMC chip, and a display screen, wherein the video processing chip is configured to decode the received code stream to obtain a video frame, and the MEMC chip is configured to perform motion estimation and motion compensation on the received video frame to improve a frame rate of the video frame.
  • the display is used to display video frames received from the MEMC chip.
  • the MEMC chip Since the frame rate of the video frame obtained by the video processing chip is usually smaller than the refresh rate of the display screen, in order to meet the requirement of the display refresh rate, the MEMC chip performs motion estimation and motion compensation on the video frame of the low frame rate output by the video processing chip to output. A video frame with a higher frame rate to meet the display refresh rate.
  • the above prior art has the following technical problem: since the video frame acquired by the video processing chip is the original video frame, if the frame rate or resolution of the original video frame changes, the frame rate of the video frame transmitted by the video processing chip to the MEMC chip or The resolution will also change accordingly, because the correspondence between frame rate, resolution and interface frequency is agreed between the video processing chip and the MEMC chip, for example, the resolution is Full High Definition (FHD), frame rate.
  • FHD Full High Definition
  • the interface frequency between the video processing chip and the MEMC is 74.25MHz; when the resolution is Ultra High Definition (UHD), the frame rate is 60fps, the interface frequency between the video processing chip and the MEMC is 297MHz.
  • the interface frequency needs to be adjusted between the video processing chip and the MEMC chip, that is, the interface timing is adjusted. This can cause a brief black screen on the display, reducing the smoothness of the video played on the display.
  • the embodiment of the invention provides a method for processing a video frame, a video processing chip and a MEMC chip, and the frame processing is performed according to a fixed interface frequency between the video processing chip and the MEMC chip, thereby improving the smoothness of playing video on the display screen. .
  • the present invention provides a method of processing a video frame, the method comprising:
  • the video processing chip acquires a plurality of video frames, wherein a frame rate of the plurality of video frames is a first frame rate, a resolution of the plurality of video frames is a first resolution, and a first resolution is a original of each video frame.
  • the video processing chip adjusts each video frame from a first resolution to a second resolution, wherein the second resolution is a predetermined resolution of the video processing chip and the MEMC chip, and the second resolution is greater than the first resolution. ;
  • the video processing chip inserts at least one invalid frame in the plurality of video frames according to a second frame rate such that a frame rate of the transport frame stream composed of the plurality of video frames and the at least one invalid frame is a second frame rate, and Transmitting the transport frame stream to the MEMC chip, wherein the second frame rate is a predetermined frame rate of the video processing chip and the MEMC chip, and the resolution of the at least one invalid frame is the second resolution.
  • the method further includes:
  • the video processing chip sends the appointment information to the MEMC chip, the appointment information includes a second frame rate, a second resolution, and location information, wherein the location information is used to indicate all pixels of each video frame at the first resolution.
  • the composed pixel area is located in a pixel area composed of all the pixels of each video frame at the second resolution.
  • a pixel area composed of all pixels of each video frame at a first resolution is a first pixel area
  • each video frame When the pixel area composed of all the pixels is the second pixel area at the second resolution, the video processing chip adjusts each video frame from the first resolution to the second resolution, including:
  • the video processing chip For each video frame, the video processing chip adds a padding pixel region outside the first pixel region according to the position information to form a second pixel region including the first pixel region and the padding pixel region.
  • the video processing chip inserts at least one of the multiple video frames according to the second frame rate.
  • the method further includes:
  • the video processing chip generates the at least one invalid frame.
  • the method further includes:
  • the video processing chip marks an invalid identification in each invalid frame, the invalid identification being used to identify each invalid frame.
  • the second resolution is the same as the resolution of the display screen
  • the display screen is used to display the frame stream processed by the video processing chip and the MEMC chip.
  • each invalid frame is the multiple video frames A repeating frame of a video frame.
  • the present invention provides another method of processing a video frame, the method comprising:
  • the MEMC chip receives a transport frame stream sent by the video processing chip at a second frame rate, where the transport frame stream includes a plurality of video frames and at least one invalid frame, and the resolution of the plurality of video frames and the at least one invalid frame is
  • the second resolution, the second frame rate and the second resolution are respectively pre-agreed frame rates and resolutions of the video processing chip and the MEMC chip;
  • the MEMC chip performs motion estimation and motion compensation on the plurality of video frames of the first frame rate to generate a display frame stream of a third frame rate, and the third frame rate satisfies a refresh rate required when the display screen displays the display frame stream.
  • the third frame rate is greater than the first frame rate.
  • the method before the MEMC chip receives the transport frame stream sent by the video processing chip at the second frame rate, the method further includes:
  • the MEMC chip receives the appointment information sent by the video processing chip, the appointment information includes a second frame rate, a second resolution, and location information, where the location information is used to indicate all pixels of each video frame at the first resolution.
  • the pixel area composed of dots is located at all images of each video frame at the second resolution.
  • the position in the pixel region composed of the prime points, the first resolution is the original resolution of each video frame, and the second resolution is greater than the first resolution.
  • the pixel area formed by all the pixels in each video frame at the first resolution is the first pixel area
  • each video frame The pixel area composed of all the pixels in the second resolution is the second pixel area
  • the MEMC chip performs motion estimation and motion compensation on the plurality of video frames of the first frame rate to generate a display frame stream of the third frame rate.
  • the method also included:
  • the MEMC chip For each video frame, the MEMC chip acquires the first pixel area from the second pixel area according to the position information
  • the method further includes:
  • the MEMC chip expands the resolution of each frame in the display frame stream to a third resolution, wherein the third resolution is the resolution of the display screen, and the third resolution is greater than the first resolution.
  • each invalid frame includes an invalid identifier
  • the MEMC chip acquires the multiple in the transport frame stream.
  • Video frames include:
  • the MEMC chip acquires the plurality of video frames in the transport frame stream according to an invalid identifier of each invalid frame in the transport stream.
  • each invalid frame is a repetition of one video frame of the multiple video frames frame.
  • the method further includes :
  • the MEMC chip transmits the display frame stream after the resolution is expanded to the display screen.
  • the present invention provides a video processing chip, where the video processing chip includes:
  • a video frame obtaining module configured to acquire a plurality of video frames, and send the plurality of video frames to a first video processing engine, where a frame rate of the plurality of video frames is a first frame rate, and the plurality of video frames are The resolution is the first resolution, and the first resolution is the original resolution of each video frame;
  • the first video processing engine is used to:
  • the first video output interface is configured to receive the transport frame stream sent by the first video processing engine, and send the transport frame stream to the MEMC chip.
  • the video processing chip further includes:
  • a first information contract interface configured to send, to the MEMC chip, the appointment information, where the agreement information includes a second frame rate, a second resolution, and location information, where the location information is used to indicate that each video frame is at the first resolution.
  • the pixel area composed of all the pixels is located at a position in a pixel area composed of all the pixels of each video frame at the second resolution.
  • the pixel area composed of all the pixels of each video frame at the first resolution is the first pixel area
  • each video frame is The pixel area composed of all the pixels in the second resolution is the second pixel area
  • the first video processing engine specifically includes:
  • a padding pixel region is added outside the first pixel region according to the position information to form a second pixel region including the first pixel region and the padding pixel region.
  • the first video processing engine is further configured to:
  • the first video processing engine is further configured to:
  • An invalid identifier is marked in each invalid frame, which is used to identify each invalid frame.
  • the present invention provides a MEMC chip, the MEMC chip comprising:
  • a video input interface configured to receive a transport frame stream sent by the video processing chip at a second frame rate, and send the transport frame stream to a second video processing engine, where the transport frame stream includes multiple video frames and at least one invalid a frame, the resolution of the plurality of video frames and the at least one invalid frame is a second resolution, and the second frame rate and the second resolution are respectively a predetermined frame rate and resolution of the video processing chip and the MEMC chip;
  • the second video processing engine is configured to acquire the plurality of video frames in the transport frame stream, the frame rate of the multiple video frames is a first frame rate, and send the multiple video frames to the MEMC processing engine; ,
  • the MEMC processing engine is configured to perform motion estimation and motion compensation on the plurality of video frames of the first frame rate to generate a display frame stream of a third frame rate, where the third frame rate is required for the display screen to display the display frame stream.
  • the refresh rate, the third frame rate is greater than the first frame rate.
  • the MEMC chip further includes:
  • a second information contract interface configured to receive the agreement information sent by the video processing chip, where the agreement information includes a second frame rate, a second resolution, and location information, where the location information is used to indicate that each video frame is in the first
  • the pixel area composed of all the pixels is located in the pixel area composed of all the pixels of each video frame at the second resolution
  • the first resolution is the original resolution of each video frame
  • the second resolution is Greater than the first resolution
  • a pixel area composed of all pixels in each video frame at a first resolution is a first pixel area, and each video frame is used.
  • the pixel area composed of all the pixels at the second resolution is the second pixel area, and the second video processing engine is further configured to:
  • the MEMC processing engine is further configured to send the generated display frame stream to the second video processing engine.
  • the MEMC processing engine specifically includes:
  • the MEMC processing engine further includes:
  • a second video output interface configured to receive the display frame stream after the resolution is expanded by the second video processing engine, and send the display frame stream with the enlarged resolution to the display screen.
  • the present invention provides a terminal device, including:
  • Video processing chip for:
  • Obtaining a plurality of video frames wherein a frame rate of the plurality of video frames is a first frame rate, a resolution of the plurality of video frames is a first resolution, and a first resolution is a original resolution of each video frame;
  • the MEMC chip is used to:
  • the display screen is configured to receive and display the display frame stream output by the MEMC chip.
  • the video processing chip sends a transmission frame stream to the MEMC chip according to a predetermined resolution and a frame rate, and the agreed resolution and the frame rate correspond to a fixed interface frequency. Therefore, the video processing chip and the MEMC chip can perform frame stream transmission according to the fixed interface frequency, and the video processing chip and the MEMC even when the resolution and frame rate of the video frame acquired by the video processing chip change. There is no need to adjust the interface frequency between chips, it will not This causes a black screen on the display to improve the smoothness of the video played on the display.
  • FIG. 1 is a schematic structural diagram of a terminal device according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for processing a video frame according to an embodiment of the present invention
  • FIG. 3a is a pixel area of a video frame at a first resolution according to the present invention.
  • FIG. 3b is a pixel area of a video frame at a second resolution according to the present invention.
  • FIG. 4 is a flowchart of a method for processing a video frame according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a video processing chip according to an embodiment of the present invention.
  • 6a is a structure of a video frame acquisition module in the video processing chip structure depicted in FIG. 5;
  • 6b is another structure of a video frame acquisition module in the video processing chip structure depicted in FIG. 5;
  • FIG. 7 shows the structure of an MEMC chip according to an embodiment of the present invention.
  • the terminal device 100 includes a video processing chip 101, a MEMC chip 102, and a display screen 103.
  • the terminal device 100 is a device having video processing and display capabilities, such as a television.
  • the video processing chip 101 and the MEMC chip 102 can be two independent chips or two modules in one integrated chip.
  • the video processing chip 101 can be understood as the main chip of the terminal device 100.
  • the general idea of the technical solution related to the present invention is introduced in conjunction with FIG. 1 : after the video processing chip 101 acquires the original video frame, the original video frame is in accordance with the resolution and frame rate agreed with the MEMC chip 102 in advance. The resolution adjustment and the frame rate adjustment are respectively performed, and the adjusted video frame is sent to the MEMC chip 102, and the MEMC chip 102 performs motion estimation and motion compensation on the received video frame, and then sends the video frame to the display screen 103. The video display is completed by the display 103.
  • FIG. 2 illustrates a method for processing a video frame according to an embodiment of the present invention.
  • an execution body is a video processing chip
  • the method for processing a video frame includes:
  • the video processing chip acquires multiple video frames.
  • the frame rate of the plurality of video frames is a first frame rate
  • the resolution of the plurality of video frames is a first resolution
  • the first resolution is an original resolution of each video frame.
  • the video processing chip decodes the video input signal received by the network interface or the digital radio frequency interface to obtain the multiple video frames, or the video processing chip directly receives the multiple video frames through the video input interface, where
  • the video input interface may be a Video Graphics Array (VGA) interface or a High Definition Multimedia Interface (HDMI).
  • VGA Video Graphics Array
  • HDMI High Definition Multimedia Interface
  • the following resolution adjustment and frame rate conversion may be directly performed on the multiple video frames, or the multiple video frames may be denoised first. Processing, and then performing the following resolution adjustment and frame rate conversion on the plurality of video frames after the denoising process.
  • whether the plurality of video frames are subjected to denoising processing is not limited, as long as the multiple videos are The frame is an original video frame, and the pixel information of the plurality of video frames at the first resolution is original pixel information.
  • the video processing chip adjusts each video frame from a first resolution to a second resolution.
  • the second resolution is a predetermined resolution of the video processing chip and the MEMC chip, and the second resolution is greater than the first resolution
  • the video processing chip needs to adjust each video frame from the first resolution to the second resolution before the video processing chip adjusts the video resolution to the second resolution.
  • the MEMC chip transmits the appointment information, the appointment information including the second resolution.
  • the second resolution is the same as the resolution of the display screen, and the display screen is used to display the view through the view The frequency processing chip and the frame stream processed by the MEMC chip.
  • the video processing chip After the video processing chip adjusts each video frame from the first resolution to the second resolution, the video processing chip sends the resolution-adjusted plurality of video frames to the MEMC chip, and the MEMC chip receives After the plurality of video frames, each video frame needs to extract a pixel region composed of all the pixels corresponding to the first resolution from the pixel region composed of all the pixels corresponding to the second resolution, to obtain each pixel frame.
  • Original pixel information of the video frame therefore, the appointment information includes location information, which is used to indicate that each pixel frame is composed of pixel regions of each pixel at the first resolution.
  • the video processing chip adjusts each video frame from the first resolution to the second resolution according to the position information, according to the position of the MEMC chip
  • the information extracts a pixel area composed of pixels corresponding to the first resolution from each of the pixel regions composed of all the pixels corresponding to the second resolution.
  • each video frame includes a plurality of pixel points, and a pixel area composed of all the pixel points of each video frame at the first resolution is a first pixel area, and each video frame is composed of all the pixel points at the second resolution.
  • the pixel area is the second pixel area, and the video processing chip adjusts each video frame from the first resolution to the second resolution, including:
  • the video processing chip For each video frame, the video processing chip adds a padding pixel region outside the first pixel region according to the position information to form a second pixel region including the first pixel region and the padding pixel region.
  • FIG. 3a depicts a pixel region composed of all pixels of a video frame at a first resolution, ie, a first pixel region
  • FIG. 3b depicts a pixel composed of all pixels at a second resolution.
  • the filling method described in FIG. 3b is only an example as long as it is outside the first pixel area.
  • the present invention does not limit the pixel value of the filled pixel area.
  • the video processing chip inserts at least one invalid frame in the multiple video frames according to the second frame rate, so that a frame rate of the transport frame stream composed of the multiple video frames and the at least one invalid frame is a second frame rate. And transmitting the transport frame stream to the MEMC chip.
  • the second frame rate is a pre-agreed frame rate of the video processing chip and the MEMC chip, and therefore, the agreement information sent by the video processing chip to the MEMC chip further includes a second frame rate, and
  • the second frame rate is greater than the first frame rate, and the unit of the frame rate is usually frame per second, that is, fps, indicating the number of frames per unit time;
  • the video processing chip Since the second frame rate is greater than the first frame rate, the video processing chip needs to insert at least one invalid frame in the plurality of video frames such that a frame rate of the transport frame stream output by the video processing chip is a second frame rate, and therefore, The function of the at least one invalid frame is to increase the frame rate of the transport frame stream output by the video processing chip to the MEMC chip to achieve a predetermined second frame rate; further, the video processing chip is configured according to the second frame rate. The video processing chip generates the at least one invalid frame before inserting at least one invalid frame in the plurality of video frames. Further, since the MEMC chip needs to identify an invalid frame in the transmission frame stream after receiving the transmission frame rate stream, the video processing chip needs to mark each invalid frame after generating the at least one invalid frame. Invalid ID, which is used to identify each invalid frame.
  • the role of the invalid frame is to increase the frame rate, and since the subsequent transmission of the frame stream consisting of the plurality of video frames and the invalid frame by the MEMC chip, it is only necessary to acquire the frame in the transport frame stream.
  • a plurality of video frames therefore, the present invention does not limit the data information contained in the invalid frames, as long as the frames that can achieve the effect of increasing the frame rate belong to the category of invalid frames.
  • each invalid frame may be a repeated frame of one video frame of the multiple video frames, and correspondingly, the invalid identifier in each invalid frame is a duplicate identifier to identify the invalid frame as a repeated frame.
  • the resolution of each frame in the transmission frame stream transmitted by the video processing chip to the MEMC chip needs to be a predetermined second resolution, the resolution of the at least one invalid frame is also required to be the second. Resolution.
  • the video processing chip since the video processing chip sends a transmission frame stream to the MEMC chip according to a predetermined resolution and a frame rate, the agreed resolution and the frame rate correspond to a fixed interface frequency, therefore,
  • the video processing chip and the MEMC chip can perform frame stream transmission according to the fixed interface frequency, and the video processing chip and the MEMC chip are used even when the resolution and frame rate of the video frame acquired by the video processing chip are changed. There is no need to adjust the interface frequency between them, it will not cause a black screen on the display, and improve the smoothness of the video played on the display.
  • FIG. 4 illustrates a method for processing a video frame according to another embodiment of the present invention.
  • the execution body is a MEMC chip
  • the method for processing the video frame includes:
  • the MEMC chip receives a transport frame stream sent by the video processing chip at a second frame rate.
  • the transmission frame stream includes a plurality of video frames and at least one invalid frame, the resolution of the plurality of video frames and the at least one invalid frame is a second resolution, and the second frame rate and the second resolution are respectively the video.
  • the MEMC chip receives the transmission frame stream sent by the video processing chip at the second frame rate.
  • the method for processing video frames further includes:
  • the MEMC chip receives the agreement information sent by the video processing chip, where the agreement information includes a second frame rate, a second resolution, and location information, where the first resolution is the original resolution of each video frame, and the second resolution is Greater than the first resolution, the position information is used to indicate that the pixel area composed of all the pixels of each video frame at the first resolution is located in the pixel area composed of all the pixels of each video frame at the second resolution. .
  • the MEMC chip receives the video processing chip at the second frame rate according to the interface frequency corresponding to the second frame rate and the second resolution.
  • the transmitted transport frame stream Since the video processing chip and the MEMC chip agree on the second frame rate and the second resolution, the MEMC chip receives the video processing chip at the second frame rate according to the interface frequency corresponding to the second frame rate and the second resolution.
  • the transmitted transport frame stream Since the video processing chip and the MEMC chip agree on the second frame rate and the second resolution, the MEMC chip receives the video processing chip at the second frame rate according to the interface frequency corresponding to the second frame rate and the second resolution.
  • the MEMC chip acquires the multiple video frames in the transport frame stream, where a frame rate of the multiple video frames is a first frame rate.
  • each invalid frame in the transport frame stream is marked with an invalid identifier
  • the invalid identifier can identify each invalid frame, and therefore, the MEMC chip can acquire the transport frame according to the invalid identifier of each invalid frame in the transport frame stream.
  • the plurality of video frames in the stream is marked with an invalid identifier
  • the frame rate of the plurality of video frames is the first frame rate, and thus the frame rate of the plurality of video frames obtained by the MEMC chip from the transport stream is the first frame rate.
  • each invalid frame may be a repeated frame of one video frame of the multiple video frames
  • the invalid identifier in each invalid frame is a duplicate identifier to identify the invalid frame as a repeated frame
  • the MEMC chip according to the The duplicate identification of each repeated frame in the transport frame stream may acquire the plurality of video frames in the transport frame stream.
  • the MEMC chip performs motion estimation and motion compensation on the plurality of video frames of the first frame rate to generate a display frame stream of the third frame rate.
  • the third frame rate satisfies the refresh rate required when the display screen displays the display frame stream, and the third frame rate is large. At the first frame rate.
  • the MEMC chip inserts a motion compensation frame between two video frames in the multiple video frames to generate a display frame stream of a third frame rate. Since the MEMC technology is prior art, the present invention The specific process of performing motion estimation and motion compensation on the MEMC chip to perform motion estimation and motion compensation on the plurality of video frames of the first frame rate to generate a display frame stream of the third frame rate is not further described.
  • the MEMC chip further records each video frame from the second resolution after acquiring the plurality of video frames and before performing motion estimation and motion compensation on the plurality of video frames of the first frame rate. Extracting a pixel region composed of all pixels corresponding to the first resolution in a pixel region composed of all the pixels to obtain original pixel information of each video frame, and performing the plurality of video frames of the first frame rate After motion estimation and motion compensation, the MEMC chip expands the resolution of each frame in the display frame stream to a third resolution, wherein the third resolution is greater than the first resolution, and the third resolution is the resolution of the display screen. Rate, as follows:
  • the location information is used to indicate that each video frame has a pixel region composed of all pixels at the first resolution, and all pixel points are located at the second resolution of each video frame.
  • a position in the pixel area of the composition a pixel area composed of all the pixels of each video frame at the first resolution is a first pixel area, and a pixel area composed of all the pixels of each video frame at the second resolution is The second pixel area includes a first pixel area and a filled pixel area, as specifically seen in Figures 3a and 3b.
  • the MEMC chip After acquiring the plurality of video frames of the second resolution, the MEMC chip extracts, according to the position information, each video frame from a pixel region composed of all pixels corresponding to the second resolution, corresponding to the first resolution. a pixel area composed of all the pixels to obtain original pixel information of each video frame. Specifically, for each video frame, the MEMC chip acquires the first pixel area from the second pixel area according to the position information, by the first The video frame composed of the pixel area is the video frame of the first resolution, that is, the original video frame.
  • the resolution of each frame in the display frame stream is a first resolution
  • the MEMC chip further needs to display each frame in the frame stream.
  • the resolution is expanded to a third resolution.
  • the MEMC chip expands the first pixel area corresponding to each frame in the display frame stream to a third pixel area corresponding to the third resolution, and the video consists of the third pixel area.
  • the frame is the video frame of the third resolution.
  • the implementation of expanding the first pixel region to the third pixel region and adjusting the first pixel region to the second pixel region is different, and expanding the first pixel region to the third pixel.
  • the region is to generate a new pixel value by interpolating a pixel value in the first pixel region to perform expansion of the pixel region, the newly generated pixel value being related to the pixel value in the first pixel region, however, the first pixel region is to be Adjusting to the second pixel area is to fill the pixel value outside the first pixel area to perform expansion of the pixel area, the filled pixel value being independent of the pixel value in the first pixel area.
  • the MEMC chip transmits the display frame stream after the resolution is expanded to the display screen, and the display screen receives the display frame stream. After the video is displayed.
  • the MEMC chip can receive the transmission frame stream sent by the video processing chip according to the pre-agreed resolution and the interface frequency corresponding to the frame rate, and the resolution of the video frame acquired by the video processing chip.
  • the rate and the frame rate change there is no need to adjust the interface frequency between the video processing chip and the MEMC chip, which does not cause a black screen on the display screen, and improves the smoothness of the video played on the display screen.
  • FIG. 5 illustrates a structure of a video processing chip 101 according to an embodiment of the present invention.
  • the video processing chip 101 includes a video frame acquiring module 501, a first video processing engine 502, and a first video output interface 503.
  • the video frame obtaining module 501 is configured to acquire a plurality of video frames, where the frame rate of the plurality of video frames is a first frame rate, the resolution of the multiple video frames is a first resolution, and the first resolution is each video.
  • the native resolution of the frame Specifically, the structure of the video frame obtaining module 501 can be as shown in FIG. 6a or 6b.
  • the video frame acquisition module 501 includes a first input interface 5001.
  • the first input interface 5001 can be a video input interface, such as a VGA or HDMI interface.
  • the video input signal received by the first input interface 5001 does not need to be decoded.
  • the received video input signal is a video frame;
  • the video frame acquisition module 501 includes a second input interface 5002 and a video decoder 5003, wherein the second input interface 5002 is configured to receive a video input signal and transmit the received video input signal.
  • the video decoder 5003 is configured to decode the received video input signal to obtain a plurality of video frames.
  • the second input interface 5002 is a network interface or a digital radio frequency interface, and the second input interface 5002 is used.
  • the received video input signal needs to be decoded to become the original video frame.
  • the video frame obtaining module 501 After acquiring the multiple video frames, the video frame obtaining module 501 sends the multiple video frames to the first video processing engine 502.
  • the first video processing engine 502 is configured to:
  • each video frame is adjusted from a first resolution to a second resolution, wherein the second resolution is a predetermined resolution of the video processing chip 101 and the MEMC chip, and second The resolution is greater than the first resolution;
  • a frame rate of the transport frame stream composed of the plurality of video frames and the at least one invalid frame is a second frame rate, wherein the second frame rate For a predetermined frame rate of the video processing chip 101 and the MEMC chip, the resolution of the at least one invalid frame is a second resolution;
  • the transport frame stream is sent to the first video output interface 503.
  • the first video processing engine 502 may directly perform resolution adjustment and frame rate conversion on the multiple video frames, or first perform denoising processing on the multiple video frames. Then, the resolution adjustment and the frame rate conversion are performed on the plurality of video frames after the denoising process.
  • whether the plurality of video frames are denoised is not limited, as long as the multiple video frames are original. Video frames are fine.
  • the first video output interface 503 is configured to receive a transport frame stream sent by the first video processing engine 502, and send the transport frame stream to the MEMC chip.
  • the video output interface can be a Low Voltage Differential Signaling (LVDS) interface or a V-by-One interface.
  • LVDS Low Voltage Differential Signaling
  • the video processing chip 101 further includes:
  • the first information contract interface 504 is configured to send the agreement information to the MEMC chip, where the agreement information includes a second frame rate, a second resolution, and location information, where the location information is used to indicate that each video frame is in the first resolution.
  • the pixel area composed of all the pixels at the time is located in the pixel area composed of all the pixels of each video frame at the second resolution.
  • the first information contract interface 504 may be a vertical blanking interval (Vertical Blanking Interval). , VBI) interface or custom interface.
  • each video frame has a pixel area composed of all pixels at the first resolution as a first pixel area, and a pixel area composed of all the pixels of each video frame at the second resolution is a second pixel area
  • the specific implementation manner of adjusting the resolution by the first video processing engine 502 is as follows:
  • a padding pixel region is added outside the first pixel region according to the position information in the appointment information to form a second pixel region including the first pixel region and the padding pixel region.
  • first video processing engine 502 is further configured to generate at least one invalid frame.
  • the first video processing engine 502 after generating the at least one invalid frame, marks an invalid identifier in each invalid frame, wherein the invalid identifier is used to identify each invalid frame.
  • each invalid frame may be a repeated frame of one video frame of the multiple video frames, and correspondingly, the invalid identifier in each invalid frame is a duplicate identifier to identify the invalid frame as a repeated frame.
  • the video processing chip provided in this embodiment sends a transmission frame stream to the MEMC chip according to a predetermined resolution and a frame rate, and the agreed resolution and frame rate correspond to a fixed interface frequency. Therefore, the video processing chip and the MEMC chip can The frame stream is transmitted according to the fixed interface frequency. Even when the resolution and the frame rate of the video frame acquired by the video processing chip are changed, there is no need to adjust the interface frequency between the video processing chip and the MEMC chip, which does not cause A black screen appears on the display to improve the smoothness of the video played on the display.
  • FIG. 7 illustrates a structure of a MEMC chip 102 provided by another embodiment of the present invention.
  • the MEMC chip 102 includes a video input interface 701, a second video processing engine 702, and a MEMC processing engine 703.
  • the video input interface 701 is configured to receive a transport frame stream sent by the video processing chip at a second frame rate, and send the transport frame stream to the second video processing engine 702, where the transport frame stream includes multiple video frames and at least An invalid frame, the resolution of the plurality of video frames and the at least one invalid frame is a second resolution, and the second frame rate and the second resolution are respectively pre-agreed frame rates of the video processing chip and the MEMC chip 102 Resolution.
  • the second video processing engine 702 is configured to acquire the multiple video frames in the transport frame stream sent by the video input interface 701, and send the multiple video frames to the MEMC processing engine 703, where the frame rate of the multiple video frames is A frame rate, in particular, the second video processing engine 702 can obtain the plurality of video frames in the transport frame stream according to the invalid identifier of each invalid frame in the transport frame stream.
  • the MEMC processing engine 703 is configured to perform motion estimation and operation on the multiple video frames of the first frame rate.
  • the motion compensation is to generate a display frame stream of a third frame rate, and the third frame rate satisfies a refresh rate required when the display screen displays the display frame stream, and the third frame rate is greater than the first frame rate.
  • the MEMC chip 102 further includes a second information contract interface 704.
  • the second information contract interface 704 is configured to receive the agreement information sent by the video processing chip, where the agreement information includes a second frame rate, a second resolution, and location information, where the location information is used to indicate that each video frame is in the first A pixel region composed of all pixels at a resolution is located in a pixel region composed of all pixels of each video frame at a second resolution, the first resolution being the original resolution of each video frame, and the second resolution The rate is greater than the first resolution.
  • the second video processing engine 702 is further configured to:
  • the first pixel area is obtained from the second pixel area according to the position information, that is, each video frame is extracted from the pixel area composed of all the pixel points corresponding to the second resolution, and the first resolution is extracted.
  • a pixel area composed of all pixels to obtain original pixel information of each video frame, and then transmitting the reduced resolution multiple video frames to the MEMC processing engine 703 for motion estimation and motion compensation;
  • the MEMC processing engine 703 is further configured to send the generated display frame stream to the second video processing engine 702.
  • the second video processing engine 702 may perform image enhancement processing, such as sharpening, on each frame in the display frame stream to improve the image. Displays the display quality of the frame stream. Therefore, the display frame stream sent by the second video processing engine 702 to the second video output interface 705 can also be subjected to image enhancement processing, which is not limited in the present invention.
  • the MEMC chip 102 also includes a second video output interface 705.
  • the second video output interface 705 is configured to receive the display frame stream after the resolution is expanded by the second video processing engine 702, and send the display frame stream with the expanded resolution to the display screen for video display.
  • the MEMC chip provided in this embodiment can receive the transport frame stream sent by the video processing chip according to the pre-agreed resolution and the interface frequency corresponding to the frame rate.
  • the resolution and frame rate of the video frame acquired by the video processing chip change, There is no need to adjust the interface frequency between the video processing chip and the MEMC chip, which does not cause a black screen on the display screen, and improves the smoothness of the video played on the display screen.
  • an embodiment of the present invention provides a terminal device 100, which includes a video processing chip 100, a MEMC chip 102, and a display screen 103.
  • Video processing chip 101 for:
  • Obtaining a plurality of video frames wherein a frame rate of the plurality of video frames is a first frame rate, a resolution of the plurality of video frames is a first resolution, and a first resolution is a original resolution of each video frame;
  • the transport frame stream is sent to the MEMC chip 102.
  • MEMC chip 102 for:
  • the display frame stream is sent to the display screen 103.
  • the display screen 103 is configured to receive and display a display frame stream output by the MEMC chip 102.
  • the specific structure of the video processing chip 101 and the MEMC chip 102 can be referred to the description of the corresponding embodiment of FIG. 5 and FIG. 7, respectively, and details are not described herein.
  • the above video processing chip 101 and MEMC chip 102 can each be implemented by digital logic circuits, each of which is used by logic operations to perform the method mentioned in the previous corresponding embodiment.
  • any of the video processing chip 101 and the MEMC chip 102 may be implemented by a general purpose processor that runs a related processing method by executing a computer software program.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the aforementioned storage medium Including: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.

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Abstract

本发明实施例公开了一种处理视频帧的方法、视频处理芯片和运动估计和运动补偿MEMC芯片，该处理视频帧的方法包括：视频处理芯片获取多个视频帧；该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率；该视频处理芯片根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率；将该传输帧流发送给MEMC芯片。由于该视频处理芯片和该MEMC芯片可以按照约定的分辨率和帧率对应的接口频率进行帧流的传输，在该视频处理芯片获取的该多个视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。

Description

处理视频帧的方法、视频处理芯片以及运动估计和运动补偿MEMC芯片
本申请要求于2015年01月04日提交中国专利局、申请号为201510003855.4，发明名称为“处理视频帧的方法、视频处理芯片以及运动估计和运动补偿MEMC芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及多媒体技术，尤其涉及一种处理视频帧的方法、视频处理芯片以及MEMC芯片。
背景技术
现有的电视和手机等终端设备，为提升用户观看视频的体验，通常采用运动估计和运动补偿(Motion Estimate and Motion Compensation，MEMC)技术以提高视频播放的流畅度，该终端设备一般包括视频处理芯片、MEMC芯片和显示屏，其中，视频处理芯片用于对接收的码流进行解码以获取视频帧，MEMC芯片用于对接收的视频帧做运动估计和运动补偿以提高视频帧的帧率，显示屏用于显示从MEMC芯片中接收的视频帧。
由于视频处理芯片获取的视频帧的帧率通常小于显示屏的刷新率，为满足显示屏刷新率的要求，MEMC芯片将视频处理芯片输出的低帧率的视频帧进行运动估计和运动补偿以输出帧率更高的视频帧，从而满足显示屏刷新率的需要。
上述现有技术存在如下技术问题：由于视频处理芯片获取的视频帧是原始视频帧，如果原始视频帧的帧率或分辨率发生改变，则视频处理芯片传输给MEMC芯片的视频帧的帧率或分辨率也会相应的发生改变，由于视频处理芯片和MEMC芯片之间约定了帧率、分辨率和接口频率的对应关系，比如，在分辨率为全高清(Full High Definition，FHD)，帧率为30fps时，视频处理芯片和MEMC之间的接口频率为74.25MHz；在分辨率为超高清(Ultra High Definition，UHD)，帧率为60fps时，视频处理芯片和MEMC之间的接口频率为297MHz，因此，在视频处理芯片传输给MEMC芯片的视频帧的帧率或分辨率发生变化时，视频处理芯片和MEMC芯片之间需要调整接口频率，即调整接口时序，这 会导致显示屏上出现短暂的黑屏，降低显示屏上播放视频的流畅度。
发明内容
本发明实施例提供了一种处理视频帧的方法、视频处理芯片以及MEMC芯片，该视频处理芯片和该MEMC芯片之间按照固定的接口频率进行帧流的传输，提高显示屏播放视频的流畅度。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，本发明提供了一种处理视频帧的方法，该方法包括：
视频处理芯片获取多个视频帧，其中，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为该视频处理芯片和MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
该视频处理芯片根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，并且将该传输帧流发送给该MEMC芯片，其中，第二帧率为噶及视频处理芯片和该MEMC芯片预先约定的帧率，该至少一个无效帧的分辨率为第二分辨率。
结合第一方面，在第一种可能的实现方式中，该方法还包括：
该视频处理芯片向该MEMC芯片发送约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置。
结合第一方面的第一种可能的实现方式，在第二种可能的实现方式中，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，则该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率包括：
针对每个视频帧，该视频处理芯片根据该位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
结合第一方面，或者第一方面的第一或第二种可能的实现方式，在第三种可能的实现方式中，该视频处理芯片根据第二帧率在该多个视频帧中插入至少一个无效帧之前，该方法还包括：
该视频处理芯片生成该至少一个无效帧。
结合第一方面的第三种可能的实现方式，在第四种可能的实现方式中，在该视频处理芯片生成该至少一个无效帧之后，该方法还包括：
该视频处理芯片在每个无效帧中标记无效标识，该无效标识用于标识每个无效帧。
结合第一方面，或者第一方面的第一或第二或第三或第四种可能的实现方式，在第五种可能的实现方式中，第二分辨率与显示屏的分辨率相同，该显示屏用于显示经过该视频处理芯片和该MEMC芯片处理后的帧流。
结合第一方面，或者第一方面的第一或第二或第三或第四或第五种可能的实现方式，在第六种可能的实现方式中，每个无效帧为该多个视频帧中一个视频帧的重复帧。
第二方面，本发明提供了另一种处理视频帧的方法，该方法包括：
MEMC芯片接收视频处理芯片以第二帧率发送的传输帧流，其中，该传输帧流包括多个视频帧和至少一个无效帧，该多个视频帧和所述至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为该视频处理芯片和该MEMC芯片预先约定的帧率和分辨率；
该MEMC芯片获取该传输帧流中该多个视频帧，被获取的该多个视频帧的帧率为第一帧率；
该MEMC芯片将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大于第一帧率。
结合第二方面，在第一种可能的实现方式中，在MEMC芯片接收视频处理芯片以第二帧率发送的传输帧流之前，该方法还包括：
该MEMC芯片接收该视频处理芯片发送的约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像 素点组成的像素区域中的位置，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率。
结合第二方面的第一种可能的实现方式，在第二种可能的实现方式中，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，在该MEMC芯片将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流之前，该方法还包括：
针对每个视频帧，该MEMC芯片根据该位置信息从第二像素区域中获取第一像素区域；
在该MEMC芯片将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流之后，该方法还包括：
该MEMC芯片将该显示帧流中每帧的分辨率扩大为第三分辨率，其中，第三分辨率为该显示屏的分辨率，第三分辨率大于第一分辨率。
结合第一方面，或者第一方面的第一或第二种可能的实现方式，在第三种可能的实现方式中，每个无效帧包括无效标识，该MEMC芯片获取该传输帧流中该多个视频帧包括：
该MEMC芯片根据该传输流中每个无效帧的无效标识获取该传输帧流中该多个视频帧。
结合第一方面，或者第一方面的第一或第二或第三种可能的实现方式，在第四种可能的实现方式中，每个无效帧为该多个视频帧中一个视频帧的重复帧。
结合第二方面的第二种可能的实现方式，在第五种可能的实现方式中，在该MEMC芯片将该显示帧流中每帧的分辨率扩大为第三分辨率之后，该方法还包括：
该MEMC芯片将分辨率扩大后的该显示帧流发送给该显示屏。
第三方面，本发明提供一种视频处理芯片，该视频处理芯片包括：
视频帧获取模块，用于获取多个视频帧，并且将该多个视频帧发送给第一视频处理引擎，其中，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
第一视频处理引擎，用于：
接收该视频帧获取模块发送的该多个视频帧；
将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为该视频处理芯片和MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为该视频处理芯片和该MEMC芯片预先约定的帧率，该至少一个无效帧的分辨率为第二分辨率；
将该传输帧流发送给第一视频输出接口；以及，
该第一视频输出接口，用于接收第一视频处理引擎发送的该传输帧流，并且将该传输帧流发送给该MEMC芯片。
结合第三方面，在第一种可能的实现方式中，该视频处理芯片还包括：
第一信息约定接口，用于向该MEMC芯片发送约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置。
结合第三方面的第一种可能的实现，在第二种可能的实现方式中，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，该第一视频处理引擎具体包括：
针对每个视频帧，用于根据该位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
结合第三方面，或者第三方面的第一或第二种可能的实现方式，在第三种可能的实现方式中，该第一视频处理引擎还用于：
生成至少一个无效帧。
结合第三方面的第三种可能的实现方式，在第四种可能的实现方式中，该第一视频处理引擎还用于：
在每个无效帧中标记无效标识，该无效标识用于标识每个无效帧。
第四方面，本发明提供一种MEMC芯片，该MEMC芯片包括：
视频输入接口，用于接收视频处理芯片以第二帧率发送的传输帧流，并且将该传输帧流发送给第二视频处理引擎，其中，该传输帧流包括多个视频帧和至少一个无效帧，该多个视频帧和该至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为该视频处理芯片和该MEMC芯片预先约定的帧率和分辨率；
所述第二视频处理引擎，用于获取该传输帧流中该多个视频帧，该多个视频帧的帧率为第一帧率，并且将该多个视频帧发送给MEMC处理引擎；以及，
该MEMC处理引擎，用于将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大于第一帧率。
结合第四方面，在第一种可能的实现方式中，该MEMC芯片还包括：
第二信息约定接口，用于接收该视频处理芯片发送的约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率。
结合第四方面的第一种可能的实现方式，在第二种可能的实现方式中，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，该第二视频处理引擎还用于：
针对每个视频帧，根据该位置信息从第二像素区域中获取第一像素区域；
接收该MEMC处理引擎发送的该显示帧流，将该显示帧流中每帧的分辨率扩大为第三分辨率，并且将分辨率扩大后的该显示帧流发送给第二视频输出接口，其中，第三分辨率为所述显示屏的分辨率，第三分辨率大于第一分辨率；
该MEMC处理引擎，还用于将生成的显示帧流发送给该第二视频处理引擎。
结合第四方面，或者第四方面的第一或第二种可能的实现方式，在第三种可能的实现方式中，该MEMC处理引擎具体包括：
用于根据该传输帧流中每个无效帧的无效标识获取该传输帧流中该多个 视频帧。
结合第四方面的第二种可能的实现方式，该MEMC处理引擎还包括：
第二视频输出接口，用于接收第二视频处理引擎发送的分辨率扩大后的该显示帧流，并且将分辨率扩大后的该显示帧流发送给该显示屏。
第五方面，本发明提供了一种终端设备，包括：
视频处理芯片，用于：
获取多个视频帧，其中，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为该视频处理芯片和MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为该视频处理芯片和该MEMC芯片预先约定的帧率，该至少一个无效帧的分辨率为第二分辨率；
将该传输帧流发送给该MEMC芯片；
该MEMC芯片，用于：
接收该视频处理芯片以第二帧率发送的传输帧流；
获取该传输帧流中该多个视频帧，被获取的该多个视频帧的帧率为第一帧率；
将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，其中，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大于第一帧率；
将该显示帧流发送给该显示屏；以及，
该显示屏，用于接收并显示该MEMC芯片输出的该显示帧流。
在本发明实施例提供的处理视频帧的方法中，由于该视频处理芯片按照预先约定的分辨率和帧率向MEMC芯片发送传输帧流，而约定的分辨率和帧率对应固定的接口频率，因此，该视频处理芯片和该MEMC芯片可以按照该固定的接口频率进行帧流的传输，即使在该视频处理芯片获取的视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会 导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的终端设备的结构；
图2为本发明一个实施例提供的处理视频帧的方法的流程图；
图3a为本发明提供的一个视频帧在第一分辨率时的像素区域；
图3b为本发明提供的一个视频帧在第二分辨率时的像素区域；
图4为本发明另一个实施例提供的处理视频帧的方法的流程图；
图5为本发明一个实施例提供的视频处理芯片的结构；
图6a为图5描述的视频处理芯片结构中视频帧获取模块的一种结构；
图6b为图5描述的视频处理芯片结构中视频帧获取模块的另一种结构；
图7为本发明一个实施例提供的MEMC芯片的结构。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1描述了本发明所涉及的终端设备的结构，该终端设备100包括视频处理芯片101、MEMC芯片102和显示屏103，其中，终端设备100为具备视频处理和显示能力的设备，比如电视、手机等，视频处理芯片101和MEMC芯片102可以为两个独立的芯片，也可以为一个集成芯片里的两个模块，一般地，视频处理芯片101可以理解为终端设备100的主芯片。
结合图1介绍本发明涉及的技术方案的总体思路：视频处理芯片101获取到原始视频帧后，对原始视频帧按照预先和MEMC芯片102约定的分辨率和帧率 分别进行分辨率调整和帧率调整，将做上述调整后的视频帧发送给MEMC芯片102，MEMC芯片102对接收到的视频帧进行运动估计和运动补偿等相关处理后再发送给显示屏103，由显示屏103完成视频显示。
为更好理解上述技术方案，下面将结合具体的实施例对上述技术方案进行详细的说明。
图2描述了本发明实施例提供的一种处理视频帧的方法，本实施例中执行主体为视频处理芯片，该处理视频帧的方法包括：
S201、该视频处理芯片获取多个视频帧。
其中，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率。
具体的，该视频处理芯片对由网络接口或数字射频接口接收到的视频输入信号进行解码以获取该多个视频帧，或者，该视频处理芯片通过视频输入接口直接接收该多个视频帧，其中，该视频输入接口具体可以为视频图形阵列(Video Graphics Array，VGA)接口或高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)等。
需要说明的是，该视频处理芯片在获取到该多个视频帧后，可以直接对该多个视频帧进行如下的分辨率调整和帧率转换，也可以首先对该多个视频帧进行去噪处理，然后再对经过去噪处理后的该多个视频帧进行如下的分辨率调整和帧率转换，本发明中对该多个视频帧是否经过去噪处理不做限定，只要该多个视频帧为原始视频帧即可，该多个视频帧在第一分辨率时的像素信息为原始像素信息。
S202、该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率。
其中，第二分辨率为该视频处理芯片和MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
由于第二分辨率为该视频处理芯片和MEMC芯片预先约定的分辨率，因此，该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率之前，该视频处理芯片还需要向该MEMC芯片发送约定信息，该约定信息包括第二分辨率。
优选地，第二分辨率与显示屏的分辨率相同，该显示屏用于显示经过该视 频处理芯片和该MEMC芯片处理后的帧流。
由于该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率后，该视频处理芯片会将分辨率调整后的该多个视频帧发送给该MEMC芯片，该MEMC芯片在接收到该多个视频帧后，还需要将每个视频帧从第二分辨率对应的所有像素点组成的像素区域中提取出第一分辨率对应的所有像素点组成的像素区域，以获取每个视频帧的原始像素信息，因此，该约定信息除了包含第二分辨率，还包含位置信息，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，该视频处理芯片根据该位置信息将每个视频帧从第一分辨率调整为第二分辨率，该MEMC芯片根据该位置信息将每个视频帧从第二分辨率对应的所有像素点组成的像素区域中提取出第一分辨率对应的像素点组成的像素区域。
具体的，每个视频帧包括多个像素点，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，则该视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率包括：
针对每个视频帧，该视频处理芯片根据该位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
为方便理解，图3a描述了一个视频帧在第一分辨率时所有像素点组成的像素区域，即第一像素区域，图3b描述了一个视频帧在第二分辨率时所有像素点组成的像素区域，即第二像素区域，由图3b可知，第二像素区域包括第一像素区域和填充像素区域，该填充像素区域不需要如图3b所示一定要分布在第一像素区域的四周填充，只要在第一像素区域之外即可，图3b描述的填充方式只是一种示例，另外，本发明对该填充像素区域的像素值不做限定。
S203、该视频处理芯片根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，将该传输帧流发送给该MEMC芯片。
其中，第二帧率为该视频处理芯片和该MEMC芯片预先约定的帧率，因此上述该视频处理芯片向该MEMC芯片发送的约定信息中还包括第二帧率，并且 第二帧率大于第一帧率，帧率的单位通常为frame per second，即fps，表示每单位时间内帧的数量；
由于第二帧率大于第一帧率，该视频处理芯片需要在该多个视频帧中插入至少一个无效帧以使得该视频处理芯片输出的传输帧流的帧率为第二帧率，因此，该至少一个无效帧的作用是为了使得该视频处理芯片向该MEMC芯片输出的传输帧流的帧率得到提高，以达到预先约定的第二帧率；进一步，该视频处理芯片根据第二帧率在该多个视频帧中插入至少一个无效帧之前，该视频处理芯片生成该至少一个无效帧。进一步，由于该MEMC芯片在接收到该传输帧率流后需要识别出该传输帧流中的无效帧，因此，该视频处理芯片在生成该至少一个无效帧后，需要在每个无效帧中标记无效标识，该无效标识用于识别每个无效帧。
本发明中，无效帧的作用是为了提高帧率，并且，由于在后续该MEMC芯片接收到由该多个视频帧和无效帧组成的传输帧流之后，只需要获取该传输帧流中的该多个视频帧，因此，本发明对无效帧所包含的数据信息不予限制，只要是能达到提高帧率效果的帧都属于无效帧的范畴。
优选地，每个无效帧可以是该多个视频帧中一个视频帧的重复帧，相应地，每个无效帧中的无效标识为重复标识，以标识该无效帧为重复帧。需要说明的是，由于该视频处理芯片传输给该MEMC芯片的传输帧流中每帧的分辨率都需要为预先约定的第二分辨率，因此该至少一个无效帧的分辨率也要求为第二分辨率。
本实施例提供的处理视频帧的方法中，由于该视频处理芯片按照预先约定的分辨率和帧率向MEMC芯片发送传输帧流，而约定的分辨率和帧率对应固定的接口频率，因此，该视频处理芯片和该MEMC芯片可以按照该固定的接口频率进行帧流的传输，即使在该视频处理芯片获取的视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。
图4描述了本发明另一个实施例提供的一种处理视频帧的方法，本实施例中执行主体为MEMC芯片，该处理视频帧的方法包括：
S401、该MEMC芯片接收视频处理芯片以第二帧率发送的传输帧流。
其中，该传输帧流包括多个视频帧和至少一个无效帧，该多个视频帧和该至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为该视频处理芯片和该MEMC芯片预先约定的帧率和分辨率；
由于第二帧率和第二分辨率分别为该视频处理芯片和该MEMC芯片预先约定的帧率和分辨率，因此，在该MEMC芯片接收该视频处理芯片以第二帧率发送的传输帧流之前，该处理视频帧的方法还包括：
该MEMC芯片接收该视频处理芯片发送的约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置。
由于该视频处理芯片和该MEMC芯片约定了第二帧率和第二分辨率，因此，该MEMC芯片按照第二帧率和第二分辨率对应的接口频率接收该视频处理芯片以第二帧率发送的传输帧流。
S402、该MEMC芯片获取该传输帧流中该多个视频帧，该多个视频帧的帧率为第一帧率。
由于该传输帧流中每个无效帧都被标记了无效标识，该无效标识可以识别每个无效帧，因此，该MEMC芯片根据该传输帧流中每个无效帧的无效标识可以获取该传输帧流中的该多个视频帧。
由图2描述的实施例可知，该多个视频帧的帧率为第一帧率，因此该MEMC芯片从该传输流中获取的该多个视频帧的帧率为第一帧率。
优选地，每个无效帧可以是该多个视频帧中一个视频帧的重复帧，则每个无效帧中的无效标识为重复标识，以标识该无效帧为重复帧，则该MEMC芯片根据该传输帧流中每个重复帧的重复标识可以获取该传输帧流中的该多个视频帧。
S403、该MEMC芯片将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流。
其中，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大 于第一帧率。
具体的，通过采用MEMC技术，该MEMC芯片在该多个视频帧中前后两个视频帧之间插入运动补偿帧以生成第三帧率的显示帧流，由于MEMC技术是现有技术，本发明对该MEMC芯片将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流的具体过程不做进一步说明。
进一步，该MEMC芯片在获取到该多个视频帧之后以及在将第一帧率的该多个视频帧进行运动估计和运动补偿之前，该MEMC芯片还将每个视频帧从第二分辨率对应的所有像素点组成的像素区域中提取出第一分辨率对应的所有像素点组成的像素区域，以获取每个视频帧的原始像素信息，并且在将第一帧率的该多个视频帧进行运动估计和运动补偿之后，该MEMC芯片将该显示帧流中每帧的分辨率扩大为第三分辨率，其中，第三分辨率大于第一分辨率，第三分辨率为该显示屏的分辨率，具体如下：
由于该MEMC芯片接收的约定信息中包括位置信息，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，第二像素区域包括第一像素区域和填充像素区域，具体可以参见图3a和图3b。
该MEMC芯片在获取到第二分辨率的该多个视频帧之后，按照该位置信息将每个视频帧从第二分辨率对应的所有像素点组成的像素区域中提取出第一分辨率对应的所有像素点组成的像素区域，以获取每个视频帧的原始像素信息，具体的，针对每个视频帧，该MEMC芯片根据该位置信息从第二像素区域中获取第一像素区域，由第一像素区域组成的视频帧为第一分辨率的视频帧，即为原始视频帧。
在将第一帧率的该多个视频帧进行运动估计和运动补偿之后，该显示帧流中每帧的分辨率为第一分辨率，该MEMC芯片还需要将该显示帧流中每帧的分辨率扩大为第三分辨率，具体的，该MEMC芯片将该显示帧流中每帧对应的第一像素区域扩大为第三分辨率对应的第三像素区域，由第三像素区域组成的视频帧即为第三分辨率的视频帧。
需要说明的是，本发明中，将第一像素区域扩大为第三像素区域和将第一像素区域调整为第二像素区域的实现方式是不一样的，将第一像素区域扩大为第三像素区域是将第一像素区域中的像素值通过插值运算生成新的像素值以进行像素区域的扩充，该新生成的像素值与第一像素区域中的像素值相关，然而，将第一像素区域调整为第二像素区域是在第一像素区域之外填充像素值以进行像素区域的扩充，该填充的像素值与第一像素区域中像素值无关。
进一步，在该MEMC将该显示帧流中每帧的分辨率扩大为第三分辨之后，该MEMC芯片将分辨率扩大后的该显示帧流发送给该显示屏，该显示屏接收到显示帧流后进行视频显示。
本实施例提供的处理视频帧的方法中，该MEMC芯片可以按照预先约定的分辨率和帧率对应的接口频率接收视频处理芯片发送的传输帧流，在该视频处理芯片获取的视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。
上文中结合图2至图4，详细描述了本发明实施例提供的处理视频帧的方法，下面将结合图5至图7，详细描述本发明实施例提供的视频处理芯片和MEMC芯片。
图5描述了本发明一个实施例提供的视频处理芯片101的结构，该视频处理芯片101包括：视频帧获取模块501、第一视频处理引擎502和第一视频输出接口503。
视频帧获取模块501，用于获取多个视频帧，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率。具体的，视频帧获取模块501的结构可以如图6a或图6b所示。
图6a中，视频帧获取模块501包括第一输入接口5001，第一输入接口5001可以为视频输入接口，如VGA或HDMI接口，第一输入接口5001接收的视频输入信号无需经过解码，此种情况，接收的视频输入信号即为视频帧；
图6b中，视频帧获取模块501包括第二输入接口5002和视频解码器5003，其中，第二输入接口5002用于接收视频输入信号并且将接收的视频输入信号发 送给视频解码器5003，视频解码器5003用于对接收的视频输入信号进行解码以获取多个视频帧，此种情况，第二输入接口5002为网络接口或数字射频接口，第二输入接口5002接收的视频输入信号需要经过解码才能成为原始视频帧。
视频帧获取模块501在获取该多个视频帧后，将该多个视频帧发送给第一视频处理引擎502。
第一视频处理引擎502，用于：
接收视频帧获取模块501发送的该多个视频帧，；
在获取到该多个视频帧后，将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为该视频处理芯片101和MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
根据第二帧率在该多个视频帧中插入至少一个无效帧以使得该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为该视频处理芯片101和该MEMC芯片预先约定的帧率，该至少一个无效帧的分辨率为第二分辨率；
将该传输帧流发送给第一视频输出接口503。
需要说明的是，第一视频处理引擎502在获取该多个视频帧后，可以直接对该多个视频帧进行分辨率调整和帧率转换，也可以首先对该多个视频帧进行去噪处理，然后再对经过去噪处理后的该多个视频帧进行分辨率调整和帧率变换，本发明中对该多个视频帧是否经过去噪处理不做限定，只要该多个视频帧为原始视频帧即可。
第一视频输出接口503，用于接收第一视频处理引擎502发送的传输帧流，并且将该传输帧流发送给该MEMC芯片。具体的，该视频输出接口可以为低压差分信号(Low Voltage Differential Signaling，LVDS)接口或V-by-One接口。
进一步，该视频处理芯片101还包括：
第一信息约定接口504，用于向该MEMC芯片发送约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，具体的，第一信息约定接口504可以为垂直消隐期(Vertical Blanking Interval，VBI)接口或者自定义接口。
相应地，假设每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，则第一视频处理引擎502调整分辨率的具体实现方式如下：
针对每个视频帧，根据该约定信息中的位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
进一步，第一视频处理引擎502还用于生成至少一个无效帧。
第一视频处理引擎502在生成上述至少一个无效帧之后，在每个无效帧中标记无效标识，其中，该无效标识用于标识每个无效帧。
优选地，每个无效帧可以是该多个视频帧中一个视频帧的重复帧，相应地，每个无效帧中的无效标识为重复标识，以标识该无效帧为重复帧。
本实施例提供的视频处理芯片按照预先约定的分辨率和帧率向MEMC芯片发送传输帧流，而约定的分辨率和帧率对应固定的接口频率，因此，该视频处理芯片和该MEMC芯片可以按照该固定的接口频率进行帧流的传输，即使在该视频处理芯片获取的视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。
图7描述了本发明又一个实施例提供的MEMC芯片102的结构，该MEMC芯片102包括：视频输入接口701、第二视频处理引擎702和MEMC处理引擎703。
视频输入接口701，用于接收视频处理芯片以第二帧率发送的传输帧流，并且将该传输帧流发送给第二视频处理引擎702，其中，该传输帧流包括多个视频帧和至少一个无效帧，该多个视频帧和该至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为该视频处理芯片和该MEMC芯片102预先约定的帧率和分辨率。
第二视频处理引擎702，用于获取视频输入接口701发送的传输帧流中该多个视频帧，并且将该多个视频帧发送给MEMC处理引擎703，该多个视频帧的帧率为第一帧率，具体的，第二视频处理引擎702可以根据该传输帧流中每个无效帧的无效标识获取该传输帧流中该多个视频帧。
MEMC处理引擎703，用于将第一帧率的该多个视频帧进行运动估计和运 动补偿以生成第三帧率的显示帧流，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大于第一帧率。
进一步，该MEMC芯片102还包括第二信息约定接口704。
第二信息约定接口704，用于接收该视频处理芯片发送的约定信息，该约定信息包括第二帧率、第二分辨率和位置信息，其中，该位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率。
假设每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，则该第二视频处理引擎702在获取该传输帧流中该多个视频帧之后，还用于：
针对每个视频帧，根据该位置信息从第二像素区域中获取第一像素区域，即将每个视频帧从第二分辨率对应的所有像素点组成的像素区域中提取出第一分辨率对应的所有像素点组成的像素区域，以获取每个视频帧的原始像素信息，然后再将分辨率缩小后的该多个视频帧发送给MEMC处理引擎703以做运动估计和运动补偿；
接收MEMC处理引擎703发送的显示帧流，将该显示帧流中每帧的分辨率扩大为第三分辨率，并且将分辨率扩大后的该显示帧流发送给第二视频输出接口705，其中，第三分辨率为该显示屏的分辨率，第三分辨率大于第一分辨率。
相应地，MEMC处理引擎703还用于将生成的显示帧流发送给第二视频处理引擎702。需要说明的是，第二视频处理引擎702除了扩大该显示帧流中每帧的分辨率之外，还可以对该显示帧流中的每帧进行图像增强处理，比如锐化等，以提高该显示帧流的显示质量。因此，第二视频处理引擎702向第二视频输出接口705发送的显示帧流还可以经过图像增强处理，本发明对此不做限制。
该MEMC芯片102还包括第二视频输出接口705。
第二视频输出接口705用于接收第二视频处理引擎702发送的分辨率扩大后的该显示帧流，并且将分辨率扩大后的该显示帧流发送给该显示屏以作视频显示。
本实施例提供的MEMC芯片可以按照预先约定的分辨率和帧率对应的接口频率接收视频处理芯片发送的传输帧流，在该视频处理芯片获取的视频帧的分辨率和帧率发生变化时，该视频处理芯片和该MEMC芯片之间无需调整接口频率，不会导致显示屏上出现黑屏，提高显示屏播放视频的流畅度。
结合图1，本发明一个实施例提供了终端设备100，该终端设备100包括视频处理芯片100、MEMC芯片102以及显示屏103。
视频处理芯片101，用于：
获取多个视频帧，其中，该多个视频帧的帧率为第一帧率，该多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为视频处理芯片101和MEMC芯片102预先约定的分辨率，第二分辨率大于第一分辨率；
根据第二帧率在该多个视频帧中插入至少一个无效帧以使得由该多个视频帧和该至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为视频处理芯片101和MEMC芯片102预先约定的帧率，该至少一个无效帧的分辨率为第二分辨率；
将该传输帧流发送给MEMC芯片102。
MEMC芯片102，用于：
接收视频处理芯片以第二帧率发送的传输帧流；
获取该传输帧流中该多个视频帧，被获取的该多个视频帧的帧率为第一帧率；
将第一帧率的该多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，其中，第三帧率满足显示屏显示该显示帧流时所需的刷新率，第三帧率大于第一帧率；
将该显示帧流发送给显示屏103。
显示屏103，用于接收并显示MEMC芯片102输出的显示帧流。
视频处理芯片101和MEMC芯片102的具体结构可分别参考图5和图7对应的实施例的描述，在此不予赘述。
以上视频处理芯片101和MEMC芯片102分别可以通过数字逻辑电路来实现，每个数字逻辑电路通过逻辑运算用来执行之前对应实施例所提到的方法。或者可以通过视频处理芯片101和MEMC芯片102的任一个可通过通用处理器实现，所述通用处理器通过执行计算机软件程序运行相关处理方法。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质 包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (24)

  1. 一种处理视频帧的方法，其特征在于，包括：
    视频处理芯片获取多个视频帧，其中，所述多个视频帧的帧率为第一帧率，所述多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
    所述视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为所述视频处理芯片和运动估计和运动补偿MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
    所述视频处理芯片根据第二帧率在所述多个视频帧中插入至少一个无效帧以使得由所述多个视频帧和所述至少一个无效帧组成的传输帧流的帧率为第二帧率，并且将所述传输帧流发送给所述MEMC芯片，其中，第二帧率为所述视频处理芯片和所述MEMC芯片预先约定的帧率，所述至少一个无效帧的分辨率为第二分辨率。
  2. 如权利要求1所述的处理视频帧的方法，其特征在于，所述方法还包括：
    所述视频处理芯片向所述MEMC芯片发送约定信息，所述约定信息包括第二帧率、第二分辨率和位置信息，其中，所述位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置。
  3. 如权利要求2所述的处理视频帧的方法，其特征在于，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，所述视频处理芯片将每个视频帧从第一分辨率调整为第二分辨率包括：
    针对每个视频帧，所述视频处理芯片根据所述位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
  4. 如权利要求1-3任一所述的处理视频帧的方法，其特征在于，所述视频处理芯片根据第二帧率在所述多个视频帧中插入至少一个无效帧之前，所述方法还包括：
    所述视频处理芯片生成所述至少一个无效帧。
  5. 如权利要求4所述的处理视频帧的方法，其特征在于，在所述视频处理芯片生成所述至少一个无效帧之后，所述方法还包括：
    所述视频处理芯片在每个无效帧中标记无效标识，其中，所述无效标识用于标识每个无效帧。
  6. 如权利要求1-5任一所述的处理视频帧的方法，其特征在于，第二分辨率与显示屏的分辨率相同，所述显示屏用于显示经过所述视频处理芯片和所述MEMC芯片处理后的帧流。
  7. 如权利要求1-6任一所述的处理视频帧的方法，其特征在于，每个无效帧为所述多个视频帧中一个视频帧的重复帧。
  8. 一种处理视频帧的方法，其特征在于，包括：
    运动估计和运动补偿MEMC芯片接收视频处理芯片以第二帧率发送的传输帧流，其中，所述传输帧流包括多个视频帧和至少一个无效帧，所述多个视频帧和所述至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为所述视频处理芯片和所述MEMC芯片预先约定的帧率和分辨率；
    所述MEMC芯片获取所述传输帧流中所述多个视频帧，被获取的所述多个视频帧的帧率为第一帧率；
    所述MEMC芯片将第一帧率的所述多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，第三帧率满足显示屏显示所述显示帧流时所需的刷新率，第三帧率大于第一帧率。
  9. 如权利要求8所述的处理视频帧的方法，其特征在于，在MEMC芯片接收视频处理芯片以第二帧率发送的传输帧流之前，所述方法还包括：
    所述MEMC芯片接收所述视频处理芯片发送的约定信息，所述约定信息包括第二帧率、第二分辨率和位置信息，其中，所述位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率。
  10. 如权利要求9所述的处理视频帧的方法，其特征在于，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，在所述MEMC芯片将第 一帧率的所述多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流之前，所述方法还包括：
    针对每个视频帧，所述MEMC芯片根据所述位置信息从第二像素区域中获取第一像素区域；
    在所述MEMC芯片将第一帧率的所述多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流之后，所述方法还包括：
    所述MEMC芯片将所述显示帧流中每帧的分辨率扩大为第三分辨率，其中，第三分辨率为所述显示屏的分辨率，第三分辨率大于第一分辨率。
  11. 如权利要求8-10任一所述的处理视频帧的方法，其特征在于，每个无效帧包括无效标识，
    所述MEMC芯片获取所述传输帧流中所述多个视频帧包括：
    所述MEMC芯片根据所述传输流中每个无效帧的无效标识获取所述传输帧流中所述多个视频帧。
  12. 如权利要求8-11任一所述的处理视频帧的方法，其特征在于，每个无效帧为所述多个视频帧中一个视频帧的重复帧。
  13. 如权利要求10所述的处理视频帧的方法，其特征在于，在所述MEMC芯片将所述显示帧流中每帧的分辨率扩大为第三分辨率之后，所述方法还包括：
    所述MEMC芯片将分辨率扩大后的所述显示帧流发送给所述显示屏。
  14. 一种视频处理芯片，其特征在于，包括：
    视频帧获取模块，用于获取多个视频帧，并且将所述多个视频帧发送给第一视频处理引擎，其中，所述多个视频帧的帧率为第一帧率，所述多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
    第一视频处理引擎，用于：
    接收所述视频帧获取模块发送的所述多个视频帧；
    将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为所述视频处理芯片和运动估计和运动补偿MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
    根据第二帧率在所述多个视频帧中插入至少一个无效帧以使得由所述多 个视频帧和所述至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为所述视频处理芯片和所述MEMC芯片预先约定的帧率，所述至少一个无效帧的分辨率为第二分辨率；
    将所述传输帧流发送给第一视频输出接口；以及，
    所述第一视频输出接口，用于接收第一视频处理引擎发送的所述传输帧流，并且将所述传输帧流发送给所述MEMC芯片。
  15. 如权利要求14所述的视频处理芯片，其特征在于，还包括：
    第一信息约定接口，用于向所述MEMC芯片发送约定信息，所述约定信息包括第二帧率、第二分辨率和位置信息，其中，所述位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置。
  16. 如权利要求15所述的视频处理芯片，其特征在于，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，所述第一视频处理引擎具体包括：
    针对每个视频帧，用于根据所述位置信息在第一像素区域之外增加填充像素区域以形成包括第一像素区域和填充像素区域的第二像素区域。
  17. 如权利要求14-16任一所述的视频处理芯片，其特征在于，所述第一视频处理引擎还用于：
    生成所述至少一个无效帧。
  18. 如权利要求17所述的视频处理芯片，其特征在于，所述第一视频处理引擎还用于：
    在每个无效帧中标记无效标识，其中，所述无效标识用于标识每个无效帧。
  19. 一种运动估计和运动补偿MEMC芯片，其特征在于，包括：
    视频输入接口，用于接收视频处理芯片以第二帧率发送的传输帧流，并且将所述传输帧流发送给第二视频处理引擎，其中，所述传输帧流包括多个视频帧和至少一个无效帧，所述多个视频帧和所述至少一个无效帧的分辨率为第二分辨率，第二帧率和第二分辨率分别为所述视频处理芯片和所述MEMC芯片预先约定的帧率和分辨率；所述第二视频处理引擎，用于获取所述传输帧流中所 述多个视频帧，所述多个视频帧的帧率为第一帧率，并且将所述多个视频帧发送给MEMC处理引擎；以及，
    所述MEMC处理引擎，用于将第一帧率的所述多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，第三帧率满足显示屏显示所述显示帧流时所需的刷新率，第三帧率大于第一帧率。
  20. 如权利要求19所述的MEMC芯片，其特征在于，所述MEMC芯片还包括：
    第二信息约定接口，用于接收所述视频处理芯片发送的约定信息，所述约定信息包括第二帧率、第二分辨率和位置信息，其中，所述位置信息用于指示每个视频帧在第一分辨率时所有像素点组成的像素区域位于每个视频帧在第二分辨率时所有像素点组成的像素区域中的位置，第一分辨率为每个视频帧的原始分辨率，第二分辨率大于第一分辨率。
  21. 如权利要求20所述的MEMC芯片，其特征在于，每个视频帧在第一分辨率时所有像素点组成的像素区域为第一像素区域，每个视频帧在第二分辨率时所有像素点组成的像素区域为第二像素区域，所述第二视频处理引擎还用于：
    针对每个视频帧，根据所述位置信息从第二像素区域中获取第一像素区域；
    接收所述MEMC处理引擎发送的所述显示帧流，将所述显示帧流中每帧的分辨率扩大为第三分辨率，并且将分辨率扩大后的所述显示帧流发送给第二视频输出接口，其中，第三分辨率为所述显示屏的分辨率，第三分辨率大于第一分辨率；
    所述MEMC处理引擎，还用于将生成的显示帧流发送给所述第二视频处理引擎。
  22. 如权利要求19-21任一所述的MEMC芯片，其特征在于，所述MEMC处理引擎具体包括：
    用于根据所述传输帧流中每个无效帧的无效标识获取所述传输帧流中所述多个视频帧。
  23. 如权利要求21所述的MEMC芯片，其特征在于，还包括：
    所述第二视频输出接口，用于接收第二视频处理引擎发送的分辨率扩大后的所述显示帧流，并且将分辨率扩大后的所述显示帧流发送给所述显示屏。
  24. 一种终端设备，其特征在于，包括：
    视频处理芯片，用于：
    获取多个视频帧，其中，所述多个视频帧的帧率为第一帧率，所述多个视频帧的分辨率为第一分辨率，第一分辨率为每个视频帧的原始分辨率；
    将每个视频帧从第一分辨率调整为第二分辨率，其中，第二分辨率为所述视频处理芯片和运动估计和运动补偿MEMC芯片预先约定的分辨率，第二分辨率大于第一分辨率；
    根据第二帧率在所述多个视频帧中插入至少一个无效帧以使得由所述多个视频帧和所述至少一个无效帧组成的传输帧流的帧率为第二帧率，其中，第二帧率为所述视频处理芯片和所述MEMC芯片预先约定的帧率，所述至少一个无效帧的分辨率为第二分辨率；
    将所述传输帧流发送给所述MEMC芯片；
    所述MEMC芯片，用于：
    接收所述视频处理芯片以第二帧率发送的传输帧流；
    获取所述传输帧流中所述多个视频帧，被获取的所述多个视频帧的帧率为第一帧率；
    将第一帧率的所述多个视频帧进行运动估计和运动补偿以生成第三帧率的显示帧流，其中，第三帧率满足显示屏显示所述显示帧流时所需的刷新率，第三帧率大于第一帧率；
    将所述显示帧流发送给所述显示屏；以及，
    所述显示屏，用于接收并显示所述MEMC芯片输出的所述显示帧流。
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