WO2016107123A1 - 多电平拓扑的电路和功率变换器 - Google Patents

多电平拓扑的电路和功率变换器 Download PDF

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Publication number
WO2016107123A1
WO2016107123A1 PCT/CN2015/083023 CN2015083023W WO2016107123A1 WO 2016107123 A1 WO2016107123 A1 WO 2016107123A1 CN 2015083023 W CN2015083023 W CN 2015083023W WO 2016107123 A1 WO2016107123 A1 WO 2016107123A1
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Prior art keywords
terminal
switch
switch component
state
component
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PCT/CN2015/083023
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English (en)
French (fr)
Inventor
叶飞
石磊
傅电波
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP15874813.7A priority Critical patent/EP3232558B1/en
Publication of WO2016107123A1 publication Critical patent/WO2016107123A1/zh
Priority to US15/641,059 priority patent/US20170302195A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • Embodiments of the present invention relate to the field of circuits and, more particularly, to a circuit and power converter of a multi-level topology.
  • the multi-level inverter can select a bus capacitor with higher withstand voltage, and at the same time, it can reduce the output current under the same power by increasing the AC voltage of the output, thereby greatly reducing the cable. cost.
  • the output ripple of the system will gradually decrease, which means that a smaller filter can be used, which can increase the power density of the system and reduce the cost of the filter. Therefore, multi-level inverters have a broad application prospect.
  • Embodiments of the present invention provide a circuit and a power converter of a multi-level topology, wherein a required breakdown voltage value of the switch component is low, thereby ensuring performance.
  • a multi-level topology circuit comprising: five terminals and six switch components,
  • a first end of the first switch assembly of the six switch assemblies is coupled to a first one of the five terminals, a second end of the first switch assembly and a fifth terminal of the five terminals connection;
  • a first end of the second switch assembly of the six switch assemblies is coupled to a second one of the five terminals, and a second end of the second switch assembly is coupled to the first end of the first branch;
  • a second end of the third switch assembly of the six switch assemblies is coupled to a third one of the five terminals, a first end of the third switch assembly and a first end of the first branch Connecting, wherein the first branch includes a fourth switch assembly and a fifth switch assembly in series, a first end of the first branch is coupled to a first end of the fourth switch assembly and the first branch a second end of the road is connected to the first end of the fifth switch component, or a first end of the first branch is connected to a second end of the fourth switch component and a second end of the first branch Connecting the second end of the fifth switch component;
  • a second end of the sixth switch component of the six switch components is connected to a fourth terminal of the five terminals, and a first end of the sixth switch component is connected to the fifth terminal;
  • the second end of the first branch is connected to the fifth terminal.
  • the first terminal is connected to a positive pole of the first voltage source, and the second terminal is connected to a negative pole of the first voltage source;
  • the second terminal is connected to the anode of the second voltage source, and the third terminal is connected to the cathode of the second voltage source;
  • the third terminal is connected to the anode of the third voltage source, and the fourth terminal is connected to the cathode of the third voltage source.
  • the second terminal and the third terminal are respectively connected to the first input end and the second input end of the first DC/DC conversion circuit
  • the first terminal and the second terminal are respectively connected to the first output end and the second output end of the first DC/DC conversion circuit
  • the second terminal and the third terminal are respectively connected to the first input end and the second input end of the second DC/DC conversion circuit, and the third terminal and the fourth terminal are respectively connected to the second DC/ a first output end and a second output end of the DC conversion circuit;
  • the first DC/DC conversion circuit and the second DC/DC conversion circuit share the same input.
  • the first terminal is connected to a first output end of the first DC/DC conversion circuit, and the second terminal is connected to the first straight a second output of the stream/DC conversion circuit;
  • the second terminal is connected to the first input end of the first DC/DC conversion circuit
  • the second input end of the first DC/DC conversion circuit is connected to the first input end of the second DC/DC conversion circuit
  • the third terminal is connected to the second input end of the second DC/DC conversion circuit
  • the fourth terminal is connected to the first output end of the second DC/DC conversion circuit, and the third terminal is connected to the second output end of the second DC/DC conversion circuit.
  • the multi-level topology is an N-level topology, and N is an even number greater than 4, the circuit further includes: N-4 terminals And 2N-8 switch components, wherein the N-4 terminals comprise a sixth terminal to an N+1th terminal, and the 2N-8 switch components comprise a seventh switch component to a second N-2 switch component;
  • the second end of the 2i-4 switch assembly is connected to the i+1th terminal, and the second end of the 2i-4 switch assembly is connected to the first end of the (i-2)/2 branch, wherein
  • the (i-2)/2 branch includes a second ii-3 switch assembly and a second i-2 switch assembly connected in series, and the first end of the (i-2)/2 branch is connected to the first a first end of the 2i-3 switch assembly and a second end of the (i-2)/2 branch is connected to the first end of the 2i-2 switch assembly, or the (i-2) a first end of the /2 branch is connected to the second end of the 2i-3 switch assembly and a second end of the (i-2)/2 branch is connected to the second end of the 2i-2 switch assembly end;
  • the second end of the (i-2)/2 branch is connected to the fifth terminal.
  • the multi-level topology is an N-level topology
  • the circuit further includes: N-4 terminals and 2N-8 switch components,
  • the N-4 terminals include a sixth terminal to an N+1th terminal, and the 2N-8 switch components include a seventh switch component to a second N-2 switch component, and N is a positive integer greater than 4.
  • the fourth terminal is grounded.
  • a composite circuit comprising: the circuit of the multi-level topology and the coupled inductor of any of the first aspect or the first aspect of the first aspect, wherein the coupled inductor comprises M Input terminals and one output terminal;
  • the M input terminals are respectively connected to the fifth terminal of the multi-level topology circuit of the M first aspect or any of the possible implementations of the first aspect.
  • a power converter comprising: the circuit and controller of the first possible implementation of the first aspect.
  • the controller is connected to the six switch components for The state of the six switch components is controlled.
  • a value of an input voltage of the first voltage source is DC1
  • a value of an input voltage of the second voltage source is DC2, where The input voltage of the three voltage sources is DC3.
  • the controller controls states of the first switch component, the second switch component, and the fourth switch component to be in a first state, and the third switch component, the fifth switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC1+DC2+DC3;
  • the controller controls states of the second switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the third switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC2+DC3;
  • the controller controls states of the third switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC3;
  • the controller controls states of the third switch component, the fifth switch component, and the sixth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the fourth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is 0;
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly
  • the first end of the switch assembly is conductive in a direction.
  • the power converter is a four-level inverter.
  • a power converter comprising: the circuit, the input voltage source, and the controller of the second possible implementation of the first aspect.
  • the second terminal is connected to a positive pole of the input voltage source, and the third terminal is connected to a negative pole of the input voltage source;
  • the controller is coupled to the six switch assemblies for controlling states of the six switch assemblies.
  • the input voltage of the input voltage source has a value of DC1, and the first terminal after the first DC/DC conversion circuit And a value of a voltage between the second terminal and the second terminal is DC2, and a value of a voltage between the third terminal and the fourth terminal after the second DC/DC conversion circuit is DC3,
  • the controller controls states of the first switch component, the second switch component, and the fourth switch component to be in a first state, and the third switch component, the fifth switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC1+DC2+DC3;
  • the controller controls states of the second switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the third switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC1+DC3;
  • the controller controls states of the third switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC3;
  • the controller controls states of the third switch component, the fifth switch component, and the sixth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the fourth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is 0;
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly
  • the first end of the switch assembly is conductive in a direction.
  • the power converter is a four-level inverter.
  • a power converter comprising: the circuit of the third possible implementation of the first aspect, the first input voltage source, the second input voltage source, and the controller.
  • the second terminal is connected to the anode of the first input voltage source, and the second input end of the first DC/DC converter circuit is connected to the cathode of the first input voltage source;
  • a first input end of the second DC/DC conversion circuit is connected to an anode of the second input voltage source, and a third terminal is connected to a cathode of the second input voltage source;
  • the controller is coupled to the six switch assemblies for controlling states of the six switch assemblies.
  • the input voltage of the first input voltage source has a value of DC1
  • the input voltage of the second input voltage source has a value of DC2.
  • a value of a voltage between the first terminal and the second terminal after the first DC/DC conversion circuit is DC3, and the third terminal after the second DC/DC conversion circuit
  • the value of the voltage between the fourth terminals is DC4,
  • the controller controls states of the first switch component, the second switch component, and the fourth switch component to be in a first state, and the third switch component, the fifth switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC1+DC2+DC3+DC4;
  • the controller controls states of the second switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the third switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC1+DC2+DC4;
  • the controller controls states of the third switch component, the fourth switch component, and the fifth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the sixth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is DC4;
  • the controller controls states of the third switch component, the fifth switch component, and the sixth switch component to be in a first state, and the first switch component, the second switch component, and the When the state of the fourth switch component is the second state, the value of the output voltage between the fourth terminal and the fifth terminal is 0;
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly Said The first end of the switch assembly is conductive in the direction.
  • the power converter is a four-level inverter.
  • the required breakdown voltage value of the switch component is low, thereby ensuring performance, and the cost of the switch component with low withstand voltage value is low.
  • FIG. 1 is an example of a circuit diagram of a four-level topology employed in the prior art.
  • FIG. 2 is a schematic diagram of a circuit of a multi-level topology in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit of a multi-level topology in accordance with another embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a switch assembly according to an embodiment of the present invention.
  • Figure 5 is a schematic illustration of a four level topology circuit in accordance with one embodiment of the present invention.
  • FIG. 6 is a schematic illustration of a Buck-Boost circuit in accordance with one embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a circuit of a four-level topology in accordance with another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a circuit of a four-level topology in accordance with another embodiment of the present invention.
  • Figure 9 is a schematic illustration of a three phase system in accordance with one embodiment of the present invention.
  • Figure 10 is a schematic illustration of a circuit of a multi-level topology in accordance with another embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a circuit of a six-level topology in accordance with one embodiment of the present invention.
  • Figure 12 is a schematic illustration of a circuit of a multi-level topology in accordance with another embodiment of the present invention.
  • Figure 13 is a schematic illustration of a five level topology circuit in accordance with one embodiment of the present invention.
  • Figure 14 is a schematic illustration of a composite circuit in accordance with one embodiment of the present invention.
  • Figure 15 is a schematic block diagram of a power converter in accordance with one embodiment of the present invention.
  • Figure 16 is a block diagram showing the structure of a power converter in accordance with one embodiment of the present invention.
  • Figure 17 is a schematic diagram of the output voltage of a four-level inverter.
  • Figure 18 is a block diagram showing the structure of a power converter in accordance with one embodiment of the present invention.
  • Figure 19 is a block diagram showing the structure of a power converter in accordance with one embodiment of the present invention.
  • the inverter can be used to convert DC to AC.
  • An inverter constructed using a multi-level topology is a multi-level inverter. Moreover, the more the number of levels, the smaller the harmonics, and the better the output will be.
  • a four-level topology is taken as an example for description.
  • a four-level topology means that the number of levels of the output is four.
  • FIG. 1 it is a circuit diagram of a four-level topology used in the prior art.
  • the bus voltage is V bus and the sub-bus voltage is used as the reference point, then the output voltage that can be achieved by controlling the switching component is turned on or off: V bus , 2 / 3V bus , 1/3V bus and 0.
  • the breakdown voltage required for the switch components is high.
  • the higher the withstand voltage of the switching device the greater the loss at the time of conduction, and the lower the performance.
  • a saturation voltage drop of a switching device with a withstand voltage of 1700V is 1.4 times that of a switching device with a withstand voltage of 650V.
  • the topology shown in Figure 1 does not work properly. Specifically, when there is no busbar power balancing circuit, the topology output changes from four levels to three levels. The number of output levels is reduced, causing the performance of the topology to drop dramatically and the device is underutilized.
  • FIG. 2 is a schematic diagram of a circuit of a multi-level topology in accordance with one embodiment of the present invention.
  • the circuit shown in Figure 2 includes five terminals (A1-A5) and six switch assemblies (Q1-Q6).
  • each switch assembly has a first end and a second end.
  • the five terminals (A1 - A5) include a first terminal A1, a second terminal A2, a third terminal A3, a fourth terminal A4, and a fifth terminal A5.
  • the six switch components (Q1-Q6) include a first switch component Q1, a second switch component Q2, a third switch component Q3, a fourth switch component Q4, a fifth switch component Q5, and a sixth switch component Q6.
  • a first end of the first switch component Q1 of the six switch components is connected to a first terminal A1 of the five terminals, and a second end of the first switch component Q1 and the five terminals are The fifth terminal A5 is connected;
  • a first end of the second switch component Q2 of the six switch components is connected to a second terminal A2 of the five terminals, a second end of the second switch component Q2 and a first end of the first branch End A1 connection;
  • a second end of the third switch component Q3 of the six switch components is connected to a third terminal A3 of the five terminals, a first end of the third switch component Q3 and the first branch The first end is connected,
  • the first branch includes a fourth switch component Q4 and a fifth switch component Q5 connected in series, and the first end of the first branch is connected to the first end of the fourth switch component Q4 and the first The second end of the branch is connected to the first end of the fifth switch component Q5 (as shown in FIG. 2), or the first end of the first branch is connected to the second end of the fourth switch component Q4 The second end of the first branch is connected to the second end of the fifth switch component Q5 (as shown in FIG. 3);
  • a second end of the sixth switch component Q6 of the six switch components is connected to a fourth terminal A4 of the five terminals, and a first end of the sixth switch component Q6 is connected to the fifth terminal A5 ;
  • the second end of the first branch is connected to the fifth terminal A5.
  • the required breakdown voltage value of the switch component is low, thereby ensuring performance, and the cost of the switch component with low withstand voltage value is low.
  • circuits shown in Figures 2 and 3 are circuits of a four level topology.
  • the switch assembly when the switch assembly is in an on state, the switch assembly is turned on in a direction from a first end of the switch assembly to a second end of the switch assembly, and in the switch assembly The second end is also conductive in a direction to the first end of the switch assembly; when the switch assembly is in an off state, the switch assembly is at a first end of the switch assembly to a second end of the switch assembly The end is disconnected in the direction and is conducting in a direction from the second end of the switch assembly to the first end of the switch assembly.
  • the six switching components Q1-Q6 shown in Figures 2 and 3 are formed by a diode (Diode) and a first semiconductor switching transistor connected in parallel. As shown in FIG. 4, the cathode of the diode D is connected to the first end of the switch assembly, and the anode of the diode D is connected to the second end of the switch assembly.
  • Diode diode
  • FIG. 4 the cathode of the diode D is connected to the first end of the switch assembly, and the anode of the diode D is connected to the second end of the switch assembly.
  • the switch component may be a switch tube, or the switch component may also be a combination of a plurality of switch tubes in series and/or parallel.
  • the switch tube may be an insulated gate bipolar transistor (IGBT), or may be a metal-oxide-semiconductor field effect transistor (MOSFET), etc., the present invention This is not limited.
  • the subsequent embodiments of the present invention are described by taking the switch assembly shown in FIG. 4 as an example.
  • the switch assembly shown in FIG. 4 When the switch assembly shown in FIG. 4 is in an on state, the switch assembly is turned on in the direction from the first end to the second end, and is also turned on in the direction from the second end to the first end.
  • the switch assembly shown in FIG. 4 When the switch assembly shown in FIG. 4 is in the off state, the switch assembly is disconnected in the direction from the first end to the second end, and is turned on in the direction from the second end to the first end.
  • the switch component shown in FIG. 4 is referred to as the first state
  • the switch component illustrated in FIG. 4 is referred to as the second state. That is, the first state means that the switch assembly is turned on in a direction from the first end of the switch assembly to the second end of the switch assembly and from the second end of the switch assembly to the switch assembly The direction of the first end is turned on.
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at a second end of the switch assembly to the first end of the switch assembly Conducted in the direction.
  • circuit of the multi-level topology provided by the embodiment of the present invention can be driven and controlled by a combination of software and hardware, thereby enabling DC/AC conversion or AC/DC ( Conversion of AC/DC).
  • the first terminal A1, the second terminal A2, the third terminal A3, and the fourth terminal A4 in the circuit of the four-level topology as shown in FIG. 2 or FIG. 3 may be used as an input terminal.
  • the fourth terminal A4 and the fifth terminal A5 are used as an output terminal.
  • the fourth terminal A4 can be grounded, that is, the fourth terminal A4 can be used as a voltage reference point.
  • the first terminal A1 is connected to the anode of the first voltage source DC1, and the second terminal is connected to the cathode of the first voltage source DC1.
  • the second terminal is connected to the anode of the second voltage source DC2, and the third terminal is connected to the cathode of the second voltage source DC2.
  • the third terminal is connected to the anode of the third voltage source DC3, and the fourth terminal is connected to the cathode of the third voltage source DC3.
  • the embodiment of the invention adopts DC1, DC2 and DC3 with constant voltage, which can solve the problem that the prior art uses the capacitor and cannot work normally.
  • the circuit of the four-level topology shown in FIG. 5 can be controlled by turning on the switch components. Or turn off to achieve a four-level output voltage. Specifically, it can be as shown in Table 1 below.
  • the active current of the circuit of the four-level topology may be as indicated by the dashed arrow 601 in FIG.
  • the active current of the circuit of the four-level topology may be as indicated by the dotted line arrow 602 in FIG.
  • the output level is DC3, it is level 3
  • the active current of the circuit of the four-level topology can be as shown by the dashed arrow 603 in FIG.
  • the output level is 0, it is level 4
  • the active current of the circuit of the four-level topology may be as indicated by the dotted line arrow 604 in FIG.
  • a circuit of a multi-level topology may be implemented by using a direct current/direct current (DC/DC) conversion circuit.
  • the DC/DC conversion circuit may be a buck-boost circuit.
  • the DC/DC conversion circuit can be a Buck-Boost circuit, as shown in FIG.
  • the Buck-Boost circuit includes switching components Q BB1 and Q BB2 , capacitors C BB1 and C BB2 , and an inductor L BB . Assume that the voltage across capacitor C BB1 is equal to V in and the voltage across capacitor C BB2 is equal to V out . Then, in the case of V in a constant, by adjusting the Buck-Boost regulator circuit conduction ratio V out.
  • V in can be used as the input to the Buck-Boost circuit
  • V out can be used as the output of the Buck-Boost circuit.
  • both ends of C BB1 are the two inputs of the Buck-Boost circuit
  • the two ends of C BB2 are the two outputs of the Buck-Boost circuit.
  • the circuit for implementing the multi-level topology using the DC/DC conversion circuit can be as shown in FIG.
  • the second terminal A2 and the third terminal A3 are respectively connected to the first input end and the second input end of the first DC/DC conversion circuit, and the first terminal A1 and the second terminal A2 are respectively connected to the first DC/DC conversion circuit a first output and a second output.
  • the second terminal A2 and the third terminal A3 are respectively connected to the first input end and the second input end of the second DC/DC conversion circuit, and the third terminal A3 and the fourth terminal A4 are respectively connected to the second DC/DC conversion circuit a first output and a second output.
  • the first DC/DC conversion circuit and the second DC/DC conversion circuit share the same input.
  • the first DC/DC conversion circuit shown in FIG. 7 is a first Buck-Boost circuit
  • the second DC/DC conversion circuit is a second Buck-Boost circuit.
  • the first Buck-Boost circuit includes C1 and C2
  • the second Buck-Boost circuit includes C2 and C3.
  • the third terminal A3 is connected to the negative terminal of the voltage source DC0. Then, the voltage between the first terminal A1 and the second terminal A2 can be determined to be DC01 by the first DC/DC conversion circuit; and the third DC/DC conversion circuit can be used to determine between the third terminal and the fourth terminal The voltage is DC02.
  • DC01 in FIG. 7 may correspond to DC1 in FIG. 5
  • DC0 in FIG. 7 may correspond to DC2 in FIG. 5
  • DC02 in FIG. 7 may correspond to DC3 in FIG.
  • the four-level output can be similarly controlled by controlling the states of the switch components Q1 to Q6. To avoid repetition, details are not described herein.
  • the bus voltage can be adjusted by adjusting the turn-on ratio of the first Buck-Boost circuit and/or the turn-on ratio of the second Buck-Boost circuit, thereby enabling Flexible control of four-level output.
  • a circuit for implementing a multi-level topology using a DC/DC conversion circuit can be as shown in FIG.
  • the first terminal is connected to the first output end of the first DC/DC conversion circuit
  • the second terminal A1 is connected to the second output end of the first DC/DC conversion circuit
  • the second terminal A2 is connected to the first DC/DC conversion a first input end of the circuit
  • a second input end of the first DC/DC conversion circuit is coupled to the first input end of the second DC/DC conversion circuit
  • a third terminal A3 is coupled to the second DC/DC conversion circuit a second input terminal
  • the fourth terminal A4 is connected to the first output end of the second DC/DC conversion circuit
  • the third terminal is connected to the second output end of the second DC/DC converter circuit.
  • the first DC/DC conversion circuit shown in FIG. 8 is a first Buck-Boost circuit
  • the second DC/DC conversion circuit is a second Buck-Boost circuit.
  • the first Buck-Boost circuit includes C11 and C12
  • the second Buck-Boost circuit includes C21 and C22.
  • the second terminal A2 is connected to the positive electrode of one voltage source DC10, the terminal A0 between C12 and C21 is connected to the negative terminal of the voltage source DC10.
  • the terminal A0 between C12 and C21 is connected to the anode of the voltage source DC20, and the third terminal A3 is connected to the cathode of the voltage source DC20.
  • the voltage between the first terminal A1 and the second terminal A2 can be determined to be DC11 through the first Buck-Boost circuit; and the voltage between the third terminal and the fourth terminal can be determined by the second Buck-Boost circuit. For DC22.
  • DC11 in FIG. 8 may correspond to DC1 in FIG. 5
  • DC10+DC20 in FIG. 8 may correspond to DC2 in FIG. 5
  • DC22 in FIG. 8 may correspond to DC3 in FIG.
  • the four-level output can be similarly controlled by controlling the states of the switch components Q1 to Q6. To avoid repetition, details are not described herein.
  • the bus voltage can be adjusted by adjusting the turn-on ratio of the first Buck-Boost circuit and/or the turn-on ratio of the second Buck-Boost circuit, thereby enabling Flexible control of four-level output.
  • the fourth switching component Q4 and the fifth switching component Q5 in FIGS. 7 and 8 can also adopt the series connection in FIG.
  • the Buck-Boost circuit shown in FIG. 7 and FIG. 8 can also adopt other DC/DC converters, which is not limited in the embodiment of the present invention.
  • the input in Figure 2 or Figure 3 can be connected to the output of the converter or to the output of the rectifier. That is, the output of the converter or the output of the rectifier can be used as an input to the circuitry of the multi-level topology.
  • a three-phase system can be realized, as shown in FIG. It can be seen that the three-phase system shown in Figure 9 includes three fifth ports, A51, A52 and A53.
  • the three-phase system shown in FIG. 9 is composed of three four-level topologies sharing the first port to the fourth port.
  • the fourth terminal A4 may be grounded.
  • the first terminal A1, the second terminal A2, the third terminal A3, and the fourth terminal A4 may serve as an input terminal.
  • three voltage sources can be connected at A1-A4 as shown in FIG.
  • Two DC/DC conversion circuits can be connected at A1-A4 as shown in Fig. 7 or Fig. 8.
  • a higher level topology can be constructed based on the four level topology shown in FIG. 2 or FIG.
  • the multi-level topology constructed on the basis of FIG. 2 is an N-level topology, and N is an even number greater than 4, as shown in FIG. 10, the circuit further includes: N-4 terminals and 2N-8 switches.
  • the second end of the 2i-4 switch component Q(2i-4) is connected to the i+1th terminal A(i+1), and the second end of the 2i-4 switch component Q(2i-4) a first end connection of the (i-2)/2 branch, wherein the (i-2)/2 branch comprises a 2i-3 switch assembly Q(2i-3) and a 2i- in series a switch assembly Q (2i-2), the first end of the (i-2)/2 branch is connected to the first end of the second i-3 switch assembly Q (2i-3) and the first The second end of the i-2)/2 branch is connected to the first end of the second i-2 switch assembly Q(2i-2), or the first end of the (i-2)/2 branch Connecting the second end of the 2i-3 switch assembly Q (2i-3) and connecting the second end of the (i-2)/2 branch to the 2i-2 switch assembly Q (2i-2) The second end;
  • the second end of the (i-2)/2 branch is connected to the fifth terminal A5.
  • DC/AC conversion can be achieved using the multi-level topology.
  • the i-th terminal A(i) and the i-th A DC voltage source is connected between the +1 terminal A (i+1) and the N+1 terminal A (N+1) and the fourth terminal A4.
  • the state of the switch component can be adjusted to achieve an N-level output.
  • the voltage output from the fourth terminal A4 and the fifth terminal A5 is closer to sinusoidal, that is, the output voltage is an alternating voltage.
  • the circuit of the six-level topology can be as shown in FIG. 11, including: seven terminals (A1-A7) and ten switch components (Q1-Q10).
  • the seven terminals include a first terminal A1, a second terminal A2, a third terminal A3, a fourth terminal A4, a fifth terminal A5, a sixth terminal A6, and a seventh terminal A7.
  • the ten switch components include a first switch component Q1, a second switch component Q2, a third switch component Q3, a fourth switch component Q4, a fifth switch component Q5, a sixth switch component Q6, and a seventh switch component.
  • the first end of the first switch component Q1 is connected to the first terminal A1, and the second end of the first switch component Q1 is connected to the fifth terminal A5;
  • the first end of the second switch component Q2 is connected to the second terminal A2, the second end of the second switch component Q2 is connected to the first end of the first branch; the second end and the third end of the third switch component Q3
  • the terminal A3 is connected, the first end of the third switch component Q3 is connected to the first end of the first branch, wherein the first branch comprises a fourth switch component Q4 and a fifth switch component Q5 connected in series
  • the first end of the first branch is connected to the first end of the fourth switch component Q4 and the second end of the first branch is connected to the first end of the fifth switch component Q5;
  • the first end of the seventh switch component Q7 is connected to the sixth terminal A6, the second end of the seventh switch component Q7 is connected to the first end of the second branch; the second end and the seventh end of the eighth switch component Q8
  • the terminal A7 is connected, the first end of the eighth switch component Q8 is connected to the first end of the second branch, wherein the second branch comprises a ninth switch component Q9 and a tenth switch component Q10 connected in series
  • the first end of the second branch is connected to the first end of the ninth switch assembly Q9 and the second end of the second branch is connected to the first end of the tenth switch assembly Q10;
  • the second end of the sixth switch component Q6 is connected to the fourth terminal A4, and the first end of the sixth switch component Q6 is connected to the fifth terminal A5;
  • the second end of the first branch is connected to the fifth terminal A5, and the second end of the second branch is connected to the fifth terminal A5.
  • the circuit of the six-level topology shown in FIG. 11 further includes five DC voltage sources.
  • the first terminal A1 is connected to the anode of the first voltage source DC1, and the second terminal A2 is connected to the cathode of the first voltage source DC1.
  • the second terminal A2 is connected to the anode of the second voltage source DC2, and the third terminal A3 is connected to the cathode of the second voltage source DC2.
  • the third terminal A3 is connected to the anode of the third voltage source DC3, and the sixth terminal A6 is connected to the cathode of the third voltage source DC3.
  • the sixth terminal A6 is connected to the anode of the fourth voltage source DC4, and the seventh terminal A7 is connected to the cathode of the fourth voltage source DC4.
  • the seventh terminal A7 is connected to the anode of the fifth voltage source DC5, and the fourth terminal A4 is connected to the cathode of the fifth voltage source DC5.
  • the fourth terminal A4 can be grounded.
  • a six-level output voltage can be achieved by controlling the switching component to be turned “on” or "off”. Specifically, it can be as shown in Table 2 below.
  • the switch component can adopt a switch tube with a small withstand voltage value, which can save cost. Moreover, since a switching device having a low withstand voltage value is used, loss can be reduced, thereby improving system performance.
  • the fourth switching component Q4 and the fifth switching component Q5 in FIGS. 10 and 11 can also adopt the series connection in FIG.
  • the ninth switch component Q9 and the tenth switch component Q10 in Fig. 11 can also adopt the same In tandem mode.
  • the invention is not limited thereto.
  • the first terminal A1 to the fourth terminal A4, and the sixth terminal A6 to the (N+1)th terminal may serve as inputs of the circuit of the multi-level topology.
  • the fourth terminal A4 and the fifth terminal A5 can serve as outputs of the circuit of the multi-level topology.
  • the input of the circuit of the multi-level topology shown in FIG. 10 can be connected to a voltage source, or a plurality of DC/DC conversion circuits can be connected as inputs, in order to avoid repetition, here No longer.
  • the multi-level topology of the three-phase system can be similarly obtained by using the circuit of the multi-level topology shown in FIG. 10, and to avoid repetition, details are not described herein again.
  • a higher level topology can be constructed based on the four level topology shown in FIG. 2 or FIG.
  • the multi-level topology constructed on the basis of FIG. 2 is an N-level topology.
  • the circuit further includes: N-4 terminals and 2N-8 switch components, wherein the N- The four terminals include a sixth terminal A6 to an N+1th terminal A(N+1), and the 2N-8 switching components include a seventh switching component Q7 to a second N-2 switching component Q(2N-2), N Is a positive integer greater than 4;
  • the first end of the j+1th switch component Q(j+1) is connected to the jth terminal A(j), and the j+1th switch component
  • the second end of Q(j+1) is connected to the second end of the j+N-3 switch component Q(j+N-3), and the j+N-3 switch component Q(j+N-3)
  • DC/AC conversion can be achieved using the multi-level topology.
  • a DC voltage source is connected between the N+1 terminal A (N+1) and the third terminal A3, and between the third terminal A3 and the fourth terminal A4.
  • the N-level output can be realized by adjusting the state of the switch component.
  • the voltage output from the fourth terminal A4 and the fifth terminal A5 is closer to sinusoidal, that is, the output voltage is an alternating voltage.
  • the multi-level topology is a five-level topology
  • the circuit of the five-level topology can be as shown in FIG. 13, including: six terminals (A1-A6) and eight switch components ( Q1-Q8).
  • the six terminals include a first terminal A1, a second terminal A2, a third terminal A3, a fourth terminal A4, a fifth terminal A5, and a sixth terminal A6.
  • the eight switch components include a first switch component Q1, a second switch component Q2, a third switch component Q3, a fourth switch component Q4, a fifth switch component Q5, a sixth switch component Q6, and a seventh switch component.
  • Q7 and eighth switch assembly Q8 include a first switch component Q1, a second switch component Q2, a third switch component Q3, a fourth switch component Q4, a fifth switch component Q5, a sixth switch component Q6, and a seventh switch component.
  • the first end of the first switch component Q1 is connected to the first terminal A1, and the second end of the first switch component Q1 is connected to the fifth terminal A5;
  • the first end of the second switch component Q2 is connected to the second terminal A2, the second end of the second switch component Q2 is connected to the first end of the first branch; the second end and the third end of the third switch component Q3
  • the terminal A3 is connected, the first end of the third switch component Q3 is connected to the first end of the first branch, wherein the first branch comprises a fourth switch component Q4 and a fifth switch component Q5 connected in series
  • the first end of the first branch is connected to the first end of the fourth switch component Q4 and the second end of the first branch is connected to the first end of the fifth switch component Q5;
  • the first end of the seventh switch component Q7 is connected to the sixth terminal A6, the second end of the seventh switch component Q7 is connected to the second end of the eighth switch component Q8, and the first end of the eighth switch component Q8 is The first end of the first branch is connected;
  • the second end of the sixth switch component Q6 is connected to the fourth terminal A4, and the first end of the sixth switch component Q6 is connected to the fifth terminal A5;
  • the second end of the first branch is connected to the fifth terminal A5.
  • the circuit of the five-level topology shown in FIG. 13 further includes four DC voltage sources.
  • the first terminal A1 is connected to the anode of the first voltage source DC1, and the second terminal A2 is connected to the cathode of the first voltage source DC1.
  • the second terminal A2 is connected to the anode of the second voltage source DC2, and the sixth terminal A6 is connected to the cathode of the second voltage source DC2.
  • the sixth terminal A6 is connected to the anode of the third voltage source DC3, and the third terminal A3 is connected to the cathode of the third voltage source DC3.
  • the third terminal A3 is connected to the anode of the fourth voltage source DC4, and the fourth terminal A4 is connected to the cathode of the fourth voltage source DC4.
  • the fourth terminal A4 can be grounded.
  • a five-level output voltage can be achieved by controlling the switching component to be turned “on” or "off”. Specifically, it can be as shown in Table 3 below.
  • the switch component can adopt a switch tube with a small withstand voltage value, which can save cost. Moreover, since a switching device having a low withstand voltage value is used, loss can be reduced, thereby improving system performance.
  • the first terminal A1 to the fourth terminal A4, and the sixth terminal A6 to the (N+1)th terminal may serve as inputs of the circuit of the multi-level topology.
  • the fourth terminal A4 and the fifth terminal A5 can serve as outputs of the circuit of the multi-level topology.
  • the input of the circuit of the multi-level topology shown in FIG. 12 can be connected to a voltage source, or multiple DC/DC conversion circuits can be connected as inputs, in order to avoid repetition, here No longer.
  • circuit of the multi-level topology shown in FIG. 12 can be similarly obtained to obtain a three-phase system of a multi-level topology. To avoid repetition, details are not described herein again.
  • the multi-level topology in the above embodiment may be combined with the coupled inductor silicon to form a composite circuit to achieve a higher level.
  • the composite circuit includes M multi-level topologies (11-1M) and coupled inductors 140.
  • the M multi-level topologies (11-1M) include a first multi-level topology 11, a second multi-level topology 12, ..., an M-th multi-level topology 1M.
  • the coupled inductor 140 includes M input terminals and an output terminal A0. Among them, M input terminals correspond to M inductors (L 1 -L M ).
  • the M input terminals are respectively connected to the fifth terminal of the circuit of the multilevel topology (11-1M).
  • the coupled inductor shown in FIG. 14 is an M-phase coupled inductor.
  • the coupling inductor is combined with the multi-level topology to achieve a higher level, increase the equivalent switching frequency, and reduce the ripple of the output, thereby greatly reducing the cost and volume of the output filter.
  • the multi-level topology in FIG. 14 is an N-level topology, wherein when N is an even number, the N-level topology may be as shown in FIG. 10 or FIG.
  • the N-level topology When N is an odd number, the N-level topology can be as shown in FIG.
  • the equivalent switching frequency of the output is M ⁇ f
  • the number of output levels is M ⁇ N+1.
  • the number of levels of the output and the frequency of the equivalent switch are greatly increased, and the output ripple is drastically reduced, so that the cost and volume of the output filter device can be greatly reduced.
  • it also provides conditions for reducing the switching frequency the switching frequency is reduced, the switching loss can be reduced proportionally, and the efficiency of the converter system can be greatly improved.
  • FIG. 15 is a schematic block diagram of a power converter in accordance with one embodiment of the present invention.
  • the power converter 1500 shown in FIG. 15 includes a multi-level topology 1501 and a controller 1502.
  • the multi-level topology 1501 can refer to the multi-level topology in any of the foregoing embodiments of FIG. 2 or FIG. 3 or FIG. 5 and FIG. 7 to FIG.
  • the controller 1502 can be used to control the state of the switch components in the multi-level topology 1501. Specifically, the controller 1502 can change the state of the switch component by means of hardware and software.
  • the controller 1502 can be in the form of a processor.
  • the processor may be an integrated circuit chip with signal processing capabilities.
  • the control of the state of the switch component of the multi-level topology can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software.
  • the above processor may be a general purpose processor, a digital letter Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, Discrete hardware components.
  • DSP digital letter Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present invention may be implemented or carried out.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.
  • the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • ROM read-only memory
  • PROM programmable read only memory
  • Erasable PROM erasable programmable read only memory
  • EEPROM electric Erase programmable read only memory
  • flash memory a flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM).
  • SDRAM Double Data Rate SDRAM
  • DDR SDRAM Double Data Rate SDRAM
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SLDRAM Synchronous Connection Dynamic Random Access Memory
  • DR RAM direct memory bus random access memory
  • the power converter 1500 may be a five-level inverter.
  • the power converter 1500 may be a six-level inverter.
  • the power converter 1500 may be an N-level inverter.
  • the N-level inverter may further include N-1 input voltage sources.
  • the N-1 input voltage sources can be connected between the other terminals of the N+1 terminals except the fifth terminal A5.
  • FIG. 11 or FIG. 13 for the connection mode of the N-1 input voltage sources. To avoid repetition, details are not described herein again.
  • the N-level inverter may further include N-2 DC/DC conversion circuits.
  • the N-2 DC/DC conversion circuits may be connected between other terminals of the N+1 terminals except the fifth terminal A5.
  • the connection manner of the N-2 DC/DC conversion circuits can be analogized to the related description of the four-level topology in FIG. 7 or FIG. 8. To avoid repetition, details are not described herein again.
  • the power converter 1500 may be a four-level inverter. Device.
  • FIG. 16 is a schematic structural view of a power converter according to an embodiment of the present invention.
  • the power converter 1600 shown in FIG. 16 includes the circuit and controller 1601 of the four-level topology shown in FIG.
  • the controller 1601 is connected to the six switch components (Q1 to Q6) for controlling the states of the six switch components.
  • the state of the switch component can be changed by the control of the controller 1601.
  • the switch assembly can be as shown in FIG. 4.
  • the state of the switch assembly may be the first state or the second state.
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly
  • the first end of the switch assembly is conductive in a direction.
  • the value of the input voltage of the first voltage source is DC1
  • the value of the input voltage of the second voltage source is DC2
  • the value of the input voltage of the third voltage source is DC3
  • the controller 1601 controls the states of the first switch component Q1, the second switch component Q2, and the fourth switch component Q4 to be in a first state, and the third switch component Q3, the fifth switch component
  • the state of Q5 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC1+DC2+DC3;
  • the controller 1601 controls the states of the second switch component Q2, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the third switch component
  • the state of Q3 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC2+DC3;
  • the controller 1601 controls the states of the third switch component Q3, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the second switch component
  • the state of Q2 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC3;
  • the controller 1601 controls the states of the third switch component Q3, the fifth switch component Q5, and the sixth switch component Q6 to be in a first state, and the first switch component Q1, the second switch component
  • the state of Q2 and the fourth switch component Q4 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is 0;
  • FIG. 17(a) is a schematic diagram of the output voltage of the power converter 1600.
  • Figure 17 (b) is a schematic diagram of the output voltage of the power converter 1600 after filtering.
  • the power converter 1600 shown in FIG. 16 may be a four-level inverter.
  • FIG. 18 is a block diagram showing the structure of a power converter in accordance with another embodiment of the present invention.
  • the power converter 1800 shown in FIG. 18 includes the circuit of the four-level topology shown in FIG. 7, the input voltage source DC1, and the controller 1801.
  • the second terminal A2 is connected to the anode of the input voltage source DC1, and the third terminal A3 is connected to the cathode of the input voltage source DC1;
  • the controller 1801 is connected to the six switch components (Q1 to Q6) for controlling states of the six switch components.
  • controller 1801 may also be connected to the switch component in the first DC/DC conversion circuit and control the state of the switch component in the first DC/DC conversion circuit; the controller 1801 may also be connected to the second DC/ A switching component in the DC conversion circuit is coupled and controls a state of the switching component in the second DC/DC conversion circuit.
  • the value of the input voltage of the input voltage source is DC1
  • the value of the voltage between the first terminal A1 and the second terminal A2 after the first DC/DC conversion circuit is DC2
  • the value of the voltage between the third terminal A3 and the fourth terminal A4 after the second DC/DC conversion circuit is DC3
  • the controller 1801 controls the first switch component Q1 and the second switch component Q2 And when the state of the fourth switch component Q4 is the first state, and the states of the third switch component Q3, the fifth switch component Q5, and the sixth switch component Q6 are the second state, the first The value of the output voltage between the four terminals A4 and the fifth terminal A5 is DC1+DC2+DC3;
  • the controller 1801 controls the states of the second switch component Q2, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the third When the state of the switch component Q3 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC1+DC3;
  • the controller 1801 controls the states of the third switch component Q3, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the second When the state of the switch component Q2 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC3;
  • the controller 1801 controls the states of the third switch component Q3, the fifth switch component Q5, and the sixth switch component Q6 to be in a first state, and the first switch component Q1, the second When the state of the switch component Q2 and the fourth switch component Q4 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is 0;
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly
  • the first end of the switch assembly is conductive in a direction.
  • DC2 and DC3 can be adjusted by adjusting the first DC/DC conversion circuit and the second DC/DC conversion circuit, so that the range of the output voltage of the power converter can be increased. This makes the power converter more flexible.
  • the power converter 1800 shown in FIG. 18 may be a four-level inverter.
  • FIG. 19 is a block diagram showing the structure of a power converter in accordance with another embodiment of the present invention.
  • the power converter 1900 shown in FIG. 19 includes the circuit of the four-level topology shown in FIG. 8, the first input voltage source DC1, the second input voltage source DC2, and the controller 1901.
  • the second terminal A2 is connected to the anode of the first input voltage source DC1, and the second input terminal A0 of the first DC/DC converter circuit is connected to the cathode of the first input voltage source DC1;
  • the first input terminal A0 of the second DC/DC conversion circuit is connected to the anode of the second input voltage source DC2, and the third terminal A3 is connected to the cathode of the second input voltage source DC2;
  • the controller 1901 is connected to the six switch components (Q1 to Q6) for controlling states of the six switch components.
  • controller 1901 may also be connected to the switch component in the first DC/DC conversion circuit and control the state of the switch component in the first DC/DC conversion circuit; the controller 1901 may also be connected to the second DC/ A switching component in the DC conversion circuit is coupled and controls a state of the switching component in the second DC/DC conversion circuit.
  • the value of the input voltage of the first input voltage source is DC1
  • the value of the input voltage of the second input voltage source is DC2
  • the first terminal A1 after the first DC/DC conversion circuit The value of the voltage between the second terminal A2 and the second terminal A2 is DC3, and the value of the voltage between the third terminal A3 and the fourth terminal A4 after the second DC/DC conversion circuit is DC4.
  • the controller 1901 controls the states of the first switch component Q1, the second switch component Q2, and the fourth switch component Q4 to be in a first state, and the third switch component Q3, the fifth When the state of the switch component Q5 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC1+DC2+DC3+DC4;
  • the controller 1901 controls the states of the second switch component Q2, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the third When the state of the switch component Q3 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC1+DC2+DC4;
  • the controller 1901 controls states of the third switch component Q3, the fourth switch component Q4, and the fifth switch component Q5 to be in a first state, and the first switch component Q1, the second When the state of the switch component Q2 and the sixth switch component Q6 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is DC4;
  • the controller 1901 controls states of the third switch component Q3, the fifth switch component Q5, and the sixth switch component Q6 to be in a first state, and the first switch component Q1, the second When the state of the switch component Q2 and the fourth switch component Q4 is the second state, the value of the output voltage between the fourth terminal A4 and the fifth terminal A5 is 0;
  • the first state refers to a switch component being conductive in a direction from a first end of the switch assembly to a second end of the switch assembly and at a second end of the switch assembly to the switch assembly
  • the second state means that the switch assembly is disconnected in a direction from the first end of the switch assembly to the second end of the switch assembly and at the second end of the switch assembly
  • the first end of the switch assembly is conductive in a direction.
  • DC3 can be adjusted by adjusting the first DC/DC conversion circuit
  • DC4 can be adjusted by adjusting the second DC/DC conversion circuit, so that the output voltage of the power converter can be increased.
  • the range makes the power converter more flexible.
  • the power converter 1900 shown in FIG. 19 is a four-level inverter.
  • the power converter 1500 in FIG. 15 may be an N level inverter. If the N-level inverter further includes N-2 DC/DC conversion circuits at this time, it can be understood that the N-level inverter should also include an input voltage source. Specifically, the connection manner of the input voltage source can be analogized to the related description of the input voltage source in the four-level inverter in FIG. 18 or FIG. 19 above, and details are not described herein again to avoid repetition.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated in one unit. In the unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present invention which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

一种多电平拓扑的电路，包括：五个端子和六个开关组件。第一开关组件（Q1）的第一端与第一端子（A1）连接，第一开关组件的第二端与第五端子（A5）连接；第二开关组件（Q2）的第一端与第二端子（A2）连接，第二开关组件的第二端与第一支路的第一端连接；第三开关组件（Q3）的第二端与第三端子（A3）连接，第三开关组件的第一端与第一支路的第一端连接。第六开关组件（Q6）的第二端与第四端子（A4）连接，第六开关组件的第一端与第五端子连接；第一支路的第二端与第五端子连接。第一支路包括反方向串联的第四开关组件（Q4）和第五开关组件（Q5）。多电平拓扑的电路的开关组件所需的耐压值较低，进而能够保证性能，并且耐压值低的开关组件的成本较低。

Description

多电平拓扑的电路和功率变换器
本申请要求于2015年1月4日提交中国专利局、申请号为201510003885.5、发明名称为“多电平拓扑的电路和功率变换器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及电路领域，并且更具体地，涉及一种多电平拓扑的电路和功率变换器。
背景技术
在中压大容量领域，多电平逆变器的应用已经越来越广泛。在高压直流母线系统中，多电平逆变器能够选择更耐压的母线电容，同时，能够通过提高输出的交流电压，使得同等功率下的输出电流减小，进而能够大幅地降低线缆的成本。另外，随着电平数的提高，系统的输出纹波会逐渐减小，也就是说可以使用更小的滤波器，这样能够提高系统的功率密度，降低滤波器的成本。因此，多电平逆变器有较为广阔的应用前景。
然而，目前的多电平逆变器所采用的多电平拓扑中，开关组件所需的耐压值较高，这样导致在导通时的损耗较大，进而导致性能过低，并且耐压值较高的开关组件也会导致多电平逆变器的成本太高。
发明内容
本发明实施例提供一种多电平拓扑的电路和功率变换器，开关组件所需的耐压值较低，进而能够保证性能。
第一方面，提供了一种多电平拓扑的电路，包括：五个端子和六个开关组件，
所述六个开关组件中的第一开关组件的第一端与所述五个端子中的第一端子连接，所述第一开关组件的第二端与所述五个端子中的第五端子连接；
所述六个开关组件中的第二开关组件的第一端与所述五个端子中的第二端子连接，所述第二开关组件的第二端与第一支路的第一端连接；
所述六个开关组件中的第三开关组件的第二端与所述五个端子中的第三端子连接，所述第三开关组件的第一端与所述第一支路的第一端连接，其中，所述第一支路包括串联的第四开关组件和第五开关组件，所述第一支路的第一端连接所述第四开关组件的第一端且所述第一支路的第二端连接所述第五开关组件的第一端，或者，所述第一支路的第一端连接所述第四开关组件的第二端且所述第一支路的第二端连接所述第五开关组件的第二端；
所述六个开关组件中的第六开关组件的第二端与所述五个端子中的第四端子连接，所述第六开关组件的第一端与所述第五端子连接；
所述第一支路的第二端与所述第五端子连接。
结合第一方面，在第一方面的第一种可能的实现方式中，所述第一端子与第一电压源的正极连接，所述第二端子与所述第一电压源的负极连接；
所述第二端子与第二电压源的正极连接，所述第三端子与所述第二电压源的负极连接；
所述第三端子与第三电压源的正极连接，所述第四端子与所述第三电压源的负极连接。
结合第一方面，在第一方面的第二种可能的实现方式中，所述第二端子和所述第三端子分别连接第一直流/直流变换电路的第一输入端和第二输入端，所述第一端子和所述第二端子分别连接所述第一直流/直流变换电路的第一输出端和第二输出端；
所述第二端子和所述第三端子分别连接第二直流/直流变换电路的第一输入端和第二输入端，所述第三端子和所述第四端子分别连接所述第二直流/直流变换电路的第一输出端和第二输出端；
其中，所述第一直流/直流变换电路和所述第二直流/直流变换电路共用同一个输入。
结合第一方面，在第一方面的第三种可能的实现方式中，所述第一端子连接第一直流/直流变换电路的第一输出端，所述第二端子连接所述第一直流/直流变换电路的第二输出端；
所述第二端子连接所述第一直流/直流变换电路的第一输入端；
所述第一直流/直流变换电路的第二输入端连接第二直流/直流变换电路的第一输入端；
所述第三端子连接所述第二直流/直流变换电路的第二输入端；
所述第四端子连接所述第二直流/直流变换电路的第一输出端，所述第三端子连接所述第二直流/直流变换电路的第二输出端。
结合第一方面，在第一方面的第四种可能的实现方式中，所述多电平拓扑为N电平拓扑，且N为大于4的偶数，所述电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子至第N+1端子，所述2N-8个开关组件包括第七开关组件至第2N-2开关组件；
第2i-5开关组件的第一端与第i端子连接，所述第2i-5开关组件的第二端与第(i-2)/2支路的第一端连接，其中，i＝6,7,…,N；
第2i-4开关组件的第二端与第i+1端子连接，所述第2i-4开关组件的第二端与所述第(i-2)/2支路的第一端连接，其中，所述第(i-2)/2支路包括串联的第2i-3开关组件和第2i-2开关组件，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件的第一端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件的第一端，或者，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件的第二端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件的第二端；
所述第(i-2)/2支路的第二端与所述第五端子连接。
结合第一方面，在第一方面的第五种可能的实现方式中，所述多电平拓扑为N电平拓扑，所述电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子至第N+1端子，所述2N-8个开关组件包括第七开关组件至第2N-2开关组件，N为大于4的正整数；
第j+1开关组件的第一端与第j端子连接，第j+1开关组件的第二端与第j+N-3开关组件的第二端连接，所述第j+N-3开关组件的第一端与所述第一支路的第一端连接，其中，j＝6,7,…,N+1。
结合第一方面或者上述第一方面的任意一种可能的实现方式，在第一方面的第六种可能的实现方式中，所述第四端子接地。
第二方面，提供了一种复合电路，包括M个第一方面或者第一方面的任一种可能的实现方式所述的多电平拓扑的电路和耦合电感，其中，所述耦合电感包括M个输入端子和一个输出端子；
所述M个输入端子分别与所述M个第一方面或者第一方面的任一种可能的实现方式所述的多电平拓扑的电路的第五端子连接。
第三方面，提供了一种功率变换器，包括：第一方面的第一种可能的实现方式所述的电路和控制器。所述控制器，与所述六个开关组件连接，用于 控制所述六个开关组件的状态。
结合第三方面，在第三方面的第一种可能的实现方式中，所述第一电压源的输入电压的值为DC1，所述第二电压源的输入电压的值为DC2，所述第三电压源的输入电压的值为DC3，
当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3；
当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC2+DC3；
当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC3；
当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为0；
其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
结合第三方面或者第三方面的第一种可能的实现方式，在第三方面的第二种可能的实现方式中，所述功率变换器为四电平逆变器。
第四方面，提供了一种功率变换器，包括：第一方面的第二种可能的实现方式所述的电路、输入电压源和控制器。
所述第二端子与所述输入电压源的正极连接，所述第三端子与所述输入电压源的负极连接；
所述控制器，与所述六个开关组件连接，用于控制所述六个开关组件的状态。
结合第四方面，在第四方面的第一种可能的实现方式中，所述输入电压源的输入电压的值为DC1，经过所述第一直流/直流变换电路后的所述第一端子和所述第二端子之间的电压的值为DC2，经过所述第二直流/直流变换电路后的所述第三端子和所述第四端子之间的电压的值为DC3，
当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3；
当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC3；
当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC3；
当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为0；
其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
结合第四方面或者第四方面的第一种可能的实现方式，在第四方面的第二种可能的实现方式中，所述功率变换器为四电平逆变器。
第五方面，提供了一种功率变换器，包括：第一方面的第三种可能的实现方式所述的电路、第一输入电压源、第二输入电压源和控制器。
所述第二端子与所述第一输入电压源的正极连接，所述第一直流/直流变换电路的第二输入端与所述第一输入电压源的负极连接；
所述第二直流/直流变换电路的第一输入端与所述第二输入电压源的正极连接，所述第三端子与所述第二输入电压源的负极连接；
所述控制器，与所述六个开关组件连接，用于控制所述六个开关组件的状态。
结合第五方面，在第五方面的第一种可能的实现方式中，所述第一输入电压源的输入电压的值为DC1，所述第二输入电压源的输入电压的值为DC2，经过所述第一直流/直流变换电路后的所述第一端子和所述第二端子之间的电压的值为DC3，经过所述第二直流/直流变换电路后的所述第三端子和所述第四端子之间的电压的值为DC4，
当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3+DC4；
当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC4；
当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC4；
当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为0；
其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述 开关组件的第一端的方向上导通。
结合第五方面或者第五方面的第一种可能的实现方式，在第五方面的第二种可能的实现方式中，所述功率变换器为四电平逆变器。
本发明实施例所提供的多电平拓扑的电路，开关组件所需的耐压值较低，进而能够保证性能，并且耐压值低的开关组件的成本较低。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术所采用的四电平拓扑的电路图的一例。
图2是本发明一个实施例的多电平拓扑的电路的示意图。
图3是本发明另一个实施例的多电平拓扑的电路的示意图。
图4是本发明一个实施例的开关组件的结构示意图。
图5是本发明一个实施例的四电平拓扑的电路的示意图。
图6是本发明一个实施例的Buck-Boost电路的示意图。
图7是本发明另一个实施例的四电平拓扑的电路的示意图。
图8是本发明另一个实施例的四电平拓扑的电路的示意图。
图9是本发明一个实施例的三相系统的示意图。
图10是本发明另一个实施例的多电平拓扑的电路的示意图。
图11是本发明一个实施例的六电平拓扑的电路的示意图。
图12是本发明另一个实施例的多电平拓扑的电路的示意图。
图13是本发明一个实施例的五电平拓扑的电路的示意图。
图14是本发明一个实施例的复合电路的示意图。
图15是本发明一个实施例的功率变换器的示意性框图。
图16是本发明一个实施例的功率变换器的结构示意图。
图17是四电平逆变器的输出电压的一个示意图。
图18是本发明一个实施例的功率变换器的结构示意图。
图19是本发明一个实施例的功率变换器的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
逆变器可以用于将直流转换为交流。采用多电平拓扑所构成的逆变器为多电平逆变器。并且，电平数越多，谐波越小，输出的效果也会越好。
这里以四电平拓扑为例进行说明。四电平拓扑是指输出的电平数目为四个。如图1所示，为现有技术所采用的四电平拓扑的电路图。
对图1中的四电平拓扑，若母线电压为Vbus，以副母线电压为参考点，那么可以通过控制开关组件的接通或关断，能够实现的输出电压为：Vbus、2/3Vbus、1/3Vbus和0。
然而，目前的多电平逆变器所采用的多电平拓扑中，开关组件所需的耐压值较高。并且，开关器件的耐压越高，会导致在导通时的损耗较大，进而导致性能过低。例如，耐压为1700V的开关器件的饱和压降是耐压为650V的开关器件的饱和压降的1.4倍。
另一方面，当无母线功率平衡电路时，图1所示的拓扑无法正常工作。具体地，当无母线功率平衡电路时，拓扑输出会由四电平变为了三电平。输出电平数减小，使得拓扑的性能急剧下降，器件没有得到充分利用。
图2是本发明一个实施例的多电平拓扑的电路的示意图。图2所示的电路包括五个端子(A1-A5)和六个开关组件(Q1-Q6)。
其中，每个开关组件具有第一端和第二端。
其中，五个端子(A1-A5)包括第一端子A1、第二端子A2、第三端子A3、第四端子A4和第五端子A5。六个开关组件(Q1-Q6)包括第一开关组件Q1、第二开关组件Q2、第三开关组件Q3、第四开关组件Q4、第五开关组件Q5和第六开关组件Q6。
所述六个开关组件中的第一开关组件Q1的第一端与所述五个端子中的第一端子A1连接，所述第一开关组件Q1的第二端与所述五个端子中的第五端子A5连接；
所述六个开关组件中的第二开关组件Q2的第一端与所述五个端子中的第二端子A2连接，所述第二开关组件Q2的第二端与第一支路的第一端A1 连接；
所述六个开关组件中的第三开关组件Q3的第二端与所述五个端子中的第三端子A3连接，所述第三开关组件Q3的第一端与所述第一支路的第一端连接，
其中，所述第一支路包括串联的第四开关组件Q4和第五开关组件Q5，所述第一支路的第一端连接所述第四开关组件Q4的第一端且所述第一支路的第二端连接所述第五开关组件Q5的第一端(如图2所示)，或者，所述第一支路的第一端连接所述第四开关组件Q4的第二端且所述第一支路的第二端连接所述第五开关组件Q5的第二端(如图3所示)；
所述六个开关组件中的第六开关组件Q6的第二端与所述五个端子中的第四端子A4连接，所述第六开关组件Q6的第一端与所述第五端子A5连接；
所述第一支路的第二端与所述第五端子A5连接。
本发明实施例所提供的多电平拓扑的电路，开关组件所需的耐压值较低，进而能够保证性能，并且耐压值低的开关组件的成本较低。
可理解，图2和图3所示的电路为四电平拓扑的电路。
可理解，其中，第四开关组件Q4和第五开关组件Q5是反方向串联的。
可选地，当所述开关组件处于接通状态时，所述开关组件在所述开关组件的第一端至所述开关组件的第二端的方向上导通，且在所述开关组件的第二端至所述开关组件的第一端的方向上也导通；当所述开关组件处于关断状态时，所述开关组件在所述开关组件的第一端至所述开关组件的第二端的方向上断开，且在所述开关组件的第二端至所述开关组件的第一端的方向上导通。
应注意，本发明实施例对开关组件的形式不作限定。图2和图3中所示的六个开关组件Q1-Q6是由一个二极管(Diode)和第一半导体开关管并联所形成的。如图4所示，二极管D的负极连接开关组件的第一端，二极管D的正极连接开关组件的第二端。
可理解，本发明实施例中，开关组件可以是一个开关管，或者开关组件也可以是多个开关管通过串联和/或并联的形式组合而成的。其中的开关管可以为绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)、或者也可以为金属-氧化层半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)等，本发明对此不作限定。
本发明后续实施例均以图4所示的开关组件为例进行阐述。当图4所示的开关组件处于接通状态时，该开关组件在第一端至第二端的方向上导通，且在第二端至第一端的方向上也导通。当图4所示的开关组件处于关断状态时，该开关组件在第一端至第二端的方向上断开，且在第二端至第一端的方向上导通。
本发明实施例中，将图4所示的开关组件处于接通状态称为第一状态，将图4所示的开关组件处于关断状态称为第二状态。也就是说，第一状态是指：开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。第二状态是指：开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
另外，本发明实施例提供的多电平拓扑的电路可以通过软件与硬件结合的方式进行驱动控制，从而能够实现直流/交流(Direct Current/Alternating Current，DC/AC)的转换或交流/直流(AC/DC)的转换。
例如，以DC/AC为例，可以将如图2或图3所示的四电平拓扑的电路中的第一端子A1、第二端子A2、第三端子A3和第四端子A4作为输入端，将第四端子A4和第五端子A5作为输出端。其中，第四端子A4可以接地，也就是说，第四端子A4可以作为电压参考点。
可选地，作为一个实施例，如图5所示，第一端子A1与第一电压源DC1的正极连接，第二端子与第一电压源DC1的负极连接。第二端子与第二电压源DC2的正极连接，第三端子与第二电压源DC2的负极连接。第三端子与第三电压源DC3的正极连接，第四端子与第三电压源DC3的负极连接。
本发明实施例采用电压可以恒定的DC1、DC2和DC3，能够解决现有技术采用电容造成的不能正常工作的问题。
可理解，图5中的第四开关组件Q4和第五开关组件Q5也可以采用图3中的串联方式。
应注意，图5所示的四电平拓扑的电路中，DC1、DC2和DC3的电压的大小可以互相相等，也可以互不相等，本发明对此不作限定。可理解，母线电压为Vbus＝DC1+DC2+DC3。
这样，对图5所示的四电平拓扑的电路，可以通过控制开关组件的接通 或关断，实现四电平的输出电压。具体地，可以如下表一所示。
表一
电平 Q1 Q2 Q3 Q4 Q5 Q6
DC1+DC2+DC3 1 1 0 1 0 0
DC2+DC3 0 1 0 1 1 0
DC3 0 0 1 1 1 0
0 0 0 1 0 1 1
其中，表一中的“1”表示相应的开关组件的状态为第一状态，“0”表示相应的开关组件的状态为第二状态。
假设输出电平为DC1+DC2+DC3时为电平1，此时该四电平拓扑的电路的有功电流可以如图5中的虚线箭头601所示。假设输出电平为DC2+DC3时为电平2，此时该四电平拓扑的电路的有功电流可以如图5中的点画线箭头602所示。假设输出电平为DC3时为电平3，此时该四电平拓扑的电路的有功电流可以如图5中的虚线箭头603所示。假设输出电平为0时为电平4，此时该四电平拓扑的电路的有功电流可以如图5中的点画线箭头604所示。
若假设DC1＝DC2＝DC3＝500V，那么流经Q1和Q6的最大电压为1500V，流经Q2至Q5的最大电压为500V，考虑一定的预量，本发明实施例中，Q1和Q6应采用耐压为1700V的开关器件，Q2至Q5应采用耐压为700V的开关器件。这样，与现有技术相比，6个开关组件中的两个开关组件可以采用耐压值低的开关器件，能够节约成本。并且，可理解，若DC1>DC2>DC3，那么可以采用耐压值更低的开关器件，从而进一步地节约成本。
并且，由于采用耐压值较低的开关器件，能够减少损耗，从而提高系统的性能。
可选地，作为另一个实施例，可以采用直流/直流(Direct Current/Direct Current，DC/DC)变换电路实现多电平拓扑的电路。可选地，该DC/DC变换电路可以为升降压电路。例如，DC/DC变换电路可以为Buck-Boost电路，如图6所示。
Buck-Boost电路包括开关组件QBB1和QBB2、电容CBB1和CBB2、以及电感LBB。假设电容CBB1两端的电压等于Vin，电容CBB2两端的电压等于Vout。那么，在Vin恒定的情况下，可以通过调节该Buck-Boost电路的导通比调节 Vout。
也就是说，可以将Vin作为Buck-Boost电路的输入，将Vout作为Buck-Boost电路的输出。相应地，CBB1的两端为Buck-Boost电路的两个输入端，CBB2的两端为Buck-Boost电路的两个输出端。
可选地，采用DC/DC变换电路实现多电平拓扑的电路可以如图7所示，
第二端子A2和第三端子A3分别连接第一DC/DC变换电路的第一输入端和第二输入端，第一端子A1和第二端子A2分别连接所述第一DC/DC变换电路的第一输出端和第二输出端。第二端子A2和第三端子A3分别连接第二DC/DC变换电路的第一输入端和第二输入端，第三端子A3和第四端子A4分别连接所述第二DC/DC变换电路的第一输出端和第二输出端。其中，所述第一DC/DC变换电路和所述第二DC/DC变换电路共用同一个输入。
具体地，图7所示的第一DC/DC变换电路为第一Buck-Boost电路，第二DC/DC变换电路为第二Buck-Boost电路。其中，第一Buck-Boost电路包括C1和C2，第二Buck-Boost电路包括C2和C3。
这样，若将第二端子A2连接一个电压源DC0的正极，将第三端子A3连接电压源DC0的负极。那么，可以通过第一DC/DC变换电路，确定第一端子A1和第二端子A2之间的电压为DC01；并可以通过第二DC/DC变换电路，确定第三端子和第四端子之间的电压为DC02。
参照图5可知，图7中的DC01可以相当于图5中的DC1，图7中的DC0可以相当于图5中的DC2，图7中的DC02可以相当于图5中的DC3。
这样，可以类似地通过控制开关组件Q1至Q6的状态，实现四电平输出，为避免重复，这里不再赘述。
应注意，图7所示的四电平拓扑中，可以通过调节第一Buck-Boost电路的导通比和/或第二Buck-Boost电路的导通比，来调节母线电压，从而能够实现对四电平输出的灵活控制。
可选地，采用DC/DC变换电路实现多电平拓扑的电路可以如图8所示，
第一端子连接第一DC/DC变换电路的第一输出端，第二端子A1连接所述第一DC/DC变换电路的第二输出端；第二端子A2连接所述第一DC/DC变换电路的第一输入端；所述第一DC/DC变换电路的第二输入端连接第二DC/DC变换电路的第一输入端；第三端子A3连接所述第二DC/DC变换电路的第二输入端；第四端子A4连接所述第二DC/DC变换电路的第一输出端， 所述第三端子连接所述第二DC/DC变换电路的第二输出端。
具体地，图8所示的第一DC/DC变换电路为第一Buck-Boost电路，第二DC/DC变换电路为第二Buck-Boost电路。其中，第一Buck-Boost电路包括C11和C12，第二Buck-Boost电路包括C21和C22。
这样，若将第二端子A2连接一个电压源DC10的正极，将C12和C21之间的端子A0连接电压源DC10的负极。将C12和C21之间的端子A0连接电压源DC20的正极，将第三端子A3连接电压源DC20的负极。那么，可以通过第一Buck-Boost电路，确定第一端子A1和第二端子A2之间的电压为DC11；并可以通过第二Buck-Boost电路，确定第三端子和第四端子之间的电压为DC22。
参照图5可知，图8中的DC11可以相当于图5中的DC1，图8中的DC10+DC20可以相当于图5中的DC2，图8中的DC22可以相当于图5中的DC3。
这样，可以类似地通过控制开关组件Q1至Q6的状态，实现四电平输出，为避免重复，这里不再赘述。
应注意，图8所示的四电平拓扑中，可以通过调节第一Buck-Boost电路的导通比和/或第二Buck-Boost电路的导通比，来调节母线电压，从而能够实现对四电平输出的灵活控制。
应注意，图7和图8中的第四开关组件Q4和第五开关组件Q5也可以采用图3中的串联方式。图7和图8中所示的Buck-Boost电路也可以采用其他的DC/DC变换器，本发明实施例对此不作限定。例如，图2或图3中的输入端可以连接变换器的输出端或者整流器的输出端。也就是说，可以将变换器的输出或整流器的输出作为该多电平拓扑的电路的输入。
可选地，作为另一个实施例，在图2或图3的四电平拓扑的电路的基础上，可以实现三相系统，如图9所示。可以看出，图9所示的三相系统包括三个第五端口，分别为A51、A52和A53。
可理解，图9所示的三相系统是由三个四电平拓扑共用第一端口至第四端口所构成的。
可选地，第四端子A4可以接地。
可选地，第一端子A1、第二端子A2、第三端子A3和第四端子A4可以作为输入端。例如，可以如图5所示在A1-A4连接三个电压源。或者，也 可以如图7或图8所示在A1-A4连接两个DC/DC变换电路。
可选地，作为另一个实施例，可以在图2或图3所示的四电平拓扑的基础上构建更高的电平拓扑。例如，在图2的基础上所构建的多电平拓扑为N电平拓扑，且N为大于4的偶数，如图10所示，电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子至第N+1端子，所述2N-8个开关组件包括第七开关组件至第2N-2开关组件；
第2i-5开关组件Q(2i-5)的第一端与第i端子A(i)连接，所述第2i-5开关组件Q(2i-5)的第二端与第(i-2)/2支路的第一端连接，其中，i＝6,7,…,N；
第2i-4开关组件Q(2i-4)的第二端与第i+1端子A(i+1)连接，所述第2i-4开关组件Q(2i-4)的第二端与所述第(i-2)/2支路的第一端连接，其中，所述第(i-2)/2支路包括串联的第2i-3开关组件Q(2i-3)和第2i-2开关组件Q(2i-2)，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件Q(2i-3)的第一端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件Q(2i-2)的第一端，或者，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件Q(2i-3)的第二端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件Q(2i-2)的第二端；
所述第(i-2)/2支路的第二端与所述第五端子A5连接。
这样，能够利用该多电平拓扑实现DC/AC的转换。例如，可以在第一端子A1和第二端子A2之间、第二端子A2和第三端子A3之间、第三端子A3和第六端子A6之间、第i端子A(i)和第i+1端子A(i+1)之间、第N+1端子A(N+1)和第四端子A4之间连接直流电压源，那么，可以通过调节开关组件的状态，实现N电平输出，并且在通过滤波器之后，从第四端子A4和第五端子A5输出的电压越接近于正弦，即输出的电压为交流电压。
具体地，当N＝6时，该六电平拓扑的电路可以如图11所示，包括：七个端子(A1-A7)和十个开关组件(Q1-Q10)。
其中，七个端子(A1-A7)包括第一端子A1、第二端子A2、第三端子A3、第四端子A4、第五端子A5、第六端子A6和第七端子A7。十个开关组件(Q1-Q10)包括第一开关组件Q1、第二开关组件Q2、第三开关组件Q3、第四开关组件Q4、第五开关组件Q5、第六开关组件Q6、第七开关组件Q7、第八开关组件Q8、第九开关组件Q9和第十开关组件Q10。
第一开关组件Q1的第一端与第一端子A1连接，所述第一开关组件Q1的第二端与第五端子A5连接；
第二开关组件Q2的第一端与第二端子A2连接，所述第二开关组件Q2的第二端与第一支路的第一端连接；第三开关组件Q3的第二端与第三端子A3连接，所述第三开关组件Q3的第一端与所述第一支路的第一端连接，其中，所述第一支路包括串联的第四开关组件Q4和第五开关组件Q5，所述第一支路的第一端连接所述第四开关组件Q4的第一端且所述第一支路的第二端连接所述第五开关组件Q5的第一端；
第七开关组件Q7的第一端与第六端子A6连接，所述第七开关组件Q7的第二端与第二支路的第一端连接；第八开关组件Q8的第二端与第七端子A7连接，所述第八开关组件Q8的第一端与所述第二支路的第一端连接，其中，所述第二支路包括串联的第九开关组件Q9和第十开关组件Q10，所述第二支路的第一端连接所述第九开关组件Q9的第一端且所述第二支路的第二端连接所述第十开关组件Q10的第一端；
第六开关组件Q6的第二端与第四端子A4连接，所述第六开关组件Q6的第一端与所述第五端子A5连接；
所述第一支路的第二端与所述第五端子A5连接，所述第二支路的第二端与所述第五端子A5连接。
另外，图11所示的六电平拓扑的电路还包括五个直流电压源。具体地，第一端子A1与第一电压源DC1的正极连接，第二端子A2与第一电压源DC1的负极连接。第二端子A2与第二电压源DC2的正极连接，第三端子A3与第二电压源DC2的负极连接。第三端子A3与第三电压源DC3的正极连接，第六端子A6与第三电压源DC3的负极连接。第六端子A6与第四电压源DC4的正极连接，第七端子A7与第四电压源DC4的负极连接。第七端子A7与第五电压源DC5的正极连接，第四端子A4与第五电压源DC5的负极连接。
其中，第四端子A4可以接地。
这样，可以通过调节开关组件的状态，实现六电平输出。
例如，假设五个直流电压源的电压值相等，即DC1＝DC2＝DC3＝DC4＝DC5＝DC。可以通过控制开关组件的接通或关断，实现六电平的输出电压。具体地，可以如下表二所示。
表二
电平 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10
5DC 1 1 0 1 0 0 1 0 1 0
4DC 0 1 0 1 1 0 1 0 1 0
3DC 0 0 1 1 1 0 1 0 1 0
2DC 0 0 1 0 1 0 1 0 1 1
DC 0 0 1 0 1 0 0 1 1 1
0 0 0 1 0 1 1 0 1 0 1
其中，“1”表示开关组件的状态为第一状态，“0”表示开关组件的状态为第二状态。
在图10或图11所示的多电平拓扑的电路中，开关组件可以采用耐压值较小的开关管，能够节约成本。并且，由于采用耐压值较低的开关器件，能够减少损耗，从而提高系统的性能。
应注意，图10和图11中的第四开关组件Q4和第五开关组件Q5也可以采用图3中的串联方式。图10中的第2i-3开关组件Q(2i-3)和第2i-2开关组件Q(2i-2)，图11中的第九开关组件Q9和第十开关组件Q10也可以采用同样的串联方式。本发明对此不作限定。
应注意，图10所示的多电平拓扑的电路中，第一端子A1至第四端子A4，第六端子A6至第N+1端子可以作为该多电平拓扑的电路的输入端。第四端子A4和第五端子A5可以作为该多电平拓扑的电路的输出端。
可理解，参照前述关于四电平拓扑的描述，图10所示的多电平拓扑的电路的输入端可以连接电压源，或者可以连接多个DC/DC变换电路作为输入，为避免重复，这里不再赘述。
另外，参照前述图9的描述，可以利用图10所示的多电平拓扑的电路类似地得到多电平拓扑的三相系统，为避免重复，这里不再赘述。
可选地，作为另一个实施例，可以在图2或图3所示的四电平拓扑的基础上构建更高的电平拓扑。例如，在图2的基础上所构建的多电平拓扑为N电平拓扑，如图12所示，电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子A6至第N+1端子A(N+1)，所述2N-8个开关组件包括第七开关组件Q7至第2N-2开关组件Q(2N-2)，N为大于4的正整数；
第j+1开关组件Q(j+1)的第一端与第j端子A(j)连接，第j+1开关组件 Q(j+1)的第二端与第j+N-3开关组件Q(j+N-3)的第二端连接，所述第j+N-3开关组件Q(j+N-3)的第一端与所述第一支路的第一端连接，其中，j＝6,7,…,N+1。
这样，能够利用该多电平拓扑实现DC/AC的转换。例如，可以在第一端子A1和第二端子A2之间、第二端子A2和第六端子A6之间、第j端子A(j)和第j+1端子A(j+1)之间、第N+1端子A(N+1)和第三端子A3之间、第三端子A3和第四端子A4之间连接直流电压源，那么，可以通过调节开关组件的状态，实现N电平输出，并且在通过滤波器之后，从第四端子A4和第五端子A5输出的电压越接近于正弦，即输出的电压为交流电压。
具体地，当N＝5时，该多电平拓扑为五电平拓扑，该五电平拓扑的电路可以如图13所示，包括：六个端子(A1-A6)和八个开关组件(Q1-Q8)。
其中，六个端子(A1-A6)包括第一端子A1、第二端子A2、第三端子A3、第四端子A4、第五端子A5和第六端子A6。八个开关组件(Q1-Q8)包括第一开关组件Q1、第二开关组件Q2、第三开关组件Q3、第四开关组件Q4、第五开关组件Q5、第六开关组件Q6、第七开关组件Q7和第八开关组件Q8。
第一开关组件Q1的第一端与第一端子A1连接，所述第一开关组件Q1的第二端与第五端子A5连接；
第二开关组件Q2的第一端与第二端子A2连接，所述第二开关组件Q2的第二端与第一支路的第一端连接；第三开关组件Q3的第二端与第三端子A3连接，所述第三开关组件Q3的第一端与所述第一支路的第一端连接，其中，所述第一支路包括串联的第四开关组件Q4和第五开关组件Q5，所述第一支路的第一端连接所述第四开关组件Q4的第一端且所述第一支路的第二端连接所述第五开关组件Q5的第一端；
第七开关组件Q7的第一端与第六端子A6连接，第七开关组件Q7的第二端与第八开关组件Q8的第二端连接，所述第八开关组件Q8的第一端与所述第一支路的第一端连接；
第六开关组件Q6的第二端与第四端子A4连接，所述第六开关组件Q6的第一端与所述第五端子A5连接；
所述第一支路的第二端与所述第五端子A5连接。
另外，图13所示的五电平拓扑的电路还包括四个直流电压源。具体地， 第一端子A1与第一电压源DC1的正极连接，第二端子A2与第一电压源DC1的负极连接。第二端子A2与第二电压源DC2的正极连接，第六端子A6与第二电压源DC2的负极连接。第六端子A6与第三电压源DC3的正极连接，第三端子A3与第三电压源DC3的负极连接。第三端子A3与第四电压源DC4的正极连接，第四端子A4与第四电压源DC4的负极连接。
其中，第四端子A4可以接地。
这样，可以通过调节开关组件的状态，实现五电平输出。
例如，假设四个直流电压源的电压值相等，即DC1＝DC2＝DC3＝DC4＝DC。可以通过控制开关组件的接通或关断，实现五电平的输出电压。具体地，可以如下表三所示。
表三
电平 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
4DC 1 1 0 1 0 0 1 0
3DC 0 1 0 1 1 0 1 0
2DC 0 0 0 1 1 0 1 1
DC 0 0 1 1 1 0 0 1
0 0 0 1 0 1 1 0 1
其中，“1”表示开关组件的状态为第一状态，“0”表示开关组件的状态为第二状态。
在图12或图13所示的多电平拓扑的电路中，开关组件可以采用耐压值较小的开关管，能够节约成本。并且，由于采用耐压值较低的开关器件，能够减少损耗，从而提高系统的性能。
应注意，图12和图13中的第四开关组件Q4和第五开关组件Q5也可以采用图3中的串联方式。
应注意，图12所示的多电平拓扑的电路中，第一端子A1至第四端子A4，第六端子A6至第N+1端子可以作为该多电平拓扑的电路的输入端。第四端子A4和第五端子A5可以作为该多电平拓扑的电路的输出端。
可理解，参照前述关于四电平拓扑的描述，图12所示的多电平拓扑的电路的输入端可以连接电压源，或者可以连接多个DC/DC变换电路作为输入，为避免重复，这里不再赘述。
另外，参照前述图9的描述，可以利用图12所示的多电平拓扑的电路类似地得到多电平拓扑的三相系统，为避免重复，这里不再赘述。
可选地，作为另一个实施例，上述实施例中的多电平拓扑可以与耦合电感硅磁结合，组成复合电路，实现更高的电平数。如图14所示，复合电路包括M个多电平拓扑(11-1M)和耦合电感140。其中，M个多电平拓扑(11-1M)包括第一多电平拓扑11、第二多电平拓扑12、…、第M多电平拓扑1M。耦合电感140包括M个输入端子和输出端子A0。其中，M个输入端子对应M个电感(L1-LM)。
所述M个输入端子分别与多电平拓扑(11-1M)的电路的第五端子连接。
可理解，图14中所示的耦合电感为M相耦合电感。
这样，本实施例中将耦合电感与多电平拓扑结合，能够实现更高的电平数，提高等效开关频率，减小输出的纹波，从而极大地降低输出滤波器的成本与体积。
举例来说，假设图14中的多电平拓扑均为N电平拓扑，其中，当N为偶数时，N电平拓扑可以如图10或图12所示。当N为奇数时，N电平拓扑可以如图12所示。假设N电平拓扑的工作频率为f，那么，通过与M相耦合电感进行耦合，可以得出，输出的等效开关频率为M×f，输出的电平数为M×N+1。输出的电平数以及等效开关的频率极大地增加，输出纹波急剧减小，因而可以大幅降低输出滤波器件的成本和体积。同时也为减低开关频率提供了条件，开关频率减小，开关损耗可以等比例下降，变换器系统的效率能得到大幅的提升。
图15是本发明一个实施例的功率变换器的示意性框图。图15所示的功率变换器1500包括多电平拓扑1501和控制器1502。
其中，多电平拓扑1501可以参见前述图2或图3或图5、图7至图14中任一个实施例中的多电平拓扑。
其中，控制器1502可以用于控制多电平拓扑1501中的开关组件的状态。具体地，控制器1502可以通过硬件与软件结合的方式改变开关组件的状态。其中，控制器1502可以是处理器的形式。
处理器可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，对多电平拓扑的开关组件的状态的控制可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信 号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。
软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。可以理解，本发明实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
可选地，当多电平拓扑1501为前述图13的实施例所示的五电平拓扑时，该功率变换器1500可以为五电平逆变器。
可选地，当多电平拓扑1501为前述图11的实施例所示的六电平拓扑时，该功率变换器1500可以为六电平逆变器。
可选地，当多电平拓扑1501为前述图10或图12的实施例所示的N电平拓扑时，该功率变换器1500可以为N电平逆变器。
作为一例，此时，该N电平逆变器还可以包括N-1个输入电压源。该 N-1个输入电压源可以连接在N+1个端子中除第五端子A5之外的其他的端子之间。具体地，N-1个输入电压源的连接方式可以参见图11或图13的描述，为避免重复，这里不再赘述。
作为一例，此时，该N电平逆变器还可以包括N-2个直流/直流变换电路。该N-2个直流/直流变换电路可以连接在N+1个端子中除第五端子A5之外的其他的端子之间。具体地，N-2个直流/直流变换电路的连接方式可以类比于图7或图8中四电平拓扑的相关描述，为避免重复，这里不再赘述。
可选地，当多电平拓扑1501为前述图2、图3、图5、图7或图8的实施例所示的四电平拓扑时，该功率变换器1500可以为四电平逆变器。
具体地，图16是本发明一个实施例的功率变换器的结构示意图。图16所示的功率变换器1600包括图5所示的四电平拓扑的电路和控制器1601。
控制器1601，与所述六个开关组件(Q1至Q6)连接，用于控制所述六个开关组件的状态。
可理解，本发明实施例中，可以通过控制器1601的控制，改变开关组件的状态。其中，开关组件可以如图4所示。
可选地，开关组件的状态可以为第一状态或第二状态。其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
这样，若所述第一电压源的输入电压的值为DC1，所述第二电压源的输入电压的值为DC2，所述第三电压源的输入电压的值为DC3，
当控制器1601控制所述第一开关组件Q1、所述第二开关组件Q2和所述第四开关组件Q4的状态为第一状态，且所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC1+DC2+DC3；
当控制器1601控制所述第二开关组件Q2、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第三开关组件Q3和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC2+DC3；
当控制器1601控制所述第三开关组件Q3、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC3；
当控制器1601控制所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第四开关组件Q4的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为0；
具体地，可以参见前述图5的实施例中表一所示。
例如，若假设DC1＝DC2＝DC3，且DC1+DC2+DC3＝Vbus。那么，图17(a)为功率变换器1600的输出电压的示意图。图17(b)为经过滤波之后的功率变换器1600的输出电压的示意图。
电平数越高，输出电压会越接近于正弦，因而所需滤波器的尺寸、成本会大幅降低，有利于系统实现高功率密度。
可选地，图16所示的功率变换器1600可以为四电平逆变器。
图18是本发明另一个实施例的功率变换器的结构示意图。图18所示的功率变换器1800包括图7所示的四电平拓扑的电路、输入电压源DC1和控制器1801。
所述第二端子A2与所述输入电压源DC1的正极连接，所述第三端子A3与所述输入电压源DC1的负极连接；
所述控制器1801，与所述六个开关组件(Q1至Q6)连接，用于控制所述六个开关组件的状态。
另外，控制器1801也可以与第一直流/直流变换电路中的开关组件连接，并控制该第一直流/直流变换电路中的开关组件的状态；控制器1801也可以与第二直流/直流变换电路中的开关组件连接，并控制该第二直流/直流变换电路中的开关组件的状态。
若所述输入电压源的输入电压的值为DC1，经过所述第一直流/直流变换电路后的所述第一端子A1和所述第二端子A2之间的电压的值为DC2，经过所述第二直流/直流变换电路后的所述第三端子A3和所述第四端子A4之间的电压的值为DC3，
当所述控制器1801控制所述第一开关组件Q1、所述第二开关组件Q2 和所述第四开关组件Q4的状态为第一状态，且所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC1+DC2+DC3；
当所述控制器1801控制所述第二开关组件Q2、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第三开关组件Q3和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC1+DC3；
当所述控制器1801控制所述第三开关组件Q3、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC3；
当所述控制器1801控制所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第四开关组件Q4的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为0；
其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
应注意，图18所示的实施例中，可以通过调整第一直流/直流变换电路和第二直流/直流变换电路调整DC2和DC3，这样能够增大该功率变换器的输出电压的范围，进而使得该功率变换器更加灵活。
可选地，图18所示的功率变换器1800可以为四电平逆变器。
图19是本发明另一个实施例的功率变换器的结构示意图。图19所示的功率变换器1900包括图8所示的四电平拓扑的电路、第一输入电压源DC1、第二输入电压源DC2和控制器1901。
所述第二端子A2与所述第一输入电压源DC1的正极连接，所述第一直流/直流变换电路的第二输入端A0与所述第一输入电压源DC1的负极连接；
所述第二直流/直流变换电路的第一输入端A0与所述第二输入电压源DC2的正极连接，所述第三端子A3与所述第二输入电压源DC2的负极连接；
所述控制器1901，与所述六个开关组件(Q1至Q6)连接，用于控制所述六个开关组件的状态。
另外，控制器1901也可以与第一直流/直流变换电路中的开关组件连接，并控制该第一直流/直流变换电路中的开关组件的状态；控制器1901也可以与第二直流/直流变换电路中的开关组件连接，并控制该第二直流/直流变换电路中的开关组件的状态。
若所述第一输入电压源的输入电压的值为DC1，所述第二输入电压源的输入电压的值为DC2，经过所述第一直流/直流变换电路后的所述第一端子A1和所述第二端子A2之间的电压的值为DC3，经过所述第二直流/直流变换电路后的所述第三端子A3和所述第四端子A4之间的电压的值为DC4，
当所述控制器1901控制所述第一开关组件Q1、所述第二开关组件Q2和所述第四开关组件Q4的状态为第一状态，且所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC1+DC2+DC3+DC4；
当所述控制器1901控制所述第二开关组件Q2、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第三开关组件Q3和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC1+DC2+DC4；
当所述控制器1901控制所述第三开关组件Q3、所述第四开关组件Q4和所述第五开关组件Q5的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第六开关组件Q6的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为DC4；
当所述控制器1901控制所述第三开关组件Q3、所述第五开关组件Q5和所述第六开关组件Q6的状态为第一状态，且所述第一开关组件Q1、所述第二开关组件Q2和所述第四开关组件Q4的状态为第二状态时，所述第四端子A4和所述第五端子A5之间的输出电压的值为0；
其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
应注意，图19所示的实施例中，可以通过调整第一直流/直流变换电路调整DC3，通过调整第二直流/直流变换电路调整DC4，这样能够增大该功率变换器的输出电压的范围，进而使得该功率变换器更加灵活。
可选地，图19所示的功率变换器1900为四电平逆变器。
应注意，当图15中的多电平拓扑1501为上述图10或图12所示的N电平拓扑时，图15中的功率变换器1500可以为N电平逆变器。若此时，该N电平逆变器还包括N-2个直流/直流变换电路，那么，可理解，该N电平逆变器还应该包括输入电压源。具体地，输入电压源的连接方式可以类比于上述图18或图19中的四电平逆变器中输入电压源的相关描述，为避免重复，这里不再赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一 个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种多电平拓扑的电路，其特征在于，包括：五个端子和六个开关组件，
    所述六个开关组件中的第一开关组件的第一端与所述五个端子中的第一端子连接，所述第一开关组件的第二端与所述五个端子中的第五端子连接；
    所述六个开关组件中的第二开关组件的第一端与所述五个端子中的第二端子连接，所述第二开关组件的第二端与第一支路的第一端连接；
    所述六个开关组件中的第三开关组件的第二端与所述五个端子中的第三端子连接，所述第三开关组件的第一端与所述第一支路的第一端连接，其中，所述第一支路包括串联的第四开关组件和第五开关组件，所述第一支路的第一端连接所述第四开关组件的第一端且所述第一支路的第二端连接所述第五开关组件的第一端，或者，所述第一支路的第一端连接所述第四开关组件的第二端且所述第一支路的第二端连接所述第五开关组件的第二端；
    所述六个开关组件中的第六开关组件的第二端与所述五个端子中的第四端子连接，所述第六开关组件的第一端与所述第五端子连接；
    所述第一支路的第二端与所述第五端子连接。
  2. 根据权利要求1所述的电路，其特征在于，
    所述第一端子与第一电压源的正极连接，所述第二端子与所述第一电压源的负极连接；
    所述第二端子与第二电压源的正极连接，所述第三端子与所述第二电压源的负极连接；
    所述第三端子与第三电压源的正极连接，所述第四端子与所述第三电压源的负极连接。
  3. 根据权利要求1所述的电路，其特征在于，
    所述第二端子和所述第三端子分别连接第一直流/直流变换电路的第一输入端和第二输入端，所述第一端子和所述第二端子分别连接所述第一直流/直流变换电路的第一输出端和第二输出端；
    所述第二端子和所述第三端子分别连接第二直流/直流变换电路的第一输入端和第二输入端，所述第三端子和所述第四端子分别连接所述第二直流/直流变换电路的第一输出端和第二输出端；
    其中，所述第一直流/直流变换电路和所述第二直流/直流变换电路共用同一个输入。
  4. 根据权利要求1所述的电路，其特征在于，
    所述第一端子连接第一直流/直流变换电路的第一输出端，所述第二端子连接所述第一直流/直流变换电路的第二输出端；
    所述第二端子连接所述第一直流/直流变换电路的第一输入端；
    所述第一直流/直流变换电路的第二输入端连接第二直流/直流变换电路的第一输入端；
    所述第三端子连接所述第二直流/直流变换电路的第二输入端；
    所述第四端子连接所述第二直流/直流变换电路的第一输出端，所述第三端子连接所述第二直流/直流变换电路的第二输出端。
  5. 根据权利要求1所述的电路，其特征在于，所述多电平拓扑为N电平拓扑，且N为大于4的偶数，所述电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子至第N+1端子，所述2N-8个开关组件包括第七开关组件至第2N-2开关组件；
    第2i-5开关组件的第一端与第i端子连接，所述第2i-5开关组件的第二端与第(i-2)/2支路的第一端连接，其中，i＝6,7,…,N；
    第2i-4开关组件的第二端与第i+1端子连接，所述第2i-4开关组件的第二端与所述第(i-2)/2支路的第一端连接，其中，所述第(i-2)/2支路包括串联的第2i-3开关组件和第2i-2开关组件，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件的第一端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件的第一端，或者，所述第(i-2)/2支路的第一端连接所述第2i-3开关组件的第二端且所述第(i-2)/2支路的第二端连接所述第2i-2开关组件的第二端；
    所述第(i-2)/2支路的第二端与所述第五端子连接。
  6. 根据权利要求1所述的电路，其特征在于，所述多电平拓扑为N电平拓扑，所述电路还包括：N-4个端子和2N-8个开关组件，其中，所述N-4个端子包括第六端子至第N+1端子，所述2N-8个开关组件包括第七开关组件至第2N-2开关组件，N为大于4的正整数；
    第j+1开关组件的第一端与第j端子连接，第j+1开关组件的第二端与第j+N-3开关组件的第二端连接，所述第j+N-3开关组件的第一端与所述第一支路的第一端连接，其中，j＝6,7,…,N+1。
  7. 根据权利要求1至6任一项所述的电路，其特征在于，所述第四端子接地。
  8. 一种复合电路，其特征在于，包括M个权利要求1至7任一项所述的多电平拓扑的电路和耦合电感，其中，所述耦合电感包括M个输入端子和一个输出端子；
    所述M个输入端子分别与所述M个权利要求1至7任一项所述的多电平拓扑的电路的第五端子连接。
  9. 一种功率变换器，其特征在于，包括：权利要求2所述的电路和控制器，
    所述控制器，与所述六个开关组件连接，用于控制所述六个开关组件的状态。
  10. 根据权利要求9所述的功率变换器，其特征在于，所述第一电压源的输入电压的值为DC1，所述第二电压源的输入电压的值为DC2，所述第三电压源的输入电压的值为DC3，
    当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3；
    当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC2+DC3；
    当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC3；
    当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为0；
    其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关 组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
  11. 根据权利要求9或10所述的功率变换器，其特征在于，所述功率变换器为四电平逆变器。
  12. 一种功率变换器，其特征在于，包括：权利要求3所述的电路、输入电压源和控制器，
    所述第二端子与所述输入电压源的正极连接，所述第三端子与所述输入电压源的负极连接；
    所述控制器，与所述六个开关组件连接，用于控制所述六个开关组件的状态。
  13. 根据权利要求12所述的功率变换器，其特征在于，所述输入电压源的输入电压的值为DC1，经过所述第一直流/直流变换电路后的所述第一端子和所述第二端子之间的电压的值为DC2，经过所述第二直流/直流变换电路后的所述第三端子和所述第四端子之间的电压的值为DC3，
    当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3；
    当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC3；
    当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC3；
    当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输 出电压的值为0；
    其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
  14. 根据权利要求12或13所述的功率变换器，其特征在于，所述功率变换器为四电平逆变器。
  15. 一种功率变换器，其特征在于，包括：权利要求4所述的电路、第一输入电压源、第二输入电压源和控制器，
    所述第二端子与所述第一输入电压源的正极连接，所述第一直流/直流变换电路的第二输入端与所述第一输入电压源的负极连接；
    所述第二直流/直流变换电路的第一输入端与所述第二输入电压源的正极连接，所述第三端子与所述第二输入电压源的负极连接；
    所述控制器，与所述六个开关组件连接，用于控制所述六个开关组件的状态。
  16. 根据权利要求15所述的功率变换器，其特征在于，所述第一输入电压源的输入电压的值为DC1，所述第二输入电压源的输入电压的值为DC2，经过所述第一直流/直流变换电路后的所述第一端子和所述第二端子之间的电压的值为DC3，经过所述第二直流/直流变换电路后的所述第三端子和所述第四端子之间的电压的值为DC4，
    当所述控制器控制所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第一状态，且所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC3+DC4；
    当所述控制器控制所述第二开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第三开关组件和所述第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC1+DC2+DC4；
    当所述控制器控制所述第三开关组件、所述第四开关组件和所述第五开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述 第六开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为DC4；
    当所述控制器控制所述第三开关组件、所述第五开关组件和所述第六开关组件的状态为第一状态，且所述第一开关组件、所述第二开关组件和所述第四开关组件的状态为第二状态时，所述第四端子和所述第五端子之间的输出电压的值为0；
    其中，所述第一状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上导通且在所述开关组件的第二端到所述开关组件的第一端的方向上导通，所述第二状态是指开关组件在所述开关组件的第一端到所述开关组件的第二端的方向上断开且在所述开关组件的第二端到所述开关组件的第一端的方向上导通。
  17. 根据权利要求15或16所述的功率变换器，其特征在于，所述功率变换器为四电平逆变器。
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