WO2016107073A1 - 阵列基板及其驱动方法、显示装置 - Google Patents

阵列基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2016107073A1
WO2016107073A1 PCT/CN2015/080732 CN2015080732W WO2016107073A1 WO 2016107073 A1 WO2016107073 A1 WO 2016107073A1 CN 2015080732 W CN2015080732 W CN 2015080732W WO 2016107073 A1 WO2016107073 A1 WO 2016107073A1
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Prior art keywords
storage electrode
array substrate
line
lines
auxiliary storage
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PCT/CN2015/080732
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English (en)
French (fr)
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程鸿飞
先建波
乔勇
卢永春
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京东方科技集团股份有限公司
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Priority to US14/895,126 priority Critical patent/US10261375B2/en
Publication of WO2016107073A1 publication Critical patent/WO2016107073A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to an array substrate, a driving method thereof, and a display device.
  • the liquid crystal display is a flat and ultra-thin display device which is widely used in various fields.
  • the liquid crystal display includes an array substrate on which a plurality of gate lines, a plurality of data lines, and a plurality of storage electrode lines are disposed.
  • the gate line or the data line forms a coupling capacitance with the storage electrode line, thereby reducing the driving ability of the storage electrode signal on the storage electrode line;
  • the liquid crystal display is oriented toward the large The direction of the dimension is developed, the storage electrode line on the array substrate is long, and the resistance is large, so that the driving ability of the storage electrode signal on the storage electrode line becomes weaker as the transmission distance increases.
  • At least one embodiment of the present disclosure provides an array substrate, a driving method thereof, and a display device capable of improving driving capability of a storage electrode line.
  • At least one embodiment of the present disclosure provides an array substrate including a plurality of storage electrode lines, each of the storage electrode lines including at least two storage electrode signal input ends.
  • Each of the storage electrode lines includes two storage electrode signal input ends located at both ends of the storage electrode line.
  • the array substrate further includes at least one auxiliary storage electrode line, the at least one auxiliary storage electrode line connecting at least one of the plurality of storage electrode lines, each of the at least one auxiliary storage electrode line including at least one auxiliary storage At the electrode signal input end, a node connected to the at least one auxiliary storage electrode line on the plurality of storage electrode lines serves as a storage electrode signal input end.
  • a node connected to the at least one auxiliary storage electrode line on the plurality of storage electrode lines is a part of a storage electrode signal input end.
  • Each of the at least one auxiliary storage electrode line connects all of the plurality of storage electrode lines.
  • the at least one auxiliary storage electrode line includes a first auxiliary storage electrode line and a second auxiliary storage electrode line, and the first auxiliary storage electrode line and the second auxiliary storage electrode line are each connected to a part of the storage electrode line.
  • the first auxiliary storage electrode line is connected to the storage electrode lines of an odd row, and the second auxiliary storage electrode line is connected to the storage electrode lines of an even number of rows.
  • the array substrate further includes a plurality of mutually parallel gate lines and a plurality of mutually parallel data lines, the gate lines and the data lines are disposed to cross each other, and the plurality of storage electrode lines extend along the gate line direction;
  • the at least one auxiliary storage electrode line extends in the direction of the data line.
  • At least one embodiment of the present disclosure provides an array substrate including a plurality of storage electrode lines, each of the storage electrode lines including at least two storage electrode signal input ends, and thus, can input from at least two storage electrode signals
  • the storage electrode signal is input to the storage electrode line, so that the driving capability of the storage electrode signal on the storage electrode line can be enhanced, so that the uniformity of the storage electrode signal is better in the entire display device range, thereby improving the display effect of the display device.
  • At least one embodiment of the present disclosure also provides a display device including any of the above array substrates.
  • At least one embodiment of the present disclosure further provides a driving method of an array substrate, the array substrate includes a plurality of storage electrode lines, and the driving method includes:
  • a storage electrode signal is input to at least two storage electrode signal input terminals of each of the storage electrode lines.
  • the storage electrode signal is the same as or different from the common electrode signal.
  • Each of the storage electrode lines includes two storage electrode signal input ends at each of the storage electrode lines, and the input storage electrode signals are input to at least two storage electrode signal input ends of each storage electrode line, including:
  • a storage electrode signal is input to two storage electrode signal input terminals located at both ends of each of the storage electrode lines.
  • the array substrate includes at least one auxiliary storage electrode line, the at least one auxiliary storage electrode line is connected to at least one of the plurality of storage electrode lines, and each of the at least one auxiliary storage electrode line includes at least one auxiliary storage electrode a signal input end, the node connected to the at least one auxiliary storage electrode line on the plurality of storage electrode lines serves as a storage electrode signal input end;
  • the inputting the storage electrode signal to the at least two storage electrode signal input ends of each storage electrode line includes:
  • the storage electrode signal is input to the node as the storage electrode signal input terminal by inputting the storage electrode signal to the auxiliary storage electrode signal input terminal of the at least one auxiliary storage electrode line.
  • the at least one auxiliary storage electrode line includes a first auxiliary storage electrode line and a second auxiliary storage electrode line, and the first auxiliary storage electrode line and the second auxiliary storage electrode are each connected to a part of the storage electrode line;
  • the inputting the storage electrode signal to the auxiliary storage electrode signal input end of the at least one auxiliary storage electrode line, and inputting the storage electrode signal to the node as the storage electrode signal input end includes:
  • the first storage electrode signal and the second storage electrode signal are the same or different.
  • the amplitudes of the first storage electrode signal and the second storage electrode signal are different.
  • Embodiments of the present invention provide a driving method of an array substrate, wherein the driving method of the array substrate includes inputting a storage electrode signal to at least two storage electrode signal input ends of the storage electrode line, thereby enhancing a storage electrode signal on the storage electrode line.
  • the driving capability is such that the uniformity of the electrode signals stored in the entire display device range is good, and the display effect of the display device can be improved.
  • FIG. 1 is a schematic view of an array substrate in a first embodiment of the present disclosure
  • FIG 2 is another schematic view of the array substrate in the first embodiment of the present disclosure
  • FIG. 3 is still another schematic diagram of the array substrate in the first embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of a method of driving an array substrate in a second embodiment of the present disclosure
  • FIG. 6 is another timing chart of the driving method of the array substrate in the second embodiment of the present disclosure.
  • Embodiments of the present disclosure provide an array substrate capable of improving driving capability of a storage electrode signal on a storage electrode line.
  • the array substrate includes a plurality of storage electrode lines 1, each of the storage electrode lines 1 including at least two storage electrode signal input ends 11, and thus, from at least two storage electrode signal input terminals 11
  • the storage electrode signal is simultaneously input to the storage electrode line 1, so that the driving ability of the storage electrode signal on the storage electrode line 1 can be enhanced, so that the uniformity of the storage electrode signal is better in the entire display device range, thereby improving the display device. display effect.
  • each storage electrode line 1 includes at least two storage electrode signal input ends 11”:
  • each of the storage electrode lines 1 includes two storage electrode signal input terminals 11 at both ends of the storage electrode line 1.
  • the array substrate further includes at least one auxiliary storage electrode line 2, the auxiliary storage electrode line 2 is connected to the storage electrode line 1, and each auxiliary storage electrode line 2 includes at least one auxiliary storage.
  • the electrode signal input terminal 21, a node 12 on the storage electrode line 1 connected to the auxiliary storage electrode line 2 serves as a storage electrode signal input terminal 11. It should be noted that this The embodiment does not limit the position of the node 12 on the storage electrode line 1, and those skilled in the art can select according to actual needs.
  • each storage electrode line 1 may include two storage electrode signal input ends 11 located at both ends of the storage electrode line 1, or each storage electrode line 1 may include a storage electrode signal input end located at one end of the storage electrode line 1. 11.
  • the storage electrode signal input end 11 may not be disposed at each end of each storage electrode line 1. As long as each storage electrode line 1 can be ensured to include at least two storage electrode signal input ends 11, the present disclosure may be implemented. This example does not limit this.
  • the node 12 on the storage electrode line 1 connected to the auxiliary storage electrode line 2 is used as the storage electrode signal input terminal 11, or, as shown in FIG. 3, on the storage electrode line 1 and the auxiliary storage electrode.
  • the node 12 to which the line 2 is connected serves as a part of the storage electrode signal input terminal 11, and the storage electrode line 1 further includes other storage electrode signal input terminals 11.
  • the storage electrode line 1 further includes a storage electrode signal input terminal 11 located at both ends of the storage electrode line 1.
  • each of the auxiliary storage electrode lines 2 may be connected to all of the storage electrode lines 1; or, as shown in FIG. 4, each of the auxiliary storage electrode lines 2 may be connected to only a part of the storage electrodes. Line 1.
  • the auxiliary storage electrode lines 2 on the array substrate may be arranged as follows: as shown in FIG. 4, the auxiliary storage electrode lines 2 include the first auxiliary storage electrode lines. 22 and the second auxiliary storage electrode line 23, the first auxiliary storage electrode line 22 and the second auxiliary storage electrode line 23 are each connected to a part of the storage electrode line 1.
  • the storage electrode line 1 connected to the storage electrode line 1 and the second auxiliary storage electrode line 23 connected to the first auxiliary storage electrode line 22 can be used as all the storage electrode lines 1 on the array substrate or only on the array substrate.
  • a portion of the storage electrode line, that is, the array substrate further includes other storage electrode lines that are not connected to the first auxiliary storage electrode line 22 and the second auxiliary storage electrode line 23, which are not limited in the embodiment of the present disclosure.
  • the first auxiliary storage electrode line 22 is connected to the odd-numbered storage electrode lines 1, and the second auxiliary storage electrode line 23 is connected to the even-numbered storage electrode lines 1.
  • the first auxiliary storage electrode lines 22 are connected to the storage electrode lines.
  • the storage electrode line 1 connected to the second auxiliary storage electrode line 23 serves as all of the storage electrode lines 1 on the array substrate.
  • the array substrate in the embodiment of the present disclosure further includes a plurality of mutually parallel gate lines 3 and a plurality of parallel data lines 4, and the gate lines 3 and the data lines 4 are arranged to cross each other.
  • the storage electrode line 1 extends in the direction of the gate line 3
  • the auxiliary storage electrode line 2 extends in the direction of the data line 4.
  • the gate line 3 and the data line 4 surround a plurality of pixel units, and each of the pixel units is provided with a thin film transistor and a pixel electrode, wherein a gate of the thin film transistor is connected to the gate line 3, and the source The pole is connected to the data line 4, and the drain is connected to the pixel electrode.
  • the pixel electrode and the common electrode on the color filter substrate serve as two electrodes of the liquid crystal capacitor C LC
  • the pixel electrode and the storage electrode line serve as two electrodes of the storage capacitor C ST .
  • different auxiliary inputs are input to the auxiliary storage electrode signal input terminal 24 of the first auxiliary storage electrode line 22 and the auxiliary storage electrode signal input terminal 25 of the second auxiliary storage electrode line 23, respectively.
  • the electrode signal can be flexibly adjusted to adjust the voltage on the pixel electrode.
  • An embodiment of the present disclosure provides an array substrate, the array substrate includes a plurality of storage electrode lines, each of the storage electrode lines includes at least two storage electrode signal input ends, and thus can be stored from at least two storage electrode signal input ends.
  • the electrode line inputs the storage electrode signal, so that the driving ability of the storage electrode signal on the storage electrode line can be enhanced, so that the uniformity of the storage electrode signal is better in the entire display device range, and the display effect of the display device can be improved.
  • an embodiment of the present disclosure further provides a display device including the array substrate of any of the above.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an organic light emitting display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure provides a driving method for driving the array substrate according to the first embodiment, the driving method of the array substrate includes inputting a storage electrode signal to at least two storage electrode signal input ends 11 of the storage electrode line 1.
  • the driving ability of the storage electrode signal on the storage electrode line 1 can be enhanced, so that the uniformity of the storage electrode signal is better over the entire display device range, and the display effect of the display device can be improved.
  • the storage electrode signal is the same as or different from the common electrode signal.
  • the complexity of the display device driving can be reduced.
  • the storage electrode signal is different from the common electrode signal, the flexibility of the display device driving can be improved. Therefore, those skilled in the art can adjust the actual situation. Make a choice.
  • each of the storage electrode lines 1 includes two storage electrode signal input ends 11 located at opposite ends of the storage electrode line 1, at this time, at least two storage electrode signals to the storage electrode lines 1
  • the input terminal 11 inputs the storage electrode signal, including: inputting the storage electrode signal to the two storage electrode signal input terminals 11 located at both ends of each storage electrode line 1.
  • the array substrate includes at least one auxiliary storage electrode line 2, and the auxiliary storage electrode line 2 is connected to the storage electrode line 1, each auxiliary storage electrode line 2 including at least one auxiliary storage electrode signal input terminal 21,
  • each auxiliary storage electrode line 2 including at least one auxiliary storage electrode signal input terminal 21,
  • the storage electrode is input to the at least two storage electrode signal input terminals 11 of the storage electrode line 1
  • the signal includes inputting a storage electrode signal to the node 12 on the storage electrode line 1 as the storage electrode signal input terminal 11 by inputting the storage electrode signal to the auxiliary storage electrode signal input terminal 21 of the auxiliary storage electrode line 2.
  • the auxiliary storage electrode signal input to the auxiliary storage electrode line 2 is input.
  • the terminal 21 inputs the storage electrode signal, inputs the storage electrode signal to the node 12 on the storage electrode line 1 as the storage electrode signal input terminal 11, and simultaneously inputs the storage electrode signal to the other storage electrode signal input terminal 11 of the storage electrode line 1 to The driving ability of the storage electrode signal on the storage electrode line 1 is maximized.
  • FIG. 5 is a timing chart of a driving method of the array substrate in the second embodiment of the present disclosure.
  • the storage electrode signals CS1 and CS2 are respectively input to the auxiliary storage electrode signal input terminals 21 of the two auxiliary storage electrode lines 2, and at the same time, the storage electrode lines are The other storage electrode signal input terminal 11 of 1 inputs the storage electrode signal CS, wherein CS, CS1 and CS2 are all the same to improve the driving ability of the storage electrode signal on the storage electrode line 1.
  • the auxiliary storage electrode line 2 includes a first auxiliary storage electrode line 22 and a second auxiliary storage electrode line 23, and the first auxiliary storage electrode line 22 and the second auxiliary storage electrode line 23 are each connected to a part.
  • the storage electrode signal is input to the auxiliary storage electrode signal input terminal 21 of the auxiliary storage electrode line 2
  • the storage electrode signal is input to the node 12 on the storage electrode line 1 as the storage electrode signal input terminal 11, including : a node on the storage electrode line 1 connected to the first auxiliary storage electrode line 22 as the storage electrode signal input terminal 11 by inputting the first storage electrode signal to the auxiliary storage electrode signal input terminal 24 of the first auxiliary storage electrode line 22 12 inputting the first storage electrode signal; connecting the second storage electrode signal to the auxiliary storage electrode signal input terminal 25 of the second auxiliary storage electrode line 23 to the second auxiliary storage electrode line 23 as the storage electrode signal input terminal 11
  • the node 12 of the storage electrode line 1 inputs a second storage electrode signal.
  • the storage electrode line 1 connected to the storage electrode line 1 and the second auxiliary storage electrode line 23 connected to the first auxiliary storage electrode line 22 serves as all the storage electrode lines 1 on the array substrate or
  • the electrode line 1 is stored only as a part of the array substrate, which is not limited by the embodiment of the present disclosure.
  • the array substrate further includes the first auxiliary storage.
  • the electrode line 22 and the other auxiliary electrode line 23 connected to the second auxiliary storage electrode line 23 are stored, it is necessary to input the storage electrode signal to the storage electrode signal input terminal 11 of the other storage electrode line 1.
  • the first storage electrode signal and the second storage electrode signal are the same or different.
  • the amplitudes of the first storage electrode signal and the second storage electrode signal are different, so that the voltage on the pixel electrode can be adjusted more flexibly.
  • the first auxiliary storage electrode line 22 is connected to the odd-numbered storage electrode lines 1
  • the second auxiliary storage electrode line 23 is connected to the even-numbered storage electrode lines 1
  • the first storage electrode signals are When the amplitudes of the second storage electrode signals are different, the magnitude of the voltage on the pixel electrodes can be flexibly adjusted.
  • FIG. 6 is another timing chart of the driving method of the array substrate in the second embodiment of the present disclosure.
  • the first storage electrode signal CSa is input to the auxiliary storage electrode signal input terminal 24 of the first auxiliary storage electrode line 22, and the storage electrode line to the odd-numbered rows is input.
  • the other storage electrode signal input terminal 11 of 1 inputs the storage electrode signal CS O
  • the second storage electrode signal CSb is input to the auxiliary storage electrode signal input terminal 25 of the second auxiliary storage electrode line 23, and the other storage electrode line 1 of the even-numbered row
  • the storage electrode signal input terminal 11 inputs the storage electrode signal CS E , wherein CSa and CS O are the same, CSb and CS E are the same, but the amplitudes of CSa and CS O are different from the amplitudes of CSb and CS E , thereby enabling more flexibility. Adjust the voltage on the pixel electrode.
  • Embodiments of the present disclosure provide a driving method of an array substrate, wherein the driving method of the array substrate includes inputting a storage electrode signal to at least two storage electrode signal input ends of the storage electrode line, thereby enhancing a storage electrode signal on the storage electrode line.
  • the driving capability is such that the uniformity of the electrode signals stored in the entire display device range is good, and the display effect of the display device can be improved.

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Abstract

一种阵列基板及其驱动方法、显示装置。该阵列基板包括多条存储电极线(1)，每条所述存储电极线(1)包括至少两个存储电极信号输入端(11)。该阵列基板能够提高存储电极线(1)上的存储电极信号的驱动能力。

Description

阵列基板及其驱动方法、显示装置 技术领域
本公开涉及一种阵列基板及其驱动方法、显示装置。
背景技术
液晶显示器是一种平面超薄的显示装置，其被广泛应用于各个领域。液晶显示器包括阵列基板，阵列基板上设置有多条栅线、多条数据线和多条存储电极线。
在液晶显示器的显示过程中，一方面，栅线或者数据线会与存储电极线形成耦合电容，从而降低存储电极线上的存储电极信号的驱动能力；另一方面，随着液晶显示器的向着大尺寸的方向发展，阵列基板上的存储电极线的较长，电阻较大，从而导致随着传输距离的增加存储电极线上的存储电极信号的驱动能力越来越弱。
由于以上两个方面的原因，使得在液晶显示器的使用过程中，整个液晶显示器上的存储电极线上的存储电极信号的均一性较差，进而使得液晶显示器的显示效果不佳。
发明内容
本公开的至少一个实施例提供一种阵列基板及其驱动方法、显示装置，能够提高存储电极线的驱动能力。
本公开的至少一个实施例提供了一种阵列基板，包括多条存储电极线，每条所述存储电极线包括至少两个存储电极信号输入端。
每条所述存储电极线包括位于所述存储电极线两端的两个存储电极信号输入端。
所述阵列基板还包括至少一条辅助存储电极线，所述至少一条辅助存储电极线连接所述多条存储电极线中的至少一条，所述至少一条辅助存储电极线的每一条包括至少一个辅助存储电极信号输入端，所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端。
仅将所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端。
所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端的一部分。
所述至少一条辅助存储电极线的每一条均连接所有所述多条存储电极线。
所述至少一条辅助存储电极线包括第一辅助存储电极线和第二辅助存储电极线，所述第一辅助存储电极线和所述第二辅助存储电极线各连接一部分所述存储电极线。
所述第一辅助存储电极线连接奇数行的所述存储电极线，所述第二辅助存储电极线连接偶数行的所述存储电极线。
所述阵列基板还包括多条相互平行的栅线和多条相互平行的数据线，所述栅线和所述数据线相互交叉设置，所述多条存储电极线沿所述栅线方向延伸；所述至少一条辅助存储电极线沿所述数据线方向延伸。
本公开的至少一个实施例提供了一种阵列基板，该阵列基板包括多条存储电极线，每条存储电极线包括至少两个存储电极信号输入端，因此，可以从至少两个存储电极信号输入端向存储电极线输入存储电极信号，从而可以增强存储电极线上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
此外，本公开的至少一个实施例还提供了一种显示装置，该显示装置包括以上任一阵列基板。
本公开的至少一个实施例还提供了一种阵列基板的驱动方法，所述阵列基板包括多条存储电极线，所述驱动方法包括：
向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号。
所述存储电极信号与公共电极信号相同或者不同。
每条所述存储电极线包括位于所述每条存储电极线两端的两个存储电极信号输入端，所述向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号，包括：
向位于每条所述存储电极线两端的两个存储电极信号输入端输入存储电极信号。
所述阵列基板包括至少一条辅助存储电极线，所述至少一条辅助存储电极线连接所述多条存储电极线中的至少一条，所述至少一条辅助存储电极线的每一条包括至少一个辅助存储电极信号输入端，所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端；
所述向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号，包括：
通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号。
进一步地，通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号，同时，向具有所述节点的存储电极线的除所述节点以外的其他存储电极信号输入端输入存储电极信号。
所述至少一条辅助存储电极线包括第一辅助存储电极线和第二辅助存储电极线，所述第一辅助存储电极线和所述第二辅助存储电极各连接一部分所述存储电极线；
所述通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号，包括：
通过向所述第一辅助存储电极线的辅助存储电极信号输入端输入第一存储电极信号，向所述第一辅助存储电极线与所述多条存储电极线中的至少一条相连接的节点输入第一存储电极信号；
通过向所述第二辅助存储电极线的辅助存储电极信号输入端输入第二存储电极信号，向所述第二辅助存储电极线与所述多条存储电极线中的至少一条相连接的节点输入第二存储电极信号。
所述第一存储电极信号和所述第二存储电极信号相同或者不同。
所述第一存储电极信号和所述第二存储电极信号的幅值不同。
本发明实施例提供了一种阵列基板的驱动方法，该阵列基板的驱动方法包括向存储电极线的至少两个存储电极信号输入端输入存储电极信号，从而可以增强存储电极线上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
附图说明
图1为本公开第一实施例中的阵列基板的一个示意图；
图2为本公开第一实施例中的阵列基板的另一示意图；
图3为本公开第一实施例中的阵列基板的又一示意图；
图4为本公开第一实施例中的阵列基板的再一示意图；
图5为本公开第二实施例中的阵列基板的驱动方法的一个时序图；
图6为本公开第二实施例中的阵列基板的驱动方法的另一时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
第一实施例
本公开实施例提供了一种阵列基板，能够提高存储电极线上的存储电极信号的驱动能力。
图1-图4为本公开第一实施例中的阵列基板的示意图。如图1-图4所示，该阵列基板包括多条存储电极线1，每条存储电极线1包括至少两个存储电极信号输入端11，因此，可以从至少两个存储电极信号输入端11向存储电极线1同时输入存储电极信号，从而可以增强存储电极线1上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
例如，本公开实施例提供了“每条存储电极线1包括至少两个存储电极信号输入端11”的具体实现方式：
第一种实现方式，如图1所示，每条存储电极线1包括位于存储电极线1两端的两个存储电极信号输入端11。
第二种实现方式，如图2-图3所示，阵列基板还包括至少一条辅助存储电极线2，辅助存储电极线2连接存储电极线1，每条辅助存储电极线2包括至少一个辅助存储电极信号输入端21，存储电极线1上与辅助存储电极线2连接的一个节点12作为一个存储电极信号输入端11。需要说明的是，本公 开实施例未对存储电极线1上节点12的位置进行限定，本领域技术人员可以根据实际需要进行选择。
此时，每条存储电极线1可以包括位于存储电极线1两端的两个存储电极信号输入端11，或者，每条存储电极线1可以包括位于存储电极线1一端的一个存储电极信号输入端11，或者，每条存储电极线1的两端可以均未设置有存储电极信号输入端11，只要能保证每条存储电极线1包括至少两个存储电极信号输入端11即可，本公开实施例对此不作限定。
例如，如图2所示，仅将存储电极线1上与辅助存储电极线2连接的节点12作为存储电极信号输入端11，或者，如图3所示，存储电极线1上与辅助存储电极线2连接的节点12作为存储电极信号输入端11的一部分，此时存储电极线1还包括其他存储电极信号输入端11。例如，存储电极线1还包括位于存储电极线1两端的存储电极信号输入端11。
进一步地，如图2和图3所示，每条辅助存储电极线2可以均连接所有存储电极线1；或者，如图4所示，每条辅助存储电极线2也可以仅连接部分存储电极线1。当每条辅助存储电极线2仅连接部分存储电极线1时，阵列基板上的辅助存储电极线2可以采用如下设置方式：如图4所示，辅助存储电极线2包括第一辅助存储电极线22和第二辅助存储电极线23，第一辅助存储电极线22和第二辅助存储电极线23各连接一部分存储电极线1。需要说明的是，第一辅助存储电极线22连接的存储电极线1和第二辅助存储电极线23连接的存储电极线1可以作为阵列基板上的所有存储电极线1或者仅作为阵列基板上的一部分存储电极线，即阵列基板还包括未与第一辅助存储电极线22和第二辅助存储电极线23连接的其他存储电极线，本公开实施例对此不进行限定。进一步地，第一辅助存储电极线22连接奇数行的存储电极线1，第二辅助存储电极线23连接偶数行的存储电极线1，此时，第一辅助存储电极线22连接的存储电极线1和第二辅助存储电极线23连接的存储电极线1作为阵列基板上的所有存储电极线1。
此外，如图2-图4所示，本公开实施例中的阵列基板还包括多条相互平行的栅线3和多条相互平行的数据线4，栅线3和数据线4相互交叉设置，存储电极线1沿栅线3方向延伸，辅助存储电极线2沿数据线4方向延伸。作为本公开的一个实施例，上述栅线3和数据线4围成多个像素单元，每个 像素单元内设置有薄膜晶体管和像素电极，其中，薄膜晶体管的栅极与栅线3连接，源极与数据线4连接，漏极与像素电极连接。像素电极与彩膜基板上的公共电极作为液晶电容CLC的两个电极，像素电极与存储电极线作为存储电容CST的两个电极。当阵列基板具有如图4所示的结构时，分别向第一辅助存储电极线22的辅助存储电极信号输入端24和第二辅助存储电极线23的辅助存储电极信号输入端25输入不同的辅助存储电极信号，可以灵活地调节像素电极上的电压的大小。
本公开实施例提供了一种阵列基板，该阵列基板包括多条存储电极线，每条存储电极线包括至少两个存储电极信号输入端，因此，可以从至少两个存储电极信号输入端向存储电极线输入存储电极信号，从而可以增强存储电极线上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
此外，本公开实施例还提供了一种显示装置，该显示装置包括以上任一所述的阵列基板。该显示装置可以为：液晶面板、电子纸、有机发光显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
第二实施例
本公开实施例提供了一种用以驱动第一实施例所述的阵列基板的驱动方法，该阵列基板的驱动方法包括向存储电极线1的至少两个存储电极信号输入端11输入存储电极信号，从而可以增强存储电极线1上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
需要说明的是，存储电极信号与公共电极信号相同或者不同。当存储电极信号与公共电极信号相同时，可以降低显示装置驱动的复杂性，当存储电极信号与公共电极信号不同时，可以提高显示装置驱动的灵活性，因此，本领域技术人员可以根据实际情况进行选择。
进一步地，当如图1所示，每条存储电极线1包括位于存储电极线1两端的两个存储电极信号输入端11时，此时，上述向存储电极线1的至少两个存储电极信号输入端11输入存储电极信号，包括：向位于每条存储电极线1两端的两个存储电极信号输入端11输入存储电极信号。
当如图2-图4所示，阵列基板包括至少一条辅助存储电极线2，辅助存储电极线2连接存储电极线1，每条辅助存储电极线2包括至少一个辅助存储电极信号输入端21，存储电极线1上与辅助存储电极线2连接的一个节点12作为存储电极线1的一个存储电极信号输入端11时，上述向存储电极线1的至少两个存储电极信号输入端11输入存储电极信号，包括：通过向辅助存储电极线2的辅助存储电极信号输入端21输入存储电极信号，向作为存储电极信号输入端11的存储电极线1上的节点12输入存储电极信号。
例如，当如图3或者图4所示，存储电极线1上与辅助存储电极线2连接的节点12作为部分存储电极信号输入端11时，通过向辅助存储电极线2的辅助存储电极信号输入端21输入存储电极信号，向作为存储电极信号输入端11的存储电极线1上的节点12输入存储电极信号，同时，向存储电极线1的其他存储电极信号输入端11输入存储电极信号，以最大程度上提高存储电极线1上的存储电极信号的驱动能力。
图5为本公开第二实施例中的阵列基板的驱动方法的一个时序图。示例性地，对于图3所示的阵列基板，如图5所示，向两条辅助存储电极线2的辅助存储电极信号输入端21分别输入存储电极信号CS1和CS2，同时，向存储电极线1的其他存储电极信号输入端11输入存储电极信号CS，其中，CS、CS1和CS2均相同，以提高存储电极线1上的存储电极信号的驱动能力。
进一步地，当如图4所示，辅助存储电极线2包括第一辅助存储电极线22和第二辅助存储电极线23，第一辅助存储电极线22和第二辅助存储电极线23各连接一部分存储电极线1时，上述通过向辅助存储电极线2的辅助存储电极信号输入端21输入存储电极信号，向作为存储电极信号输入端11的存储电极线1上的节点12输入存储电极信号，包括：通过向第一辅助存储电极线22的辅助存储电极信号输入端24输入第一存储电极信号，向作为存储电极信号输入端11的第一辅助存储电极线22连接的存储电极线1上的节点12输入第一存储电极信号；通过向第二辅助存储电极线23的辅助存储电极信号输入端25输入第二存储电极信号，向作为存储电极信号输入端11的第二辅助存储电极线23连接的存储电极线1的节点12输入第二存储电极信号。
需要说明的是，第一辅助存储电极线22连接的存储电极线1和第二辅助存储电极线23连接的存储电极线1作为阵列基板上的所有存储电极线1或者 仅作为阵列基板上的一部分存储电极线1，本公开实施例对此不进行限定。当第一辅助存储电极线22连接的存储电极线1和第二辅助存储电极线23连接的存储电极线1作为阵列基板上的一部分存储电极线1，即阵列基板还包括未与第一辅助存储电极线22和第二辅助存储电极线23连接的其他存储电极线1时，则还需要向其他存储电极线1的存储电极信号输入端11输入存储电极信号。
进一步地，第一存储电极信号和第二存储电极信号相同或者不同。例如，本公开实施例中，第一存储电极信号和第二存储电极信号的幅值不同，从而可以更灵活地调节像素电极上的电压。示例性地，当如图4所示，第一辅助存储电极线22连接奇数行的存储电极线1，第二辅助存储电极线23连接偶数行的存储电极线1，且第一存储电极信号和第二存储电极信号的幅值不同时，可以灵活地调节像素电极上的电压的大小。
图6为本公开第二实施例中的阵列基板的驱动方法的另一时序图。示例性地，对于图4所示的阵列基板，如图6所示，向第一辅助存储电极线22的辅助存储电极信号输入端24输入第一存储电极信号CSa，向奇数行的存储电极线1的其他存储电极信号输入端11输入存储电极信号CSO，向第二辅助存储电极线23的辅助存储电极信号输入端25输入第二存储电极信号CSb，向偶数行的存储电极线1的其他存储电极信号输入端11输入存储电极信号CSE，其中，CSa和CSO相同，CSb和CSE相同，但CSa和CSO的幅值与CSb和CSE的幅值不同，从而能够更灵活地调节像素电极上的电压。
本公开实施例提供了一种阵列基板的驱动方法，该阵列基板的驱动方法包括向存储电极线的至少两个存储电极信号输入端输入存储电极信号，从而可以增强存储电极线上的存储电极信号的驱动能力，以使得在整个显示装置范围内存储电极信号的均一性较好，进而能够改善显示装置的显示效果。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2014年12月30日递交的中国专利申请第201410841743.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims (20)

  1. 一种阵列基板，包括多条存储电极线，每条所述存储电极线包括至少两个存储电极信号输入端。
  2. 根据权利要求1所述的阵列基板，其中，每条所述存储电极线包括位于所述存储电极线两端的两个存储电极信号输入端。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括至少一条辅助存储电极线，所述至少一条辅助存储电极线连接所述多条存储电极线中的至少一条，所述至少一条辅助存储电极线的每一条包括至少一个辅助存储电极信号输入端，所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端。
  4. 根据权利要求3所述的阵列基板，其中，仅将所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端。
  5. 根据权利要求3所述的阵列基板，其中，所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端的一部分。
  6. 根据权利要求3-5任一项所述的阵列基板，其中，所述至少一条辅助存储电极线的每一条均连接所有所述多条存储电极线。
  7. 根据权利要求3-5任一项所述的阵列基板，其中，所述至少一条辅助存储电极线包括第一辅助存储电极线和第二辅助存储电极线，所述第一辅助存储电极线和所述第二辅助存储电极线各连接一部分所述存储电极线。
  8. 根据权利要求7所述的阵列基板，其中，所述第一辅助存储电极线连接奇数行的所述存储电极线，所述第二辅助存储电极线连接偶数行的所述存储电极线。
  9. 根据权利要求3-8任一项所述的阵列基板，其中，所述阵列基板还包括多条相互平行的栅线和多条相互平行的数据线，所述栅线和所述数据线相互交叉设置，所述多条存储电极线沿所述栅线方向延伸；所述至少一条辅助存储电极线沿所述数据线方向延伸。
  10. 一种显示装置，包括如权利要求1-9任一项所述的阵列基板。
  11. 一种阵列基板的驱动方法，所述阵列基板包括多条存储电极线，所述驱动方法包括：
    向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号。
  12. 根据权利要求11所述的阵列基板的驱动方法，其中，
    所述存储电极信号与公共电极信号相同。
  13. 根据权利要求11所述的阵列基板的驱动方法，其中，
    所述存储电极信号与公共电极信号不同。
  14. 根据权利要求11所述的阵列基板的驱动方法，其中，
    每条所述存储电极线包括位于所述每条存储电极线两端的两个存储电极信号输入端，所述向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号，包括：
    向位于每条所述存储电极线两端的两个存储电极信号输入端输入存储电极信号。
  15. 根据权利要求11所述的阵列基板的驱动方法，其中，
    所述阵列基板包括至少一条辅助存储电极线，所述至少一条辅助存储电极线连接所述多条存储电极线中的至少一条，所述至少一条辅助存储电极线的每一条包括至少一个辅助存储电极信号输入端，所述多条存储电极线上与所述至少一条辅助存储电极线连接的节点作为存储电极信号输入端；
    所述向每条存储电极线的至少两个存储电极信号输入端输入存储电极信号，包括：
    通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号。
  16. 根据权利要求15所述的阵列基板的驱动方法，其中，通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号，同时，向具有所述节点的存储电极线的除所述节点以外的其他存储电极信号输入端输入存储电极信号。
  17. 根据权利要求15或16所述的阵列基板的驱动方法，其中，
    所述至少一条辅助存储电极线包括第一辅助存储电极线和第二辅助存储电极线，所述第一辅助存储电极线和所述第二辅助存储电极线各连接一部分所述存储电极线；
    所述通过向所述至少一条辅助存储电极线的辅助存储电极信号输入端输 入存储电极信号，向作为存储电极信号输入端的所述节点输入存储电极信号，包括：
    通过向所述第一辅助存储电极线的辅助存储电极信号输入端输入第一存储电极信号，向所述第一辅助存储电极线与所述多条存储电极线中的至少一条相连接的节点输入第一存储电极信号；
    通过向所述第二辅助存储电极线的辅助存储电极信号输入端输入第二存储电极信号，向所述第二辅助存储电极线与所述多条存储电极线中的至少一条相连接的节点输入第二存储电极信号。
  18. 根据权利要求17所述的阵列基板的驱动方法，其中，
    所述第一存储电极信号和所述第二存储电极信号相同。
  19. 根据权利要求17所述的阵列基板的驱动方法，其中，
    所述第一存储电极信号和所述第二存储电极信号不同。
  20. 根据权利要求19所述的阵列基板的驱动方法，其中，
    所述第一存储电极信号和所述第二存储电极信号的幅值不同。
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