WO2016106828A1 - 低温多晶硅(ltps)产品结构及制造方法 - Google Patents

低温多晶硅(ltps)产品结构及制造方法 Download PDF

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Publication number
WO2016106828A1
WO2016106828A1 PCT/CN2015/070524 CN2015070524W WO2016106828A1 WO 2016106828 A1 WO2016106828 A1 WO 2016106828A1 CN 2015070524 W CN2015070524 W CN 2015070524W WO 2016106828 A1 WO2016106828 A1 WO 2016106828A1
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Prior art keywords
layer
nmos
trace
pmos
insulating layer
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English (en)
French (fr)
Inventor
田勇
赵莽
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the invention relates to the technical field of liquid crystal production, in particular to a low-temperature polysilicon product structure capable of improving yield and a manufacturing method thereof.
  • Low temperature polysilicon thin film transistor (LTPS) TFT) liquid crystal display LCD
  • LTPS low temperature polysilicon thin film transistor
  • LCD liquid crystal display
  • A-Si silicon crystal arrangement of LTPS-TFT LCD is more amorphous than Amorphous.
  • Silicon, A-Si) has an order, so that the electron mobility is relatively 100 times higher, and the peripheral driving circuit can be simultaneously fabricated on the glass substrate to achieve the goal of system integration, space saving, and cost of driving the IC.
  • the LTPS process is relative to amorphous silicon (Amorphous) Silicon, A-Si) has become very complicated and the requirements for the process have become very demanding. Therefore, optimization of low temperature polysilicon (LTPS) process design is also particularly important.
  • FIG. 2 is a flat layer in the prior art LTPS structure (Planarization) , PLN) Schematic diagram of the burrowing area.
  • a flat layer (Planarization, PLN) is usually used to dig a large second trench 40 to cover all the pads (Pad).
  • the pins of 34 or all of the integrated circuit (IC) 33 or the entire flexible circuit board 32 having a plurality of connection points are exposed.
  • the pad 34 (Pad) is the end point formed at the tip of the second trace 35 in the structure.
  • a plurality of second traces 35 are formed by the second metal layer 20, and the ends of the traces include a pad 34.
  • Some pads 34 can be connected to the circuit unit (Cell Test)
  • the pins of the test unit in addition to the pads 34 or the integrated circuit 33 (IC) pins or flexible printed circuit (FPC) Most of the 32 contacts are connected.
  • the integrated circuit 33 (IC) pin can be connected via the second metal layer 20 or directly to the flexible circuit board 32 (Flexible Print Circuit,
  • the contacts of the FPC are bonded, for example, the pads 34 of the integrated circuit 33 (IC) pins can be connected to the flexible circuit board 32 via the second trace 35 (Flexible Print Circuit, FPC) is joined.
  • the integrated circuit 33 (IC) pins and the flexible circuit board 32 are usually used.
  • Circuit, FPC The flat layer 21 corresponding to the entire area of the joint (Planarization, The PLN) is dug into a large trench 40 or the entire area of the corresponding plurality of pads 34 is dug into a large trench 40. Due to the flat layer 21 (Planarization, PLN) When the trench 40 is formed, there is excessive photoresist residue at the corner portion of the taper, so that the exposed portion is incomplete, and when the transparent conductive layer is formed, indium tin oxide (ITO) remains in the trench portion. The residual transparent conductive layer of indium tin oxide (ITO) shorts adjacent traces (such as signal lines and data lines), causing an abnormal display of the entire panel.
  • ITO indium tin oxide
  • a pad connecting a test unit of a circuit unit, a pin and a pad connecting the integrated circuit, and a pad connecting the pins of the flexible circuit board are combined with the first trace of the first metal layer.
  • the trench does not need to pass through the distribution region of the second metal (for example, the drain and source of the NMOS and the PMOS and the at least one second trace), and then the bonding of the integrated circuit or the flexible circuit board is performed. This avoids the problem of prior art short circuits and interferences using the second metal.
  • the present invention provides an embodiment of a low temperature polysilicon (LTPS) product structure, comprising: a substrate; at least one N-type metal oxide semiconductor An (NMOS) is disposed on the substrate; at least one P-type metal oxide semiconductor (PMOS) is disposed on the substrate; a first metal layer is disposed on a gate insulating layer of the NMOS and the PMOS The first metal layer is used to form a gate and at least one first trace; a plurality of pads are respectively formed at end points of each of the first traces; and a second metal layer is used to form the NMOS and a drain and a source of the PMOS and at least a second trace; an interlayer insulating layer on the first metal layer and the gate insulating layer; a flat layer in the NMOS and the PMOS a first transparent conductive layer above the flat layer and covering at least a portion of the flat layer; a protective layer above the flat layer and the first transparent conductive layer; a second transparent conductive layer located at the Above the protective layer, the
  • the N-type metal oxide semiconductor includes: a shielding layer on the substrate to cover a portion of the substrate; a barrier layer on the shielding layer and the substrate; a silicon dioxide layer on the barrier layer; an N channel
  • the layer is located on the silicon dioxide layer, the N-channel layer has a polysilicon layer and two N+-type layers, and the inner sides of the two N+-type layers are respectively bonded to the two outer sides of the N-channel layer, and the two N-type layers are respectively The ends are respectively bonded to the outer end of the polysilicon layer and the inner end of the two N+ type layers;
  • the gate insulating layer is located on the N channel layer and the silicon dioxide layer
  • the first metal layer is insulated from the N-channel layer via the gate insulating layer; an interlayer insulating layer is located at an uppermost layer of the N-type metal oxide semiconductor (NMOS); and a drain and a source And forming the second metal layer, each of the N+ type layers being connected via a via hole, the through hole penet
  • the P-type metal oxide semiconductor includes: a barrier layer on the substrate; a silicon dioxide layer on the barrier layer; a P channel layer silicon dioxide layer, the P channel layer has a polysilicon layer a two P+ type layer, the inner sides of the two P+ type layers are respectively bonded to both outer sides of the N channel layer; the gate insulating layer is located on the N channel layer and the silicon dioxide layer; a first metal layer separated from the P channel layer by an insulating layer; an interlayer insulating layer located at an uppermost layer of the P-type metal oxide semiconductor (PMOS); and a drain and a source
  • the second metal layer is formed to be connected to the P+ type layer of the P-type metal oxide semiconductor via a via hole, and the via hole is disposed through the interlayer insulating layer and the gate insulating layer.
  • the pad is electrically connected to one of the circuit unit test pins, an integrated circuit, and a flexible circuit board, and the trench is exposed to the pad.
  • a preferred embodiment of the present invention provides another embodiment of the present invention, which is a low temperature polysilicon (LTPS) product structure including a substrate; at least one N-type metal oxide semiconductor An (NMOS) is disposed on the substrate; at least one P-type metal oxide semiconductor (PMOS) is disposed on the substrate; a first metal layer is disposed on a gate insulating layer of the NMOS and the PMOS a first metal layer for forming a gate and for forming at least one first trace; a second metal layer for forming a drain and a source of the NMOS and the PMOS, and at least a second a wiring layer; an interlayer insulating layer on the first metal layer and the gate insulating layer; a flat layer above the NMOS and the PMOS; a first transparent conductive layer above the flat layer And covering at least a portion of the flat layer; a protective layer is located above the flat layer and the first transparent conductive layer; a second transparent conductive layer is located above the protective layer, and the second transparent conductive layer
  • the N-type metal oxide semiconductor comprising: a shielding layer on the substrate to cover a portion of the substrate; a barrier layer is disposed on the shielding layer and the substrate; a silicon dioxide layer is disposed on the barrier layer; an N channel layer is disposed on the silicon dioxide layer, and the N channel layer has a polysilicon layer and two N+ layers.
  • the inner sides of the two N+ type layers are respectively bonded to both outer sides of the N channel layer, and both ends of the two N-type layers are respectively bonded to the outer end of the polysilicon layer and the inner ends of the two N+ type layers; the gate insulation a layer on the N channel layer and the silicon dioxide layer
  • the first metal layer is insulated from the N-channel layer via the gate insulating layer; an interlayer insulating layer is located at an uppermost layer of the N-type metal oxide semiconductor (NMOS); and a drain and a source And forming the second metal layer, each of the N+ type layers being connected via a via hole, the through hole penetrating the interlayer insulating layer and the gate insulating layer.
  • the P-type metal oxide semiconductor wherein: a barrier layer is disposed on the substrate; a silicon dioxide layer is disposed on the barrier layer; and a P channel layer is disposed on the silicon dioxide layer, the P channel layer has a polysilicon layer and two P+ layers, and the two P+ layers
  • the inner sides of the type layer are each bonded to both outer sides of the N channel layer; the gate insulating layer is located on the N channel layer and the silicon dioxide layer; the first metal layer is via the gate An insulating layer and the P channel layer are separated from the insulation; an interlayer insulating layer is located at an uppermost layer of the P-type metal oxide semiconductor (PMOS); and a drain and a source are formed by the second metal layer, each via The via hole connects the P+ type layer of the P-type metal oxide semiconductor, and the via hole is penetrated through the interlayer insulating layer and the gate insulating layer.
  • PMOS P-type metal oxide semiconductor
  • the end of the trace includes a first pad electrically connected to a circuit unit test pin, the trench being exposed to the first pad.
  • the end of the trace includes a first pad electrically connected to an integrated circuit chip, the trench being exposed to the first pad.
  • the end point of the trace includes a first pad electrically connected to a flexible circuit board, the trench being exposed to the first pad.
  • a method for manufacturing a low temperature polysilicon product comprising: providing a substrate; forming an NMOS and a PMOS on the substrate; forming a first metal layer on the NMOS and the a gate insulating layer of the PMOS, patterned to form the gate of the NMOS and the PMOS, and at least a first trace; forming a second metal layer and patterning to form the NMOS and the a drain and a source of the PMOS and at least a second trace; forming an interlayer insulating layer on the first metal layer and the gate insulating layer; forming a flat layer on the NMOS and the PMOS, the planar layer Covering the NMOS and the drain and source of the PMOS and the second trace; forming a first transparent conductive layer on the planar layer to cover at least a portion of the planar layer; forming a protective layer on the first transparent And forming a second transparent conductive layer on the protective layer; forming a hole to form
  • An end of the first trace includes a first pad, and the first trace is electrically connected to a circuit unit test pin, and the first trench is formed above the first pad .
  • An end of the first trace includes a first pad, and the first trace is electrically connected to an integrated circuit chip, and the trench is formed above the first pad.
  • An end of the first trace includes a first pad, and the first trace is electrically connected to a flexible circuit board, and the trench is formed above the first pad.
  • the trench of the present invention does not need to pass through the distribution region of the second metal (for example, the drain and source of the NMOS and the PMOS and the at least one second trace), and the first trace in the trench is formed only by the first metal And then bonding the integrated circuit or the flexible circuit board, the interlayer insulating layer of the present invention is located on the first metal layer and the gate insulating layer, so the first trace (the first a metal layer is formed by indium tin oxide (ITO) via an interlayer insulating layer and a residual transparent conductive layer Forming isolation and separation, specifically solving the prior art, when digging the second trench of the flat layer, the second metal layer is short-circuited by the indium tin oxide (ITO) of the remaining transparent conductive layer, causing the entire panel to be Shows the disadvantages of exceptions.
  • ITO indium tin oxide
  • FIG. 1 is a schematic diagram of a low temperature polysilicon (LTPS) structure.
  • FIG. 2 is a schematic view of a burrowing area of a Planarization (PLN) in a prior art LTPS structure.
  • PPN Planarization
  • FIG. 3 is a schematic illustration of trenching of a LTPS product structure and forming a first trace from a first metal layer in accordance with an embodiment of the present invention.
  • FIG. 4 is a schematic view showing the second metal layer of FIG. 3 distributed on the first metal layer structure.
  • FIG. 1 is a structural cross-sectional view of a low temperature polysilicon film (LTPS) (which does not cover the trench 50 of the present invention) having a substrate 11 and an N-type metal oxide semiconductor (NMOS).
  • LTPS low temperature polysilicon film
  • NMOS N-type metal oxide semiconductor
  • PMOS P-type metal oxide semiconductor
  • ITO indium tin oxide
  • the substrate 11 may be glass, and the shielding layer 12 is on the substrate 11, usually composed of an amorphous silicon layer or molybdenum (A-Si/Mo).
  • the spacer layer is on the glass substrate 11 and covers the masking layer 12, which is typically composed of a barrier layer 13 of a silicon nitride layer (SiNx) and a silicon dioxide layer 14.
  • the P channel layer 16 of 42 is located on the silicon dioxide layer 14.
  • the two outer ends of the N-channel layer 15 respectively have an N+-type layer 151 and an N-type layer 152, the N+-type layer 151 is located at the outermost end of the N-channel layer 15, and the N-type layer 152 is adjacent to the N+-type layer 151, the N-channel Inside the layer 15, is the polysilicon layer 153 of the N-channel layer 15. (Poly).
  • the two outer ends of the P channel layer 16 have a P+ type layer 161, and the inside of the P channel layer 16 is a polysilicon layer 162 (Poly) of the P channel layer 16.
  • the first metal layer 19 is formed as an NMOS 41 and Gate Electrode (GE) of the PMOS 42 are located on the gate insulating layer 17, and are insulated from the N channel layer 15 or the P channel layer 16, respectively.
  • Interlayer insulating layer 18 An inter-level dielectric (ILD) is located on the first metal layer 19 and the gate insulating layer 17.
  • Flat layer 21 (Planarization, PLN) is located on the interlayer insulating layer 18.
  • the second metal layer 20 is connected to the N+ type layer 151 and the P+ type layer 161 through the via holes penetrating the interlayer insulating layer 18 and the gate insulating layer 17, respectively.
  • the second metal layer 20 is formed as a source/drain electrode layer of an N-type metal oxide semiconductor 41 (NMOS) and a P-type metal oxide semiconductor 42 (PMOS) (Source/Drain, SD).
  • the second transparent conductive layer 24 is on the flat layer 21.
  • a protective layer 23 (PV) is located on the second transparent conductive layer 24.
  • the first transparent conductive layer 22 is located on the protective layer 23 (Protective Layer, PV).
  • the first transparent conductive layer 22 and the second transparent conductive layer 24 are typically made of indium tin oxide (ITO).
  • ITO indium tin oxide
  • the flat layer 21 is located on the upper layer of the second metal layer 20, and after the flat layer 21 is dug to form the second trench 40, the prior art digs a hole.
  • the exposed range generally covers the second trace 35 formed by the second metal layer 20, the second pad 34, and other portions of the second metal layer 20 (eg, the NMOS The junction of 41 and the drain and source of the PMOS 42).
  • a low temperature polysilicon product structure capable of improving yield is provided, and as shown in FIG. 3, a trench 50 is formed.
  • Low temperature polysilicon in Figure 1 above The layer through which the trench 50 formed by the vertical burrowing of the (LTPS) structure passes is a layer formed on the silicon dioxide layer 14 and the first metal layer 19.
  • the first metal layer 19 constitutes a first trace 55 in addition to forming a gate.
  • the trench 50 only passes through the flat layer 21 and the interlayer insulating layer 18, and the trench 50 only passes through the first transparent conductive layer 22, the protective layer 23, and the first At least one of the two transparent conductive layers 24 exposes an end of the first trace 55, which is generally formed to form a first pad 54 that facilitates the connection.
  • the trench 50 for vertical burrowing does not need to pass through the distribution region of the second metal 20 (for example, NMOS 41 and the drain and source of the PMOS 42 and at least a second trace 35).
  • the trenches 50 are respectively located at the end of the first trace 55, the first pad 54, the first pad 54 connected to the circuit unit test pin, the first pad 54 connected to the integrated circuit 33, and The first pad 54 is connected to the first pad 54 connected to the flexible circuit board 32.
  • each of the trenches 50 does not need to pass through the distribution area of the second metal layer 20.
  • the low temperature polysilicon (LTPS) product structure of the present invention is to dig a plurality of trenches 50 as shown in FIG. 3 on the low temperature polysilicon (LTPS) structure shown in FIG. 1, so that the overall structure includes: the substrate 11 ;N-type metal oxide semiconductor 41 (NMOS) is located on the substrate 11 (the substrate 11 may be glass), and a P-type metal oxide semiconductor 42 (PMOS) is located on the substrate 11; a first metal layer 19 is located at the NMOS 41 and a gate insulating layer 17 of the PMOS 42, the first metal layer 19 is used to form the gate of the NMOS 41 and PMOS 42, and for forming at least a first trace 55;
  • NMOS N-type metal oxide semiconductor 41
  • PMOS P-type metal oxide semiconductor 42
  • the drain and source of 42 are connected; an interlayer insulating layer 18 is located on the first metal layer 19 and the gate insulating layer 17, so that the first trace 55 (formed by the first metal layer 19) passes through the layer Insulating layer 18 and residual transparent conductive layer of indium tin oxide (ITO)
  • ITO indium tin oxide
  • a flat layer 21 is located at the NMOS 41 and the PMOS Above the 42; the first transparent conductive layer 22 is located above the flat layer 21 and covers at least a portion of the flat layer 21; the protective layer 23 is located above the flat layer 21 and the first transparent conductive layer 22; The layer 24 is located above the protective layer 23, and the second transparent conductive layer 24 passes through the through hole of the protective layer 23 and the flat layer 21 and the NMOS.
  • the drain and source of 41 are connected.
  • At least one trench 50 passes through the planarization layer 21 and the interlayer insulating layer 18, and the trench 50 passes through the first transparent conductive layer 22, the protective layer 23, and the second transparent At least one of the conductive layers 24 is exposed to an end of the first trace 55.
  • the NMOS 41 and the PMOS 42 have a drain and a source formed in the second metal layer 20, and an NMOS
  • the drain and source of 41 are connected to the second transparent conductive layer 24, which is an NMOS 41 and a PMOS.
  • 42 is the basic component of the panel display drive, and the second trace 35 is also formed by the second metal layer 20, and some of the second traces 35 may be connected to the drain and the source at one end, and may include other traces.
  • the patterned second metal layer 20 is located between the planar layer 21 and the interlayer insulating layer 18, the second metal layer 20 is coupled to the second transparent conductive layer 24, and the second metal layer 20 is Form NMOS 41 and PMOS 42 source/drain electrode layers (Source/Drain, SD) and the second trace 35, these components may be adjacent to each other.
  • the first pad 54 at a specific end point of the patterned first trace 55 (formed by the first metal layer 19) in each trench 50 can reduce the prior art.
  • Adjacent NMOS 41 interferes with each other between the PMOS 42 source/drain electrode layer (Source/Drain, SD) and the second trace 35.
  • the N-type metal oxide semiconductor (NMOS) 41 is a structure in which the shielding layer 12, the silicon dioxide layer 14, the N channel layer 15, the gate insulating layer 17, the first metal layer 19, and the interlayer insulating layer 18 are layer by layer from the lower layer to the upper layer.
  • the N-channel layer 15 has a polysilicon layer 153 and two N+-type layers 151.
  • the inner sides of the two N+-type layers 151 are respectively bonded to the outer sides of the N-channel layer 15, and the two ends of the two N-type layers 152 are respectively bonded.
  • the drain and the source are formed by the second metal layer 20, and the N+ type layer 151 is respectively connected via a via hole, and the through hole is penetrated through the interlayer insulating layer 18 and the gate insulating layer 17.
  • the P-type metal oxide semiconductor (PMOS) 42 The structure is formed by the barrier layer 13, the silicon dioxide layer 14, the P channel layer 16, the gate insulating layer 17, the first metal layer 19, and the interlayer insulating layer 18, and is layer by layer from the lower layer to the upper layer.
  • the P-channel layer 16 has a polysilicon layer 162 and two P+-type layers 161, and the inner sides of the two P+-type layers 161 are respectively bonded to both outer sides of the N-channel layer 15.
  • the drain and the source are formed by the second metal layer 20, and the P+ type layer 161 of the P-type metal oxide semiconductor 42 is connected via a via hole, and the via hole is penetrated through the interlayer insulating layer.
  • FIG. 3 is a schematic diagram of forming a first trace from the first metal in the trench.
  • the specific trenches 50 of this embodiment are respectively limited to a specific distribution area where the patterned first metal layer 19 extends.
  • the present invention is because the trench 50 only passes through the flat layer 21 and the interlayer insulating layer 18, and the trench 50 only passes through the first transparent conductive layer 22, the protective layer 23, and At least one of the second transparent conductive layers 24 is exposed to an end of the first trace 55.
  • the trench 50 does not need to pass through the distribution region of the second metal layer 20 (for example, NMOS 41 and the drain and source of the PMOS 42 and at least a second trace 35).
  • FIG. 4 is a schematic view showing the structure of the second metal layer 20 of FIG. 3 distributed on the first metal layer 19 .
  • the end of the first trace 55 formed by the first metal layer 19 of the present invention comprises a first pad 54.
  • the trench 50 does not need to pass through the distribution region of the second metal layer 20, and the interlayer insulating layer 18 is located in the The first metal layer 19 and the gate insulating layer 17, so that only the trench 50 of the first pad 54 of the first trace 55 is exposed in the embodiment of the present invention, and the trench is exposed to the second metal without the prior art.
  • the short circuit generated by layer 20 and the shortcomings of interference are examples of the first metal layer 19 and the shortcomings of interference.
  • the present invention provides a method of manufacturing a low temperature polysilicon product. Referring to Figures 1 and 3, the method includes the following steps.
  • a substrate 11 is provided, which may be a glass substrate 11.
  • N-type metal oxide semiconductor (NMOS) 41 and a P-type metal oxide semiconductor (PMOS) 42 is on the substrate 11.
  • the N-type metal oxide semiconductor (NMOS) 41 As shown in FIG. 1, the shielding layer 12, the silicon dioxide layer 14, the N channel layer 15, the gate insulating layer 17, the first metal layer 19, the interlayer insulating layer 18, and the layer by layer from the lower layer to the upper layer are covered. Structure.
  • the N-channel layer 15 has a polysilicon layer 153 and two N+-type layers 151. The inner sides of the two N+-type layers 151 are respectively bonded to the outer sides of the N-channel layer 15, and the two ends of the two N-type layers 152 are respectively bonded.
  • the drain and the source are formed by the second metal layer 20, and as described later, the N+ type layer 151 is connected via via holes, and the via hole is penetrated through the interlayer insulating layer 18 and the gate. Insulation layer 17.
  • the P-type metal oxide semiconductor (PMOS) 42 As shown in FIG. 1, the barrier layer 13, the silicon dioxide layer 14, the P channel layer 16, the gate insulating layer 17, the first metal layer 19, and the interlayer insulating layer 18 are layer by layer from the lower layer to the upper layer. structure.
  • the P-channel layer 16 has a polysilicon layer 162 and two P+-type layers 161, and the inner sides of the two P+-type layers 161 are respectively bonded to both outer sides of the N-channel layer 15.
  • the drain and the source are formed by the second metal layer 20, and as described later, the P+ type layer 161 of the P-type metal oxide semiconductor 42 is connected via a via hole, and the through hole is bored in the The interlayer insulating layer 18 and the gate insulating layer 17 are described.
  • a gate insulating layer 17 of 42 is patterned and patterned to form the gates of the NMOS 41 and the PMOS 42 and at least a first trace 55.
  • a first transparent conductive layer 22 is formed on the planar layer 21 to cover at least a portion of the planar layer 21.
  • a protective layer 23 is formed on the first transparent conductive layer 22 and the flat layer 21.
  • a second transparent conductive layer 24 is formed on the protective layer 23.
  • the NMOS 41 and the PMOS 42 have a drain and a source formed in the second metal layer 20, and an NMOS
  • the drain and source of 41 are connected to the second transparent conductive layer 24, which is an NMOS 41 and a PMOS.
  • 42 is a basic component of the panel display driving, and the second trace 35 is also formed by the second metal layer 20, and some of the second traces 35 may be connected to the drain and the source at one end.
  • the second metal layer 20 is located between the flat layer 21 and the interlayer insulating layer 18, the second metal layer 20 is coupled to the second transparent conductive layer 24, and the second metal layer 20 constitutes an NMOS.
  • 41 and PMOS 42 source/drain electrode layers (Source/Drain, SD) and second trace 35, these components may be adjacent to each other.
  • the hole is formed into at least one trench 50, the trench 50 passes through the flat layer 21 and the interlayer insulating layer 18, and the trench 50 passes through the first transparent conductive layer 22, At least one of the protective layer 23 and the second transparent conductive layer 24 is exposed to an end of the first trace 55.
  • a first pad 54 may be formed at an end of the first trace 55, and the first trace 55 may be electrically connected to a circuit unit test pin or electrically connected to an integrated circuit 33 chip, or A flexible circuit board 32 is electrically connected.
  • the trench 50 is formed above the first pad 54.
  • Embodiments of the structure and method of the present invention provide a process flow benefit of a low temperature polysilicon film (LTPS), since the interlayer insulating layer 18 is located on the first metal layer 19 and the gate insulating layer 17, so the first step Line 55 (formed by the first metal layer 19) via the interlayer insulating layer 18 and the remaining transparent conductive layer of indium tin oxide (ITO) Forming the isolation separation, the trench substantially exposes only the end of the first trace 55 formed by the first metal layer 19, specifically solving the prior art flat layer 21 trenching, reducing the transparent conductive layer (ITO) in the second metal layer 20 The residue of the distribution area causes the second trace 35, the second pad 34, and the junction with the other portions of the second metal layer 20 to be short-circuited, improving the quality of the panel display.
  • LTPS low temperature polysilicon film
  • ITO indium tin oxide
  • the reticle 50 reticle design provided by the present invention exposes only a specific end point only in the peripheral non-display area, wherein the grooving 50 does not need to pass through the distribution area of the second metal 20 (for example, NMOS 41 and PMOS The drain and source of 42 and at least a second trace 35). Therefore, only the first pad 54 of the first trace 55 and a portion of the first trace 55 are exposed, and the second metal layer 20 need not be exposed, thereby avoiding the prior art structure because the trench 40 makes the distribution of the second metal genus 20. Defects caused by exposure at the area.
  • the second metal 20 for example, NMOS 41 and PMOS
  • the adjacent signal lines are not short-circuited due to the residual of the transparent conductive layer (ITO), thereby reducing the display abnormality of the entire panel.
  • ITO transparent conductive layer
  • Embodiments of the present invention can be applied to liquid crystal displays (LCDs) of low temperature polysilicon, and are suitable for wide viewing angle technology (Advanced) Fringe Field Switching, AFFS), can also be applied to organic light-emitting diodes (Organic Light-Emitting) Diode, OLED).
  • LCDs liquid crystal displays
  • AFFS Advanced Fringe Field Switching
  • OLED organic Light-Emitting diodes

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Abstract

一种低温多晶硅（LTPS）产品结构及制造方法，结构包括：基材（11），位于基材（11）上的NMOS（41）和PMOS（42）；第一金属层（19），位于NMOS（41）和PMOS（42）的栅极绝缘层（17）上，第一金属层（19）用于形成栅极以及用于形成至少一第一走线（55）；第二金属层（20），用于形成NMOS（41）和PMOS（42）的漏极和源极以及至少一第二走线（35）；层间绝缘层（18），位于第一金属层（19）以及栅极绝缘层（17）上；至少一挖槽（50），用以曝露第一走线（55）的一端点，避免走线间的干扰，以提升产品的品质。

Description

低温多晶硅(LTPS)产品结构及制造方法 技术领域
本发明涉及液晶生产技术领域，特别涉及一种可提升良率的低温多晶硅产品结构及其制造方法。
 背景技术
采用低温多晶硅薄膜晶体管(LTPS TFT)的液晶显示屏幕(LCD)具有高分辨率、反应速度快、高亮度、高开口率等优点，加上由于LTPS-TFT LCD的硅结晶排列较非晶硅(Amorphous silicon， A-Si)有次序，使得电子移动率相对高100倍以上，可以将外围驱动电路同时制作在玻璃基板上，达到系统整合的目标、节省空间及驱动IC的成本。但是LTPS的工艺流程相对于非晶硅(Amorphous silicon，A-Si)来说变得非常的复杂，对于工艺的要求也变得非常的苛刻。因此对于低温多晶硅(LTPS)工艺设计的优化也显得尤为重要。
请参照图2，为先前技术LTPS结构中平坦层(Planarization ,PLN)挖洞区域示意图。在低温多晶硅(LTPS)工艺中，通常是在平坦层(Planarization, PLN)挖洞形成一个大第二挖槽40将全部的垫(Pad) 34或全部的集成电路(IC)33的管脚或具有多个连接点的整个软性电路板32暴露出。所述垫34(Pad)是形成于结构中第二走线35末梢的端点。
由于平坦层(Planarization, PLN)较厚，在进行透明导电层的氧化铟锡(ITO)曝光时,由于该处光阻较厚，曝光不完全，光阻会有残留，导致第二走线35或管脚之间短路(short)，干扰所传输的讯号，影响面板显示。
请参考图2，结构中，由第二金属层20形成多条第二走线35，各走线的端点包含一垫34。有些垫34可连接电路单元(Cell Test)测试单元的管脚，此外垫34可与集成电路33(IC)的管脚或者软性电路板 (Flexible Print Circuit, FPC) 32的多数个接点相接。集成电路33(IC)管脚，可以经由第二金属层20或直接与软性电路板32(Flexible Print Circuit, FPC)的接点相接合，例如集成电路33(IC)管脚的垫34可经由第二走线35与软性电路板32(Flexible Print Circuit, FPC)相接合。
 技术问题
先前技术中，通常是将集成电路33(IC)管脚以及软性电路板32(Flexible Print Circuit, FPC)的接点整个区域对应的平坦层21(Planarization, PLN)挖成一个大挖槽40，或是将对应多数个垫34的整个区域挖成一个大挖槽40。由于在平坦层21(Planarization, PLN)形成挖槽40时，在尖锥(Taper)角部分有过多光阻的残留，使得曝光部分不彻底，形成透明导电层时，造成氧化铟锡(ITO)在沟槽部分的残留。残留的透明导电层的氧化铟锡(ITO)会把相邻的走线(例如信号线和数据线)短路在一起，造成整个面板的显示异常。
技术解决方案
为解决上述问题，根据本发明，连接电路单元测试管脚的垫、连接集成电路的管脚和垫、以及连接软性电路板管脚的垫是与第一金属层的第一走线相结合，并形成挖槽以曝露所述第一走线的一端点处的垫，所述挖槽仅穿过所述平坦层和所述层间绝缘层，以及所述挖槽仅穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层。所述挖槽不需穿过第二金属的分布区(例如NMOS与PMOS的漏极和源极以及至少一第二走线)，然后再进行集成电路或软性电路板的黏合(Bonding)，从而避免了先前技术使用第二金属的短路与干扰的问题。
本发明提供了一实施例，为一种低温多晶硅(LTPS)产品结构，其中，包括:一基材；至少一N型金属氧化半导体 (NMOS)位于所述基材上；至少一P型金属氧化半导体(PMOS)位于所述基材上；一第一金属层，位于所述NMOS与所述PMOS的一栅极绝缘层上，所述第一金属层用于形成一栅极以及至少一第一走线；多个垫，分别形成于各所述第一走线的端点处；一第二金属层，用于形成所述NMOS与所述PMOS的漏极和源极以及至少一第二走线；一层间绝缘层，位于所述第一金属层以及所述栅极绝缘层上；一平坦层位于所述NMOS以及所述PMOS上方；一第一透明导电层位于所述平坦层上方并覆盖所述平坦层至少一部分；一保护层位于所述平坦层和所述第一透明导电层上方；一第二透明导电层位于所述保护层上方，所述第二透明导电层经由穿过所述保护层以及所述平坦层的通孔与所述NMOS的漏极和源极相连结；至少一挖槽，所述挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的端点处的垫。
所述N型金属氧化半导体包括:一遮蔽层位于所述基材上以覆盖部分基材；一阻隔层位于所述遮蔽层以及基材上；一二氧化硅层位于阻隔层上；一N通道层位于二氧化硅层上，所述N通道层具一多晶硅层、两N+型层，所述两N+型层的内侧各自接合于所述N通道层的两外侧，两N-型层的两端各自接合于所述多晶硅层外侧端以及两N+型层的内侧端；所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上 ；所述第一金属层，经由所述栅极绝缘层与所述N通道层绝缘分隔；一层间绝缘层，位于所述N型金属氧化半导体(NMOS)最上层；以及漏极和源极，由所述第二金属层形成，各自经由通孔连结所述N+型层,所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
所述P型金属氧化半导体，包括:一阻隔层位于所述基材上；一二氧化硅层位于阻隔层上；一P通道层位二氧化硅层上，所述P通道层具一多晶硅层、两P+型层，所述两P+型层的内侧各自接合于所述N通道层的两外侧；所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上；所述第一金属层，经由所述栅极绝缘层与所述P通道层与绝缘分隔；一层间绝缘层，位于所述P型金属氧化半导体(PMOS)最上层；以及漏极和源极，由所述第二金属层形成，各自经由通孔连结所述P型金属氧化半导体的所述P+型层，所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
所述垫是与一电路单元测试管脚、一集成电路、一软性电路板其中之一电性相连，所述挖槽是曝露出所述垫。
本发明的一优选实施例提供了本发明另一实施例，为一种低温多晶硅(LTPS)产品结构，其中，包括一基材；至少一N型金属氧化半导体 (NMOS)位于所述基材上；至少一P型金属氧化半导体(PMOS)位于所述基材上；一第一金属层，位于所述NMOS与所述PMOS的一栅极绝缘层上，所述第一金属层用于形成一栅极、以及用于形成至少一第一走线；一第二金属层，用于形成所述NMOS与所述PMOS的漏极和源极以及至少一第二走线；一层间绝缘层，位于所述第一金属层以及所述栅极绝缘层上；一平坦层位于所述NMOS以及所述PMOS上方；一第一透明导电层位于所述平坦层上方并覆盖所述平坦层至少一部分；一保护层位于所述平坦层和所述第一透明导电层上方；一第二透明导电层位于所述保护层上方，所述第二透明导电层经由穿过所述保护层以及所述平坦层的通孔与所述NMOS的漏极和源极相连结；至少一挖槽，所述挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的一端点。
所述N型金属氧化半导体，其中，包括:一遮蔽层位于所述基材上以覆盖部分基材； 一阻隔层位于所述遮蔽层以及基材上；一二氧化硅层位于阻隔层上；一N通道层位于二氧化硅层上，所述N通道层具一多晶硅层、两N+型层，所述两N+型层的内侧各自接合于所述N通道层的两外侧，两N-型层的两端各自接合于所述多晶硅层外侧端以及两N+型层的内侧端；所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上 ；所述第一金属层，经由所述栅极绝缘层与所述N通道层绝缘分隔；一层间绝缘层，位于所述N型金属氧化半导体(NMOS)最上层；以及漏极和源极，由所述第二金属层形成，各自经由通孔连结所述N+型层,所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
所述P型金属氧化半导体，其中，包括: 一阻隔层位于所述基材上；一二氧化硅层位于阻隔层上；一P通道层位二氧化硅层上，所述P通道层具一多晶硅层、两P+型层，所述两P+型层的内侧各自接合于所述N通道层的两外侧；所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上；所述第一金属层，经由所述栅极绝缘层与所述P通道层与绝缘分隔；一层间绝缘层，位于所述P型金属氧化半导体(PMOS)最上层；以及漏极和源极，由所述第二金属层形成，各自经由通孔连结所述P型金属氧化半导体的所述P+型层，所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
所述走线的所述端点，其中，包括一第一垫，所述第一垫是与一电路单元测试管脚电性相连，所述挖槽是曝露出所述第一垫。
所述走线的所述端点，其中，包括一第一垫，所述第一垫是与一集成电路芯片电性相连，所述挖槽是曝露出所述第一垫。
所述走线的所述端点，其中，包括一第一垫，所述第一垫是与一软性电路板电性相连，所述挖槽是曝露出所述第一垫。
本发明再一实施例，为一种低温多晶硅产品的制造方法，，其中，包括:提供一基材；形成NMOS与PMOS于所述基材上；形成第一金属层于所述NMOS与所述PMOS的一栅极绝缘层上，并加以图案化以构成所述NMOS与所述PMOS的栅极以及至少一第一走线；形成第二金属层并加以图案化以构成所述NMOS与所述PMOS的漏极与源极以及至少一第二走线；形一层间绝缘层于所述第一金属层以及所述栅极绝缘层上；形成平坦层于NMOS与PMOS上，所述平坦层覆盖所述NMOS与所述PMOS的漏极和源极以及所述第二走线；形成第一透明导电层于所述平坦层上以覆盖至少一部分所述平坦层；形成保护层于第一透明导电层与所述平坦层上；形成第二透明导电层于所述保护层上；挖洞形成至少一挖槽，所述第一挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的一端点。
所述第一走线的端点，其中，包含一第一垫，且所述第一走线与一电路单元测试管脚电性相连，所述第一挖槽形成于所述第一垫的上方。
所述第一走线的端点，其中，包含一第一垫，且所述第一走线与一集成电路芯片电性相连，所述挖槽形成于所第一述垫的上方。
所述第一走线的端点，其中，包含一第一垫，且所述第一走线与一软性电路板电性相连，所述挖槽形成于所述第一垫的上方。
有益效果
本发明所述挖槽不需穿过第二金属的分布区(例如NMOS与PMOS的漏极和源极以及至少一第二走线)，而且挖槽内第一走线仅由第一金属形成，然后再进行集成电路或软性电路板的黏合(Bonding)，本发明所述一层间绝缘层，位于所述第一金属层以及所述栅极绝缘层上，因此第一走线(第一金属层形成)经由层间绝缘层和残留的透明导电层的氧化铟锡(ITO) 形成隔绝分离，具体解决先前技术，挖平坦层第二挖槽时，第二金属层因残留的透明导电层的氧化铟锡(ITO)会把相邻的走线短路在一起，造成整个面板的显示异常的缺点。
 附图说明
图1为低温多晶硅(LTPS)结构示意图。
图2为先前技术LTPS结构中平坦层(Planarization ,PLN)挖洞区域示意图。
图3为根据本发明之实施例之LTPS产品结构的挖槽以及由第一金属层形成第一走线的示意图。
图4 为图3的第二金属层分布于第一金属层结构上示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
请参考图1所示，为低温多晶硅薄膜(LTPS)的结构剖面示意图(并不涵盖本发明的挖槽50)，所述结构具有基材11，N型金属氧化半导体 (NMOS) 41、P型金属氧化半导体(PMOS) 42形成于基材11上，以及氧化铟锡(ITO)的透明导电层22、24。所述基材11可以是玻璃，遮蔽层12位于基材11上，通常由非晶硅层或钼(A-Si/Mo)组成。间隔层位于玻璃基材11上并覆盖遮蔽层12，间隔层通常由氮化硅层(SiNx)的阻隔层13，以及二氧化硅层14组成。NMOS 41的N通道层15或PMOS 42的P通道层16位于二氧化硅层14上。N通道层15的两外侧端，分别具有N+型层151以及N-型层152，N+型层151位于N通道层15的最外侧端，N-型层152邻接于N+型层151，N通道层15的内部，是N通道层15的多晶硅层153 (Poly)。P通道层16的两外侧端，具有P+型层161，P通道层16的内部，是P通道层16的多晶硅层162 (Poly)。第一金属层19形成为NMOS 41与PMOS 42的栅极(Gate Electrode，GE)，位于栅极绝缘层17上，分别与N通道层15或P通道层16绝缘。层间绝缘层18 (inter-level dielectric，ILD)位于第一金属层19以及栅极绝缘层17上。平坦层21(Planarization, PLN)位于层间绝缘层18上。第二金属层20通过穿越层间绝缘层18，以及栅极绝缘层17的通孔分别与N+型层151以及P+型层161连接。第二金属层20形成为N型金属氧化半导体41(NMOS)以及P型金属氧化半导体42(PMOS)的源极/漏极电极层(Source/Drain, SD)。第二透明导电层24位于平坦层21上。保护层23( Protective Layer, PV) 位于第二透明导电层24上。第一透明导电层22，位于保护层 23( Protective Layer, PV)上。第一透明导电层22以及第二透明导电层24通常是以氧化铟锡(ITO)制成。第一透明导电层22穿过保护层 23以及平坦层21与第二金属层20连结。
上述结构下，如上所述，先前技术中，如图2所示，平坦层21位在第二金属层20的上层，平坦层21挖洞产生第二挖槽40后，先前技术挖一个洞的外露范围，通常涵盖第二金属层20形成的第二走线35、第二垫34、以及与第二金属层20其他部分(例如所述NMOS 41与所述PMOS 42的漏极和源极)的交界处。
根据本发明一实施例，提供一种可提升良率的低温多晶硅产品结构，如图3所示，形成挖槽50。将上述图1中的低温多晶硅 (LTPS)结构垂直挖洞形成的挖槽50所经过的层，为形成于二氧化硅层14以及第一金属层19之上的层。所述第一金属层19除了形成栅极之外并构成第一走线55。所述挖槽50仅穿过所述平坦层21和所述层间绝缘层18，以及所述挖槽50仅穿过所述第一透明导电层22、所述保护层23、以及所述第二透明导电层24中至少之一层以曝露所述第一走线55的一端点，所述端点处通常是形成有利于连接的第一垫54。垂直挖洞的所述挖槽50不需穿过第二金属20的分布区(例如NMOS 41与PMOS 42的漏极和源极以及至少一第二走线35)。
于本实施例中，所述挖槽50分别位于第一走线55端点的第一垫54、与电路单元测试管脚连接的第一垫54、与集成电路33连接的第一垫54、与软性电路板32连接的第一垫54上并曝露出所述第一垫54。于本实施例中，每个挖槽50都不需穿过第二金属层20的分布区。
如上所述，本发明一种低温多晶硅(LTPS)产品结构，是在图1所示的低温多晶硅(LTPS)结构上挖设如图3的多个挖槽50，所以整体结构包括:基材11；N型金属氧化半导体41 (NMOS)位于所述基材11上(基材11可以是玻璃)，以及P型金属氧化半导体42(PMOS)位于所述基材11上；第一金属层19，位于所述NMOS 41与所述PMOS 42的一栅极绝缘层17上，所述第一金属层19用于形成NMOS 41与PMOS 42的栅极、以及用于形成至少一第一走线55；
第二金属层20，用于形成所述NMOS 41与所述PMOS 42的漏极和源极以及至少一第二走线35，其中一些第二走线35可以与所述NMOS 41与所述PMOS 42的漏极和源极相连；一层间绝缘层18，位于所述第一金属层19以及所述栅极绝缘层17上，因此第一走线55(第一金属层19形成)经由层间绝缘层18和残留的透明导电层的氧化铟锡(ITO) 形成隔绝分离，具体解决先前技术平坦层21挖槽时，第二金属层20所产生的相邻短路的问题。
平坦层21位于所述NMOS 41以及所述PMOS 42上方；第一透明导电层22位于所述平坦层21上方并覆盖所述平坦层21至少一部分；保护层23位于所述平坦层21和所述第一透明导电层22上方；第二透明导电层24位于所述保护层23上方，所述第二透明导电层24经由穿过所述保护层23以及所述平坦层21的通孔与所述NMOS 41的漏极和源极相连结。
至少一挖槽50穿过所述平坦层21和所述层间绝缘层18，以及所述挖槽50穿过所述第一透明导电层22、所述保护层23、以及所述第二透明导电层24中至少之一层以曝露所述第一走线55的一端点。
NMOS 41以及PMOS 42的结构中具有漏极和源极是第二金属层20形成，NMOS 41的漏极和源极连结第二透明导电层24，是NMOS 41以及PMOS 42是面板显示驱动的基本组件，第二走线35也由第二金属层20形成，其中一些第二走线35可以一端连结漏极和源极，并可包含其他走线。请参考图1以及图3，图案化的第二金属层20位于平坦层21与层间绝缘层18之间，第二金属层20与第二透明导电层24相连结，第二金属层20是构成NMOS 41与PMOS 42源极/漏极电极层(Source/Drain, SD)以及第二走线35，这些部件可能彼此相邻。于本实施例中，如图3所示，各挖槽50内的图案化的第一走线55(第一金属层19形成)伸的特定端点处的第一垫54上，可以减少先前技术中相邻的NMOS 41与PMOS 42源极/漏极电极层(Source/Drain, SD)以及第二走线35之间彼此干扰。
所述N型金属氧化半导体(NMOS) 41，是由遮蔽层12、二氧化硅层14、N通道层15、栅极绝缘层17、第一金属层19、层间绝缘层18、逐层由下层往上层覆盖的结构。其中N通道层15具一多晶硅层153、两N+型层151，所述两N+型层151的内侧各自接合于所述N通道层15的两外侧，两N-型层152的两端各自接合于所述多晶硅层153外侧端以及两N+型层151的内侧端。而漏极和源极，由所述第二金属层20形成，各自经由通孔连结所述N+型层151,所述通孔穿设于所述层间绝缘层18以及所述栅极绝缘层17。
所述P型金属氧化半导体 (PMOS) 42 ，是由阻隔层13、二氧化硅层14、P通道层16、栅极绝缘层17、第一金属层19、层间绝缘层18、逐层由下层往上层覆盖的结构。其中P通道层16具一多晶硅层162、两P+型层161，所述两P+型层161的内侧各自接合于所述N通道层15的两外侧。而漏极和源极，由所述第二金属层20形成，各自经由通孔连结所述P型金属氧化半导体42的所述P+型层161，所述通孔穿设于所述层间绝缘层18以及所述栅极绝缘层17。
如上所述，请参考图3，为挖槽内由第一金属形成第一走线示意图。本实施例具体挖槽50分别局限在图案化的第一金属层19所延伸的特定分布区上。本发明由于所述挖槽50仅穿过所述平坦层21和所述层间绝缘层18，以及所述挖槽50仅穿过所述第一透明导电层22、所述保护层23、以及所述第二透明导电层24中至少之一层以曝露所述第一走线55的一端点。所述挖槽50不需穿过第二金属层20的分布区(例如NMOS 41与PMOS 42的漏极和源极以及至少一第二走线35)。
请参考图4，是第为图3的第二金属层20分布于第一金属层19结构上示意图。本发明结构由第一金属层19形成第一走线55的端点包含一第一垫54，挖槽50不需穿过第二金属层20的分布区，而且有层间绝缘层18位于所述第一金属层19以及所述栅极绝缘层17上，因此本发明之实施例中仅暴露第一走线55的第一垫54的挖槽50，没有习知技术之挖槽曝露第二金属层20所产生的短路以及干扰缺点。
本发明提供一种低温多晶硅产品的制造方法，请参阅图1以及图3，所述方法包括以下步骤。
提供一基材11，该基材11可以是玻璃基材11。
形成N型金属氧化半导体(NMOS) 41与P型金属氧化半导体(PMOS) 42于所述基材11上。所述N型金属氧化半导体 (NMOS) 41 ，如图1中所示，是由遮蔽层12、二氧化硅层14、N通道层15、栅极绝缘层17、第一金属层19、层间绝缘层18、逐层由下层往上层覆盖的结构。其中N通道层15具一多晶硅层153、两N+型层151，所述两N+型层151的内侧各自接合于所述N通道层15的两外侧，两N-型层152的两端各自接合于所述多晶硅层153外侧端以及两N+型层151的内侧端。而漏极和源极是由第二金属层20形成，如后述，各自经由通孔连结所述N+型层151,所述通孔穿设于所述层间绝缘层18以及所述栅极绝缘层17。所述P型金属氧化半导体(PMOS)42 ，如图1中所述，是阻隔层13、二氧化硅层14、P通道层16、栅极绝缘层17、第一金属层19、层间绝缘层18、逐层由下层往上层覆盖的结构。其中P通道层16具一多晶硅层162、两P+型层161，所述两P+型层161的内侧各自接合于所述N通道层15的两外侧。而漏极和源极是由所述第二金属层20形成，如后述，各自经由通孔连结所述P型金属氧化半导体42的所述P+型层161，所述通孔穿设于所述层间绝缘层18以及所述栅极绝缘层17。
形成第一金属层19于所述NMOS 41与所述PMOS 42的一栅极绝缘层17上，并加以图案化以构成所述NMOS 41与所述PMOS 42的栅极以及至少一第一走线55。
形成第二金属层20并加以图案化以构成所述NMOS 41与所述PMOS 42的漏极与源极以及至少一第二走线35，其中第二走线35可以连接所述NMOS 41与所述PMOS 42的漏极与源极；
形成平坦层21于NMOS 41与PMOS 42上，所述平坦层21覆盖所述NMOS 41与所述PMOS 42的漏极和源极以及所述第二走线35。
形成第一透明导电层22于所述平坦层21上以覆盖至少一部分所述平坦层21。
形成保护层23于第一透明导电层22与所述平坦层21上。
形成第二透明导电层24于所述保护层23上。
NMOS 41以及PMOS 42的结构中具有漏极和源极是第二金属层20形成，NMOS 41的漏极和源极连结第二透明导电层24，是NMOS 41以及PMOS 42是面板显示驱动的基本组件，第二走线35也由第二金属层20形成的，其中一些第二走线35可以一端连结漏极和源极，请参考图1以及图3，图案化的第二金属层20位于平坦层21与层间绝缘层18之间，第二金属层20与第二透明导电层24相连结，第二金属层20构成NMOS 41与PMOS 42源极/漏极电极层(Source/Drain, SD)以及第二走线35，这些部件可能彼此相邻。
然后，挖洞形成至少一挖槽50，所述挖槽50穿过所述平坦层21和所述层间绝缘层18，以及所述挖槽50穿过所述第一透明导电层22、所述保护层23、以及所述第二透明导电层24中至少之一层以曝露所述第一走线55的一端点。
所述第一走线55的端点处可形成第一垫54，且所述第一走线55可与一电路单元测试管脚电性相连，或与一集成电路33芯片电性相连，或与一软性电路板32电性相连。所述挖槽50形成于所述第一垫垫54的上方。
本发明结构和方法的实施例提供低温多晶硅薄膜(LTPS)的工艺流程有益效果，由于有层间绝缘层18位于所述第一金属层19以及所述栅极绝缘层17上，因此第一走线55(第一金属层19形成)经由层间绝缘层18和残留的透明导电层的氧化铟锡(ITO) 形成隔绝分离，挖槽基本上仅暴露第一金属层19形成的第一走线55之端点，具体解决先前技术平坦层21挖槽时，减少因为透明导电层(ITO)在第二金属层20分布区域的残留所造成第二走线35、第二垫34、以及与第二金属层20其他部分的交界处短路，提升面板显示的品质。
本发明提供的挖槽50光罩设计，仅在外围的非显示区域只对特定端点进行曝光，其中挖槽50不需穿过第二金属20的分布区(例如NMOS 41与PMOS 42的漏极和源极以及至少一第二走线35)。因此仅把第一走线55的第一垫54以及部分第一走线55裸露出来，不需要将第二金属层20裸露出来，避免先前技术结构因为挖槽40使第二金属属20的分布区域处外露造成的缺陷。因此根据本发明，在进行集成电路33或软性电路板32的黏合(Bonding)时，便不会由于透明导电层(ITO)的残留造成相邻信号线短路，从而减少整个面板的显示异常。
本发明的实施例可以应用在低温多晶硅的液晶显示器(LCD)、适用在广视角技术(Advanced Fringe Field Switching, AFFS)上，也可以应用在有机发光二极管（Organic Light-Emitting Diode，OLED）上。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种低温多晶硅(LTPS)产品结构，其中，包括：
    一基材；
    至少一N型金属氧化半导体 (NMOS)位于所述基材上；
    至少一P型金属氧化半导体(PMOS)位于所述基材上；
    一第一金属层，位于所述NMOS与所述PMOS的一栅极绝缘层上，所述第一金属层用于形成一栅极以及至少一第一走线；
    多個垫，分別形成於各所述第一走线的端点处；
    一第二金属层，用于形成所述NMOS与所述PMOS的漏极和源极以及至少一第二走线；
    一层间绝缘层，位于所述第一金属层以及所述栅极绝缘层上；
    一平坦层位于所述NMOS以及所述PMOS上方；
    一第一透明导电层位于所述平坦层上方并覆盖所述平坦层至少一部分；
    一保护层位于所述平坦层和所述第一透明导电层上方；
    一第二透明导电层位于所述保护层上方，所述第二透明导电层经由穿过所述保护层以及所述平坦层的通孔与所述NMOS的漏极和源极相连结；
    至少一挖槽，所述挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的端点處的垫。
  2. 根据权利要求1所述低温多晶硅产品结构，其中，所述N型金属氧化半导体包括:
    一遮蔽层位于所述基材上以覆盖部分基材；
    一阻隔层位于所述遮蔽层以及基材上；
    一二氧化硅层位于阻隔层上；
    一N通道层位于二氧化硅层上，所述N通道层具一多晶硅层、两N+型层，所述两N+型层的内侧各自接合于所述N通道层的两外侧，两N-型层的两端各自接合于所述多晶硅层外侧端以及两N+型层的内侧端；
    所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上 ；
    所述第一金属层，经由所述栅极绝缘层与所述N通道层绝缘分隔；
    一层间绝缘层，位于所述N型金属氧化半导体(NMOS)最上层；以及
    漏极和源极，由所述第二金属层形成，各自经由通孔连结所述N+型层,所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
  3. 根据权利要求1所述的低温多晶硅产品结构，其中，所述P型金属氧化半导体，包括:
    一阻隔层位于所述基材上；
    一二氧化硅层位于阻隔层上；
    一P通道层位二氧化硅层上，所述P通道层具一多晶硅层、两P+型层，所述两P+型层的内侧各自接合于所述N通道层的两外侧；
    所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上；
    所述第一金属层，经由所述栅极绝缘层与所述P通道层与绝缘分隔；
    一层间绝缘层，位于所述P型金属氧化半导体(PMOS)最上层；以及
    漏极和源极，由所述第二金属层形成，各自经由通孔连结所述P型金属氧化半导体的所述P+型层，所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
  4. 据权利要求1所述的低温多晶硅产品结构，其中，所述垫是与一电路单元测试管脚、一集成电路、一软性电路板其中之一电性相连，所述挖槽是曝露出所述垫。
  5. 一种低温多晶硅(LTPS)产品结构，其中，包括:
    一基材；
    至少一N型金属氧化半导体 (NMOS)位于所述基材上；
    至少一P型金属氧化半导体(PMOS)位于所述基材上；
    一第一金属层，位于所述NMOS与所述PMOS的一栅极绝缘层上，所述第一金属层用于形成一栅极、以及用于形成至少一第一走线；
    一第二金属层，用于形成所述NMOS与所述PMOS的漏极和源极以及至少一第二走线；
    一层间绝缘层，位于所述第一金属层以及所述栅极绝缘层上；
    一平坦层位于所述NMOS以及所述PMOS上方；
    一第一透明导电层位于所述平坦层上方并覆盖所述平坦层至少一部分；
    一保护层位于所述平坦层和所述第一透明导电层上方；
    一第二透明导电层位于所述保护层上方，所述第二透明导电层经由穿过所述保护层以及所述平坦层的通孔与所述NMOS的漏极和源极相连结；
    至少一挖槽，所述挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的一端点。
  6. 6、 根据权利要求5所述低温多晶硅产品结构，其中，所述N型金属氧化半导体包括:
    一遮蔽层位于所述基材上以覆盖部分基材；
    一阻隔层位于所述遮蔽层以及基材上；
    一二氧化硅层位于阻隔层上；
    一N通道层位于二氧化硅层上，所述N通道层具一多晶硅层、两N+型层，所述两N+型层的内侧各自接合于所述N通道层的两外侧，两N-型层的两端各自接合于所述多晶硅层外侧端以及两N+型层的内侧端；
    所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上 ；
    所述第一金属层，经由所述栅极绝缘层与所述N通道层绝缘分隔；
    一层间绝缘层，位于所述N型金属氧化半导体(NMOS)最上层；以及
    漏极和源极，由所述第二金属层形成，各自经由通孔连结所述N+型层,所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
  7. 7、 根据权利要求5所述的低温多晶硅产品结构，其中，所述P型金属氧化半导体，包括:
    一阻隔层位于所述基材上；
    一二氧化硅层位于阻隔层上；
    一P通道层位二氧化硅层上，所述P通道层具一多晶硅层、两P+型层，所述两P+型层的内侧各自接合于所述N通道层的两外侧；
    所述栅极绝缘层，位于所述N通道层以及所述二氧化硅层上；
    所述第一金属层，经由所述栅极绝缘层与所述P通道层与绝缘分隔；
    一层间绝缘层，位于所述P型金属氧化半导体(PMOS)最上层；以及
    漏极和源极，由所述第二金属层形成，各自经由通孔连结所述P型金属氧化半导体的所述P+型层，所述通孔穿设于所述层间绝缘层以及所述栅极绝缘层。
  8. 根据权利要求5所述的低温多晶硅产品结构，其中，所述第一走线的所述端点包括一垫，所述垫是与一电路单元测试管脚电性相连，所述挖槽是曝露出所述垫。
  9. 根据权利要求5所述的低温多晶硅产品结构，其中，所述第一走线的所述端点包括一垫，所述垫是与一集成电路芯片电性相连，所述挖槽是曝露出所述垫。
  10. 根据权利要求5所述的低温多晶硅产品结构，其中，所述第一走线的所述端点包括一垫，所述垫是与一软性电路板电性相连，所述挖槽是曝露出所述垫。
  11. 一种低温多晶硅产品的制造方法，其中，包括:
    提供一基材；
    形成NMOS与PMOS于所述基材上；
    形成第一金属层于所述NMOS与所述PMOS的一栅极绝缘层上，并加以图案化以构成所述NMOS与所述PMOS的栅极以及至少一第一走线；
    形成第二金属层并加以图案化以构成所述NMOS与所述PMOS的漏极与源极以及至少一第二走线；
    形一层间绝缘层于所述第一金属层以及所述栅极绝缘层上；
    形成平坦层于NMOS与PMOS上，所述平坦层覆盖所述NMOS与所述PMOS的漏极和源极以及所述第二走线；
    形成第一透明导电层于所述平坦层上以覆盖至少一部分所述平坦层；
    形成保护层于第一透明导电层与所述平坦层上；
    形成第二透明导电层于所述保护层上；
    挖洞形成至少一挖槽，所述挖槽穿过所述平坦层和所述层间绝缘层，以及所述挖槽穿过所述第一透明导电层、所述保护层、以及所述第二透明导电层中至少之一层以曝露所述第一走线的一端点。
  12. 根据权利要求11所述的低温多晶硅产品的制造方法，其中，所述第一走线的端点包含一第一垫，且所述第一走线与一电路单元测试管脚电性相连，所述挖槽形成于所述第一垫的上方。
  13. 根据权利要求11所述的低温多晶硅产品的制造方法，其中，所述第一走线的端点包含一第一垫，且所述第一走线与一集成电路芯片电性相连，所述挖槽形成于所第一述垫的上方。
  14. 根据权利要求11所述的低温多晶硅产品的制造方法，其中，所述第一走线的端点包含一第一垫，且所述第一走线与一软性电路板电性相连，所述挖槽形成于所述垫的上方。
PCT/CN2015/070524 2014-12-31 2015-01-12 低温多晶硅(ltps)产品结构及制造方法 Ceased WO2016106828A1 (zh)

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