WO2016090733A1 - 一种获取像素的灰阶补偿值的方法 - Google Patents

一种获取像素的灰阶补偿值的方法 Download PDF

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WO2016090733A1
WO2016090733A1 PCT/CN2015/071062 CN2015071062W WO2016090733A1 WO 2016090733 A1 WO2016090733 A1 WO 2016090733A1 CN 2015071062 W CN2015071062 W CN 2015071062W WO 2016090733 A1 WO2016090733 A1 WO 2016090733A1
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sub
matrix
polynomial
regions
area
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PCT/CN2015/071062
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English (en)
French (fr)
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胡厚亮
朱立伟
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深圳市华星光电技术有限公司
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Priority to US14/418,182 priority Critical patent/US9953554B2/en
Publication of WO2016090733A1 publication Critical patent/WO2016090733A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for acquiring gray scale compensation values of pixels.
  • the manufacturing process of the display panel may cause defects such as dots, lines, strips, blocks, etc. due to insufficient process or materials.
  • Gray scale compensation can be performed by adjusting the external circuit voltage to improve some defects; or gray scale compensation can be performed by the Mura processing structure in the back-end process to improve the defect and improve the yield of the display panel.
  • the grayscale compensation value corresponding to the defect can be obtained by the image processing method, and then the grayscale compensation values are stored in the Mura processing structure, and are directly called when the grayscale compensation is performed.
  • the hardware implementation of the Mura processing structure is to open up a storage space corresponding to the resolution of the display panel. This requires the Mura processing structure to have a large storage space, which increases the hardware cost of the Mura processing structure.
  • An embodiment of the present invention provides a method for acquiring a grayscale compensation value of a pixel, where the method includes:
  • the method further includes:
  • the polynomial coefficients of each of the first sub-regions are determined, and the determined polynomial coefficients are stored.
  • the determining the polynomial coefficients of each of the first sub-regions includes:
  • the first matrix is constructed according to the arrangement of the second sub-regions, and the elements of the first matrix are the average gray-scale compensation values of the second sub-regions;
  • a polynomial of the row number and the column number of the elements in the first matrix is obtained according to the fitted surface, thereby determining the polynomial coefficients of the respective first sub-regions.
  • the obtaining the range of the argument of the pre-set polynomial, obtaining the grayscale compensation value of each first sub-region according to the corresponding polynomial further includes:
  • the number of rows of the expanded second matrix is equal to the number of pixels in each row of the display area, and the number of columns is equal to the number of pixels in each column of the display area;
  • the extended second matrix includes:
  • the blocks corresponding to the elements are integrated to obtain the expanded second matrix.
  • the determining the polynomial coefficients of each of the first sub-regions includes:
  • a third matrix is constructed according to the arrangement of each pixel therein;
  • a polynomial of the row number and the column number of the elements in the third matrix is obtained according to the fitted surface, thereby determining the polynomial coefficients of the respective first sub-regions.
  • the first preset rule includes the number of pixels per row and column of each first sub-region or the number of first sub-regions.
  • the second preset rule comprises a general formula of a polynomial.
  • the smoothing filtering process on the extended matrix includes:
  • the expanded matrix is smoothed using a low pass filter.
  • the polynomial has two independent variables, which are respectively the row number and the column number of the elements in the first matrix.
  • the polynomial has two independent variables, which are respectively the row number and the column number of the elements in the third matrix.
  • the present invention has the following beneficial effects: the method for acquiring the grayscale compensation value of the pixel provided in the embodiment of the present invention only needs to be based on the pre-stored polynomial coefficients of the first sub-region, the first preset rule, and the second
  • the preset rule and the range of the argument of the polynomial can obtain the gray scale compensation value of each first sub-area, which greatly reduces the storage space of the Mura processing structure and reduces the Mura compared with the prior art. Handle the hardware cost of the structure.
  • FIG. 1 is a flowchart 1 of a method for acquiring a grayscale compensation value of a pixel according to an embodiment of the present invention
  • FIG. 2 is a second flowchart of a method for acquiring a grayscale compensation value of a pixel according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of constructing a first matrix according to an embodiment of the present invention.
  • FIG. 5 is a first diagram of a gray scale compensation effect according to an embodiment of the present invention.
  • Figure 6 is a partial enlarged view of Figure 5;
  • FIG. 7 is a flowchart 3 of a method for acquiring a grayscale compensation value of a pixel according to an embodiment of the present invention.
  • FIG. 8 is a flowchart 4 of a method for acquiring a grayscale compensation value of a pixel according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a copy and tile processing element according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of an extended second matrix according to an embodiment of the present invention.
  • FIG. 11 is a second diagram of a gray scale compensation effect according to an embodiment of the present invention.
  • Figure 12 is a partial enlarged view of Figure 11;
  • FIG. 13 is a flowchart 5 of a method for acquiring a grayscale compensation value of a pixel according to an embodiment of the present invention
  • FIG. 14 is a schematic structural diagram of a Mura processing structure according to an embodiment of the present invention.
  • a method for acquiring a grayscale compensation value of a pixel includes:
  • Step S101 Acquire a display area of the display panel.
  • the resolution of the display panel is determined, thereby determining the number of pixels that need to acquire the grayscale compensation value.
  • the resolution of the display panel is M ⁇ N, where M and N are both positive integers.
  • Step S102 The display area is divided into a plurality of first sub-areas according to the first preset rule, and each of the first sub-areas includes at least two pixels.
  • the first preset rule includes the number of pixels in each row and each column of each first sub-area 1.
  • the first preset rule may also be the number of the first sub-areas 1, that is, the display needs to display a display panel. How many first sub-areas 1 are divided into regions. In the embodiment of the present invention, the first first preset rule is adopted.
  • Step S103 Acquire a pre-stored polynomial coefficient of each first sub-area, and construct a polynomial corresponding to each first sub-area according to the second preset rule.
  • corresponding polynomial coefficients are stored in advance for each first sub-area 1.
  • the polynomial coefficients corresponding to the first sub-area 1 are called.
  • the polynomial coefficients of the different first sub-regions 1 are substituted, and the polynomial for each first sub-region 1 is obtained.
  • the polynomial coefficients of each first sub-area 1 can be stored in the form of a table in a hardware structure for realizing the acquired gray-scale compensation value, which is convenient for calling, and prevents the first sub-area 1 and the polynomial coefficients from being uncorresponding when called. phenomenon.
  • the highest number of times of the polynomial may be selected according to actual conditions.
  • a fourth-order polynomial is preferred, and in order to reduce the compensation error, the polynomial coefficient is usually reserved to four decimal places.
  • Step S104 Obtain a value range of the argument of the preset polynomial, and obtain a grayscale compensation value of each first sub-region according to the corresponding polynomial.
  • the gray scale compensation value of each first sub-area 1 can be obtained. Then, according to the pre-stored gray scale compensation value voltage coefficient, the gray scale compensation voltage of each first sub-area 1 can be calculated, and then compensated for each first sub-area 1.
  • the method for acquiring the grayscale compensation value of the pixel provided in the embodiment of the present invention only needs to be based on the pre-stored polynomial coefficients of the first sub-region, the first preset rule, the second preset rule, and the polynomial self.
  • the value range of the variable can obtain the gray scale compensation value of each first sub-area 1.
  • the storage space of the Mura processing structure is greatly reduced, which is beneficial to reducing the hardware cost of the Mura processing structure.
  • the resolution of the display panel in the embodiment of the present invention is M ⁇ N, and it is assumed that each grayscale depth is 8 bits, and five discontinuous grayscale compensations are stored in the Mura processing structure of the display panel. Value factor.
  • Other gray scale compensation value coefficients can be obtained by interpolation according to the five gray scale compensation value coefficients.
  • each Polynomial is a fourth-order polynomial at this time, then each Polynomial correspondence requires 15 coefficients. Assuming that the maximum value of the integer part of each polynomial coefficient is 254 (applicable to most display panels), and each polynomial coefficient is retained to four decimal places, the maximum value of each polynomial coefficient can be 254.9999.
  • the Mura processing structure it is usually processed with binary numbers, so for each polynomial coefficient, there are:
  • each polynomial coefficient needs to store is 4177919, and its binary representation is 11 1111 1011 1111 1111 1111.
  • the total storage space of each first sub-area 1 is:
  • the storage space required for the method for obtaining the grayscale compensation value of the pixel provided by the embodiment of the present invention is greatly reduced.
  • a smaller storage space can be obtained by adjusting the first preset rule, the second preset rule, etc., which is advantageous for further reducing the storage capacity of the Mura processing structure and reducing the cost of the Mura processing structure.
  • the polynomial coefficients of each first sub-area 1 should be determined, and the determined polynomial coefficients are stored. In order to execute the method shown in Figure 1, it is called directly.
  • the determining the polynomial coefficient of each first sub-area 1 may include the following steps:
  • Step S201 Acquire a display area of the display panel.
  • Step S202 The display area is divided into a plurality of first sub-areas according to the first preset rule, and each of the first sub-areas includes at least two pixels.
  • Steps S201 and S202 are respectively equivalent to steps S101 and S102 in FIG. 1, and thus are not described herein again.
  • Step S203 dividing each first sub-area into a plurality of second sub-areas.
  • each first sub-area 1 contains more pixels, for example, each line of the first sub-area 1 includes 16 pixels, and each column also includes 16 pixels.
  • each first sub-area 1 may be equally divided into a plurality of second sub-areas 2, for example, each first sub-area. 1 is divided equally into 64 second sub-regions 2.
  • Step S204 Acquire an average grayscale compensation value of pixels in each second subregion.
  • the gray scale compensation value of each pixel in the second sub-area 2 is obtained, and an average value thereof, that is, an average gray scale compensation value is obtained.
  • Step S205 For each first sub-area, construct a first matrix according to an arrangement situation of each second sub-area, and an element of the first matrix is an average gray-scale compensation value of each second sub-area.
  • Step S206 Construct a corresponding fitting surface according to each of the first matrix and the second preset rule.
  • a fitting surface equal to the number of the first matrix should be constructed, that is, the first matrix and the fitting surface are in one-to-one correspondence.
  • a fitting curved surface is constructed, which conforms to the second predetermined rule, that is, the general formula of a polynomial. Since the fourth-order polynomial has a small amount of calculation and a good fitting effect for the first matrix of 8 rows and 8 columns in FIG. 3, a 4th-order polynomial is preferred in the embodiment of the present invention.
  • the general formula of the fourth-order polynomial is as follows:
  • f(x,y) p 00 +p 10 x+p 01 y+p 20 x 2 +p 11 xy+p 02 y 2 +p 30 x 3 +p 21 x 2 y+p 12 xy 2 +p 03 y 3 +p 40 x 4 +p 31 x 3 y+p 22 x 2 y 2 +p 13 xy 3 +p 04 y 4
  • p 00 , p 10 , etc. are the polynomial coefficients of the polynomial, a total of 15; x and y are the independent variables of the polynomial. At this point, the polynomial has two independent variables, x and y, which are the row and column numbers of the elements in the first matrix.
  • Each point in Figure 4 is the element in the first matrix.
  • the sum of squares due to error (SSE) of the fitted surface fitted with the fourth-order polynomial and the elements in the first matrix is 4.292, and the mean square error (MSE) is 0.067.
  • the determining coefficient R-square is 0.991, which indicates that the fitting surface has an ideal fitting effect on each element in the first matrix.
  • Step S207 Obtain a polynomial about the row number and the column number of the first matrix according to the fitting curved surface, thereby determining polynomial coefficients of each first sub-region.
  • the method of acquiring the grayscale compensation value of the pixel as shown in FIG. 1 can be performed.
  • the gray-scale compensation value obtained by using the polynomial coefficient is the second sub-area 2, which is not the gray-scale compensation value of one pixel.
  • the gray scale compensation value obtained by directly using the polynomial coefficient is compensated, it may cause the block effect shown in FIG. 6 to affect the display effect of the display panel.
  • the method further includes:
  • Step S301 Integrate each first matrix according to the arrangement of each first sub-area to form a second matrix.
  • each first matrix is a sub-matrix of the second matrix
  • the second matrix is composed of these sub-matrices, which is similar to the process of constructing the first matrix shown in FIG.
  • Step S302 Expand the second matrix, and the number of rows of the expanded second matrix is equal to the number of pixels in each row of the display area, and the number of columns is equal to the number of pixels in each column of the display area.
  • the second matrix can be extended by using the following method:
  • Step S401 Perform copy and tile processing on each element of the second matrix to obtain a block corresponding to the element, and the number of rows and the number of columns of the block are consistent with the second sub-region.
  • the second matrix has j ⁇ k elements.
  • the element b 11 in the second matrix it is copied and tiled. Since the number of rows and the number of columns of the second sub-region 2 at this time are both 2, the b11 is copied and tiled into 2 ⁇ 2 blocks. This processing is also performed for other elements in the second matrix.
  • Step S402 Integrate the blocks corresponding to the elements according to the arrangement of the elements to obtain the expanded second matrix.
  • the second matrix originally has j ⁇ k elements, where j is the ratio of the number of pixels included in each row of the display panel to the number of pixels included in each row of the second sub-region. Similarly, where k is the ratio of the number of pixels included in each column of the display panel to the number of pixels included in each column of the second sub-region.
  • the total number of elements of the expanded second matrix is consistent with the total number of pixels of the display panel.
  • Step S303 performing smoothing processing on the expanded second matrix, obtaining grayscale compensation values corresponding to each pixel, and performing grayscale compensation.
  • the smoothing filtering process is preferably performed by a low-pass filter, in particular, the number of rows and the number of columns are the same as those of the second matrix,
  • the prime is a low-pass filter that reciprocates the product of the number of rows and the number of columns.
  • the low-pass filter shown below should be selected for smoothing:
  • Each element of the second matrix subjected to the smoothing filtering process corresponds to a gray scale compensation value of a pixel at a corresponding position on the display panel. As shown in FIG. 11, after the gray scale compensation value is performed according to each element of the second matrix, even if the magnification is as shown in FIG. 12, there is no obvious block phenomenon.
  • the first matrix may be expanded first, and then the expanded first matrix may be integrated into the second matrix, and then the second matrix is subjected to smoothing processing.
  • This embodiment of the present invention does not limit this.
  • the method for determining a polynomial coefficient includes:
  • Step S501 Acquire a display area of the display panel.
  • Step S502 The display area is divided into a plurality of first sub-areas according to the first preset rule, and each of the first sub-areas includes at least two pixels.
  • Step S503 Acquire a grayscale compensation value of each pixel of each first subregion.
  • Step S504 For each first sub-area, construct a third matrix according to the arrangement of each pixel.
  • Step S505 Construct a corresponding fitting surface according to each of the third matrix and the second preset rule.
  • Step S506 Obtain a polynomial about a row number and a column number of an element in the third matrix according to the fitting curved surface, thereby determining a polynomial coefficient of each first sub-region.
  • the polynomial coefficients of the polynomials of the first sub-regions 1 may be organized into a lookup table.
  • the lookup table data is then burned into the flash memory (Flash) of the drive system board of the display panel by a host computer (for example, a computer) through a Micro Control Unit (MCU).
  • flash flash
  • MCU Micro Control Unit
  • the Field-Programmable Gate Array (FPGA) of the driver system board reads the polynomial coefficients in the Flash and writes them to Double Rate Synchronous Dynamic Random Access Memory (DDR).
  • DDR Double Rate Synchronous Dynamic Random Access Memory
  • the FPGA calculates the grayscale compensation value using the polynomial coefficients, and corrects the grayscale value of the pixel to bring the final grayscale value to the display panel.

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Abstract

一种获取像素的灰阶补偿值的方法包括：获取显示面板的显示区域（S101）；根据第一预设规则，将显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素（S102）；获取预存储的、各第一子区域的多项式系数，根据第二预设规则，构建对应各第一子区域的多项式（S103）；获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值（S104）。

Description

一种获取像素的灰阶补偿值的方法
本申请要求享有2014年12月10日提交的名称为“一种获取像素的灰阶补偿值的方法”的中国专利申请CN201410752853.0的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种获取像素的灰阶补偿值的方法。
背景技术
在制作显示面板的过程中，显示面板的生产过程中会由于制程或材料的不足导致面板出现点、线、带、块状等缺陷(Mura)。可通过调节外部电路电压进行灰阶补偿，从而改善部分缺陷；或在后端工序中经过Mura处理结构进行灰阶补偿，改善这种缺陷，从而提升显示面板的良品率。
在Mura处理结构中，可通过图像处理方式得到缺陷对应的灰阶补偿值，再将各灰阶补偿值存放在Mura处理结构中，留待进行灰阶补偿时直接调用。目前Mura处理结构的硬件实现方式是开辟与显示面板解析度对应的存储空间。这就要求Mura处理结构具有较大的存储空间，提高了Mura处理结构的硬件成本。
发明内容
本发明的目的在于提供一种获取像素的灰阶补偿值的方法，以降低Mura处理结构的存储空间大小。
本发明实施例提供了一种获取像素的灰阶补偿值的方法，该方法包括：
获取显示面板的显示区域；
根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
获取预存储的、各第一子区域的多项式系数，根据第二预设规则，构建对应各第一子 区域的多项式；
获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值。
其中，所述方法还包括：
确定各第一子区域的多项式系数，并存储所确定的多项式系数。
其中，所述确定各第一子区域的多项式系数包括：
获取显示面板的显示区域；
根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
将各第一子区域平均划分为若干个第二子区域；
获取各第二子区域内的像素的平均灰阶补偿值；
针对各第一子区域，根据其中各第二子区域的排布情况，构建第一矩阵，第一矩阵的元素为各第二子区域的平均灰阶补偿值；
根据各第一矩阵和第二预设规则，构建对应的拟合曲面；
根据拟合曲面，获得关于第一矩阵中元素的行号和列号的多项式，从而确定各第一子区域的多项式系数。
其中，所述获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值之后，还包括：
根据各第一子区域排布的情况，整合各第一矩阵，构成第二矩阵；
扩展第二矩阵，扩展后的第二矩阵的行数与显示区域每行的像素个数相等，列数与显示区域每列的像素个数相等；
对扩展后的第二矩阵进行平滑滤波处理，获得各像素对应的灰阶补偿值，进行灰阶补偿。
其中，所述扩展第二矩阵包括：
对第二矩阵的各个元素，进行复制和平铺处理，获得该元素对应的块，该块的行数和列数与第二子区域一致；
根据各元素的排布情况，将各元素对应的块整合，获得扩展后的第二矩阵。
其中，所述确定各第一子区域的多项式系数包括：
获取显示面板的显示区域；
根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
获取各第一子区域的各像素的灰阶补偿值；
针对各第一子区域，根据其中各像素的排布情况，构建第三矩阵；
根据各第三矩阵和第二预设规则，构建对应的拟合曲面；
根据拟合曲面，获得关于第三矩阵中元素的行号和列号的多项式，从而确定各第一子区域的多项式系数。
其中，所述第一预设规则包括各第一子区域每行和每列的像素的个数或第一子区域的数目。
其中，所述第二预设规则包括多项式的通式。
其中，所述对扩展后的矩阵进行平滑滤波处理包括：
利用低通滤波器，对扩展后的矩阵进行平滑处理。
其中，所述多项式的自变量有两个，分别为第一矩阵中的元素的行号和列号。
其中，所述多项式的自变量有两个，分别为第三矩阵中的元素的行号和列号。
本发明带来了以下有益效果：针对本发明实施例中提供的获取像素的灰阶补偿值的方法，仅需要根据预先存储的各第一子区域的多项式系数、第一预设规则、第二预设规则以及多项式的自变量的取值范围，即可得到各第一子区域的灰阶补偿值，相对于现有技术而言，大大降低了Mura处理结构的存储空间大小，有利于降低Mura处理结构的硬件成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图 做简单的介绍：
图1是本发明实施例提供的获取像素的灰阶补偿值的方法流程图一；
图2是本发明实施例提供的获取像素的灰阶补偿值的方法流程图二；
图3是本发明实施例提供的第一矩阵的构建示意图；
图4是本发明实施例提供的拟合曲面图；
图5是本发明实施例提供的灰阶补偿效果图一；
图6是图5的局部放大示意图；
图7是本发明实施例提供的获取像素的灰阶补偿值的方法流程图三；
图8是本发明实施例提供的获取像素的灰阶补偿值的方法流程图四；
图9是本发明实施例提供的复制和平铺处理元素的示意图；
图10是本发明实施例提供的扩展第二矩阵的示意图；
图11是本发明实施例提供的灰阶补偿效果图二；
图12是图11的局部放大示意图；
图13是本发明实施例提供的获取像素的灰阶补偿值的方法流程图五；
图14是本发明实施例提供的Mura处理结构的结构示意图。
具体实施方式
本实施例中提供了一种获取像素的灰阶补偿值的方法，如图1所示，该方法包括：
步骤S101、获取显示面板的显示区域。
即确定该显示面板的分辨率，从而确定需要获取灰阶补偿值的像素的个数。在本发明实施例中，假设该显示面板的分辨率为M×N，其中，M和N均为正整数。
步骤S102、根据第一预设规则，将显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素。
其中，第一预设规则包括各第一子区域1每行和每列的像素的个数；第一预设规则也可为第一子区域1的数目，即表征需将一显示面板的显示区域平均划分为多少个第一子区域1。本发明实施例中，采用第一种第一预设规则。
步骤S103、获取预存储的、各第一子区域的多项式系数，根据第二预设规则，构建对应各第一子区域的多项式。
在本发明实施例中，针对各第一子区域1，预先存储了对应的多项式系数。在依次对各第一子区域1进行处理时，调用该第一子区域1对应的多项式系数。之后，根据第二预设规则提供的多项式的通式，将不同的第一子区域1的多项式系数代入，即可得到针对各第一子区域1的多项式。
各第一子区域1的多项式系数，可利用表格的形式存储在实现该获取灰阶补偿值的硬件结构中，便于调用，并防止发生第一子区域1和多项式系数在调用时不对应的不良现象。
其中，该多项式的最高次数可根据实际情况进行选择，在本发明实施例中，优选4阶多项式，且为了减少补偿误差，多项式系数通常保留到小数点后四位。
步骤S104、获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值。
根据预设置的多项式的自变量的取值范围，可得到各第一子区域1的灰阶补偿值。之后，根据预存储的灰阶补偿值电压系数，可计算得到各第一子区域1的灰阶补偿电压，进而针对各第一子区域1进行补偿。
显然，针对本发明实施例中提供的获取像素的灰阶补偿值的方法，仅需要根据预先存储的各第一子区域的多项式系数、第一预设规则、第二预设规则以及多项式的自变量的取值范围，即可得到各第一子区域1的灰阶补偿值，相对于现有技术而言，大大降低了Mura处理结构的存储空间大小，有利于降低Mura处理结构的硬件成本。
下面，利用具体数据来说明本发明对减小Mura处理结构的存储空间的贡献：
前文中说过，本发明实施例中的显示面板的分辨率为M×N，假设各灰阶深度为8比特(bit)，在显示面板的Mura处理结构中存储5个不连续的灰阶补偿值系数。其他灰阶补偿值系数可根据该5个灰阶补偿值系数，采用插值方式得到。
对于现有技术，由于需要针对各像素开辟其对应的存储空间，则该显示面板针对像素需要开辟的存储空间为：S＝M*N*8*5bit。若是M＝3840，N＝2160，则S＝3840*2160*8*5bit＝331776000bit＝40500千字节(byte，1byte＝8bit)，显然，这是一不小的存储空间。
而对于本发明提供的技术方案而言，由于第一预设规则、第二预设规则和多项式的自变量的取值范围所占空间较小，因此可以忽略不计。假设此时多项式为4阶多项式，则各 多项式对应需要15个系数。假设各多项式系数整数部分的最大值为254(可适用于绝大部分的显示面板)，且各多项式系数保留至小数点后四位，则各多项式系数的最大值可为254.9999。考虑到对于Mura处理结构而言，通常是采用二进制的数字进行处理，因此针对各多项式系数，有：
254.9999×214＝4177918.3616
则各多项式系数需要存储的最大整数为4177919，其二进制表示为11 1111 1011 1111 1111 1111。针对各多项式系数，其对应的存储空间为：S1＝22bit。则15个多项式系数共需要存储空间：S2＝S1×15＝330bit。对于M＝3840，N＝2160的显示面板而言，假设各第一子区域1每行具有16个像素，每列也具有16个像素，则共有(3840×2160)/162＝32400个第一子区域1。则对于该显示面板而言，各第一子区域1共需要存储空间为：
S3＝S2×32400＝10692000bit＝1336500Byte＝1305.18KByte
与前文提供的例子一致，针对各第一子区域1，存储5个不连续的灰阶补偿值系数，则各显示面板所需要的存储空间为：
S4＝S3×5＝6525.88Kbyte
可见，本发明实施例提供的获取像素的灰阶补偿值的方法所需要的存储空间大大降低。另外，还可通过调节第一预设规则、第二预设规则等来获得更小的存储空间，有利于进一步减小Mura处理结构的存储容量，降低Mura处理结构的成本。
显然，在本发明实施例的技术方案中，执行在图1所示的方法之前，应当确定各第一子区域1的多项式系数，并存储所确定的多项式系数。以便于执行图1所示的方法时，直接调用。
具体的，如图2所示，该确定各第一子区域1的多项式系数可包括如下步骤：
步骤S201、获取显示面板的显示区域。
步骤S202、根据第一预设规则，将显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素。
步骤S201、步骤S202分别等同于与图1中的步骤S101、步骤S102，因此在此不再赘述。
步骤S203、将各第一子区域平均划分为若干个第二子区域。
当第一子区域1所包含的像素较多时，例如第一子区域1的每行包括16个像素，每列也包括16个像素。为了能够获取到较为精确的多项式系数，同时减少所需处理的数据量，如图3所示，可将各第一子区域1平均划分为若干个第二子区域2，例如各第一子区域1平均划分为64个第二子区域2。此时各第二子区域2包括162/64＝4个像素，即各第二子区域2的每行包括2个像素，每列也包括2个像素。
步骤S204、获取各第二子区域内的像素的平均灰阶补偿值。
获取第二子区域2内的各像素的灰阶补偿值，并求其平均值，即平均灰阶补偿值。
步骤S205、针对各第一子区域，根据其中各第二子区域的排布情况，构建第一矩阵，第一矩阵的元素为各第二子区域的平均灰阶补偿值。
如图3所示，获得各第二子区域2的平均灰阶补偿值(acd，其中，c、d为1-8的整数)后，根据第一子区域1中的各第二子区域2的排布情况，构建第一矩阵。
步骤S206、根据各第一矩阵和第二预设规则，构建对应的拟合曲面。
具体的，应构建与第一矩阵个数相等的拟合曲面，即第一矩阵和拟合曲面是一一对应的。
如图4所示，针对图3所示的第一矩阵，构建拟合曲面，该拟合曲面符合第二预设规则——即某一多项式的通式。由于对于图3中的8行8列的第一矩阵而言，4阶多项式的计算量较少且拟合效果好，因此本发明实施例中优选4阶多项式。4阶多项式的通式如下：
f(x，y)＝p00+p10x+p01y+p20x2+p11xy+p02y2+p30x3+p21x2y+p12xy2+p03y3+p40x4+p31x3y+p22x2y2+p13xy3+p04y4
上式中，p00、p10等即为该多项式的多项式系数，共计15个；x和y为该多项式的自变量。此时，多项式的自变量有两个，即x和y，分别为第一矩阵中的元素的行号和列号。
图4中各点为第一矩阵中的各元素。利用4阶多项式拟合出来的拟合曲面与第一矩阵中各元素的误差平方和(The sum of squares due to error，简称SSE)为4.292，均方误差(Mean squared error，简称MSE)为0.067，决定系数R-square为0.991，表示该拟合曲面对第一矩阵中各元素的拟合效果较为理想。
步骤S207、根据拟合曲面，获得关于第一矩阵的行号和列号的多项式，从而确定各第一子区域的多项式系数。
结合图4的拟合曲面和4阶多项式，可得到4阶多项式中的15个多项式系数的确切值。为了保证该4阶多项式的准确性，对于每一多项式系数而言，需保留至小数点后四位。
得到多项式系数后，即可执行如图1所示的获取像素的灰阶补偿值的方法。
具体的，对于此时的第一子区域1而言，利用多项式系数获取到的灰阶补偿值为第二子区域2的，并非一个像素的灰阶补偿值。如图5所示，若是直接利用多项式系数获取到的灰阶补偿值进行补偿，将有可能导致图6所示的块状效应，影响显示面板的显示效果。
为了保证显示面板的显示质量，在本发明实施例中，如图7所示，在步骤S104之后，还包括：
步骤S301、根据各第一子区域排布的情况，整合各第一矩阵，构成第二矩阵。
即每一第一矩阵都是第二矩阵的子矩阵，第二矩阵是由这些子矩阵组合而成的，与图3所示的构建第一矩阵的过程类似。
步骤S302、扩展第二矩阵，扩展后的第二矩阵的行数与显示区域每行的像素个数相等，列数与显示区域每列的像素个数相等。
具体的，如图8所示，可利用如下方法扩展第二矩阵：
步骤S401、对第二矩阵的各个元素，进行复制和平铺处理，获得该元素对应的块，该块的行数和列数与第二子区域一致。
如图9所示，假设第二矩阵具有j×k个元素。针对第二矩阵中的元素b11，对其进行复制和平铺处理。由于此时的第二子区域2的行数和列数均为2，则将该b11复制、平铺为2×2的块。对于第二矩阵中的其他元素也执行该处理。
步骤S402、根据各元素的排布情况，将各元素对应的块整合，获得扩展后的第二矩阵。
如图10所示，第二矩阵原本具有j×k个元素，其中j为显示面板每行所包括的像素个数与第二子区域每行所包括的像素个数的比值，此时为
Figure PCTCN2015071062-appb-000001
类似的，其中k为显示面板每列所包括的像素个数与第二子区域每列所包括的像素个数的比值
Figure PCTCN2015071062-appb-000002
将b11等各元素的块整合后，各元素的块放置的位置与各元素一一对应，从而得到扩展后的第二矩阵。
显然，扩展后的第二矩阵的元素总数与显示面板的像素总数一致。
步骤S303、对扩展后的第二矩阵进行平滑滤波处理，获得各像素对应的灰阶补偿值，进行灰阶补偿。
其中，平滑滤波处理优选低通滤波器进行，尤其是行数与列数都与第二矩阵相同、元 素均为行数和列数乘积的倒数的低通滤波器。
则对于前文中的2行2列的第二矩阵，此时应当选取如下所示的低通滤波器进行平滑处理：
Figure PCTCN2015071062-appb-000003
进行平滑滤波处理后的第二矩阵的各元素，即相当于显示面板上对应位置处的像素的灰阶补偿值。如图11所示，根据第二矩阵的各元素进行灰阶补偿值后，即使放大如图12所示，也无较为明显的块状现象。
需要说明的是，上述步骤中，也可先扩展第一矩阵、之后再将扩展后的第一矩阵整合为第二矩阵，接着对第二矩阵进行平滑滤波处理。本发明实施例对此不进行限定。
进一步的，对于分辨率较低的显示面板或第一子区域1划分较细的显示面板而言，若各第一子区域1所包含的像素个数较少(例如仅有4个)，则在确定第一子区域1的多项式系数时，无需对第一子区域1再次划分，直接利用第一子区域1的各像素的灰阶补偿值确定多项式系数。具体的，如图13所示，确定多项式系数的方法包括：
步骤S501、获取显示面板的显示区域。
步骤S502、根据第一预设规则，将显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素。
步骤S503、获取各第一子区域的各像素的灰阶补偿值。
步骤S504、针对各第一子区域，根据其中各像素的排布情况，构建第三矩阵。
步骤S505、根据各第三矩阵和第二预设规则，构建对应的拟合曲面。
步骤S506、根据拟合曲面，获得关于第三矩阵中元素的行号和列号的多项式，从而确定各第一子区域的多项式系数。
类似的，此时，多项式的自变量有两个，即x和y，分别为第三矩阵中的元素的行号和列号。
在本发明实施例中，可将各第一子区域1的多项式的多项式系数整理为查找表。如图14所示，之后利用上位机(例如电脑)，通过微控制单元(Micro Control Unit，简称MCU)将查找表数据烧录到显示面板的驱动系统板的闪存(Flash)中。在需要获取灰阶补偿值时， 驱动系统板的现场可编程门阵列(Field-Programmable Gate Array，简称FPGA)读取Flash中的多项式系数并写至双倍速率同步动态随机存储器(Double Data Rate，简称DDR)。之后FPGA利用多项式系数计算出灰阶补偿值，并对像素的灰阶值进行校正，将最终的灰阶值至显示面板。
虽然本发明所公开的实施方式如上，但的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (11)

  1. 一种获取像素的灰阶补偿值的方法，其中，包括：
    获取显示面板的显示区域；
    根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
    获取预存储的、各第一子区域的多项式系数，根据第二预设规则，构建对应各第一子区域的多项式；
    获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值。
  2. 根据权利要求1所述的方法，其中，还包括：
    确定各第一子区域的多项式系数，并存储所确定的多项式系数。
  3. 根据权利要求2所述的方法，其中，所述确定各第一子区域的多项式系数包括：
    获取显示面板的显示区域；
    根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
    将各第一子区域平均划分为若干个第二子区域；
    获取各第二子区域内的像素的平均灰阶补偿值；
    针对各第一子区域，根据其中各第二子区域的排布情况，构建第一矩阵，第一矩阵的元素为各第二子区域的平均灰阶补偿值；
    根据各第一矩阵和第二预设规则，构建对应的拟合曲面；
    根据拟合曲面，获得关于第一矩阵中元素的行号和列号的多项式，从而确定各第一子区域的多项式系数。
  4. 根据权利要求3所述的方法，其中，所述获取预设置的多项式的自变量的取值范围，根据对应的多项式，获取各第一子区域的灰阶补偿值之后，还包括：
    根据各第一子区域排布的情况，整合各第一矩阵，构成第二矩阵；
    扩展第二矩阵，扩展后的第二矩阵的行数与显示区域每行的像素个数相等，列数与显 示区域每列的像素个数相等；
    对扩展后的第二矩阵进行平滑滤波处理，获得各像素对应的灰阶补偿值，进行灰阶补偿。
  5. 根据权利要求4所述的方法，其中，所述扩展第二矩阵包括：
    对第二矩阵的各个元素，进行复制和平铺处理，获得该元素对应的块，该块的行数和列数与第二子区域一致；
    根据各元素的排布情况，将各元素对应的块整合，获得扩展后的第二矩阵。
  6. 根据权利要求2所述的方法，其中，所述确定各第一子区域的多项式系数包括：
    获取显示面板的显示区域；
    根据第一预设规则，将所述显示区域平均划分为多个第一子区域，各第一子区域至少包括两个像素；
    获取各第一子区域的各像素的灰阶补偿值；
    针对各第一子区域，根据其中各像素的排布情况，构建第三矩阵；
    根据各第三矩阵和第二预设规则，构建对应的拟合曲面；
    根据拟合曲面，获得关于第三矩阵中元素的行号和列号的多项式，从而确定各第一子区域的多项式系数。
  7. 根据权利要求1所述的方法，其中，
    所述第一预设规则包括第一子区域每行和每列的像素的个数或第一子区域的数目。
  8. 根据权利要求1所述的方法，其中，
    所述第二预设规则包括多项式的通式。
  9. 根据权利要求4所述的方法，其中，所述对扩展后的矩阵进行平滑滤波处理包括：
    利用低通滤波器，对扩展后的矩阵进行平滑处理。
  10. 根据权利要求3所述的方法，其中，所述多项式的自变量有两个，分别为第一矩阵中的元素的行号和列号。
  11. 根据权利要求6所述的方法，其中，所述多项式的自变量有两个，分别为第三矩阵中的元素的行号和列号。
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