WO2016090597A1 - 支持多模式可配置的六输入查找表结构和fpga器件 - Google Patents

支持多模式可配置的六输入查找表结构和fpga器件 Download PDF

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WO2016090597A1
WO2016090597A1 PCT/CN2014/093567 CN2014093567W WO2016090597A1 WO 2016090597 A1 WO2016090597 A1 WO 2016090597A1 CN 2014093567 W CN2014093567 W CN 2014093567W WO 2016090597 A1 WO2016090597 A1 WO 2016090597A1
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input
signal
output
lookup table
outputs
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PCT/CN2014/093567
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English (en)
French (fr)
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樊平
耿嘉
王元鹏
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京微雅格（北京）科技有限公司
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Priority to US14/761,410 priority Critical patent/US9584128B2/en
Priority to CN201480013815.1A priority patent/CN105874714B/zh
Priority to PCT/CN2014/093567 priority patent/WO2016090597A1/zh
Publication of WO2016090597A1 publication Critical patent/WO2016090597A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration

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  • the present invention relates to the field of integrated circuit technology, and more particularly to a six-input lookup table structure and an FPGA device supporting multi-mode configurability.
  • FPGA Field-Programmable Gate Array
  • the Look-Up-Table is the main component of modern FPGA devices.
  • the LUT is essentially a Random-Access Memory (RAM).
  • RAM Random-Access Memory
  • the FPGA development software automatically calculates all possible results of the logic circuit and writes the result to the RAM in advance, so that each logical input of one signal is equivalent to inputting one. The address is checked to find out the content corresponding to the address, and then output.
  • the number of gate arrays of programmable logic devices is increasing, such as the widespread application of 10 million gate-level FPGAs.
  • the number of FPGA gates increases, the function implementation capability is enhanced, and the function is increased, but the performance is degraded accordingly. If the chip area becomes larger, the power consumption becomes higher, the speed becomes slower, etc., these will restrict the performance of the entire system. Therefore, it is not only required to reduce the process size and increase the number of gate arrays, but also to improve the application capability of each logic block.
  • the utilization rate reduces the occupied area of resources, and at the same time, it can improve the working speed of the chip and complete more functions and applications with limited resources.
  • the object of the present invention is to provide a six-input lookup table structure and an FPGA device supporting multi-mode configurability, which has higher flexibility, logic implementation capability and computing capability, in view of the deficiencies of the prior art. It can effectively improve the utilization of routing resources, reduce the occupied area of resources, and at the same time improve the working speed of the FPGA chip, and use the limited resources to complete more functions and applications.
  • an embodiment of the present invention provides a six-input lookup table structure that supports multi-mode configurability, including:
  • the six-input lookup table has six signal inputs and two signal outputs
  • the six-input lookup table structure includes:
  • the first five input lookup table receives five data signals input by five signal input ends of the six input lookup table, outputs a first output signal according to the five bit data signals, and outputs the first output The signal is output by the first signal output end of the six-input lookup table;
  • the second five-input lookup table receives a five-bit data signal input by the five signal input ends of the six-input lookup table signal, and outputs a second output signal according to the five-bit data signal;
  • the first gater outputs a control signal according to the set configuration mode, controls the second gate strobe to output the first output signal or the second output signal, and outputs the second gate strobe output
  • the first output signal or the second output signal is output by the second signal output of the six-input lookup table.
  • the first gate is specifically a second selector, and includes a first input terminal, a second input terminal, and an output terminal;
  • a first input end of the first gate is connected to a sixth bit data signal input by the other signal input end except the five signal input ends, and the second input end is connected to a preset constant;
  • One choice The output of the transistor is coupled to the strobe signal input of the second gate.
  • the second gater when the first gater outputs the preset constant according to the configuration mode, the second gater outputs the second output signal according to the preset constant strobe, and The second output signal is output by the second signal output of the six-input lookup table for implementing the logic function of the two five-input lookup tables for the six-input lookup table structure.
  • the other signal input terminal of the six-input lookup table except the five signal inputs is further used for The adder that is connected to the six-input lookup table inputs an addend.
  • the preset constant is zero.
  • the second strobe strobes and outputs the first output according to the sixth bit data signal a signal or a second output signal, and outputting the first output signal or the second output signal from a second signal output terminal of the six-input lookup table for implementing a six-input lookup table for the six-input lookup table structure Logic function.
  • an embodiment of the present invention provides an FPGA device, where the FPGA device includes the multi-input configurable six-input lookup table structure described in the above first aspect.
  • the multi-mode configurable six-input lookup table structure provided by the embodiment of the present invention can implement a logic function of a six-input lookup table or a logic function of implementing two five-input lookup tables, and has higher flexibility and logic implementation capability. And computing power, can effectively improve the utilization of routing resources, reduce the footprint of resources, while also improving the working speed of FPGA chips, using limited resources to complete more functions and applications.
  • FIG. 1 is a schematic diagram of an input and output port of a six-input lookup table structure according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a structure of a six-input lookup table according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a logic unit (LC) of an FPGA according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a logical area (LP) of an FPGA according to an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of input and output of a six-input lookup table structure supporting multi-mode configurable according to an embodiment of the present invention.
  • the six-input lookup table of the present invention is applied to the FPGA, and includes: six signal input terminals f0 to f5 and two signal output terminals A, B;
  • the six-input lookup table can be configured in one of two modes: a six-input lookup table mode or two five-input lookup table modes.
  • the logical structure inside the six-input lookup table can be as shown in FIG. 2, including two five inputs. Enter the lookup table LUT5x, LUT5xy and two gates mux1, mux2.
  • the LUT5x receives f0[1] ⁇ f4[1] input from the five signal input ends of the six-input lookup table, outputs the first output signal x3 according to f0[1] ⁇ f4[1], and outputs the first output signal x3. Outputted by the first signal output terminal A of the six-input lookup table;
  • the LUT5xy receives f0[1] ⁇ f4[1] input from five signal input terminals of the six-input lookup table, and outputs a second output signal x1 according to the five-bit data signal;
  • the mux1 outputs a control signal ct l according to the set configuration mode, and controls the mux2 strobe to output the first output signal x3 or the second output signal x1, and is output by the second signal output terminal B of the six-input lookup table.
  • mux1 is an alternative one, comprising two inputs and one output.
  • Mux1 outputs ct l as a preset constant according to the configuration mode.
  • the preset constant is a digital signal low level 0.
  • the mux2 outputs a second output signal x1 outputted by the LUT5xy according to the low level of the digital signal, and outputs the second output signal x1 from the second signal output terminal B of the six-input lookup table.
  • the six-input lookup table structure implements the logic of two independent five-input lookup tables.
  • the signal input terminal f5 of the six-input lookup table is idle and is not occupied by the logic of the two five-input lookup tables. Therefore, the signal input terminal f5 can also be used for the FPGA as shown in FIG.
  • LC Logic Cell
  • mux1 outputs ct l as f5[1] according to the configuration mode
  • mux2 outputs the first output signal x3 or the second output signal x1 according to f5[1], and the first output signal x3 or the first Two
  • the output signal x1 is output by the second signal output terminal B of the six-input lookup table.
  • the logic function of the six-input lookup table is implemented by using the six-input lookup table structure provided by this embodiment.
  • the multi-mode configurable six-input lookup table structure provided by the embodiment of the present invention can implement a logic function of a six-input lookup table or a logic function of implementing two five-input lookup tables, and has higher flexibility and logic implementation capability. And computing power, can effectively improve the utilization of routing resources, reduce the footprint of resources, while also improving the working speed of FPGA chips, using limited resources to complete more functions and applications.
  • the embodiment of the present invention further provides an FPGA device including the multi-input configurable six-input lookup table structure described in the foregoing embodiment, where the FPGA device includes multiple logic components (Logic). Element, LE), each LE includes 4 logical regions (Logic Parcel, LP) as shown in FIG. 4, and each LP includes two LCs as shown in FIG. 3, and each LC shown in FIG. It includes a six-input lookup table FG6X2 that supports multi-mode configurability, a full adder, and two registers (Q2, Q10 or Q3, Q11 shown in the figure).
  • the six-input lookup table FG6X2 can implement the logic function of a six-input lookup table or the logic function of implementing two five-input lookup tables.
  • the steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both.
  • the software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

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  • Mathematical Physics (AREA)
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  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

一种支持多模式可配置的六输入查找表结构和FPGA器件，六输入查找表具有六个信号输入端（f0-f5）和两个信号输出端（A、B）；其结构包括：第一五输入查找表（LUT5x）、第二五输入查找表（LUT5xy）、第一选通器（mux1）和第二选通器（mux2）；其中，第一五输入查找表（LUT5x）根据六输入查找表的五个信号输入端输入的五位数据信号（f0[1]-f4[1]）输出第一输出信号（x3），并将第一输出信号（x3）由六输入查找表的第一信号输出端（A）输出；第二五输入查找表（LUT5xy）根据六输入查找表的五个信号输入端输入的五位数据信号（f0[1]-f4[1]）输出第二输出信号（x1）；第一选通器（mux1）根据设定的配置模式输出控制信号（ct1），控制第二选通器（mux2）选通输出第一输出信号（x3）或第二输出信号（x1），并将第二选通器（mux2）选通输出的第一输出信号（x3）或第二输出信号（x1）由六输入查找表的第二信号输出端（B）输出。

Description

支持多模式可配置的六输入查找表结构和FPGA器件 技术领域
本发明涉及集成电路技术领域，特别是一种支持多模式可配置的六输入查找表结构和FPGA器件。
背景技术
现场可编程门阵列(Field－Programmable Gate Array，FPGA)是一种具有丰富硬件资源、强大并行处理能力和灵活可重配置能力的逻辑器件。这些特征使得FPGA在数据处理、通信、网络等很多领域得到了越来越多的广泛应用。
查找表(Look-Up-Table，LUT)是现代FPGA器件的主要元件，LUT本质上是一个随机存取存储器(Random-Access Memory，RAM)。目前FPGA中多使用4输入的LUT，每一个LUT可以看成一个有4位地址线的16x1的RAM。当用户通过原理图或HDL语言描述了一个逻辑电路以后，FPGA开发软件会自动计算逻辑电路的所有可能的结果，并把结果事先写入RAM,这样，每输入一个信号进行逻辑运算就等于输入一个地址进行查表，找出地址对应的内容，然后输出即可。
随着应用系统功能的增强和规模增大，要求可编程逻辑器件的门阵列数日益增大，如千万门级FPGA的广泛应用。FPGA门数的增多，函数实现能力增强，功能增大，但会造成其性能相应下降。如芯片面积变大，功耗变高，速度变慢等，这些都会制约整个系统的性能。因此不仅需要在减小工艺尺寸，提高门阵列数目的同时，还需要提高各逻辑块的应用能力。
提高查找表的灵活性，逻辑实现和运算能力，可以有效地提高布线资源 的利用率，减少资源的占用面积，同时可以提高芯片的工作速度，用有限的资源完成更多的功能和应用。
发明内容
本发明的目的是针对现有技术的缺陷，提供了一种支持多模式可配置的六输入查找表结构和FPGA器件，该六输入查找表结构具有更高的灵活性，逻辑实现能力和运算能力，可以有效的提高布线资源的利用率，减少资源的占用面积，同时还能提高FPGA芯片的工作速度，利用有限的资源完成更多的功能和应用。
第一方面，本发明实施例提供了一种支持多模式可配置的六输入查找表结构，包括：
所述六输入查找表具有六个信号输入端和两个信号输出端；
所述六输入查找表结构包括：
第一五输入查找表、第二五输入查找表、第一选通器和第二选通器；
其中，所述第一五输入查找表接收所述六输入查找表的五个信号输入端输入的五位数据信号，根据所述五位数据信号输出第一输出信号，并将所述第一输出信号由所述六输入查找表的第一信号输出端输出；
所述第二五输入查找表接收所述六输入查找表信号的所述五个信号输入端输入的五位数据信号，根据所述五位数据信号输出第二输出信号；
所述第一选通器根据设定的配置模式输出控制信号，控制第二选通器选通输出所述第一输出信号或第二输出信号，并将所述第二选通器选通输出的第一输出信号或第二输出信号由所述六输入查找表的第二信号输出端输出。
优选的，所述第一选通器具体为二选一选通器，包括第一输入端、第二输入端和输出端；
所述第一选通器的第一输入端接入除所述五个信号输入端外的其余一个信号输入端输入的第六位数据信号，第二输入端接入预置常量；所述第一选 通器的输出端与所述第二选通器的选通信号输入端相连接。
进一步优选的，当所述第一选通器根据所述配置模式输出所述预置常量时，所述第二选通器根据所述预置常量选通输出所述第二输出信号，并将所述第二输出信号由所述六输入查找表的第二信号输出端输出，用以所述六输入查找表结构实现两个五输入查找表的逻辑功能。
进一步优选的，当所述第一选通器选通输出所述预置常量时，所述六输入查找表的除所述五个信号输入端外的其余一个信号输入端还用于，向与所述六输入查找表相连接的加法器输入加数。
进一步优选的，所述预置常量为0。
进一步优选的，当所述第一选通器根据所述配置模式输出所述第六位数据信号时，所述第二选通器根据所述第六位数据信号选通输出所述第一输出信号或第二输出信号，并将所述第一输出信号或第二输出信号由所述六输入查找表的第二信号输出端输出，用以所述六输入查找表结构实现六输入查找表的逻辑功能。
第二方面，本发明实施例提供了一种FPGA器件，所述FPGA器件包括上述第一方面所述的支持多模式可配置的六输入查找表结构。
本发明实施例提供的支持多模式可配置的六输入查找表结构，能够实现一个六输入查找表的逻辑功能或者实现两个五输入查找表的逻辑功能，具有更高的灵活性，逻辑实现能力和运算能力，可以有效的提高布线资源的利用率，减少资源的占用面积，同时还能提高FPGA芯片的工作速度，利用有限的资源完成更多的功能和应用。
附图说明
图1为本发明实施例提供的六输入查找表结构的输入输出端口示意图；
图2为本发明实施例提供的六输入查找表结构的示意图；
图3为本发明实施例提供的FPGA的一个逻辑单元(LC)的示意图；
图4为本发明实施例提供的FPGA的一个逻辑区(LP)的示意图。
下面通过附图和实施例，对本发明的技术方案做进一步的详细描述。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它的实施例，都属于本发明保护的范围。
图1为本发明实施例提供的支持多模式可配置的六输入查找表结构的输入输出示意图。如图所示，本发明的六输入查找表应用于FPGA内部，包括：六个信号输入端f0～f5和两个信号输出端A、B；
具体的端口描述可以如下表1所示。
端口 位宽 输入输出 功能描述
f0 1 I 数据输入
f1 1 I 数据输入
f2 1 I 数据输入
f3 1 I 数据输入
f4 1 I 数据输入
f5 1 I 数据输入
A 1 O 第一LUT5的数据输出
B 1 O LUT6或第二LUT5的数据输出
表1
在FPGA上电时，六输入查找表可以被配置为以下两种模式中的其中一种：六输入查找表模式或者两个五输入查找表模式。
具体的，六输入查找表内部的逻辑结构可以如图2所示，包括两个五输 入查找表LUT5x、LUT5xy和两个选通器mux1、mux2。
其中，LUT5x接收六输入查找表的五个信号输入端输入的f0[1]～f4[1]，根据f0[1]～f4[1]输出第一输出信号x3，并将第一输出信号x3由六输入查找表的第一信号输出端A输出；
所述LUT5xy接收六输入查找表的五个信号输入端输入的f0[1]～f4[1]，根据所述五位数据信号输出第二输出信号x1；
mux1根据设定的配置模式输出控制信号ct l，控制mux2选通输出所述第一输出信号x3或第二输出信号x1，并由所述六输入查找表的第二信号输出端B输出。
进一步具体的，mux1为二选一选通器，包括两个输入端和一个输出端。
当六输入查找表被配置为两个五输入查找表模式时：
mux1根据配置模式输出ct l为预置常量，在本实施例所示的六输入查找表结构的示意图中，预置常量为数字信号低电平0。mux2根据数字信号低电平选通输出LUT5xy输出的第二输出信号x1，并将第二输出信号x1由六输入查找表的第二信号输出端B输出。
因为LUT5x输出的第一输出信号x3由六输入查找表的第一信号输出端A输出，因此，在这种配置模式下，六输入查找表结构实现的是两个独立的五输入查找表的逻辑功能。
此时，六输入查找表的信号输入端f5是闲置的，没有被两个五输入查找表的逻辑所占用，因此，信号输入端f5还可以用于，向在如图3所示的FPGA的逻辑单元(Logic cell，LC)中与六输入查找表相连接的加法器输入加数。具体可以参考图3中加粗线条所示的信号传输路径。由此可以节省一个信号输入端口的资源，提高了布线资源的利用率。
当六输入查找表被配置为六输入查找表模式时：
再如图2所示，mux1根据配置模式输出ct l为f5[1],mux2根据f5[1]选通输出第一输出信号x3或第二输出信号x1，并将第一输出信号x3或第二 输出信号x1由六输入查找表的第二信号输出端B输出。
其具体逻辑可以预先设置，比如规定，当f5[1]＝0时，第二信号输出端B输出第一输出信号x3；比如当f5[1]＝1时，第二信号输出端B输出第二输出信号x1；或者，当f5[1]＝0时，第二信号输出端B输出第二输出信号x1；比如当f5[1]＝1时，第二信号输出端B输出第一输出信号x3。由此利用本实施例提供的六输入查找表结构实现六输入查找表的逻辑功能。
本发明实施例提供的支持多模式可配置的六输入查找表结构，能够实现一个六输入查找表的逻辑功能或者实现两个五输入查找表的逻辑功能，具有更高的灵活性，逻辑实现能力和运算能力，可以有效的提高布线资源的利用率，减少资源的占用面积，同时还能提高FPGA芯片的工作速度，利用有限的资源完成更多的功能和应用。
相应的，本发明实施例还提供了一种包括上述实施例所述的支持多模式可配置的六输入查找表结构的FPGA器件，本发明所述的FPGA器件中，包括多个逻辑元件(Logic Element,LE)，每个LE包括4个如图4所示的逻辑区(Logic Parcel，LP)，每个LP中包括两个如图3所示的LC，在图4所示的每个LC中包括一个支持多模式可配置的六输入查找表FG6X2、一个全加器和两个寄存器(图中所示Q2、Q10或者Q3、Q11)。六输入查找表FG6X2能够实现一个六输入查找表的逻辑功能或者实现两个五输入查找表的逻辑功能，
专业人员应该还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或算法的步骤可以用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 一种支持多模式可配置的六输入查找表结构，其特征在于，所述六输入查找表具有六个信号输入端和两个信号输出端；
    所述六输入查找表结构包括：
    第一五输入查找表、第二五输入查找表、第一选通器和第二选通器；
    其中，所述第一五输入查找表接收所述六输入查找表的五个信号输入端输入的五位数据信号，根据所述五位数据信号输出第一输出信号，并将所述第一输出信号由所述六输入查找表的第一信号输出端输出；
    所述第二五输入查找表接收所述六输入查找表信号的所述五个信号输入端输入的五位数据信号，根据所述五位数据信号输出第二输出信号；
    所述第一选通器根据设定的配置模式输出控制信号，控制第二选通器选通输出所述第一输出信号或第二输出信号，并将所述第二选通器选通输出的第一输出信号或第二输出信号由所述六输入查找表的第二信号输出端输出。
  2. 根据权利要求1所述的结构，其特征在于，所述第一选通器具体为二选一选通器，包括第一输入端、第二输入端和输出端；
    所述第一选通器的第一输入端接入除所述五个信号输入端外的其余一个信号输入端输入的第六位数据信号，第二输入端接入预置常量；所述第一选通器的输出端与所述第二选通器的选通信号输入端相连接。
  3. 根据权利要求2所述的结构，其特征在于，当所述第一选通器根据所述配置模式输出所述预置常量时，所述第二选通器根据所述预置常量选通输出所述第二输出信号，并将所述第二输出信号由所述六输入查找表的第二信号输出端输出，用以所述六输入查找表结构实现两个五输入查找表的逻辑功能。
  4. 根据权利要求3所述的结构，其特征在于，当所述第一选通器选通输出所述预置常量时，所述六输入查找表的除所述五个信号输入端外的其余一个信号输入端还用于，向与所述六输入查找表相连接的加法器输入加数。
  5. 根据权利要求2或3所述的结构，其特征在于，所述预置常量为0。
  6. 根据权利要求2所述的结构，其特征在于，当所述第一选通器根据所述配置模式输出所述第六位数据信号时，所述第二选通器根据所述第六位数据信号选通输出所述第一输出信号或第二输出信号，并将所述第一输出信号或第二输出信号由所述六输入查找表的第二信号输出端输出，用以所述六输入查找表结构实现六输入查找表的逻辑功能。
  7. 一种FPGA器件，其特征在于，所述FPGA器件包括上述权利要求1-6任一所述的支持多模式可配置的六输入查找表结构。
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