WO2016086689A1

WO2016086689A1 - Trench schottky barrier diode and manufacturing method therefor

Info

Publication number: WO2016086689A1
Application number: PCT/CN2015/087589
Authority: WO
Inventors: 胡守时; 陈永南
Original assignee: 无锡华润上华半导体有限公司
Priority date: 2014-12-05
Filing date: 2015-08-20
Publication date: 2016-06-09
Also published as: CN105720109A

Abstract

A trench Schottky barrier diode and a manufacturing method therefor. The diode comprises: a semiconductor substrate (200); a back metal layer (208), located on a back surface of the semiconductor substrate (200); an epitaxial layer (201), located on a front surface of the semiconductor substrate (200), the epitaxial layer (201) comprising a plurality of first trench filling structures and second trench filling structures, feature sizes of the first trench filling structures being less than feature sizes of the second trench filling structures, the first trench filling structures being gate oxide layers (204) growing on a side wall and the bottom of a first trench (202) and gate material layers (205) growing on the gate oxide layers (204), and the second trench filling structures comprising gate oxide layers (204) located on a side wall and the bottom of a second trench (203) and gate material layers (205) growing on side walls of the gate oxide layers (204); and a barrier metal layer (207), located on a surface of the epitaxial layer (201). The Schottky barrier diode can improve an integration level, a forward current density and a peak repetitive Withstand voltage of a device.

Description

Trench type Schottky barrier diode and preparation method thereof

[Technical Field]

The present invention relates to a semiconductor component, and more particularly to a trench type Schottky barrier diode and a method of fabricating the same.

【Background technique】

Metal-semiconductor (M-S) junctions are formed by metal-to-semiconductor contacts that produce two of the most important effects: rectification and ohmic effects. A diode fabricated using metal-semiconductor rectifying contact characteristics is called a Schottky barrier diode, which has a similar current-voltage relationship with a PN junction diode, that is, they all have unidirectional conductivity.

Schottky diodes are usually designed in a planar shape. Because of the simple manufacturing process of this structure, only active region and metal layer lithography are required. The disadvantages are low current density, low device withstand voltage, and large die area. Conducive to integration. Since the metal lapped structure can eliminate the peripheral effect in the Schottky diode and the metal lap joint structure is relatively simple, it is generally more suitable to use it as a Schottky barrier diode structure. In addition, in order to improve the withstand voltage of the device, the Schottky barrier diode needs to have a ring ring structure on the periphery of the die. The Schottky barrier diode having the above structure requires a large die area to increase the contact area between the metal and the semiconductor to obtain a large current capability, and further increases the ring ring and ring injection for improving the withstand voltage, but generally It can only reach 50V.

[Summary of the Invention]

In view of this, it is necessary to provide a trench type Schottky barrier diode having a high degree of integration, a high reverse withstand voltage, and a simple manufacturing process.

A trench type Schottky barrier diode comprising:

Semiconductor substrate

a back metal layer on the back side of the semiconductor substrate;

An epitaxial layer on a front surface of the semiconductor substrate, the epitaxial layer includes a plurality of first trench fill structures and a second trench fill structure, the first trench fill structure having a feature size smaller than the second trench fill a feature size of the structure, wherein the first trench fill structure is a gate oxide layer grown on a sidewall and a bottom of the first trench, and a gate material layer grown on the gate oxide layer The second trench fill structure includes a gate oxide layer on the sidewalls and the bottom of the second trench, and a gate material layer grown on the sidewall of the gate oxide layer;

A barrier metal layer on the surface of the epitaxial layer.

A method for preparing a trench type Schottky barrier diode, comprising the steps of:

Forming a plurality of first trenches and second trenches in an epitaxial layer on a front surface of the semiconductor substrate, the first trench having a feature size smaller than a feature size of the second trench;

Forming a gate oxide layer on sidewalls and bottoms of the first trench and the second trench;

Forming a gate material layer, the gate material layer completely filling the first trench and formed on a gate oxide sidewall portion of the second trench;

Depositing a barrier metal layer on the epitaxial layer on the front side of the semiconductor substrate;

A back metal layer is formed on the back surface of the semiconductor substrate.

By forming a plurality of trench filling structures, device feature size can be significantly reduced, and device integration can be improved; using trench MOS (Metal Oxide) The conduction reduction barrier of the structure under the forward voltage can greatly increase the forward current density of the device; forming a dielectric layer in the second trench can greatly improve the reverse withstand voltage of the device, simplify the process steps, and reduce manufacturing cost.

[Description of the Drawings]

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.

1A-1C are schematic cross-sectional views showing three Schottky barrier diode structures;

2A-2G are schematic cross-sectional views of the device obtained in each step of the method for fabricating a trench type Schottky barrier diode according to an embodiment;

3 is a flow chart showing the steps of a method of fabricating a trench type Schottky barrier diode according to an embodiment.

【detailed description】

In the following description, numerous specific details are set forth in the However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some of the technical features well known in the art have not been described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be set forth in the following description in order to explain the trench type Schottky barrier diode proposed by the present invention and a method of fabricating the same. It is apparent that the practice of the invention is not limited to the specific details familiar to those skilled in the semiconductor arts. The preferred embodiments of the present invention are described in detail below, but the present invention may have other embodiments in addition to the detailed description.

It is to be understood that the terms "comprising" and """ A number of other features, integers, steps, operations, elements, components, and/or combinations thereof.

The three Schottky barrier diode structures in the prior art are as follows: In FIG. 1A, the N epitaxial film 101 formed on the N+ silicon substrate 100 is subjected to cleaning treatment and thermal oxidation, and then a window is opened by standard photolithography techniques. And by depositing metal 102 by evaporation or sputtering in a vacuum system, the metal pattern is determined by another step of photolithography, which is the simplest structure that does not provide ideal Schottky barrier properties due to corner effects. FIG. 1B is a metal lap joint structure which overlaps the metal on the oxide layer 103 formed on the N epitaxial film 101 by thermal oxidation (the lap area should be small), thereby eliminating the peripheral effect; the structure of FIG. 1C A method of reducing the edge effect by an additional P+ diffusion ring (protective ring) 104 is employed to obtain a desired IV characteristic, and a P+ diffusion ring 104 is formed in the depletion layer 105 in the N epitaxial film 101. Since the metal lap joint structure is relatively simple, it is generally more suitable to use it as a structure of a Schottky barrier diode. In addition, in order to improve the withstand voltage of the device, the Schottky barrier diode needs to have a ring ring structure on the periphery of the die. The Schottky barrier diode having the above three structures requires a large die area to increase the contact area between the metal and the semiconductor, thereby obtaining a large current capability, and further increasing the ring ring and ring injection for increasing the withstand voltage. But generally only reach 50V.

In order to overcome the deficiencies of the existing planar technology for preparing Schottky barrier diodes, the present invention provides a process-effective trench-type Schottky diode device structure and a method for fabricating the same, which utilizes a trench MOS structure to reduce device size. And improve the current capability and withstand voltage characteristics of the device.

2G, in the trench type Schottky barrier diode of an embodiment, an epitaxial layer 201 is formed on the upper portion of the front surface of the semiconductor substrate 200; and a plurality of first trench fills are formed in the epitaxial layer 201. a structure and a second trench filling structure, wherein a feature size of the first trench filling structure is smaller than a feature size of the second trench filling structure, wherein the first trench filling structure is a gate structure, and the gate structure is grown a trench oxide sidewall 204 and a bottom gate oxide layer 204, a gate material layer 205 grown on the gate oxide layer 204, and a barrier metal layer 207 grown on the gate oxide layer 204 and the gate material layer 205. The second trench filling structure is a structure for improving the reverse withstand voltage of the Schottky barrier diode. The second trench filling structure is grown on the gate oxide layer 204 at the sidewalls and the bottom of the second trench. A gate material layer 205 on the sidewall of the gate oxide layer 204, a dielectric layer 206 grown on the bottom of the gate oxide layer 204, and a barrier metal layer 207 grown on the gate material layer 205 and the dielectric layer 206 are formed. A recess structure is formed on the second trench-filled barrier metal layer 207 to expose a portion of the dielectric layer 206 to improve withstand voltage. The contact between the barrier metal layer 207 and the remaining portion of the front surface of the semiconductor substrate 200 constitutes the Schottky barrier diode; a back metal layer 208 is formed on the back surface of the semiconductor substrate 200.

Please refer to FIG. 2A - FIG. 2G and FIG. 3 A method of fabricating a trench-type Schottky barrier diode according to an embodiment includes the following steps. First, as shown in FIG. 2A, a semiconductor substrate 200 is provided. The constituent material of the semiconductor substrate 200 may be an undoped single. Crystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and insulator GeOI, silicon carbide, gallium arsenide, gallium nitride, etc. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is selected from single crystal silicon.

Next, an epitaxial layer 201 is formed on the upper portion of the front surface of the semiconductor substrate 200. As an example, an epitaxial layer 201 is formed using a deposition process such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra high vacuum chemical vapor deposition (UHVCVD), and rapid thermal chemical vapor deposition (RTCVD). One of physical vapor deposition (PVD), atomic layer deposition (ALD), and molecular beam epitaxy (MBE). While the deposition is performed, the formed epitaxial layer 201 may be doped with N-type or P-type ions, such as phosphorus ions or arsenic ions, and the P-type ions are boron ions or indium ions.

Next, as shown in FIG. 2B, a plurality of first trenches 202 and second trenches 203 are formed in the epitaxial layer 201, and the feature size of the first trenches 202 is smaller than the feature size of the second trenches 203. The size and number of feature sizes of the trenches may depend on the parameters of the device to be fabricated. Preferably, the first trench 202 has a width of about 0.5-1.5 μm and the second trench 203 has a width of about 20-100 μm. The groove depth is about 1-5 μm. The process step of forming the trench includes: forming a mask layer having a pattern of the trench on the epitaxial layer 201, and the mask layer may be a single photoresist layer or a hard mask laminated from bottom to top a film layer and a photoresist layer, the constituent material of the hard mask layer may be silicon nitride, phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), etc.; the mask layer is used as a mask, and the epitaxial layer is etched. Layer 201 to form a plurality of trenches therein; removing the mask layer. After the trench is formed, the morphology of the trench can also be improved by an oxidation or etching process.

Next, as shown in FIG. 2C, a gate oxide layer 204 is formed on the sidewalls and the bottom of the trench. As an example, the gate oxide layer 204 is formed by a process such as dry oxygen or wet oxygen. The constituent material may be silicon dioxide, and the thickness may be determined according to the parameters of the device to be prepared, and is not specifically limited herein.

Next, as shown in FIG. 2D, a gate material layer 205 is grown in the trench, wherein the gate material layer 205 is completely filled in the first trench 202, and the gate is grown on the sidewall of the second trench 203. Material layer 205. As an example, the process step of forming the gate material layer 205 includes: depositing a gate material layer on the epitaxial layer 201 to completely fill the trench, and performing the deposition while doping phosphorus in the formed gate material layer or Boron; etchback is performed to retain the gate material layer 205 in the first trench 202 and the gate material layer 205 on the sidewalls of the second trench 203. The constituent material of the gate material layer 205 may be polysilicon.

Next, as shown in FIG. 2E, after the gate material layer 205 is formed on the sidewall of the second trench 203, the dielectric layer 206 may continue to be formed in the second trench 203. As an example, the process step of forming the dielectric layer 206 includes depositing a dielectric layer to cover the side of the gate material layer 205 and the exposed bottom of the gate oxide layer 204; photolithography defining the active region pattern and by dry etching or wet method Etching, leaving the dielectric layer in the second trench 203. The constituent material of the dielectric layer 206 may be silicon nitride, phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), or the like formed by a conventional method familiar to those skilled in the art, and the thickness may be according to a device to be prepared. The parameters are not specifically limited herein. The dielectric layer 206 can greatly improve the reverse withstand voltage of the device, and the value can exceed 100V, thereby eliminating the complicated ring structure and injection of the process, simplifying the process steps, and reducing the manufacturing cost. It should be noted that if the requirement for the reverse withstand voltage of the device is not high, the above-described process steps of forming the dielectric layer 206 may be omitted.

Next, as shown in FIG. 2F, a barrier metal layer 207 is deposited over the semiconductor substrate 200, covering the epitaxial layer 201, the dielectric layer 206, the gate material layer 205, and the exposed gate oxide layer 204. To further increase the withstand voltage of the device, a patterning process may be performed to define a pattern of the barrier metal layer 207 in the second trench 203, which may be determined according to the parameters of the device to be fabricated and removed by etching. a barrier metal layer 207, in which a recess structure is formed in the barrier metal layer 207, through which the lower dielectric layer 206 is exposed (in the case where the dielectric layer 206 is not formed, the lower gate is exposed through the recess structure) Polar oxide layer 204). As an example, the constituent material of the barrier metal layer 207 may be a metal such as aluminum, titanium, tungsten, gold, or the like which can form Schottky contact with the semiconductor substrate 200 or an alloy of the above metals, and the thickness may be according to parameters of the device to be prepared. However, there is no specific limit here.

Next, as shown in FIG. 2G, a back metal layer 208 is formed on the back surface of the semiconductor substrate 200. As an example, the process step of forming the back metal layer 208 includes: performing a thinning treatment on the back surface of the semiconductor substrate 200, and the thickness can be reduced according to the parameters of the device to be prepared, which is not specifically limited herein; A layer is provided to cover the back surface of the semiconductor substrate 200.

So far, the process steps performed by the method according to the present embodiment are completed, and then, the fabrication of the entire semiconductor device can be completed by a subsequent process. According to this embodiment, By forming a plurality of trench filling structures, device feature size can be significantly reduced, and device integration can be improved; using a trench MOS structure to lower the barrier under forward voltage can greatly increase the forward current density of the device, that is, the device is Having a lower forward voltage at the same current; forming a dielectric layer 206 in the second trench 203 can greatly increase the reverse withstand voltage of the device, and the value can exceed 100V, thereby eliminating the complicated ring structure of the process. And injection, simplifying process steps and reducing manufacturing costs.

Referring to Fig. 3, there is shown a flow chart of the steps of a method of fabricating a trench type Schottky barrier diode of an embodiment for briefly showing the flow of the entire manufacturing process.

In step 301, a semiconductor substrate is provided;

In step 302, a plurality of first trenches and second trenches are formed in the semiconductor substrate, the feature size of the first trenches being smaller than the feature size of the second trenches;

In step 303, a gate oxide layer is formed on the sidewalls and the bottom of the first trench and the second trench;

In step 304, a gate material layer is formed, which completely fills the first trench and is formed on the sidewall portion of the second trench;

In step 305, after forming a gate material layer on the sidewall of the second trench, forming a dielectric layer in the second trench;

In step 306, depositing a barrier metal layer on the semiconductor substrate;

In step 307, a back metal layer is formed on the back surface of the semiconductor substrate.

The present invention has been described by the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of illustration and description. Further, those skilled in the art can understand that the present invention is not limited to the above embodiments, and various modifications and changes can be made according to the teachings of the present invention. These modifications and modifications are all claimed in the present invention. Within the scope. The scope of the invention is defined by the appended claims and their equivalents.

Claims

A trench type Schottky barrier diode, comprising:

Semiconductor substrate

a back metal layer on the back side of the semiconductor substrate;

An epitaxial layer on a front surface of the semiconductor substrate, the epitaxial layer includes a plurality of first trench fill structures and a second trench fill structure, the first trench fill structure having a feature size smaller than the second trench fill a feature size of the structure, wherein the first trench fill structure is a gate oxide layer grown on a sidewall and a bottom of the first trench, and a gate material layer grown on the gate oxide layer The second trench fill structure includes a gate oxide layer on the sidewalls and the bottom of the second trench, and a gate material layer grown on the sidewall of the gate oxide layer;

A barrier metal layer on the surface of the epitaxial layer.
The trench type Schottky barrier diode according to claim 1, wherein the barrier metal layer in the second trench filling structure further has a groove structure, and the groove structure is used to expose the A gate oxide layer under the barrier metal layer.
The trench type Schottky barrier diode according to claim 1, wherein a dielectric layer is further disposed between the gate oxide layer and the barrier metal layer in the second trench filling structure.
The trench type Schottky barrier diode according to claim 3, wherein the barrier metal layer in the second trench filling structure further has a groove structure, and the groove structure is used to expose the A dielectric layer below the barrier metal layer.
A method for preparing a trench type Schottky barrier diode, comprising the steps of:

Forming a plurality of first trenches and second trenches in an epitaxial layer on a front surface of the semiconductor substrate, the first trench having a feature size smaller than a feature size of the second trench;

Forming a gate oxide layer on sidewalls and bottoms of the first trench and the second trench;

Forming a gate material layer, the gate material layer completely filling the first trench and formed on a gate oxide sidewall portion of the second trench;

Depositing a barrier metal layer on the epitaxial layer on the front side of the semiconductor substrate;

A back metal layer is formed on the back surface of the semiconductor substrate.
The method according to claim 5, wherein after the step of depositing the barrier metal layer, further comprising: etching a barrier metal layer in the second trench, a potential in the second trench A recess structure is formed in the barrier metal layer to expose a gate oxide layer under the barrier metal layer.
The method according to claim 5, wherein the step of depositing the barrier metal layer further comprises the step of forming a dielectric layer in the second trench: depositing on the epitaxial layer on the front side of the semiconductor substrate a dielectric layer; lithography defines an active area pattern and preserves a dielectric layer in the second trench by etching.
The method according to claim 5, wherein the forming the first trench and the second trench comprises: forming a first trench and a second trench on the semiconductor substrate a mask layer of the pattern, the mask layer being a single photoresist layer or a hard mask layer and a photoresist layer stacked from bottom to top; etching the semiconductor liner with the mask layer as a mask a bottom to form a plurality of the first trenches and the second trenches therein; removing the mask layer.
The method of claim 5 wherein the step of forming the gate material layer comprises depositing a gate material layer on the semiconductor substrate to completely fill the first trench and the first Two trenches; performing etchback, leaving a layer of gate material in the first trench and a layer of gate material on sidewalls of the second trench.
The method according to claim 9, wherein the gate material layer is doped with phosphorus or boron, and the gate material layer is made of polysilicon.
The method according to claim 7, wherein the constituent material of the dielectric layer comprises silicon nitride, phosphosilicate glass or tetraethyl orthosilicate, and the constituent material of the barrier metal layer comprises aluminum, titanium, A metal or a metal alloy of tungsten or gold that forms Schottky contact with the semiconductor substrate.
The method according to claim 7, wherein after the step of depositing the barrier metal layer, further comprising: etching a barrier metal layer in the second trench, a potential in the second trench A recess structure is formed in the barrier metal layer to expose the dielectric layer under the barrier metal layer.