WO2016085169A1 - Quaternary nitride power semiconductor device and manufacturing method therefor - Google Patents

Quaternary nitride power semiconductor device and manufacturing method therefor Download PDF

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WO2016085169A1
WO2016085169A1 PCT/KR2015/012205 KR2015012205W WO2016085169A1 WO 2016085169 A1 WO2016085169 A1 WO 2016085169A1 KR 2015012205 W KR2015012205 W KR 2015012205W WO 2016085169 A1 WO2016085169 A1 WO 2016085169A1
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nitride layer
layer
quaternary nitride
quaternary
semiconductor device
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PCT/KR2015/012205
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French (fr)
Korean (ko)
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김종민
고유민
송근만
허종곤
신현범
강호관
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(재)한국나노기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate

Definitions

  • the present invention relates to a quaternary nitride power semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a two-dimensional electron by controlling polarization by controlling a stress acting on a gallium plane quaternary nitride during growth of a gallium plane quaternary nitride semiconductor. It relates to a gallium plane quaternary nitride power semiconductor device in which the gas formation position is reversed, and a method of manufacturing the same.
  • a power semiconductor device has a control and conversion function that distributes power to a system, and is used in a power supply device or a power conversion device to save energy and reduce a product. It is a device for supplying power to various electric devices such as AC / DC conversion, motor, or stably supplying desired voltage and current. It is applied to pivotal electronic applications such as computing, telecommunications, and automobiles. In conjunction with the development of electric vehicles, the field of application is expanding. R & D on high-speed switching, minimizing power loss, small chip size, and heat treatment contributes to power saving and eco-friendliness of various components used in display / LED drive ICs, portable devices, home appliances, renewable energy, alternative energy, automobiles, etc. .
  • Power semiconductor devices are optimized for the conversion or control of power, and are classified into silicon-based devices and compound-based devices.
  • Silicon-based devices have high breakdown voltage, large current, and high frequency, and Bipolar, IGBT, TD MOS, LDMOS, etc.
  • compound-based devices include SiC (silicon carbide) devices and GaN (Galium Nitride) devices. to be.
  • GaN power semiconductor device has the advantages of wide band gap characteristics and high temperature (700 °C) stability, and is emerging as a core device for next generation energy saving as a high power switching device as well as a high output power amplifier.
  • HEMT High Electron Mobility Transistor
  • 2DEG Two-dimensional electron gas
  • 1 and 2 illustrate the basic structure and energy band edge diagram of HEMT using 2DEG as an example of n-AlGaAs / i-GaAs / Si-GaAs HEMT.
  • 1 shows a heterojunction structure of n-AlGaAs / i-GaAs / Si-GaAs HEMT, wherein a 2DEG layer is formed on the epitaxially grown AlGaAs and GaAs junction interface, and a gate electrode is provided on the AlGaAs top surface.
  • FIG. 2 is an energy band diagram at the equilibrium state of the HEMT of FIG. 1, in which the conduction band edge (E ⁇ ) and E ⁇ (Fermi Energy) determine the electron density at 2DEG.
  • E ⁇ conduction band edge
  • E ⁇ Fermi Energy
  • AlGaN / GaN-based HEMTs are attracting attention as microwave applications and power semiconductor devices due to their wide band-gap, high breakdown field and excellent channel characteristics.
  • AlGaN / GaN / SiC-based HEMTs grown on the Ga-face show potential as power amplifiers from L-band (40-60 GHz) to W-band (75-110 GHz), and at heterojunction interfaces. Has excellent interfacial properties.
  • the upper surface has been manufactured in such a manner that the upper surface becomes the gallium surface, and recently, the device is grown to the nitrogen surface.
  • N-face AlGaN / GaN / SiC-based HEMTs have a low gate leakage current and can operate in E-mode (Ehancement mode) without gate recess.
  • E-mode Evolution mode
  • carrier confinement is improved under reverse bias in the GaN / AlGaN / GaN structure, and the contact resistance of the source / drain electrode can be reduced.
  • the nitrogen surface structure has a rough surface at the time of growth, so that the crystal quality is lower than that of the gallium surface device, and thus the electron mobility is lowered.
  • the present invention solves the deterioration of crystal quality of heterojunction interface, which is a disadvantage of nitrogen plane HEMT, and at the same time, the advantages of gallium and nitrogen plane HEMT, such as low gate leakage current, improved carrier confinement, E-mode operation, and reduced source / drain contact resistance. It is intended to present a quaternary nitride power semiconductor device having a method of manufacturing the same.
  • the power semiconductor device including the quaternary nitride layer according to the embodiment of the present invention is formed by forming a polarization direction of the quaternary nitride layer toward the upper surface of the quaternary nitride layer.
  • a gas is formed on top of the quaternary nitride layer.
  • the quaternary nitride layer is a gallium surface quaternary nitride layer grown so that a gallium surface is formed on the upper surface, and the four kinds of elements constituting the quaternary nitride layer have a predetermined composition ratio so that the two-dimensional electron gas is formed in the quaternary system. It is preferably formed on top of the nitride layer.
  • the quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N, and In and Al have a predetermined composition ratio, so that compressive stress acts on the quaternary nitride layer to polarize the quaternary nitride layer. It is preferable that the silver face upwards.
  • the quaternary nitride layer may be formed on the gallium nitride buffer layer formed on the substrate, and further include a gallium nitride cap layer formed on the quaternary nitride layer, and a gallium surface may be formed thereon.
  • the quaternary nitride layer is preferably made of a - ⁇ - ⁇ N (0 ⁇ x0.5, 0 ⁇ y0.5) In ⁇ Al ⁇ Ga 1.
  • composition x of In is 0.1 or more and 0.5 or less
  • composition y of Al is 0.05 or more and 0.2 or less.
  • a two-dimensional electron gas may be formed on the top of the quaternary nitride layer to form a bureid channel of the HEMT.
  • the gallium nitride cap layer is 1 nm to 30 nm, the quaternary nitride layer is preferably 1 nm to 30 nm.
  • Method of manufacturing a quaternary nitride power semiconductor device comprises the steps of forming a buffer layer GaN buffer layer on a substrate; Forming a quaternary nitride layer epitaxially growing a quaternary nitride layer made of four kinds of elements including Ga and N on the GaN buffer layer; And a cap layer forming step of growing a GaN cap layer on the quaternary nitride layer. It includes.
  • the polarization of the quaternary nitride layer may be adjusted to control the formation position of the two-dimensional electron gas.
  • the two-dimensional electron gas is formed on the contact interface between the quaternary nitride layer and the GaN cap layer.
  • the quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N, and the polarization of the quaternary nitride layer may be determined by the composition ratio of In and Al.
  • the quaternary nitride layer may be formed of a - ⁇ - ⁇ N In ⁇ Al ⁇ Ga 1 (0 ⁇ x0.5, 0 ⁇ y0.5). It is preferable that the composition x of In is 0.1 or more and 0.5 or less, and the composition y of Al is 0.05 or more and 0.2 or less.
  • a compressive stress is applied to the quaternary nitride layer, and the polarization direction of the quaternary nitride layer faces upward, and the two-dimensional electron gas is a contact interface between the quaternary nitride layer and the GaN cap layer. It is preferably formed in.
  • a two-dimensional electron gas may be formed on the top of the quaternary nitride layer to form a bureid channel of the HEMT.
  • the gallium plane quaternary power semiconductor device can operate in an E-mode (Enhancement mode) without the gate recess.
  • E-mode Evolution mode
  • the inclination of the relative Ec to the substrate side is increased, the leakage current is reduced, the carrier confinement is improved, and the contact resistance of the source / drain electrodes is reduced.
  • Power semiconductor device has the effect of increasing the degree of freedom of device structure design and manufacturing.
  • 1 is a view schematically showing a heterojunction structure of n-AlGaAs / i-GaAs / Si-GaAs HEMT.
  • FIG. 2 is an energy band diagram corresponding to the HEMT of FIG. 1.
  • FIG. 3 is a diagram illustrating a heterostructure of a conventional Ga-face quaternary nitride semiconductor device and a band gap diagram corresponding thereto.
  • FIG. 4 is a schematic diagram of a heterostructure of a gallium plane quaternary nitride semiconductor device according to an embodiment of the present invention and a band gap diagram corresponding thereto.
  • FIG. 5 schematically illustrates the polarization induction charge ⁇ and the position of 2DEG formation according to the polarization change of the quaternary nitride semiconductor.
  • FIG. 6 is a graph showing the correlation between lattice constants and energy band gaps of various nitride semiconductors of AlN, Al ⁇ Ga 1 - ⁇ N, GaN, Ga ⁇ In 1 - ⁇ N, Al ⁇ In 1 - ⁇ N, InN; to be.
  • FIG. 10 is a relation diagram of polarization induced charge density according to the composition ratio of Al (aluminum) and In (Indium, Indium) in In ⁇ Al ⁇ Ga 1 - ⁇ - ⁇ N / GaN.
  • FIG. 11 is a table showing strains and polarization induced charges in samples 1 to 11 having different composition ratios shown in FIG. 10.
  • Figure 13 (a) is a schematic diagram showing the position of 2DEG formation in the basic structure of a conventional gallium surface InAlGaN / GaN-based power semiconductor device.
  • Figure 13 (b) is a schematic diagram of a gallium surface InAlGaN / GaN based power semiconductor device according to an embodiment of the present invention.
  • FIG. 14 is a view schematically showing a method and a structure of a multilayer multi-channel monolithic device according to another embodiment of the present invention.
  • 3 (a) and 3 (b) are diagrams showing a heterostructure of a conventional Ga-face quaternary nitride semiconductor device and a band gap diagram corresponding thereto.
  • a first GaN layer is formed on a substrate and an InAl Aluminum Gallium Nitride (InAlGaN) layer is formed on the first GaN layer.
  • the surface is epitaxially grown so that the second GaN layer is formed as a cap layer, and gate, drain, and source electrodes are formed thereon to form a device.
  • the electrode may be formed directly on the InAlGaN layer without the second GaN layer.
  • Polarization of the nitride semiconductor is composed of a spontaneous polarization (P ⁇ ) and strain polarization (strain polarization, P ⁇ ) due to stress.
  • the spontaneous polarization is, but properties of the material itself, the strain polarization (P ⁇ ) is the crystal orientation of the strain polarization (P ⁇ ) by the stress acting on the nitride semiconductor, the spontaneous polarization (P ⁇ ) and strain polarization (P ⁇ ) Synthesis determines the total polarization (P).
  • FIG. 3 (a) schematically shows a 2DEG due to tensile force, polarization, and polarization inductive charge in the gallium plane GaN / InAlGaN / GaN structure.
  • FIG. 3 (b) shows an energy band gap diagram in the gallium plane GaN / InAlGaN / GaN structure of FIG. 3 (a), and the interface with the first GaN (Gallium Nitride) layer under the InAlGaN layer, that is, FIG. Quantum wells can be identified at a depth of 50 nm, which is where 2DEG is produced.
  • a 2DEG is generally formed at the bottom of the InAlGaN layer to operate in a D-mode (depletion mode) .
  • a special processing method such as a gate recess is used. You cannot operate in E-mode (Enhancement mode) without it.
  • the present invention proposes a quaternary nitride power semiconductor device having a number of advantages of nitrogen-based nitride-based HEMT while maintaining gallium surface growth to solve the problem of deterioration of interfacial crystal quality of nitrogen-based nitride power semiconductors and a method of manufacturing the same. .
  • 4 (a) and 4 (b) are schematic diagrams and corresponding band gap diagrams of a heterostructure of a gallium plane quaternary nitride semiconductor device according to an embodiment of the present invention.
  • a first GaN layer is formed on a sapphire, silicon, or silicon carbide substrate, and InAlGaN is formed on the first GaN layer.
  • An Indium Aluminum Gallium Nitride) layer is epitaxially grown, and a second GaN layer is formed thereon.
  • each layer is formed so that the gallium surface is on the upper surface.
  • FIG. 4 (a) schematically shows the 2DEG due to the compressive stress, polarization, and polarization induction charge in the gallium plane GaN / InAlGaN / GaN structure.
  • FIG. 4 (b) shows an energy band gap diagram corresponding to the structure of FIG. 4 (a), at an interface with a second GaN (Gallium Nitride) layer on top of the InAlGaN layer, ie, at 75 nm close to the surface. You can identify the quantum well, and this is where 2DEG is generated.
  • GaN GaN Nitride
  • 5 (a) to 5 (d) show that the position of 2DEG formation changes as the polarization of the quaternary nitride semiconductor changes, spontaneous polarization (P ⁇ ), polarization due to stress (P ⁇ ), total polarization (P), and polarization It is shown schematically using the induced charge ( ⁇ ).
  • FIG. 5 (a) illustrates a case where tensile stress is generated in an InAlGaN layer, wherein 2DEG is formed at an interface between InAlGaN and a GaN layer below it, and the charge density (x, y) induced at the interface is represented by the following equation ( Same as 1).
  • FIG. 5 (b) shows a case where a relatively small compressive stress occurs in the InAlGaN layer, wherein 2DEG is formed at the interface between InAlGaN and the GaN layer below it, but the charge density (x, y) induced at the interface is shown in FIG. decrease in a). At this time, the polarization inductive charge density (x, y) is obtained as in the formula (2).
  • FIG. 5 (c) shows the case where the synthetic polarization of the compressive stress and the spontaneous polarization generated in the InAlGaN layer is the same as the polarization of the GaN layer.
  • the charge density (x, y) induced at the heterojunction interface is 0 do. That is, the polarization inductive charge density (x, y) is represented by equation (3)
  • Such polarization reversal is possible by controlling the stress of InAlGaN to be a compressive stress rather than a tensile stress, and the stress can be controlled by adjusting the composition ratio of In (Indium) and Al (Aluminum) of the quaternary nitride semiconductor InAlGaN.
  • FIG. 6 is a graph showing the correlation between lattice constants and energy band gaps of various nitride semiconductors of AlN, Al ⁇ Ga 1 - ⁇ N, GaN, Ga ⁇ In 1 - ⁇ N, Al ⁇ In 1 - ⁇ N, InN; to be.
  • FIG. 7 is a graph showing polarization induced charge density according to the composition on the z-axis when In and Al are x and y in InAlGaN, respectively.
  • the red plane is a plane having a zero polarization inductive charge density
  • the green plane is a polarization induced charge density according to the composition of In and Al in InAlGaN.
  • the polarization inductive charge density becomes zero, and the position where the polarization induced charge, that is, the 2DEG is formed, is reversed based on this straight line. According to this graph, it can be seen that the position at which 2DEG is formed can be controlled by adjusting the composition ratio of In and Al.
  • FIG. 8 is a graph showing the relationship between lattice constants according to the composition of In and Al in InAlGaN.
  • the green plane corresponds to the lattice constant of InAlGaN corresponding to the constant value on the z-axis when the composition of In and Al of InAlGaN is x and y, respectively
  • the red plane represents the lattice constant of GaN.
  • the straight line where the green plane meets the red plane is when the lattice constant of InAlGaN coincides with the lattice constant of GaN.
  • the simulation graphs of FIGS. 6 to 8 above show the results as predicted theoretically.
  • the lattice constant of InAlGaN changes according to the composition ratio of In and Al, which is an InAlGaN layer and GaN. Induce a change in stress between layers.
  • the InAlGaN polarization is changed to reverse the polarization direction, and the position at which the 2DEG is formed is reversed. That is, the amount and position of the polarization inductive charge in InAlGaN is a function of the composition ratio of In and Al.
  • Peak angle separation is related to stress, and it can be seen that 2DEG is formed from the value of electron mobility and sheet concentration at the interface.
  • FIG. 10 shows polarization induced charge densities according to the composition ratios of Al (aluminum) and In (Indium, Indium) in In ⁇ Al ⁇ Ga 1 - ⁇ - ⁇ N / GaN
  • FIG. 11 shows the composition ratios shown in FIG. Tables showing strain and polarization induced charges in different samples 1-11. In this table, polarization reversal occurs when the polarization induced charge density is positive.
  • FIG. 12 is a band gap diagram of samples 1 to 11 of FIGS. 10 and 11, and when the composition ratios of Al (aluminum) and In (indium) are changed from sample 1 to sample 11, in particular, samples 9 and 10 , 11 and the like, it can be seen that 2DEG is formed at the upper interface of the InAlGaN layer.
  • Quaternary nitride layer is made of In ⁇ Al ⁇ Ga 1 - ⁇ - ⁇ N (0 ⁇ x0.5, 0 ⁇ y0.5), and the composition x is 0.1 or more 0.5 or less of In, Al composition y of from 0.05 If more than 0.2, 2DEG may be formed on the upper interface of the InAlGaN layer.
  • the numerical value is only one embodiment of the present invention, and by adjusting the composition ratio of In and Al, another composition ratio that can control the position where 2DEG is generated in InAlGaN to the upper surface may be obtained. As such, by controlling the composition ratio of the quaternary nitride semiconductor, the position of 2DEG formation can be adjusted through polarization control.
  • 13 (a) and 13 (b) show the structure of the semiconductor device according to the 2DEG formation position of the quaternary InAlGaN nitride power semiconductor device.
  • FIG. 13 (a) shows a basic structure of a conventional gallium plane InAlGaN / GaN based power semiconductor device, wherein 2DEG is formed on the bottom surface of InAlGaN.
  • the gallium surface GaN / InAlGaN / GaN based power semiconductor device according to the embodiment of the present invention shown in FIG. the HEMT buried channel structure is possible. In other words, a channel is formed on the upper surface of InAlGaN, which can block electron movement toward the substrate, thereby reducing leakage current toward the substrate and improving carrier confinement.
  • the gallium plane GaN / InAlGaN / GaN-based power semiconductor devices of the present invention make E-mode (Enhancement mode) operation easier. And the contact resistance of the source / drain electrodes is reduced.
  • a buffer layer forming step of forming a GaN buffer layer on a substrate Forming a quaternary nitride layer epitaxially growing a quaternary nitride layer including four kinds of elements including Ga and N on the GaN buffer layer; And a cap layer forming step of growing a GaN cap layer on the quaternary nitride layer.
  • the substrate is preferably a sapphire, silicon, silicon carbide substrate, the nitride layer is all grown to the gallium plane, the quaternary nitride layer includes In, Al, Ga, N.
  • the composition ratio of In and Al may be a predetermined ratio, for example, composition x of 0.1 or more and 0.5 or less, and composition y of Al may be 0.05 or more and 0.2 or less. have.
  • the quaternary nitride layer epitaxially grows while the compressive stress is applied, thereby inverting the polarization.
  • the quaternary nitride layer is preferably formed at about 1 nm to 30 nm, but is not necessarily limited thereto.
  • the gallium nitride cap layer is preferably formed to 1 nm to 30 nm, but is not limited thereto.
  • a multilayer multi-mode nitride semiconductor device can be implemented.
  • a first GaN layer, a first InAlGaN layer (InAlGaN-2), a barrier layer, a second GaN layer, a second InAlGaN layer (InAlGaN-1), and a third GaN layer are sequentially epitaxially grown on a gallium surface on a substrate. Let's do it.
  • the composition ratio of In and Al may be adjusted to be different so that the polarization directions of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN layer (InAlGaN-1) are different from each other.
  • the composition ratio of In and Al of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN-1 layer (InAlGaN-1) is controlled to adjust the composition ratio of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN layer (InAlGaN-1).
  • 2DEG can be formed on the lower and upper surfaces respectively.
  • 2DEGs are formed at the lower interface of the first InAlGaN layer (InAlGaN-2) and the upper interface of the second InAlGaN layer (InAlGaN-1), respectively.
  • the third and fourth InAlGaN layers may be formed in the same manner.
  • the gate, drain, and source electrodes are formed on the third GaN layer to form channel 1 (H1), and some regions of the stacked nitride semiconductors are etched to the barrier layer except for the region where channel 1 is formed. isolation) and a gate, a drain, and a source electrode are formed on the first InAlGaN layer (InAlGaN-2).
  • Channel 2 (H2) may be formed in the partial region etched by the above method.
  • the channel 1 is formed in the upper interface of the second InAlGaN layer (InAlGaN-1) 2DEG is operated in the E-mode, the channel 2 is formed in the lower interface of the first InAlGaN layer (InAlGaN-2) D-mode
  • This multi-mode multilayer nitride semiconductor device can implement a plurality of channels operating in different modes in a single device in different layers, thereby improving the design freedom of the device without noise or malfunction caused by signal interference between the channels. There is.

Abstract

A gallium surface quaternary nitride power semiconductor device according to the present invention comprises: a gallium nitride buffer layer formed on a substrate; a quaternary nitride layer formed on the gallium nitride buffer layer; and a gallium nitride cap layer formed on the quaternary nitride layer, wherein a two-dimensional electron gas is formed on the top end of the quaternary nitride layer by adjusting the composition ratio of the quaternary nitride layer such that a polarisation direction faces the top surface of the quaternary nitride layer. The quaternary nitride is composed of four element types such as In, Al, Ga and N, wherein In and Al have a pre-determined composition ratio, accordingly compressive stress is applied to the quaternary nitride layer, and the polarisation of the quaternary nitride layer is adjusted so as to face toward the top part thereof.

Description

4원계 질화물 전력반도체소자 및 이의 제조 방법Quaternary nitride power semiconductor device and manufacturing method thereof
본 발명은 4원계 질화물 전력반도체소자 및 이의 제조 방법에 관한 것으로서, 보다 상세하게는 갈륨면 4원계 질화물 반도체의 성장 과정에서 갈륨면 4원계 질화물에 작용하는 응력을 조절함으로써 분극을 조절하여 2차원 전자가스 형성 위치가 역전된 갈륨면 4원계 질화물 전력반도체소자 및 이를 제조하는 방법에 관한 것이다.The present invention relates to a quaternary nitride power semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a two-dimensional electron by controlling polarization by controlling a stress acting on a gallium plane quaternary nitride during growth of a gallium plane quaternary nitride semiconductor. It relates to a gallium plane quaternary nitride power semiconductor device in which the gas formation position is reversed, and a method of manufacturing the same.
전력반도체소자는 전력을 시스템에 맞게 배분하는 제어 및 변환 기능을 가진 소자로서, 에너지를 절약하고 제품을 축소하기 위하여 전력공급 장치나 전력변환 장치에 사용된다. 교류/직류 변환, 모터를 비롯한 각종 전기기기에 전력을 공급하거나 안정적으로 원하는 전압과 전류를 공급하기 위한 소자로서, 컴퓨팅통신가전산전자동차 등 중추적인 전자 애플리케이션에 적용되며, 최근에는 모바일 기기의 증가와 전기 자동차의 개발과 맞물려 적용 영역이 확대되고 있다. 고속 스위칭, 전력손실 최소화, 소형 칩 사이즈, 발열처리 등에 관한 R&D로 디스플레이/LED 드라이브 IC, 휴대형 기기, 가전기기, 신재생/대체 에너지, 자동차 등에 사용되는 각종 부품의 절전화 및 친환경화에 기여하고 있다. A power semiconductor device has a control and conversion function that distributes power to a system, and is used in a power supply device or a power conversion device to save energy and reduce a product. It is a device for supplying power to various electric devices such as AC / DC conversion, motor, or stably supplying desired voltage and current. It is applied to pivotal electronic applications such as computing, telecommunications, and automobiles. In conjunction with the development of electric vehicles, the field of application is expanding. R & D on high-speed switching, minimizing power loss, small chip size, and heat treatment contributes to power saving and eco-friendliness of various components used in display / LED drive ICs, portable devices, home appliances, renewable energy, alternative energy, automobiles, etc. .
전력반도체소자는 전력의 변환이나 제어용으로 최적화되어 있는데, 크게 실리콘 기반 소자 및 화합물 기반 소자로 분류된다. 실리콘 기반 소자는 고내압화, 큰전류화, 고주파수화 되어 있으며, Bipolar, IGBT, TD MOS, LDMOS 등이 있고, 화합물 기반 소자는 SiC(탄화규소) 소자 및 GaN(Galium Nitride, 질화갈륨) 소자가 대표적이다. Power semiconductor devices are optimized for the conversion or control of power, and are classified into silicon-based devices and compound-based devices. Silicon-based devices have high breakdown voltage, large current, and high frequency, and Bipolar, IGBT, TD MOS, LDMOS, etc., and compound-based devices include SiC (silicon carbide) devices and GaN (Galium Nitride) devices. to be.
실리콘 기반 전력반도체는 고전압 환경에서 전력전달 효율이 낮아 에너지 낭비가 커서 전력전달 효율성이 높은 질화갈륨 등 신소자를 이용한 연구가 부상하고 있다. GaN 전력반도체소자는 와이드 밴드 갭 특성과 고온(700℃) 안정성의 장점이 있고, 고출력 전력증폭기뿐만 아니라 고전력 스위칭 소자로써 차세대 에너지 절감용 핵심소자로 부각되고 있다. Silicon-based power semiconductors are emerging as research using new devices such as gallium nitride, which has high power transmission efficiency due to high energy consumption due to low power transmission efficiency in a high voltage environment. GaN power semiconductor device has the advantages of wide band gap characteristics and high temperature (700 ℃) stability, and is emerging as a core device for next generation energy saving as a high power switching device as well as a high output power amplifier.
한편 HEMT(High Electron Mobility Transistor)는 에너지 밴드-갭(Energy band gap)이 서로 다른 두 물질의 접합계면(heterojunction)을 채널로서 이용하는 전계 효과형 트랜지스터(Field-Effect Transistor)의 일종이다. HEMT의 이종 접합계면에는 2차원 전자가스(2 Dimensional Electron Gas, 2DEG)가 생성되는데, 이 전자는 이온산란을 받기 어렵기 때문에 일반 반도체 중의 캐리어 보다 각별히 높은 이동도를 갖는다. 또한 이종접합계면(Heterojunction)에서 전자가 z 축 방향으로는 구속되지만 2차원 평면(x-y 평면)에서는 자유롭게 이동하여 높은 이동도를 갖는 캐리어로서 기능하게 되므로, 게이트 전극을 설치하여 이 캐리어를 제어하면 여러 가지 우수한 특성을 가진 FET를 만들 수 있다. On the other hand, HEMT (High Electron Mobility Transistor) is a type of field-effect transistor that uses a heterojunction of two materials having different energy band gaps as a channel. Two-dimensional electron gas (2DEG) is generated at the heterojunction interface of HEMT, and since the electrons are hardly subjected to ion scattering, they have a higher mobility than carriers in general semiconductors. In addition, in the heterojunction, electrons are constrained in the z-axis direction but move freely in the two-dimensional plane (xy plane) to function as carriers with high mobility. It is possible to make FETs with excellent characteristics.
도 1, 2는 2DEG을 이용한 HEMT의 기본 구조와 에너지 밴드 에지 다이어그램을 n-AlGaAs/i-GaAs/Si-GaAs HEMT를 예로서 도시한 것이다. 도 1은n-AlGaAs/i-GaAs/Si-GaAs HEMT의 이종접합구조를 나타낸 것으로, 에피택셜 성장한 AlGaAs와 GaAs의 접합계면에 2DEG층이 생성되고, AlGaAs의 상면에 게이트 전극이 제공된다.1 and 2 illustrate the basic structure and energy band edge diagram of HEMT using 2DEG as an example of n-AlGaAs / i-GaAs / Si-GaAs HEMT. 1 shows a heterojunction structure of n-AlGaAs / i-GaAs / Si-GaAs HEMT, wherein a 2DEG layer is formed on the epitaxially grown AlGaAs and GaAs junction interface, and a gate electrode is provided on the AlGaAs top surface.
도 2는 도 1의 HEMT의 평형상태에서의 에너지 밴드 다이어그램으로서, 여기서 전도대(Conduction band edge, EΓ)와 EΖ(Fermi Energy)이 2DEG에서의 전자 밀도(electron density)를 결정한다. FIG. 2 is an energy band diagram at the equilibrium state of the HEMT of FIG. 1, in which the conduction band edge (E Γ ) and E Ζ (Fermi Energy) determine the electron density at 2DEG.
한편 AlGaN/GaN 기반 HEMT는 와이드 밴드-갭과 높은 항복 전계 및 우수한 채널 특성으로 인해 마이크로파 응용분야와 전력반도체소자로서 각광받고 있다. On the other hand, AlGaN / GaN-based HEMTs are attracting attention as microwave applications and power semiconductor devices due to their wide band-gap, high breakdown field and excellent channel characteristics.
갈륨면(Ga-face)으로 성장한 AlGaN/GaN/SiC 기반 HEMT는 L-band(40~60 GHz)에서 W-band(75~110 GHz)까지 전력증폭기로서의 가능성을 보여주고 있으며, 이종 접합 계면에서의 계면 특성이 우수하다. InAlN/GaN 구조 HEMT의 경우도 상면(上面)이 갈륨면이 되도록 성장하는 방식으로 제조 되어 왔으며 최근에는 질소면으로 성장하여 소자를 제작하는 경우도 있다. AlGaN / GaN / SiC-based HEMTs grown on the Ga-face show potential as power amplifiers from L-band (40-60 GHz) to W-band (75-110 GHz), and at heterojunction interfaces. Has excellent interfacial properties. In the case of the InAlN / GaN structure HEMT, the upper surface has been manufactured in such a manner that the upper surface becomes the gallium surface, and recently, the device is grown to the nitrogen surface.
질소면(N-face) AlGaN/GaN/SiC 기반 HEMT는 게이트 누설 전류(Gate Leakage current)가 작고, 게이트 리세스 없이 E-mode(Enhancement mode) 동작이 가능하다. 또한 GaN/AlGaN/GaN 구조에서 reverse bias 하에서 캐리어(carrier) confinement가 개선되며, 소스(Source)/드레인(Drain) 전극의 접촉저항(contact resistance)을 줄일 수 있다는 장점이 있다. 그러나 질소면 구조는 성장 시에 표면이 거칠어 결정 품질이 갈륨면 소자와 비교할 때 저하되고 따라서 electron mobility가 떨어지는 등의 문제가 있다.N-face AlGaN / GaN / SiC-based HEMTs have a low gate leakage current and can operate in E-mode (Ehancement mode) without gate recess. In addition, carrier confinement is improved under reverse bias in the GaN / AlGaN / GaN structure, and the contact resistance of the source / drain electrode can be reduced. However, there is a problem that the nitrogen surface structure has a rough surface at the time of growth, so that the crystal quality is lower than that of the gallium surface device, and thus the electron mobility is lowered.
본 발명은 질소면 HEMT의 단점인 이종 접합계면의 결정품질 저하를 해결하면서 동시에 낮은 게이트 누설전류, 캐리어 confinement 개선, E-mode 동작 가능, 소스/드레인 접촉 저항 감소 등 갈륨면과 질소면 HEMT의 장점을 가지는 4원계 질화물 전력반도체소자 및 이를 제조하는 방법을 제시하고자 한다.The present invention solves the deterioration of crystal quality of heterojunction interface, which is a disadvantage of nitrogen plane HEMT, and at the same time, the advantages of gallium and nitrogen plane HEMT, such as low gate leakage current, improved carrier confinement, E-mode operation, and reduced source / drain contact resistance. It is intended to present a quaternary nitride power semiconductor device having a method of manufacturing the same.
상기와 같은 과제를 해결하기 위해 본 발명의 일 실시예에 따른 4원계 질화물층을 포함하는 전력반도체소자는 4원계 질화물층의 분극 방향이 상기 4원계 질화물층의 상면을 향하도록 형성됨으로써 2차원 전자가스가 상기 4원계 질화물층의 상단에 형성되는 것을 특징으로 한다. 상기 4원계 질화물층은 갈륨면이 상부면에 형성되도록 성장된 갈륨면 4원계 질화물층이고, 상기 4원계 질화물층을 이루는 4 종류의 원소들은 소정의 조성비를 가짐으로써 2차원 전자가스가 상기 4원계 질화물층의 상단에 형성되는 것이 바람직하다.In order to solve the above problems, the power semiconductor device including the quaternary nitride layer according to the embodiment of the present invention is formed by forming a polarization direction of the quaternary nitride layer toward the upper surface of the quaternary nitride layer. A gas is formed on top of the quaternary nitride layer. The quaternary nitride layer is a gallium surface quaternary nitride layer grown so that a gallium surface is formed on the upper surface, and the four kinds of elements constituting the quaternary nitride layer have a predetermined composition ratio so that the two-dimensional electron gas is formed in the quaternary system. It is preferably formed on top of the nitride layer.
상기 4원계 질화물층은 In, Al, Ga 및 N의 4종류의 원소로 이루어지고, In과 Al은 소정의 조성비를 가짐으로써 상기 4원계 질화물층에 압축응력이 작용하여 상기 4원계 질화물층의 분극은 상부 방향을 향하는 것이 바람직하다. The quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N, and In and Al have a predetermined composition ratio, so that compressive stress acts on the quaternary nitride layer to polarize the quaternary nitride layer. It is preferable that the silver face upwards.
상기 4원계 질화물층은 기판 위에 형성된 질화갈륨 버퍼층 위에 형성되고, 상기 4원계 질화물층 위에 형성된 질화갈륨 캡층을 더 포함하고, 갈륨면이 상부에 형성될 수 있다.The quaternary nitride layer may be formed on the gallium nitride buffer layer formed on the substrate, and further include a gallium nitride cap layer formed on the quaternary nitride layer, and a gallium surface may be formed thereon.
상기 4원계 질화물층은 InωAlψGa1 -ω- ψN (0<x0.5, 0<y0.5) 으로 이루어지는 것이 바람직하다.The quaternary nitride layer is preferably made of a -ω- ψ N (0 <x0.5, 0 <y0.5) In ω Al ψ Ga 1.
상기 In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하인 것이 바람직하다.It is preferable that the composition x of In is 0.1 or more and 0.5 or less, and the composition y of Al is 0.05 or more and 0.2 or less.
상기 4원계 질화물층의 상단에는 2차원 전자가스가 형성되어 HEMT의 bureid channel이 형성될 수 있다. A two-dimensional electron gas may be formed on the top of the quaternary nitride layer to form a bureid channel of the HEMT.
상기 질화갈륨 캡층은 1 nm 내지 30 nm이고, 4원계 질화물층은 1 nm 내지 30 nm인 것이 바람직하다. The gallium nitride cap layer is 1 nm to 30 nm, the quaternary nitride layer is preferably 1 nm to 30 nm.
본 발명의 일 실시예에 의한 4원계 질화물 전력반도체소자의 제조방법은 기판 위에 GaN 버퍼층을 형성하는 버퍼층 형성 단계; 상기 GaN버퍼층 위에 Ga과 N을 포함하는 4종류의 원소로 이루어지는 4원계 질화물층을 갈륨면 에피택셜 성장시키는 4원계 질화물층 형성 단계; 및 상기 4원계 질화물층 위에 GaN 캡층을 성장시키는 캡층 형성 단계; 를 포함한다. 상기 4원계 질화물층 형성 단계에서 상기 4원계 질화물층의 분극을 조절하여, 2차원 전자가스의 형성 위치를 조절할 수 있다.Method of manufacturing a quaternary nitride power semiconductor device according to an embodiment of the present invention comprises the steps of forming a buffer layer GaN buffer layer on a substrate; Forming a quaternary nitride layer epitaxially growing a quaternary nitride layer made of four kinds of elements including Ga and N on the GaN buffer layer; And a cap layer forming step of growing a GaN cap layer on the quaternary nitride layer. It includes. In the step of forming the quaternary nitride layer, the polarization of the quaternary nitride layer may be adjusted to control the formation position of the two-dimensional electron gas.
상기 2차원 전자가스는 상기 4원계 질화물층과 상기 GaN 캡층의 접촉계면에 형성된다.The two-dimensional electron gas is formed on the contact interface between the quaternary nitride layer and the GaN cap layer.
상기 4원계 질화물층은 In, Al, Ga 및 N의 4종류의 원소로 이루어지고, 상기 4원계 질화물층의 분극은 In과 Al의 조성비에 의해 결정될 수 있다.The quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N, and the polarization of the quaternary nitride layer may be determined by the composition ratio of In and Al.
상기 4원계 질화물층은 InωAlψGa1 -ω- ψN (0<x0.5, 0<y0.5) 으로 이루어질 수 있다. In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하인 것이 바람직하다.The quaternary nitride layer may be formed of a -ω- ψ N In ω Al ψ Ga 1 (0 <x0.5, 0 <y0.5). It is preferable that the composition x of In is 0.1 or more and 0.5 or less, and the composition y of Al is 0.05 or more and 0.2 or less.
상기 GaN 캡층 위에 게이트 전극, 소스 전극 및 드레인 전극을 형성하는 단계를 포함하는 것이 바람직하다.It is preferable to include forming a gate electrode, a source electrode and a drain electrode on the GaN cap layer.
상기 4원계 질화물층 형성 단계에서 상기 4원계 질화물층에 압축응력이 인가되고 상기 4원계 질화물층의 분극 방향은 상측을 향하고, 상기 2차원 전자가스는 상기 4원계 질화물층과 상기 GaN 캡층의 접촉계면에 형성되는 것이 바람직하다.In the quaternary nitride layer forming step, a compressive stress is applied to the quaternary nitride layer, and the polarization direction of the quaternary nitride layer faces upward, and the two-dimensional electron gas is a contact interface between the quaternary nitride layer and the GaN cap layer. It is preferably formed in.
상기 4원계 질화물층의 상단에 2차원 전자가스가 형성되어 HEMT의 bureid channel이 형성될 수 있다.A two-dimensional electron gas may be formed on the top of the quaternary nitride layer to form a bureid channel of the HEMT.
상기와 같은 본 발명에 따른 전력반도체 소자 및 그 제조 방법에 의하면, 4원계 질화물 반도체의 분극을 제어하여 2차원 전자가스의 형성 위치를 조절함으로써 질소면 HEMT의 장점인 낮은 게이트 누설 전류 갈륨면 HEMT에서 구현할 수 있다. According to the power semiconductor device and the manufacturing method according to the present invention as described above, by controlling the polarization of the quaternary nitride semiconductor to adjust the formation position of the two-dimensional electron gas in the low gate leakage current gallium surface HEMT which is an advantage of the nitrogen surface HEMT Can be implemented.
또한, 본 발명에 의한 갈륨면 4원계 전력반도체소자는 게이트 리세스 없이도 E-mode(Enhancement mode)로 동작할 수 있다. 기판 측으로 상대적인 Ec의 경사가 높아져 누설 전류가 감소되고, 캐리어 confinement가 개선되는 효과가 있으며, 소스/드레인 전극의 접촉저항이 감소하는 효과가 있다. In addition, the gallium plane quaternary power semiconductor device according to the present invention can operate in an E-mode (Enhancement mode) without the gate recess. The inclination of the relative Ec to the substrate side is increased, the leakage current is reduced, the carrier confinement is improved, and the contact resistance of the source / drain electrodes is reduced.
또한, 갈륨면 HEMT로서 이종접합 계면에서 계면 결정품질이 우수하다.In addition, it is excellent in interfacial crystal quality at the heterojunction interface as a gallium surface HEMT.
본 발명의 일 실시예의 따른 전력반도체 소자는 소자구조 설계 및 제작의 자유도가 증가하는 효과가 있다.Power semiconductor device according to an embodiment of the present invention has the effect of increasing the degree of freedom of device structure design and manufacturing.
도 1은 n-AlGaAs/i-GaAs/Si-GaAs HEMT의 이종접합 구조를 개략적으로 나타낸 도면이다.1 is a view schematically showing a heterojunction structure of n-AlGaAs / i-GaAs / Si-GaAs HEMT.
도 2는 도 1의 HEMT에 상응하는 에너지 밴드 다이어그램이다.FIG. 2 is an energy band diagram corresponding to the HEMT of FIG. 1.
도 3은 종래의 갈륨면(Ga-face) 4원계 질화물 반도체소자의 이종구조(heterostructure)와 이에 대응하는 밴드 갭 다이어그램을 나타낸 도면이다.FIG. 3 is a diagram illustrating a heterostructure of a conventional Ga-face quaternary nitride semiconductor device and a band gap diagram corresponding thereto.
도 4는 본 발명의 일 실시예에 의한 갈륨면 4원계 질화물 반도체소자의 이종구조(heterostructure)의 개략도와 이에 대응하는 밴드 갭 다이어그램이다. 4 is a schematic diagram of a heterostructure of a gallium plane quaternary nitride semiconductor device according to an embodiment of the present invention and a band gap diagram corresponding thereto.
도 5는 4원계 질화물 반도체의 분극 변화에 따른 분극유도전하(σ) 및 2DEG 형성 위치를 개략적으로 도시한 것이다.FIG. 5 schematically illustrates the polarization induction charge σ and the position of 2DEG formation according to the polarization change of the quaternary nitride semiconductor.
도 6은 AlN, AlωGa1 - ωN, GaN, GaωIn1 - ωN, AlωIn1 - ωN, InN의 여러 질화물 반도체의 격자 상수와 에너지 밴드 갭의 상관 관계를 도시한 도면이다.6 is a graph showing the correlation between lattice constants and energy band gaps of various nitride semiconductors of AlN, Al ω Ga 1 - ω N, GaN, Ga ω In 1 - ω N, Al ω In 1 - ω N, InN; to be.
도 7은 InAlGaN의 In과 Al의 조성과 이에 따른 분극 유도전하 밀도(polarization induced charge density)의 관계를 나타낸 그래프이다.7 is a graph showing the relationship between the composition of In and Al of InAlGaN and the polarization induced charge density accordingly.
도 8는 InAlGaN에서 In과 Al의 조성에 따른 격자 상수(lattice constant)의 관계를 나타낸 그래프이다.8 is a graph showing the relationship between lattice constants according to the composition of In and Al in InAlGaN.
도 9는 In과 Al의 조성이 다른 4 샘플에서의 실험값을 나타낸 표이다.9 is a table showing experimental values in four samples having different compositions of In and Al.
도 10은 InωAlψGa1 -ω- ψN/GaN에서 Al(알루미늄)과 In(인듐, Indium)의 조성비에 따른 분극 유도전하밀도의 관계도이다. 10 is a relation diagram of polarization induced charge density according to the composition ratio of Al (aluminum) and In (Indium, Indium) in In ω Al ψ Ga 1 -ω- ψ N / GaN.
도 11은 도 10에 표시된 조성비가 각기 상이한 샘플 1 내지 11에서 strain과 분극 유도전하를 나타낸 표이다.FIG. 11 is a table showing strains and polarization induced charges in samples 1 to 11 having different composition ratios shown in FIG. 10.
도 12(a)내지 12(c)는 도 10, 11의 샘플 1 내지 11에 대한 밴드 갭 다이어그램이다.12 (a) to 12 (c) are band gap diagrams for samples 1 to 11 of FIGS. 10 and 11.
도 13(a)는 종래의 갈륨면 InAlGaN/GaN 기반 전력반도체소자의 기본 구조에서 2DEG 형성 위치를 나타낸 개략도이다.Figure 13 (a) is a schematic diagram showing the position of 2DEG formation in the basic structure of a conventional gallium surface InAlGaN / GaN-based power semiconductor device.
도 13(b)는 본 발명의 일 실시예에 따른 갈륨면 InAlGaN/GaN 기반 전력반도체소자의 개략도이다.Figure 13 (b) is a schematic diagram of a gallium surface InAlGaN / GaN based power semiconductor device according to an embodiment of the present invention.
도 14는 본 발명의 또 다른 일 실시예에 따른 다층 멀티 채널 모놀리식 소자의 제조 방법과 구조를 개략적으로 표시한 도면이다.14 is a view schematically showing a method and a structure of a multilayer multi-channel monolithic device according to another embodiment of the present invention.
이하에서는 본 발명에 대하여 보다 구체적으로 이해할 수 있도록 첨부된 도면을 참조한 바람직한 실시 예를 들어 설명하기로 한다.Hereinafter, a preferred embodiment with reference to the accompanying drawings to be described in more detail with respect to the present invention will be described.
도 3(a), 3(b)는 종래의 갈륨면(Ga-face) 4원계 질화물 반도체소자의 이종구조(heterostructure)와 이에 대응하는 밴드 갭 다이어그램을 나타낸 도면이다.3 (a) and 3 (b) are diagrams showing a heterostructure of a conventional Ga-face quaternary nitride semiconductor device and a band gap diagram corresponding thereto.
도 3(a)를 참조하면, 종래의 갈륨면 4원계 질화물 반도체소자는 기판 상에 제1 GaN(Gallium Nitride)층이 형성되고, 제1 GaN층 상에 InAlGaN(Indium Aluminum Gallium Nitride)층이 갈륨면이 상면에 오도록 애피택셜 성장하고, 그 위에 캡층으로 제2 GaN층이 형성되고 위에 게이트, 드레인, 소스 전극이 형성되어 소자를 형성하게 된다. 제2 GaN층 없이 바로 InAlGaN층 위에 전극을 형성할 수도 있다. Referring to FIG. 3A, in the conventional gallium-based quaternary nitride semiconductor device, a first GaN layer is formed on a substrate and an InAl Aluminum Gallium Nitride (InAlGaN) layer is formed on the first GaN layer. The surface is epitaxially grown so that the second GaN layer is formed as a cap layer, and gate, drain, and source electrodes are formed thereon to form a device. The electrode may be formed directly on the InAlGaN layer without the second GaN layer.
질화물 반도체의 분극(P)은 자발분극(PΤΠ)과 응력에 의한 스트레인분극(strain polarization, PΠΕ)으로 이루어진다. 자발분극은 물질 자체의 특성이지만, 스트레인 분극(PΠΕ)은 질화물 반도체에 작용하는 응력에 의해 스트레인 분극(PΠΕ)의 방향은 결정되고, 자발분극(PΤΠ)과 스트레인 분극(PΠΕ)의 합성에 의해 전체 분극(P)이 결정된다. Polarization of the nitride semiconductor (P) is composed of a spontaneous polarization (P ΤΠ) and strain polarization (strain polarization, P ΠΕ) due to stress. Of the spontaneous polarization is, but properties of the material itself, the strain polarization (P ΠΕ) is the crystal orientation of the strain polarization (P ΠΕ) by the stress acting on the nitride semiconductor, the spontaneous polarization (P ΤΠ) and strain polarization (P ΠΕ) Synthesis determines the total polarization (P).
갈륨면 GaN/InAlGaN/GaN 구조에서 GaN층과 InAlGaN층의 격자 상수의 차이로 인해 GaN층 위에 형성되는 InAlGaN층에 인장응력(tensile)이 작용하고, 이 인장응력에 의한 스트레인 분극이 생긴다. 이 스트레인 분극으로 인해 InAlGaN층의 전체 분극(Polarization)이 결정되며, 이 분극에 의해 도펀트 없이도 접착계면에서 분극유도전하(polarization induced charge)가 생성된다. 이러한 분극유도전하는 InAlGaN층 하부인 제1 GaN(Gallium Nitride)층과의 계면에 2DEG을 형성한다. 도 3(a)에는 이러한 갈륨면 GaN/InAlGaN/GaN 구조에서의 인장력과 분극, 분극유도전하에 의한 2DEG이 개략적으로 도시되어 있다. In the GaN / InAlGaN / GaN structure, the tensile stress acts on the InAlGaN layer formed on the GaN layer due to the difference in lattice constant between the GaN layer and the InAlGaN layer, resulting in strain polarization caused by the tensile stress. This strain polarization determines the total polarization of the InAlGaN layer, which creates polarization induced charges at the adhesion interface without the dopant. This polarization inductive charge forms a 2DEG at the interface with the first GaN (Gallium Nitride) layer under the InAlGaN layer. FIG. 3 (a) schematically shows a 2DEG due to tensile force, polarization, and polarization inductive charge in the gallium plane GaN / InAlGaN / GaN structure.
도 3(b)는 도 3(a)의 갈륨면 GaN/InAlGaN/GaN 구조에서의 에너지 밴드 갭 다이어그램을 도시한 것으로, InAlGaN층의 하부인 제1 GaN(Gallium Nitride)층과의 계면, 즉, 깊이 50 nm에서 양자우물(quantum well)을 확인할 수 있고, 이 위치가 2DEG이 생성되는 위치이다. FIG. 3 (b) shows an energy band gap diagram in the gallium plane GaN / InAlGaN / GaN structure of FIG. 3 (a), and the interface with the first GaN (Gallium Nitride) layer under the InAlGaN layer, that is, FIG. Quantum wells can be identified at a depth of 50 nm, which is where 2DEG is produced.
이러한 종래의 InAlGaN barrier의 경우 InAlGaN 층 하단에 2DEG이 형성되어 D-mode(depletion mode)로 동작하는 것이 일반적이고, 이 경우 질소면 AlGaN/GaN/SiC 기반 HEMT와 달리 게이트 리세스 등과 같은 특별한 처리방법 없이는 E-mode(Enhancement mode)로 동작할 수 없다. In the case of the conventional InAlGaN barrier, a 2DEG is generally formed at the bottom of the InAlGaN layer to operate in a D-mode (depletion mode) .In this case, unlike a nitrogen-based AlGaN / GaN / SiC-based HEMT, a special processing method such as a gate recess is used. You cannot operate in E-mode (Enhancement mode) without it.
본 발명은 질소면 질화물 전력반도체의 계면 결정품질 저하 문제를 해소하기 위해 갈륨면 성장을 유지하면서도 동시에 질소면 질화물 기반 HEMT의 여러 장점들을 가지는 4원계 질화물 전력반도체소자 및 이를 제조하는 방법을 제시하고자 한다.The present invention proposes a quaternary nitride power semiconductor device having a number of advantages of nitrogen-based nitride-based HEMT while maintaining gallium surface growth to solve the problem of deterioration of interfacial crystal quality of nitrogen-based nitride power semiconductors and a method of manufacturing the same. .
도 4(a), 4(b)는 본 발명의 일 실시예에 의한 갈륨면 4원계 질화물 반도체소자의 이종구조(heterostructure)의 개략도와 이에 대응하는 밴드 갭 다이어그램이다. 4 (a) and 4 (b) are schematic diagrams and corresponding band gap diagrams of a heterostructure of a gallium plane quaternary nitride semiconductor device according to an embodiment of the present invention.
도 4(a)를 참조하면, 갈륨면 4원계 질화물 반도체소자는 사파이어, 실리콘 또는 실리콘 카바이드 기판(미도시) 상에 제1 GaN(Gallium Nitride)층이 형성되고, 제1 GaN층 상에 InAlGaN(Indium Aluminum Gallium Nitride)층이 에피택셜 성장하고, 그 위에 제2 GaN층이 형성된다. 여기에서 갈륨면이 상면에 오도록 각 층은 형성된다. InAlGaN에 작용하는 응력을 조절하게 되면 분극(total polarization) 방향을 역전시킬 수 있고, 2차 전자가스(2DEG)가 형성되는 위치를 변경하여 갈륨면의 HEMT 구조와 다르게 buried channel 구조가 가능한 소자를 구현할 수 있다. Referring to FIG. 4A, in the gallium-based quaternary nitride semiconductor device, a first GaN layer is formed on a sapphire, silicon, or silicon carbide substrate, and InAlGaN is formed on the first GaN layer. An Indium Aluminum Gallium Nitride) layer is epitaxially grown, and a second GaN layer is formed thereon. Here, each layer is formed so that the gallium surface is on the upper surface. By controlling the stress acting on InAlGaN, the direction of total polarization can be reversed and the position where secondary electron gas (2DEG) is formed can be changed to realize a device that can be buried channel structure unlike HEMT structure of gallium. Can be.
도 4(a)에 의하면, 갈륨면 GaN/InAlGaN/GaN 구조에서 InAlGaN에 인장응력(tensile strain)이 아닌 압축응력(compressive strain)이 생기는 경우(응력의 조절에 관해서는 후술함), 이 압축응력에 의해 nAlGaN층 상부인 제2 GaN(Gallium Nitride)층을 향하는 스트레인 분극(PΠΕ)이 생기고, 이 분극에 의해 InAlGaN층 상부인 제2 GaN(Gallium Nitride)층과의 계면에 2DEG이 형성된다. 도 4(a)에는 이러한 갈륨면 GaN/InAlGaN/GaN 구조에서의 압축응력과 분극, 분극유도전하에 의한 2DEG이 개략적으로 도시되어 있다.According to Fig. 4 (a), when compressive stresses other than tensile strains are generated in InAlGaN in the gallium plane GaN / InAlGaN / GaN structure (to be described later, the compressive stress is controlled). As a result, strain polarization (P ? ) Is directed toward the second GaN (Gallium Nitride) layer over the nAlGaN layer, and 2DEG is formed at the interface with the second GaN (Gallium Nitride) layer over the InAlGaN layer. FIG. 4 (a) schematically shows the 2DEG due to the compressive stress, polarization, and polarization induction charge in the gallium plane GaN / InAlGaN / GaN structure.
즉, 갈륨면 InAlGaN의 분극을 제어하여 질소면 HEMT에서 가능하던 buried channel을 갈륨면 HEMT에서 형성함으로써, 결정품질의 저하 없이 질소면 HEMT의 여러 가지 장점을 가지는 소자를 구현할 수 있다.That is, by controlling the polarization of the gallium plane InAlGaN to form a buried channel in the gallium plane HEMT that was possible in the nitrogen plane HEMT, it is possible to implement a device having various advantages of the nitrogen plane HEMT without deterioration of crystal quality.
도 4(b)는 도 4(a)의 구조에 상응하는 에너지 밴드 갭 다이어그램을 도시한 것으로, InAlGaN층의 상부인 제2 GaN(Gallium Nitride)층과의 계면, 즉, 표면에 가까운 75 nm에서 양자우물(quantum well)을 확인할 수 있고, 이 위치가 2DEG이 생성되는 위치이다. FIG. 4 (b) shows an energy band gap diagram corresponding to the structure of FIG. 4 (a), at an interface with a second GaN (Gallium Nitride) layer on top of the InAlGaN layer, ie, at 75 nm close to the surface. You can identify the quantum well, and this is where 2DEG is generated.
도 5(a) 내지 5(d)는 4원계 질화물 반도체의 분극이 변화함에 따라 2DEG 형성 위치가 달라지는 것을 자발분극(PΤΠ), 응력에 의한 분극(PΠΕ), 전체분극(P), 분극유도전하(σ)를 이용하여 개략적으로 도시한 것이다. 5 (a) to 5 (d) show that the position of 2DEG formation changes as the polarization of the quaternary nitride semiconductor changes, spontaneous polarization (P ΤΠ ), polarization due to stress (P ΠΕ ), total polarization (P), and polarization It is shown schematically using the induced charge (σ).
도 5(a)는 InAlGaN 층에 인장응력이 생기는 경우로서, 이때 InAlGaN과 그 하부의 GaN층의 계면에 2DEG 이 형성되고, 이 때, 계면에 유도되는 전하 밀도 (x, y)는 다음 식(1)과 같다. FIG. 5 (a) illustrates a case where tensile stress is generated in an InAlGaN layer, wherein 2DEG is formed at an interface between InAlGaN and a GaN layer below it, and the charge density (x, y) induced at the interface is represented by the following equation ( Same as 1).
식(1)Formula (1)
Figure PCTKR2015012205-appb-I000001
Figure PCTKR2015012205-appb-I000001
도 5(b)는 InAlGaN 층에 상대적으로 작은 압축응력이 생기는 경우로서, 이때 InAlGaN과 그 하부의 GaN층의 계면에 2DEG 이 형성되지만, 계면에 유도되는 전하 밀도 (x, y)는 도 5(a)에서 보다 감소하게 된다. 이 때, 분극유도전하밀도 (x, y)는 식 (2)와 같이 구해진다. FIG. 5 (b) shows a case where a relatively small compressive stress occurs in the InAlGaN layer, wherein 2DEG is formed at the interface between InAlGaN and the GaN layer below it, but the charge density (x, y) induced at the interface is shown in FIG. decrease in a). At this time, the polarization inductive charge density (x, y) is obtained as in the formula (2).
식 (2)Formula (2)
Figure PCTKR2015012205-appb-I000002
Figure PCTKR2015012205-appb-I000002
도 5(c)는 InAlGaN 층에 생기는 압축응력의 의한 분극과 자발분극의 합성 분극이 GaN 층의 분극과 동일한 경우로서, 이 경우에는 이종접합계면에 유도되는 전하 밀도 (x, y)가 0이 된다. 즉, 분극유도전하밀도 (x, y)는 식(3)FIG. 5 (c) shows the case where the synthetic polarization of the compressive stress and the spontaneous polarization generated in the InAlGaN layer is the same as the polarization of the GaN layer. In this case, the charge density (x, y) induced at the heterojunction interface is 0 do. That is, the polarization inductive charge density (x, y) is represented by equation (3)
Figure PCTKR2015012205-appb-I000003
Figure PCTKR2015012205-appb-I000003
과 같다.Same as
도 5(d)는 압축응력이 증가하여 InAlGaN의 분극이 역전되는 것으로, InAlGaN과 그 상부의 GaN층의 계면에 2DEG 이 형성된다. 계면에 유도되는 분극유도전하밀도 (x, y)는 식 (4)와 같이 구해진다.5 (d) shows that the compressive stress is increased to reverse polarization of InAlGaN, and 2DEG is formed at the interface between InAlGaN and the GaN layer thereon. The polarization inductive charge density (x, y) induced at the interface is obtained as in Equation (4).
식(4)Formula (4)
Figure PCTKR2015012205-appb-I000004
Figure PCTKR2015012205-appb-I000004
이러한 분극 역전은 InAlGaN의 응력이 인장응력이 아닌 압축응력이 되도록 조절함으로써 가능하고, 응력의 조절은 4원계 질화물 반도체 InAlGaN의 In(Indium)과 Al(Aluminum)의 조성비를 조절함으로써 가능하다. Such polarization reversal is possible by controlling the stress of InAlGaN to be a compressive stress rather than a tensile stress, and the stress can be controlled by adjusting the composition ratio of In (Indium) and Al (Aluminum) of the quaternary nitride semiconductor InAlGaN.
이하, 도 6 내지 8을 참조하여 본 발명의 일 실시예에 따른 4원계 질화물 전력반도체소자의 조성비에 따른 응력 변화와 분극유도전하, 격자 상수의 관계 등을 설명한다. Hereinafter, the relationship between stress variation, polarization inductive charge, and lattice constant according to the composition ratio of the quaternary nitride power semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 6 to 8.
도 6은 AlN, AlωGa1 - ωN, GaN, GaωIn1 - ωN, AlωIn1 - ωN, InN의 여러 질화물 반도체의 격자 상수와 에너지 밴드 갭의 상관 관계를 도시한 도면이다.6 is a graph showing the correlation between lattice constants and energy band gaps of various nitride semiconductors of AlN, Al ω Ga 1 - ω N, GaN, Ga ω In 1 - ω N, Al ω In 1 - ω N, InN; to be.
도 7은 InAlGaN에서 In과 Al의 조성이 각기 x, y 일 때, 이 조성에 따른 분극 유도전하 밀도(polarization induced charge density)를 z축에 나타낸 그래프이다. 도 7에서 붉은 색 평면은 분극유도전하 밀도가 0인 평면이고, 녹색 평면은 InAlGaN에서 In과 Al의 조성에 따른 분극 유도전하 밀도를 나타낸 것이다. 녹색 평면이 붉은 색 평면과 만나는 직선상에서 분극유도전하밀도는 0이 되고, 이 직선을 기준으로 분극 유도 전하, 즉 2DEG이 형성되는 위치가 역전된다. 이 그래프에 의하면, In과 Al의 조성비를 조절함으로써, 2DEG이 형성되는 위치를 조절할 수 있음을 알 수 있다.FIG. 7 is a graph showing polarization induced charge density according to the composition on the z-axis when In and Al are x and y in InAlGaN, respectively. In FIG. 7, the red plane is a plane having a zero polarization inductive charge density, and the green plane is a polarization induced charge density according to the composition of In and Al in InAlGaN. On the straight line where the green plane meets the red plane, the polarization inductive charge density becomes zero, and the position where the polarization induced charge, that is, the 2DEG is formed, is reversed based on this straight line. According to this graph, it can be seen that the position at which 2DEG is formed can be controlled by adjusting the composition ratio of In and Al.
도 8는 InAlGaN에서 In과 Al의 조성에 따른 격자 상수(lattice constant)의 관계를 나타낸 그래프이다. 도 8에서 녹색 평면은 InAlGaN의 In과 Al의 조성이 각기 x, y 일 때, InAlGaN의 격자 상수를 z축 상의 상수 값에 대응시킨 것이고, 붉은 평면은 GaN의 격자 상수를 나타낸 것이다. 녹색 평면이 붉은 평면과 만나는 직선은 InAlGaN의 격자 상수가 GaN의 격자 상수와 일치하는 경우이다. 8 is a graph showing the relationship between lattice constants according to the composition of In and Al in InAlGaN. In FIG. 8, the green plane corresponds to the lattice constant of InAlGaN corresponding to the constant value on the z-axis when the composition of In and Al of InAlGaN is x and y, respectively, and the red plane represents the lattice constant of GaN. The straight line where the green plane meets the red plane is when the lattice constant of InAlGaN coincides with the lattice constant of GaN.
위 도 6 내지 8의 시뮬레이션 그래프들은 이론적으로 예측한 바와 같은 결과를 보여주고 있는데, GaN/InAlGaN/GaN 구조에서 In과 Al의 조성 비에 따라 InAlGaN의 격자 상수가 변화하고, 이는 곧 InAlGaN 층과 GaN층 사이의 응력의 변화를 유도한다. 이에 따라 InAlGaN 분극이 변화하여 분극방향이 역전될 수 있고, 2DEG이 형성되는 위치가 역전된다. 즉, InAlGaN에서 분극유도전하의 양과 위치는 In과 Al의 조성 비의 함수가 된다. The simulation graphs of FIGS. 6 to 8 above show the results as predicted theoretically. In the GaN / InAlGaN / GaN structure, the lattice constant of InAlGaN changes according to the composition ratio of In and Al, which is an InAlGaN layer and GaN. Induce a change in stress between layers. As a result, the InAlGaN polarization is changed to reverse the polarization direction, and the position at which the 2DEG is formed is reversed. That is, the amount and position of the polarization inductive charge in InAlGaN is a function of the composition ratio of In and Al.
한편, 도 9는 In과 Al의 조성이 다른 4가지 GaN/InAlGaN/GaN 소체소자에서의 Peak angle separation, 밴드 갭 에너지, electron mobility, sheet concentration의 실험값을 나타낸 표이다. Peak angle separation는 응력과 관련되고, 접합계면에서의 electron mobility, sheet concentration 값으로부터 2DEG이 형성된 것을 확인할 수 있다. 9 is a table showing experimental values of peak angle separation, band gap energy, electron mobility, and sheet concentration in four GaN / InAlGaN / GaN element devices having different compositions of In and Al. Peak angle separation is related to stress, and it can be seen that 2DEG is formed from the value of electron mobility and sheet concentration at the interface.
도 10은 InωAlψGa1 -ω- ψN/GaN에서 Al(알루미늄)과 In(인듐, Indium)의 조성비에 따른 분극 유도전하밀도를 나타낸 것이고, 도 11은 도 10에 표시된 조성비가 각기 상이한 샘플 1 내지 11에서 strain과 분극 유도전하를 나타낸 표이다. 이 표에서 분극 유도전하 밀도가 양의 값인 경우 분극 역전이 일어난다.FIG. 10 shows polarization induced charge densities according to the composition ratios of Al (aluminum) and In (Indium, Indium) in In ω Al ψ Ga 1 -ω- ψ N / GaN, and FIG. 11 shows the composition ratios shown in FIG. Tables showing strain and polarization induced charges in different samples 1-11. In this table, polarization reversal occurs when the polarization induced charge density is positive.
도 12는 도 10, 11의 샘플 1 내지 11에 대한 밴드 갭 다이어그램을 나타낸 것으로서, 샘플 1에서 샘플 11까지 Al(알루미늄)과 In(인듐, Indium)의 조성비를 변화시켰을 때, 특히 샘플 9, 10, 11 등에서 2DEG이 InAlGaN층의 상부 계면에 형성되는 것을 확인할 수 있다. FIG. 12 is a band gap diagram of samples 1 to 11 of FIGS. 10 and 11, and when the composition ratios of Al (aluminum) and In (indium) are changed from sample 1 to sample 11, in particular, samples 9 and 10 , 11 and the like, it can be seen that 2DEG is formed at the upper interface of the InAlGaN layer.
4원계 질화물층은 InωAlψGa1 -ω- ψN (0<x0.5, 0<y0.5)으로 이루어지고, In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하인 경우 2DEG이 InAlGaN층의 상부 계면에 형성될 수 있다. 상기 수치는 본 발명의 일 실시예에 불과하고, In과 Al의 조성비를 조절함으로써 InAlGaN에서 2DEG이 생기는 위치를 상면으로 조절할 수 있는 다른 조성비를 얻을 수도 있을 것이다. 이와 같이 4원계 질화물 반도체의 조성비를 제어함으로써 분극 제어를 통해 2DEG 형성 위치를 조절할 수 있다.Quaternary nitride layer is made of In ω Al ψ Ga 1 -ω- ψ N (0 <x0.5, 0 <y0.5), and the composition x is 0.1 or more 0.5 or less of In, Al composition y of from 0.05 If more than 0.2, 2DEG may be formed on the upper interface of the InAlGaN layer. The numerical value is only one embodiment of the present invention, and by adjusting the composition ratio of In and Al, another composition ratio that can control the position where 2DEG is generated in InAlGaN to the upper surface may be obtained. As such, by controlling the composition ratio of the quaternary nitride semiconductor, the position of 2DEG formation can be adjusted through polarization control.
도 13(a), 13(b)에는 4원계 InAlGaN 질화물 전력반도체 소자의 2DEG 형성 위치에 따른 반도체 소자의 구조가 도시되어 있다.13 (a) and 13 (b) show the structure of the semiconductor device according to the 2DEG formation position of the quaternary InAlGaN nitride power semiconductor device.
도 13(a)는 종래의 갈륨면 InAlGaN/GaN 기반 전력반도체소자의 기본 구조로서, 2DEG이 InAlGaN의 하면에 형성된다. 반면에 도 13(b)에 도시된 본 발명의 일 실시예에 의한 갈륨면 GaN/InAlGaN/GaN 기반 전력반도체소자는 2DEG이 InAlGaN층(30)의 상면에 형성되고, 종래의 질소면 소자에서만 가능하던 HEMT의 buried channel 구조가 가능해진다. 즉, InAlGaN 상면에서 channel이 형성이 되고 기판 방향으로의 전자 움직임을 blocking을 해 줄 수 있어 기판쪽으로 누설전류가 감소하고, 캐리어 confinement가 개선되는 효과가 있다.FIG. 13 (a) shows a basic structure of a conventional gallium plane InAlGaN / GaN based power semiconductor device, wherein 2DEG is formed on the bottom surface of InAlGaN. On the other hand, in the gallium surface GaN / InAlGaN / GaN based power semiconductor device according to the embodiment of the present invention shown in FIG. However, the HEMT buried channel structure is possible. In other words, a channel is formed on the upper surface of InAlGaN, which can block electron movement toward the substrate, thereby reducing leakage current toward the substrate and improving carrier confinement.
또한 D-mode(depletion mode)로 동작하는 종래의 갈륨면 InAlGaN/GaN 전력반도체소자와 달리 본 발명의 갈륨면 GaN/InAlGaN/GaN 기반 전력반도체소자는 E-mode(Enhancement mode) 동작을 용이하게 만들 수 있고, 소스/드레인 전극의 접촉저항이 감소하는 효과가 있다. In addition, unlike conventional gallium plane InAlGaN / GaN power semiconductor devices operating in a D-mode (depletion mode), the gallium plane GaN / InAlGaN / GaN-based power semiconductor devices of the present invention make E-mode (Enhancement mode) operation easier. And the contact resistance of the source / drain electrodes is reduced.
본 발명의 일 실시예에 의한 전력반도체소자 제조방법을 설명하면, 기판 위에 GaN 버퍼층을 형성하는 버퍼층 형성 단계; 상기 GaN 버퍼층 위에 Ga과 N을 포함하는 4종류의 원소로 이루어지는 4원계 질화물층을 갈륨면 에피택셜 성장시키는 4원계 질화물층 형성 단계; 및 상기 4원계 질화물층 위에 GaN 캡층을 성장시키는 캡층 형성 단계를 거친다.Referring to the power semiconductor device manufacturing method according to an embodiment of the present invention, a buffer layer forming step of forming a GaN buffer layer on a substrate; Forming a quaternary nitride layer epitaxially growing a quaternary nitride layer including four kinds of elements including Ga and N on the GaN buffer layer; And a cap layer forming step of growing a GaN cap layer on the quaternary nitride layer.
이 때, 상기 기판은 사파이어, 실리콘, 실리콘 카바이드 기판인 것이 바람직하고, 질화물층은 모두 갈륨면으로 성장하며, 4원계 질화물층은 In, Al, Ga, N을 포함한다. 상기 GaN 버퍼층 위에 4원계 질화물층을 에피택셜 성장시킬 때 In과 Al의 조성비를 소정의 비, 예를 들어 In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하로 할 수 있다. 이 때 GaN 버퍼층과 4원계 질화물층의 격자 상수의 차이로 인하여 4원계 질화물층에는 압축응력이 작용하면서 에피택셜 성장하게 되고 이로 인하여 분극이 역전된다. In this case, the substrate is preferably a sapphire, silicon, silicon carbide substrate, the nitride layer is all grown to the gallium plane, the quaternary nitride layer includes In, Al, Ga, N. When epitaxially growing a quaternary nitride layer on the GaN buffer layer, the composition ratio of In and Al may be a predetermined ratio, for example, composition x of 0.1 or more and 0.5 or less, and composition y of Al may be 0.05 or more and 0.2 or less. have. At this time, due to the difference in the lattice constant between the GaN buffer layer and the quaternary nitride layer, the quaternary nitride layer epitaxially grows while the compressive stress is applied, thereby inverting the polarization.
상기 조성비에 반드시 한정되는 것은 아니고, 최적의 조성비를 적절히 선택함으로써 4원계 질화물층의 분극의 방향을 제어할 수 있으며, 이에 의해 2DEG의 형성 위치를 제어하여 4원계 질화물의 상부에 위치하게 할 수 있다. 4원계 질화물층은 1 nm 내지 30 nm 정도로 형성되는 것이 바람직하지만 반드시 이에 한정되는 것은 아니다. 한편, 질화갈륨 캡층도 1 nm 내지 30 nm로 형성하는 것이 바람직하나 이에 한정되는 것은 아니다.It is not necessarily limited to the composition ratio, and by appropriately selecting the optimum composition ratio, the direction of polarization of the quaternary nitride layer can be controlled, whereby the formation position of the 2DEG can be controlled to be located above the quaternary nitride. . The quaternary nitride layer is preferably formed at about 1 nm to 30 nm, but is not necessarily limited thereto. On the other hand, the gallium nitride cap layer is preferably formed to 1 nm to 30 nm, but is not limited thereto.
이하에서는 본 발명의 또 다른 실시예를 도 14를 참고하여 설명한다. 본 발명의 또 다른 실시예에 의하면, 다층의 멀티 모드 질화물 반도체소자를 구현할 수 있다. Hereinafter, another embodiment of the present invention will be described with reference to FIG. 14. According to another embodiment of the present invention, a multilayer multi-mode nitride semiconductor device can be implemented.
기판 위에 제1 GaN층, 제1 InAlGaN층(InAlGaN-2), 배리어층, 제2 GaN층, 제2 InAlGaN층(InAlGaN-1), 제3 GaN층을 순차로 갈륨면으로 에피택셜 성장시켜 형성시킨다. 이 때, 제1 InAlGaN층(InAlGaN-2)과 제2 InAlGaN층(InAlGaN-1)의 분극 방향을 각기 달리하도록 In과 Al의 조성비를 다르게 조절하여 성장시킬 수 있다. 즉, 제1 InAlGaN층(InAlGaN-2)과 제2 InAlGaN층(InAlGaN-1)의 In과 Al의 조성비를 조절하여 제1 InAlGaN층(InAlGaN-2)과 제2 InAlGaN층(InAlGaN-1)의 2DEG이 각기 하면과 상면에 형성되도록 할 수 있다. 도 14에는 제1 InAlGaN층(InAlGaN-2)의 하부 계면과 제2 InAlGaN층(InAlGaN-1)의 상부 계면에 2DEG이 각기 형성되도록 하였으나, 반대로 형성되도록 할 수도 있다. 또한, 추가로 제3, 제4 InAlGaN층을 동일한 방식으로 형성할 수도 있다. A first GaN layer, a first InAlGaN layer (InAlGaN-2), a barrier layer, a second GaN layer, a second InAlGaN layer (InAlGaN-1), and a third GaN layer are sequentially epitaxially grown on a gallium surface on a substrate. Let's do it. In this case, the composition ratio of In and Al may be adjusted to be different so that the polarization directions of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN layer (InAlGaN-1) are different from each other. That is, the composition ratio of In and Al of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN-1 layer (InAlGaN-1) is controlled to adjust the composition ratio of the first InAlGaN layer (InAlGaN-2) and the second InAlGaN layer (InAlGaN-1). 2DEG can be formed on the lower and upper surfaces respectively. In FIG. 14, 2DEGs are formed at the lower interface of the first InAlGaN layer (InAlGaN-2) and the upper interface of the second InAlGaN layer (InAlGaN-1), respectively. In addition, the third and fourth InAlGaN layers may be formed in the same manner.
이후, 제3 GaN층 위에 게이트, 드레인 및 소스 전극을 형성하여 채널1(H1)을 형성하고, 채널 1을 형성된 영역을 제외하고, 적층 형성된 질화물 반도체의 일부 영역을 배리어층까지 식각한 후 아이솔레이션(isolation)을 형성하고, 제1 InAlGaN층(InAlGaN-2) 위에 게이트, 드레인 및 소스 전극을 형성한다. 이와 같은 방법에 의해 식각된 상기 일부 영역에 채널 2(H2)를 형성할 수 있다.Subsequently, the gate, drain, and source electrodes are formed on the third GaN layer to form channel 1 (H1), and some regions of the stacked nitride semiconductors are etched to the barrier layer except for the region where channel 1 is formed. isolation) and a gate, a drain, and a source electrode are formed on the first InAlGaN layer (InAlGaN-2). Channel 2 (H2) may be formed in the partial region etched by the above method.
상기 채널 1은 2DEG이 제2 InAlGaN층(InAlGaN-1)의 상부 계면에 형성된 것으로 E-mode로 작동하고, 상기 채널 2는 제1 InAlGaN층(InAlGaN-2)의 하부 계면에 형성된 것으로 D-mode로 작동할 수 있으므로, 하나의 소자에 서로 다른 모드로 작동하는 모놀리식(monolithic) HEMT가 구현된다. 이 멀티모드 다층 질화물 반도체소자는 단일 소자 내에서 다른 모드로 동작하는 채널들을 층을 달리하여 다수 개로 구현할 수 있으므로, 채널들 간의 신호 간섭에 의한 노이즈나 오작동이 없으면서도 소자 설계 자유도가 향상되는 우수한 효과가 있다. The channel 1 is formed in the upper interface of the second InAlGaN layer (InAlGaN-1) 2DEG is operated in the E-mode, the channel 2 is formed in the lower interface of the first InAlGaN layer (InAlGaN-2) D-mode As a result, monolithic HEMTs are implemented in one device that operates in different modes. This multi-mode multilayer nitride semiconductor device can implement a plurality of channels operating in different modes in a single device in different layers, thereby improving the design freedom of the device without noise or malfunction caused by signal interference between the channels. There is.

Claims (17)

  1. 4원계 질화물층을 포함하는 전력반도체소자에 있어서,In the power semiconductor device comprising a quaternary nitride layer,
    상기 4원계 질화물층은 분극 방향이 상기 4원계 질화물층의 상면을 향하도록 형성됨으로써 2차원 전자가스가 상기 4원계 질화물층의 상단에 형성되는 전력반도체소자.The quaternary nitride layer has a polarization direction toward the upper surface of the quaternary nitride layer, so that a two-dimensional electron gas is formed on top of the quaternary nitride layer.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 4원계 질화물층은 갈륨면이 상부면에 형성되도록 성장된 갈륨면 4원계 질화물층이고, 상기 4원계 질화물층을 이루는 4 종류의 원소들은 소정의 조성비를 가짐으로써 2차원 전자가스가 상기 4원계 질화물층의 상단에 형성되는 전력반도체소자.The quaternary nitride layer is a gallium surface quaternary nitride layer grown so that a gallium surface is formed on the upper surface, and the four kinds of elements constituting the quaternary nitride layer have a predetermined composition ratio so that the two-dimensional electron gas is formed in the quaternary system. Power semiconductor device formed on top of the nitride layer.
  3. 청구항 1 또는 청구항 2에 있어서, The method according to claim 1 or 2,
    상기 4원계 질화물층은 In, Al, Ga 및 N의 4종류의 원소로 이루어지고, The quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N,
    In과 Al은 소정의 조성비를 가짐으로써 상기 4원계 질화물층에 압축응력이 작용하여 상기 4원계 질화물층의 분극은 상부 방향을 향하는 전력 반도체소자.In and Al have a predetermined composition ratio so that compressive stress acts on the quaternary nitride layer so that the polarization of the quaternary nitride layer is directed upward.
  4. 청구항 3에 있어서, The method according to claim 3,
    상기 4원계 질화물층은 기판 위에 형성된 질화갈륨 버퍼층 위에 형성되고, 상기 4원계 질화물층 위에 형성된 질화갈륨 캡층을 더 포함하고, 갈륨면이 상부에 형성되는 전력반도체 소자.The quaternary nitride layer is formed on the gallium nitride buffer layer formed on the substrate, further comprising a gallium nitride cap layer formed on the quaternary nitride layer, the gallium surface is formed on the power semiconductor device.
  5. 청구항 3에 있어서,The method according to claim 3,
    상기 4원계 질화물층은 InωAlψGa1 -ω- ψN (0<x0.5, 0<y0.5)으로 이루어지는 전력반도체 소자.The quaternary nitride layer is composed of a power semiconductor device -ω- ψ N (0 <x0.5, 0 <y0.5) In ω Al ψ Ga 1.
  6. 청구항 5에 있어서, The method according to claim 5,
    In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하인 전력반도체 소자.A power semiconductor device in which the composition x of In is 0.1 or more and 0.5 or less, and the composition y of Al is 0.05 or more and 0.2 or less.
  7. 청구항 1에 있어서, The method according to claim 1,
    상기 4원계 질화물층의 상단에 2차원 전자가스가 형성되어 HEMT의 bureid channel이 형성되는 전력반도체 소자. 2D electron gas is formed on the top of the quaternary nitride layer to form a bureid channel of the HEMT.
  8. 청구항 4에 있어서,The method according to claim 4,
    상기 질화갈륨 캡층은 1 nm 내지 30 nm인 전력반도체 소자.The gallium nitride cap layer is a power semiconductor device of 1 nm to 30 nm.
  9. 청구항 4에 있어서,The method according to claim 4,
    상기 4원계 질화물층은 1 nm 내지 30 nm인 전력반도체 소자.The quaternary nitride layer is a power semiconductor device of 1 nm to 30 nm.
  10. 기판 위에 GaN 버퍼층을 형성하는 버퍼층 형성 단계;A buffer layer forming step of forming a GaN buffer layer on the substrate;
    상기 GaN버퍼층 위에 Ga과 N을 포함하는 4종류의 원소로 이루어지는 4원계 질화물층을 갈륨면 에피택셜 성장시키는 4원계 질화물층 형성 단계; 및Forming a quaternary nitride layer epitaxially growing a quaternary nitride layer made of four kinds of elements including Ga and N on the GaN buffer layer; And
    상기 4원계 질화물층 위에 GaN 캡층을 성장시키는 캡층 형성 단계; 를 포함하고,A cap layer forming step of growing a GaN cap layer on the quaternary nitride layer; Including,
    상기 4원계 질화물층 형성 단계에서 상기 4원계 질화물층의 분극을 조절하여, 2차원 전자가스의 형성 위치를 조절하는 전력반도체소자 제조 방법.And controlling the polarization of the quaternary nitride layer in the quaternary nitride layer forming step, thereby controlling the formation position of the two-dimensional electron gas.
  11. 청구항 10에 있어서, The method according to claim 10,
    상기 2차원 전자가스의 형성 위치는 상기 4원계 질화물층과 상기 GaN 캡층의 접촉계면인 전력반도체소자 제조 방법.And the formation position of the two-dimensional electron gas is a contact interface between the quaternary nitride layer and the GaN cap layer.
  12. 청구항 10 또는 청구항 11에 있어서,The method according to claim 10 or 11,
    상기 4원계 질화물층은 In, Al, Ga 및 N의 4종류의 원소로 이루어지고, 상기 4원계 질화물층의 분극은 In과 Al의 조성비에 의해 결정되는 전력반도체소자 제조 방법.The quaternary nitride layer is composed of four kinds of elements of In, Al, Ga, and N, and the polarization of the quaternary nitride layer is determined by the composition ratio of In and Al.
  13. 청구항 12에 있어서,The method according to claim 12,
    상기 4원계 질화물층은 InωAlψGa1 -ω- ψN (0<x0.5, 0<y0.5)으로 이루어지는 전력반도체 소자.The quaternary nitride layer is composed of a power semiconductor device -ω- ψ N (0 <x0.5, 0 <y0.5) In ω Al ψ Ga 1.
  14. 청구항 13에 있어서, The method according to claim 13,
    In의 조성 x는 0.1 이상 0.5 이하이고, Al의 조성 y는 0.05 이상 0.2 이하인 전력반도체 소자 제조 방법.The composition x of In is 0.1 or more and 0.5 or less, and the composition y of Al is 0.05 or more and 0.2 or less.
  15. 청구항 10에 있어서, The method according to claim 10,
    상기 GaN 캡층 위에 게이트 전극, 소스 전극 및 드레인 전극을 형성하는 단계를 포함하는 전력반도체 소자 제조 방법.And forming a gate electrode, a source electrode, and a drain electrode on the GaN cap layer.
  16. 청구항 10에 있어서,The method according to claim 10,
    상기 4원계 질화물층 형성 단계에서 상기 4원계 질화물층에 압축응력이 인가되고 상기 4원계 질화물층의 분극 방향은 상측을 향하고, 상기 2차원 전자가스는 상기 4원계 질화물층과 상기 GaN 캡층의 접촉계면에 형성되는 전력반도체소자 제조 방법.In the quaternary nitride layer forming step, a compressive stress is applied to the quaternary nitride layer, and the polarization direction of the quaternary nitride layer faces upward, and the two-dimensional electron gas is a contact interface between the quaternary nitride layer and the GaN cap layer. The power semiconductor device manufacturing method formed on.
  17. 청구항 10에 있어서,The method according to claim 10,
    상기 4원계 질화물층의 상단에 2차원 전자가스가 형성되어 HEMT의 bureid channel이 형성되는 전력반도체소자 제조 방법.And a two-dimensional electron gas formed on top of the quaternary nitride layer to form a bureid channel of the HEMT.
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