WO2016082800A1 - 一种内存管理方法、装置以及内存控制器 - Google Patents

一种内存管理方法、装置以及内存控制器 Download PDF

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Publication number
WO2016082800A1
WO2016082800A1 PCT/CN2015/095886 CN2015095886W WO2016082800A1 WO 2016082800 A1 WO2016082800 A1 WO 2016082800A1 CN 2015095886 W CN2015095886 W CN 2015095886W WO 2016082800 A1 WO2016082800 A1 WO 2016082800A1
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Prior art keywords
sub
row
memory
activation instruction
access request
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PCT/CN2015/095886
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English (en)
French (fr)
Inventor
肖世海
杨伟
赵俊峰
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP15862610.1A priority Critical patent/EP3217406B1/en
Priority to JP2017528499A priority patent/JP6395937B2/ja
Priority to KR1020177017450A priority patent/KR101992729B1/ko
Publication of WO2016082800A1 publication Critical patent/WO2016082800A1/zh
Priority to US15/607,360 priority patent/US10127955B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present invention relates to the field of computers, and in particular, to a method and apparatus for activating a memory.
  • the memory has a row and column structure, and the cell formed by the intersection of any row and any column is a storage unit. Therefore, any one of the storage units corresponds to a row number and a Column number, when accessing a storage unit in a row, first activate the entire row. To access a storage unit numbered "00" (that is, in row 0 and column 0), first activate 9 storages in row 0. The power consumption of the unit is more than 85% of the memory power consumption. Therefore, the power consumption of the current data center is large.
  • a method of fine-grained access to the memory is proposed.
  • the main idea of the solution is: only need to activate the storage unit to be accessed each time it is activated, and do not need to be in the same row.
  • the storage unit is activated.
  • the memory receives a row activation instruction, the row is not activated immediately.
  • the column activation instruction is received, the row address in the row activation instruction and the column address in the column activation instruction are determined to be activated.
  • the storage unit is then activated by the storage unit, thus reducing power consumption in the data center.
  • the embodiment of the invention provides a method and a device for activating a memory, which are used to solve the defect that the method for activating the memory existing in the prior art is low in efficiency.
  • a method of activating memory comprising:
  • Finding a second memory access request from the memory to-be-scheduled queue where the memory to-be-scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second sub-row of the memory, the first The child row and the second child row are in the same row of the memory;
  • the method further includes:
  • the sub-row selection vector is used to identify that the sub-row to be activated is the first sub-row and the second sub-row.
  • a method of activating memory including:
  • the first activation instruction is used to indicate activation of a first sub-line in the memory and a second sub-line in the memory, the first sub-line and the second sub-line Are all in the same row in the memory;
  • the first sub-row and the second sub-row in the memory are activated according to the first activation instruction.
  • the method before the first sub-line and the second sub-line in the memory are activated according to the first activation instruction, the method further includes:
  • the first sub-row and the second sub-row in the memory are activated according to the sub-row selection vector in the first activation instruction.
  • a memory controller including:
  • a requesting distribution module configured to acquire a first memory access request, where the first memory access request is used to request access to a first sub-line of the memory
  • a memory scheduler configured to search for a second memory access request from a memory to-be-scheduled queue, where the memory to-be-scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second sub-memory Row, the first subrow and the second subrow are in the same row of the memory;
  • the memory scheduler is further configured to merge the first memory access request and the second memory access request to generate a first activation instruction, where the first activation instruction is used to indicate activation of the a first sub-row and the second sub-row;
  • the command scheduler is configured to send the first activation instruction to the memory.
  • the method further includes:
  • the sub-row selection vector is used to identify that the sub-row to be activated is the first sub-row and the second sub-row.
  • a memory module including:
  • a latch configured to receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate activation of a first sub-line in the memory and a second sub-line in the memory, the first sub-line
  • the second sub-rows are all in the same row in the memory
  • a subrow selection decoder for activating the first subrow and the second subrow in the memory in accordance with the first activation instruction retrieved from the latch.
  • the latch is further configured to:
  • the sub-row selection decoder is specifically configured to:
  • the first sub-row and the second sub-row in the memory are activated according to the sub-row selection vector in the first activation instruction.
  • a memory controller including:
  • a requesting distribution module configured to acquire a first memory access request, where the first memory access request is used to request access to a first sub-line of the memory
  • a memory scheduler configured to acquire a first memory access request acquired by the request distribution module, and generate a first activation instruction according to the first memory access request
  • a command scheduler configured to send the first activation instruction acquired from the memory scheduler to the memory
  • the request distribution module is further configured to: search for a second memory access request from the memory to-be-scheduled queue, the memory to-be-scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the a second sub-row of the memory, the first sub-row is located in the first sub-array, and the second sub-row is in the second sub-array;
  • the memory scheduler is further configured to generate a second activation instruction according to the second memory access request
  • the command scheduler is further configured to send the second activation instruction acquired from the memory scheduler to the memory;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage Unit, any one of the storage units corresponding to a line number identifier and a column number identifier;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row.
  • the request distribution module is further configured to:
  • the third memory access request is for requesting access to a third sub-line of the memory, the third sub-line is in the same row as the first sub-row, and the second sub-row includes The column number identifier corresponding to any one of the storage units is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • the memory scheduler is specifically configured to:
  • the request distribution module is further configured to:
  • the fourth memory access request is for requesting access to a fourth sub-line of the memory, the fourth sub-row is in the same row as the second sub-row, and the fourth sub-row includes The column number identifier corresponding to any one of the storage units is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the memory scheduler is specifically configured to:
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row and the third sub-line are included
  • the column number identifiers corresponding to any one of the storage units are different.
  • a memory module including:
  • a first latch configured to receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate that the first sub-line in the memory is activated;
  • a second latch configured to receive a second activation instruction sent by the memory controller, where the second activation instruction is used to indicate activation of a second sub-row in the memory
  • the first sub-row is located in a first sub-array, and the second sub-row is in a second sub-array;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit. Any one of the storage units corresponds to a line number identifier and a column number identifier;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the first latch and the second latch are each coupled to a global buffer for data buffering.
  • the first activation instruction is further used to indicate that a third sub-line in the memory is activated, where the third sub-line is in the same row as the first sub-line in;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • the second activation instruction is further used to indicate that a fourth sub-line in the memory is activated, where the The four sub-rows are in the same row as the second sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • a method of activating memory including:
  • Finding a second memory access request from a memory to-be-scheduled queue where the memory to-be-scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second sub-memory Row, the first subrow is located in the first subarray, and the second subrow is in the second subarray;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit. Any one of the storage units corresponds to a line number identifier and a column number identifier;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row.
  • the method before the generating the first activation instruction according to the first memory access request, the method further includes:
  • the third memory access request is for requesting access to a third sub-line of the memory, the third sub-line is in the same row as the first sub-row, and the second sub-row includes The column number identifier corresponding to any one of the storage units is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • the method before the generating the second activation instruction according to the second memory access request, the method further includes:
  • the fourth memory access request is for requesting access to a fourth sub-line of the memory, the fourth sub-row is in the same row as the second sub-row, and the fourth sub-row includes The column number identifier corresponding to any one of the storage units is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row and the third sub-line are included
  • the column number identifiers corresponding to any one of the storage units are different.
  • a method of activating memory including:
  • the first activation instruction is used to indicate activation The first child line in memory
  • the first sub-row is located in a first sub-array, and the second sub-row is in a second sub-array; the first sub-array and the second sub-array each include at least one row, any one of the at least one row Include at least one sub-line, any one of the at least one sub-rows comprising at least one storage unit, any one of the storage units corresponding to a line number identifier and a column number identifier;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the first latch and the second latch are each coupled to a global buffer for data buffering.
  • the first activation instruction is further used to indicate that a third sub-line in the memory is activated, where the third sub-line is in the same line as the first sub-line in;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • the first sub-row and the third sub-row in the memory are activated by the first latch in the memory in accordance with the first activation instruction.
  • the second activation instruction is further used to indicate that a fourth sub-line in the memory is activated, where the The four sub-rows are in the same row as the second sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • the second sub-row and the fourth sub-row in the memory are activated by the second latch in the memory in accordance with the second activation instruction.
  • the storage unit In the prior art, multiple storage units cannot be activated at the same time, but after each storage unit is activated, the storage unit is precharged, and then the next storage unit can be performed.
  • the first memory access request is obtained, the first memory access request is used to request access to the first sub-line of the memory, and the operation is not performed immediately.
  • the second memory access request is for requesting access to the second sub-line of the memory, the first sub-row and the second sub-row are in the same memory In the same row or in the same row; then, combining the first memory access request and the second memory access request to generate a first activation instruction, the first activation instruction is used to indicate that the first child row and the second child row in the memory are activated, And sending the first activation command to the memory, so that the first sub-row and the second sub-row can be activated at the same time, and it is not necessary to activate the first sub-row after the first sub-row is activated, and then the first sub-row is pre-charged and then activated.
  • the second sub-row therefore, improves the efficiency of activating memory.
  • 1A is a flow chart of activating memory in an embodiment of the present invention.
  • FIG. 1B is a schematic diagram of a sub-row selection vector according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a memory controller according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a memory module according to an embodiment of the present invention.
  • FIG. 5A is another schematic diagram of a memory controller according to an embodiment of the present invention.
  • 5B is a schematic diagram of a memory in an embodiment of the present invention.
  • FIG. 6 is another schematic diagram of a memory module according to an embodiment of the present invention.
  • FIG. 7 is another flow chart of activating memory in an embodiment of the present invention.
  • FIG. 8 is another flowchart of activating memory in an embodiment of the present invention.
  • FIG. 9 is another schematic diagram of a memory controller according to an embodiment of the present invention.
  • FIG. 10 is another schematic diagram of a memory module according to an embodiment of the present invention.
  • FIG. 11 is another flow chart of activating memory in an embodiment of the present invention.
  • FIG. 12 is another flow chart of activating memory in an embodiment of the present invention.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the letter “/” in this article generally indicates that the contextual object is an "or" relationship.
  • a process for activating memory is as follows:
  • Step 100 Acquire a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • Step 110 Find a second memory access request from the memory to be scheduled queue, the memory to be scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second subrow of the memory, the first subrow and the second The child row is in the same line of memory;
  • Step 120 Combine the first memory access request and the second memory access request to generate a first activation instruction, where the first activation instruction is used to indicate that the first sub-row and the second sub-row in the memory are activated;
  • Step 130 Send the first activation instruction to the memory.
  • the sub-row selection vector is used to identify that the sub-row to be activated is the first sub-row and the second sub-row.
  • the values in the sub-row selection vector respectively correspond to one sub-row, and the value is used to indicate whether the corresponding sub-row is activated or not, as shown in FIG. 1B.
  • the value in the sub-row selection vector is 0, it indicates that the corresponding sub-row is activated.
  • the value in the sub-row selection vector is 1, it indicates that the corresponding sub-row is not activated.
  • other forms may be used to indicate the corresponding Whether the sub-rows are activated or not be detailed here.
  • the sub-row selection vector when the sub-row selection vector is sent, it may be sent simultaneously with the first activation instruction, for example, the sub-row selection vector is carried in the first activation instruction. At this time, in specific implementation, The sub-row selection vector and the first activation instruction are simultaneously written on the memory bus; or, when the sub-row selection vector is transmitted, the sub-row selection vector may be transmitted before the first activation instruction is sent, at which time, in specific implementation, The sub-row selection vector is written over the bus before the first active instruction is written on the memory bus.
  • the data in the first sub-row and the second sub-row are taken into the corresponding sub-line buffer, and for the sub-row that is not selected, Do not activate, do not take the corresponding data into the corresponding sub-line buffer.
  • FIG. 2 another process for activating memory in the embodiment of the present invention is as follows:
  • Step 200 Receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate that the first sub-row in the memory and the second sub-row in the memory are activated, and the first sub-row and the second sub-row are both in the memory.
  • the first activation instruction is used to indicate that the first sub-row in the memory and the second sub-row in the memory are activated, and the first sub-row and the second sub-row are both in the memory.
  • Step 210 Activate the first sub-line and the second sub-line in the memory according to the first activation instruction.
  • the first sub-row and the second sub-row in the memory are activated according to the sub-row selection vector in the first activation instruction.
  • an embodiment of the present invention provides a memory controller 3000, which includes a request distribution module 30, a memory scheduler 31, and a command scheduler 32, where:
  • the requesting distribution module 30 is configured to obtain a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • the memory scheduler 31 is configured to search for a second memory access request from the memory to be scheduled queue, where the memory to be scheduled queue includes multiple memory access requests, and the second memory access request is used to request access to the memory.
  • the second sub-row, the first sub-row and the second sub-row are in the same line of memory;
  • the memory scheduler 31 is further configured to merge the first memory access request and the second memory access request to generate a first activation instruction, where the first activation instruction is used to indicate that the first sub-row and the second sub-row in the memory are activated;
  • the command scheduler 32 is configured to send the first activation instruction to the memory.
  • the memory scheduler 31 is further configured to:
  • the sub-row selection vector is used to identify that the sub-row to be activated is the first sub-row and the second sub-row.
  • an embodiment of the present invention provides a memory module 4000, which includes a latch 40 and a sub-row select decoder 41, where:
  • the latch 40 is configured to receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate activation of the first sub-line in the memory and the second sub-line in the memory, the first sub-line and the second sub- Rows are in the same row in memory;
  • the sub-row selection decoder 41 is operative to activate the first sub-row and the second sub-line in memory in accordance with the first activation instruction acquired from the latch 40.
  • the latch 40 is also used to:
  • the sub-row selection decoder 41 is specifically used to:
  • the first sub-row and the second sub-row in the memory are activated according to the sub-row selection vector in the first activation instruction.
  • a memory controller 5000 in order to improve the utilization of resources of the storage unit, as shown in FIG. 5A, a memory controller 5000 is provided.
  • the memory controller 5000 includes a request distribution module 50, a memory scheduler 51, and a command scheduler 52. ,among them:
  • the requesting distribution module 50 is configured to obtain a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • the memory scheduler 51 is configured to acquire a first memory access request acquired by the request distribution module 50, and generate a first activation instruction according to the first memory access request;
  • a command scheduler 52 configured to send the first activation instruction acquired from the memory scheduler 51 to the memory
  • the request distribution module 50 is further configured to: search for a second memory access request from the memory to be scheduled queue, the memory to be scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second subrow of the memory, first The sub-row is located in the first sub-array, and the second sub-row is in the second sub-array;
  • the memory scheduler 51 is further configured to generate a second activation instruction according to the second memory access request
  • the command scheduler 52 is further configured to send the second activation instruction acquired from the memory scheduler 51 to the memory;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one
  • the line number identifier corresponds to a column number identifier
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column identifier corresponding to any one of the storage units included in the first sub-row.
  • the relationship between the sub-array, the row, the column, and the storage unit is as shown in FIG. 5B.
  • the request distribution module 50 is further configured to:
  • the third memory access request is for requesting access to the third sub-row of the memory, the third sub-row is in the same row as the first sub-row, and the second sub-row includes a column corresponding to any one of the storage units The number identifier and the column identifier corresponding to any one of the storage units included in the third sub-row are different;
  • the memory scheduler 51 is specifically used to:
  • the first memory access request and the third memory access request are combined to generate a first activation instruction.
  • the request distribution module 50 is further configured to:
  • the fourth memory access request is used to request access to the fourth sub-row of the memory
  • the fourth sub-row is in the same row as the second sub-row
  • the fourth sub-row includes a column corresponding to any one of the storage units
  • the number identifier is different from the column identifier corresponding to any one of the storage units included in the first sub-row;
  • the memory scheduler 51 is specifically used to:
  • the second memory access request and the fourth memory access request are merged to generate a second activation instruction.
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • the memory module 6000 includes a first latch 60, a first sub-row select decoder 61, and a first The second latch 62, the second sub-row selection decoder 63, wherein:
  • a first latch 60 configured to receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate that the first sub-line in the memory is activated;
  • a first sub-row selection decoder 61 for activating the first sub-line in memory according to the first activation instruction
  • a second latch 62 configured to receive a second activation instruction sent by the memory controller, where the second activation instruction is used to indicate that the second sub-line in the memory is activated;
  • a second sub-row selection decoder 63 for activating a second sub-row in memory according to the second activation instruction
  • the first sub-row is located in the first sub-array and the second sub-row is in the second sub-array;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one row number
  • the identifier corresponds to a column number identifier
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • Both the first latch 60 and the second latch 62 are coupled to a global buffer for data buffering.
  • the first activation instruction is further used to indicate that the third sub-row in the memory is activated, and the third sub-row is in the same row as the first sub-row;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • the second activation instruction is further used to indicate that the fourth sub-row in the memory is activated, and the fourth sub-row is in the same row as the second sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • the second latch can activate the second sub-row that is in the different sub-array with the first sub-row, thus improving resource utilization.
  • FIG. 7 another process for activating memory in the embodiment of the present invention is as follows:
  • Step 700 Acquire a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • Step 710 Generate a first activation instruction according to the first memory access request, and send the first activation instruction to the memory;
  • Step 720 Find a second memory access request from the memory to be scheduled queue, the memory to be scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second subrow of the memory, where the first subrow is located at the first a sub-array, the second sub-row is in the second sub-array;
  • Step 730 Generate a second activation instruction according to the second memory access request, and send the second activation instruction to the memory;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one row number
  • the identifier corresponds to a column number identifier
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the first sub-row.
  • the method before the generating the first activation instruction according to the first memory access request, the method further includes:
  • the third memory access request is for requesting access to the third sub-row of the memory, the third sub-row is in the same row as the first sub-row, and the second sub-row includes a column corresponding to any one of the storage units The number identifier and the column identifier corresponding to any one of the storage units included in the third sub-row are different;
  • the first memory access request and the third memory access request are combined to generate a first activation instruction.
  • the method before the second activation instruction is generated according to the second memory access request, the method further includes:
  • the fourth memory access request is used to request access to the fourth sub-row of the memory
  • the fourth sub-row is in the same row as the second sub-row
  • the fourth sub-row includes a column corresponding to any one of the storage units
  • the number identifier is different from the column identifier corresponding to any one of the storage units included in the first sub-row;
  • the second memory access request and the fourth memory access request are merged to generate a second activation instruction.
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row.
  • FIG. 8 another process for activating memory in the embodiment of the present invention is as follows:
  • Step 800 Receive a first activation instruction sent by a memory controller, where the first activation instruction is used to indicate that the first sub-line in the memory is activated;
  • Step 810 Activate the first sub-line in the memory according to the first activation instruction
  • Step 820 Receive a second activation instruction sent by the memory controller, where the second activation instruction is used to indicate that the second sub-line in the memory is activated;
  • Step 830 Activate a second sub-row in memory according to the second activation instruction; the first sub-row is located in the first sub-array, and the second sub-row is in the second sub-array; the first sub-array and the second sub-array each include at least a row, at least one of the at least one row includes at least one child row, and any one of the at least one child row includes at least one memory unit, and any one of the memory cells corresponds to a row number identifier and a column number identifier; the second sub- The column number identifier corresponding to any one of the memory cells included in the row is different from the column number identifier corresponding to any one of the memory cells included in the first subrow; the first latch and the second latch are both used for performing The global buffer of the data cache is connected.
  • the first activation instruction is further used to indicate that the third sub-row in the memory is activated, and the third sub-row is in the same row as the first sub-row;
  • the column number identifier corresponding to any one of the storage units included in the second sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • Activating the first sub-line in the memory according to the first activation instruction specifically includes:
  • the first sub-row and the third sub-row in memory are activated by the first latch in the memory according to the first activation instruction.
  • the second activation instruction is further used to indicate that the fourth sub-row in the memory is activated, and the fourth sub-row is in the same row as the second sub-row;
  • the column number identifier corresponding to any one of the storage units included in the fourth sub-row is different from the column number identifier corresponding to any one of the storage units included in the third sub-row;
  • the second sub-row and the fourth sub-row in memory are activated by the second latch in the memory according to the second activation command.
  • the second latch can activate the second sub-row that is in the different sub-array with the first sub-row, thus improving resource utilization.
  • 5A, 5B, 6, 7, and 8 illustrate the column numbers corresponding to any one of the storage units included in the second sub-row of the different sub-array after the first sub-row is activated.
  • the second sub-row can be activated only when the identifier corresponding to the column number corresponding to any one of the storage units included in the first sub-row is different. Further, in order to improve resource utilization, the following scheme is proposed:
  • a memory controller 9000 in order to improve the utilization of the resources of the storage unit, as shown in FIG. 9, a memory controller 9000 is provided.
  • the memory controller 9000 includes a request distribution module 90, a memory scheduler 91, and a command scheduler 92. ,among them:
  • the request distribution module 90 is configured to obtain a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • the memory scheduler 91 is configured to acquire a first memory access request acquired by the request distribution module 90, and generate a first activation instruction according to the first memory access request;
  • the command scheduler 92 is configured to send the first activation instruction acquired from the memory scheduler 91 to the memory;
  • the request distribution module 90 is further configured to: search for a second memory access request from the memory to be scheduled queue, the memory to be scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second subrow of the memory, first The sub-row is located in the first sub-array, and the second sub-row is in the second sub-array;
  • the memory scheduler 91 is further configured to generate a second activation instruction according to the second memory access request
  • the command scheduler 92 is further configured to send the second activation instruction acquired from the memory scheduler 91 to the memory;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one
  • the line number identifier corresponds to a column number identifier
  • the second sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row.
  • the request distribution module 90 is further configured to:
  • the third memory access request is used to request access to the third child of the memory a row, the third subrow is in the same row as the first subrow, and the second subrow includes a storage unit having the same column number identifier as the column number corresponding to the storage unit included in the third subrow;
  • the memory scheduler 91 is specifically used to:
  • the first memory access request and the third memory access request are combined to generate a first activation instruction.
  • the request distribution module 90 is further configured to:
  • the fourth memory access request is for requesting access to the fourth sub-line of the memory, the fourth sub-row is in the same row as the second sub-row, and the fourth sub-row includes the column number identifier and the first sub-row includes The column number corresponding to the storage unit identifies the same storage unit;
  • the memory scheduler 91 is specifically used to:
  • the second memory access request and the fourth memory access request are merged to generate a second activation instruction.
  • the fourth sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the third sub-row.
  • the second latch After the first latch activates the first sub-row, and the second sub-row includes the column number identifying the same storage unit as the column number corresponding to the storage unit included in the first sub-row, the second latch It is also possible to activate the second sub-row in a different sub-array with the first sub-row, thus improving the utilization of resources.
  • the memory module 10000 in order to improve the utilization of resources of the storage unit, as shown in FIG. 10, the memory module 10000 includes a first latch 100, a first sub-row selection decoder 101, and a second lock.
  • the first latch 100 is configured to receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate that the first sub-line in the memory is activated;
  • a first sub-row selection decoder 101 configured to activate a first sub-line in memory according to the first activation instruction
  • a second latch 102 configured to receive a second activation instruction sent by the memory controller, where the second activation instruction is used to indicate activation of the second sub-line in the memory;
  • a second sub-row selection decoder 103 configured to activate a second sub-line in memory according to the second activation instruction
  • the first sub-row is located in the first sub-array and the second sub-row is in the second sub-array;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one row number
  • the identifier corresponds to a column number identifier
  • the second sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row;
  • Neither the first latch 100 nor the second latch 102 are connected to a global buffer for data buffering.
  • the first activation instruction is further used to indicate that the third sub-row in the memory is activated, and the third sub-row is in the same row as the first sub-row;
  • the second sub-row includes a storage unit whose column number identifies the same column number as the storage unit included in the third sub-row.
  • the second activation instruction is further used to indicate that the fourth sub-row in the memory is activated, and the fourth sub-row is in the same row as the second sub-row;
  • the fourth sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row;
  • the fourth sub-row includes a storage unit whose column number identifies the same column number as the storage unit included in the third sub-row.
  • the second latch After the first latch activates the first sub-row, and the second sub-row includes the column number identifying the same storage unit as the column number corresponding to the storage unit included in the first sub-row, the second latch It is also possible to activate the second sub-row in a different sub-array with the first sub-row, thus improving the utilization of resources.
  • Step 1100 Acquire a first memory access request, where the first memory access request is used to request access to the first sub-line of the memory;
  • Step 1110 Acquire a first memory access request, and generate a first activation instruction according to the first memory access request.
  • Step 1120 Send the first activation instruction to the memory
  • Step 1130 Find a second memory access request from the memory to be scheduled queue, the memory to be scheduled queue includes a plurality of memory access requests, and the second memory access request is used to request access to the second subrow of the memory, where the first subrow is located at the first a sub-array, the second sub-row is in the second sub-array;
  • Step 1140 Generate a second activation instruction according to the second memory access request.
  • Step 1150 Send the obtained second activation instruction to the memory
  • first sub-array and the second sub-array each comprise at least one row, at least one of the at least one row
  • the row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, and any one of the storage units corresponds to a row number identifier and a column number identifier;
  • the second sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row.
  • the method before the generating the first activation instruction according to the first memory access request, the method further includes: acquiring a third memory access request, where the third memory access request is used to request access to the third sub-line of the memory, and the third The child row is in the same row as the first child row, and the second child row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the third child row;
  • the first activation instruction is generated according to the first memory access request, and the first activation instruction may be generated by combining the first memory access request and the third memory access request.
  • the method before the second activation instruction is generated according to the second memory access request, the method further includes:
  • the fourth memory access request is for requesting access to the fourth sub-line of the memory, the fourth sub-row is in the same row as the second sub-row, and the fourth sub-row includes the column number identifier and the first sub-row includes The column number corresponding to the storage unit identifies the same storage unit;
  • the second memory access request and the fourth memory access request may be merged to generate a second activation instruction.
  • the fourth sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the third sub-row.
  • the second latch After the first latch activates the first sub-row, and the second sub-row includes the column number identifying the same storage unit as the column number corresponding to the storage unit included in the first sub-row, the second latch It is also possible to activate the second sub-row in a different sub-array with the first sub-row, thus improving the utilization of resources.
  • Step 1200 Receive a first activation instruction sent by the memory controller, where the first activation instruction is used to indicate that the first sub-line in the memory is activated;
  • Step 1210 Activate the first sub-line in memory according to the first activation instruction
  • Step 1220 Receive a second activation instruction sent by the memory controller, where the second activation instruction is used to indicate that the second sub-line in the memory is activated;
  • Step 1230 Activate the second sub-line in the memory according to the second activation instruction
  • the first sub-row is located in the first sub-array and the second sub-row is in the second sub-array;
  • the first sub-array and the second sub-array each include at least one row, and any one of the at least one row includes at least one sub-row, and any one of the at least one sub-row includes at least one storage unit, any one of the storage units and one row number
  • the identifier corresponds to a column number identifier
  • the second sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row;
  • Neither the first latch nor the second latch is connected to the global buffer for data buffering.
  • the first activation instruction is further used to indicate that the third sub-row in the memory is activated, and the third sub-row is in the same row as the first sub-row;
  • the second sub-row includes a storage unit whose column number identifies the same column number as the storage unit included in the third sub-row.
  • the second activation instruction is further used to indicate that the fourth sub-row in the memory is activated, and the fourth sub-row is in the same row as the second sub-row;
  • the fourth sub-row includes a storage unit whose column number identifier is the same as the column number identifier corresponding to the storage unit included in the first sub-row;
  • the fourth sub-row includes a storage unit whose column number identifies the same column number as the storage unit included in the third sub-row.
  • the second latch After the first latch activates the first sub-row, and the second sub-row includes the column number identifying the same storage unit as the column number corresponding to the storage unit included in the first sub-row, the second latch It is also possible to activate the second sub-row in a different sub-array with the first sub-row, thus improving the utilization of resources.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the computer readable memory is stored in the computer readable memory.
  • the instructions in the production result include an article of manufacture of the instruction device that functions in a block or blocks of a flow or a flow of flowcharts and/or a block diagram.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions in one or more blocks of the flowchart or in a flow or block of the flowchart.

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Abstract

一种激活内存的方法及装置，属于计算机领域。在该方案中，获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行（100）；从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行与第二子行处于内存的同一行（110）；合并第一内存访问请求和第二内存访问请求，生成第一激活指令，第一激活指令用于指示激活内存中的第一子行和第二子行（120），将第一激活指令发送至内存（130）。这样，就可以同时将第一子行和第二子行激活，没必要在激活第一子行后，对第一子行所在的行预充电，然后，再激活第二子行，因此，提高了激活的效率。

Description

一种内存管理方法、装置以及内存控制器 技术领域
本发明涉及计算机领域，特别涉及一种激活内存的方法及装置。
背景技术
目前，数据中心的功耗的25-40％被内存所消耗，内存具有行列结构，任意一行和任意一列交叉形成的单元格为一个存储单元，因此，任意一个存储单元均对应一个行号和一个列号，访问一行中的某个存储单元时，首先要激活整个行，要访问编号为“00”(即处于0行0列)的存储单元时，首先要激活处于0行中的9个存储单元，而激活的功耗占内存功耗的85％以上，因此，目前的数据中心的功耗较大。
为了降低数据中心的功耗，提出了一种细粒度行访问内存的方法，该方案的主要思路为：每次激活时只需要激活待访问的存储单元即可，不需要将处于同一行的所有存储单元激活，内存接收到一个行激活指令时，并不立即激活此行，而是等接收到列激活指令时，根据行激活指令中的行地址和列激活指令中的列地址确定出待激活的存储单元，然后，再激活该存储单元，因此，降低了数据中心的功耗。
但是，上述方案中，不能同时对多个存储单元进行激活，而是每激活一个存储单元后，要对该存储单元进行预充电后，然后，才能对下一个存储单元进行激活操作，因此，目前激活内存的方法存在效率较低的缺陷。
发明内容
本发明实施例提供一种激活内存的方法及装置，用以解决现有技术中存在的激活内存的方法效率较低的缺陷。
本发明实施例提供的具体技术方案如下：
第一方面，提供一种激活内存的方法，包括：
获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行与所述第二子行处于所述内存的同一行；
合并所述第一内存访问请求和所述第二内存访问请求，生成第一激活指令，所述第一激活指令用于指示激活所述内存中的所述第一子行和所述第二子行；
将所述第一激活指令发送至所述内存。
结合第一方面，在第一种可能的实现方式中，从内存待调度队列中查找第二内存访问请求之后，还包括：
生成子行选择向量，并将所述子行选择向量发送至所述内存；
所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行。
第二方面，提供一种激活内存的方法，包括：
接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，所述第一子行与所述第二子行均处于所述内存中的同一行中；
根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行。
结合第二方面，在第一种可能的实现方式中，根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行之前，还包括：
接收所述内存控制器发送的子行选择向量，所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行；
根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行，具体包括：
根据所述第一激活指令中、所述子行选择向量激活处于所述内存的所述第一子行和所述第二子行。
第三方面，提供一种内存控制器，包括：
请求分发模块，用于获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
内存调度器，用于从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行与所述第二子行处于所述内存的同一行；
内存调度器还用于，合并所述第一内存访问请求和所述第二内存访问请求，生成第一激活指令，所述第一激活指令用于指示激活所述内存中的所述 第一子行和所述第二子行；
所述命令调度器，用于所述第一激活指令发送至所述内存。
结合第三方面，在第一种可能的实现方式中，从内存待调度队列中查找第二内存访问请求之后，还包括：
生成子行选择向量，并将所述子行选择向量发送至所述内存；
所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行。
第四方面，提供一种内存模块，包括：
锁存器，用于接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，所述第一子行与所述第二子行均处于所述内存中的同一行中；
子行选择解码器，用于根据从所述锁存器获取的所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行。
结合第四方面，在第一种可能的实现方式中，所述锁存器还用于：
接收所述内存控制器发送的子行选择向量，所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行；
所述子行选择解码器具体用于：
根据所述第一激活指令中、所述子行选择向量激活处于所述内存的所述第一子行和所述第二子行。
第五方面，提供一种内存控制器，包括：
请求分发模块，用于获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
内存调度器，用于获取所述请求分发模块获取到的第一内存访问请求，并根据所述第一内存访问请求生成第一激活指令；
命令调度器，用于将从所述内存调度器获取的所述第一激活指令发送至所述内存；
所述请求分发模块还用于，从所述内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
所述内存调度器还用于，根据所述第二内存访问请求生成第二激活指令；
所述命令调度器还用于，将从所述内存调度器获取的所述第二激活指令发送至所述内存；
其中，所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
其中，所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同。
结合第五方面，在第一种可能的实现方式中，所述请求分发模块还用于：
获取第三内存访问请求，所述第三内存访问请求用于请求访问内存的第三子行，所述第三子行与所述第一子行处于同一行，所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
所述内存调度器具体用于：
合并所述第一内存访问请求和所述第三内存访问请求，生成第一激活指令。
结合第五方面，以及第五方面的第一种可能的实现方式，在第二种可能的实现方式中，所述请求分发模块还用于：
获取第四内存访问请求，所述第四内存访问请求用于请求访问内存的第四子行，所述第四子行与所述第二子行处于同一行，所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
所述内存调度器具体用于：
合并所述第二内存访问请求和所述第四内存访问请求，生成第二激活指令。
结合第五方面的第二种可能的实现方式，在第三种可能的实现方式中，所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
第六方面，提供一种内存模块，包括：
第一锁存器，用于接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行；
第一子行选择解码器，用于根据所述第一激活指令激活处于所述内存中 的所述第一子行；
第二锁存器，用于接收所述内存控制器发送的第二激活指令，所述第二激活指令用于指示激活所述内存中的第二子行；
第二子行选择解码器，用于根据所述第二激活指令激活处于所述内存中的所述第二子行；
所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
所述第一锁存器和所述第二锁存器均与用于进行数据缓存的全局缓冲器相连。
结合第六方面，在第一种可能的实现方式中，所述第一激活指令还用于指示激活内存中的第三子行，所述第三子行与所述第一子行处于同一行中；
所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
结合第六方面，以及第六方面的第一种可能的实现方式，在第二种可能的实现方式中，所述第二激活指令还用于指示激活内存中的第四子行，所述第四子行与所述第二子行处于同一行中；
所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
第七方面，提供一种激活内存的方法，包括：
获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
根据所述第一内存访问请求生成第一激活指令，并将所述第一激活指令发送至所述内存；
从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子 行，所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
根据所述第二内存访问请求生成第二激活指令，并将所述第二激活指令发送至所述内存；
所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同。
结合第七方面，在第一种可能的实现方式中，根据所述第一内存访问请求生成第一激活指令之前，还包括：
获取第三内存访问请求，所述第三内存访问请求用于请求访问内存的第三子行，所述第三子行与所述第一子行处于同一行，所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据所述第一内存访问请求生成第一激活指令，具体包括：
合并所述第一内存访问请求和所述第三内存访问请求，生成第一激活指令。
结合第七方面，以及第七方面的第一种可能的实现方式，在第二种可能的实现方式中，根据所述第二内存访问请求生成第二激活指令之前，还包括：
获取第四内存访问请求，所述第四内存访问请求用于请求访问内存的第四子行，所述第四子行与所述第二子行处于同一行，所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
根据所述第二内存访问请求生成第二激活指令，具体包括：
合并所述第二内存访问请求和所述第四内存访问请求，生成第二激活指令。
结合第七方面的第二种可能的实现方式，在第三种可能的实现方式中，所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
第八方面，提供一种激活内存的方法，包括：
接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活 内存中的第一子行；
根据所述第一激活指令激活处于所述内存中的所述第一子行；
接收内存控制器发送的第二激活指令，所述第二激活指令用于指示激活内存中的第二子行；
根据所述第二激活指令激活处于所述内存中的所述第二子行；
所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
所述第一锁存器和所述第二锁存器均与用于进行数据缓存的全局缓冲器相连。
结合第八方面，在第一种可能的实现方式中，所述第一激活指令还用于指示激活内存中的第三子行，所述第三子行与所述第一子行处于同一行中；
所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据所述第一激活指令激活处于所述内存中的所述第一子行，具体包括：
由所述内存中的第一锁存器根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第三子行。
结合第八方面，以及第八方面的第一种可能的实现方式，在第二种可能的实现方式中，所述第二激活指令还用于指示激活内存中的第四子行，所述第四子行与所述第二子行处于同一行中；
所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据所述第二激活指令激活处于所述内存中的所述第二子行，具体包括：
由所述内存中的第二锁存器根据所述第二激活指令激活处于所述内存中的所述第二子行和所述第四子行。
本发明有益效果如下：
现有技术中，不能同时对多个存储单元进行激活，而是每激活一个存储单元后，要对该存储单元进行预充电后，然后，才能对下一个存储单元进行 激活操作，因此，目前激活内存的方法存在效率较低的缺陷，本发明实施例中，获取第一内存访问请求后，第一内存访问请求用于请求访问内存的第一子行，没有立即去激活第一子行，而是从内存待调度队列中查找第二内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行与第二子行处于内存的同一行中或者处于同一行中；然后，合并第一内存访问请求和第二内存访问请求，生成第一激活指令，第一激活指令用于指示激活内存中的第一子行和第二子行，并将第一激活指令发送至内存，这样，就可以同时将第一子行和第二子行激活，没必要在激活第一子行后，对第一子行所在的行预充电后才激活第二子行，因此，提高了激活内存的效率。
附图说明
图1A为本发明实施例中激活内存的一种流程图；
图1B为本发明实施例中子行选择向量的示意图；
图2为本发明实施例中激活内存的另一种流程图；
图3为本发明实施例中内存控制器的一种示意图；
图4为本发明实施例中内存模块的一种示意图；
图5A为本发明实施例中内存控制器的另一种示意图；
图5B为本发明实施例中内存的示意图；
图6为本发明实施例中内存模块的另一种示意图；
图7为本发明实施例中激活内存的另一种流程图；
图8为本发明实施例中激活内存的另一种流程图；
图9为本发明实施例中内存控制器的另一种示意图；
图10为本发明实施例中内存模块的另一种示意图；
图11为本发明实施例中激活内存的另一种流程图；
图12为本发明实施例中激活内存的另一种流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例，都属于本发明保护的范围。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字母“/”，一般表示前后关联对象是一种“或”的关系。
下面结合说明书附图对本发明优选的实施方式进行详细说明，应当理解，此处所描述的优选实施例仅用于说明和解释本发明，并不用于限定本发明，并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
下面结合附图对本发明优选的实施方式进行详细说明。
参阅图1A所示，本发明实施例中，激活内存的一种流程如下：
步骤100：获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
步骤110：从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行与第二子行处于内存的同一行；
步骤120：合并第一内存访问请求和第二内存访问请求，生成第一激活指令，第一激活指令用于指示激活内存中的第一子行和第二子行；
步骤130：将第一激活指令发送至内存。
本发明实施例中，要识别待激活的第一子行和第二子行是否处于同一行，可以查看所处的行的行地址是否相同。
本发明实施例中，为了使内存知道哪些子行要激活，哪些子行不激活，在内存待调度队列中查找第二内存访问请求之后，还包括如下操作：
生成子行选择向量，并将子行选择向量发送至内存；
子行选择向量用于标识待激活的子行是第一子行和第二子行。
例如，处于一行中有N个子行，子行选择向量中的值分别与一个子行相对应，且该值用于表示相对应的子行是被激活还是不被激活，如图1B所示，子行选择向量中的值为0时，表示对应的子行被激活，子行选择向量中的值为1时，表示对应的子行不被激活，当然，也可以用其他形式来表示对应的子行是否被激活，在此不再进行一一详述。
本发明实施例中，在发送子行选择向量时，可以与第一激活指令同时发送，如，将子行选择向量携带在第一激活指令中，此时，在具体实现时，将 子行选择向量和第一激活指令在内存总线上同时写入；或者，在发送子行选择向量时，可以在发送第一激活指令之前发送子行选择向量，此时，在具体实现时，在内存总线上第一激活指令写入之前通过总线写入子行选择向量。
本发明实施例中，在激活第一子行和第二子行后，把第一子行和第二子行中的数据取到对应的子行缓冲中去，对于不被选中的子行，不激活，不把对应的数据取到相应的子行缓冲中去。
在该方案中，在接收到第一内存访问请求时，不是立即去激活第一内存访问请求所请求访问的第一子行，而是对内存待调度队列中的内存访问请求进行调度，查找第二内存访问请求，将第一内存访问请求和第二内存访问请求合并为第一激活指令，并将第一激活指令发送至内存，这样，一次性可以激活第一子行和第二子行，提高了激活效率。
参阅图2所示，本发明实施例中，激活内存的另一种流程如下：
步骤200：接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，第一子行与第二子行均处于内存中的同一行中；
步骤210：根据第一激活指令激活处于内存中的第一子行和第二子行。
本发明实施例中，根据第一激活指令激活处于内存中的第一子行和第二子行之前，还包括如下操作：
接收内存控制器发送的子行选择向量，子行选择向量用于标识待激活的子行是第一子行和第二子行；
根据第一激活指令激活处于内存中的第一子行和第二子行时，可以采用如下方式：
根据第一激活指令中、子行选择向量激活处于内存的第一子行和第二子行。
基于上述相应方法的技术方案，参阅图3所示，本发明实施例提供一种内存控制器3000，该内存控制器3000包括请求分发模块30、内存调度器31、命令调度器32，其中：
请求分发模块30，用于获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
内存调度器31，用于从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的 第二子行，第一子行与第二子行处于内存的同一行；
内存调度器31还用于，合并第一内存访问请求和第二内存访问请求，生成第一激活指令，第一激活指令用于指示激活内存中的第一子行和第二子行；
命令调度器32，用于第一激活指令发送至内存。
本发明实施例中，内存调度器31还用于：
生成子行选择向量，并将子行选择向量发送至内存；
子行选择向量用于标识待激活的子行是第一子行和第二子行。
基于上述相应方法的技术方案，参阅图4所示，本发明实施例提供一种内存模块4000，该内存模块4000包括锁存器40、子行选择解码器41，其中：
锁存器40，用于接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，第一子行与第二子行均处于内存中的同一行中；
子行选择解码器41，用于根据从锁存器40获取的第一激活指令激活处于内存中的第一子行和第二子行。
锁存器40还用于：
接收内存控制器发送的子行选择向量，子行选择向量用于标识待激活的子行是第一子行和第二子行；
子行选择解码器41具体用于：
根据第一激活指令中、子行选择向量激活处于内存的第一子行和第二子行。
本发明实施例中，为了提高存储单元的资源的利用率，如图5A所示，提供一种内存控制器5000，该内存控制器5000包括请求分发模块50、内存调度器51、命令调度器52，其中：
请求分发模块50，用于获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
内存调度器51，用于获取请求分发模块50获取到的第一内存访问请求，并根据第一内存访问请求生成第一激活指令；
命令调度器52，用于将从内存调度器51获取的第一激活指令发送至内存；
请求分发模块50还用于，从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行位于第一子阵列，第二子行处于第二子阵列；
内存调度器51还用于，根据第二内存访问请求生成第二激活指令；
命令调度器52还用于，将从内存调度器51获取的第二激活指令发送至内存；
其中，第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
其中，第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同。
本发明实施例中，子阵列、行、列、存储单元的关系如图5B所示。
进一步的，本发明实施例中，请求分发模块50还用于：
获取第三内存访问请求，第三内存访问请求用于请求访问内存的第三子行，第三子行与第一子行处于同一行，第二子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同；
内存调度器51具体用于：
合并第一内存访问请求和第三内存访问请求，生成第一激活指令。
本发明实施例中，进一步的，请求分发模块50还用于：
获取第四内存访问请求，第四内存访问请求用于请求访问内存的第四子行，第四子行与第二子行处于同一行，第四子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同；
内存调度器51具体用于：
合并第二内存访问请求和第四内存访问请求，生成第二激活指令。
本发明实施例中，可选的，第四子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同。
在该方案中，激活第一子行后，第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同时，可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
本发明实施例中，为了提高存储单元的资源的利用率，如图6所示，内存模块6000，该内存模块6000包括第一锁存器60、第一子行选择解码器61、第 二锁存器62、第二子行选择解码器63、其中：
第一锁存器60，用于接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行；
第一子行选择解码器61，用于根据第一激活指令激活处于内存中的第一子行；
第二锁存器62，用于接收内存控制器发送的第二激活指令，第二激活指令用于指示激活内存中的第二子行；
第二子行选择解码器63，用于根据第二激活指令激活处于内存中的第二子行；
第一子行位于第一子阵列，第二子行处于第二子阵列；
第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同；
第一锁存器60和第二锁存器62均与用于进行数据缓存的全局缓冲器相连。
本发明实施例中，进一步的，第一激活指令还用于指示激活内存中的第三子行，第三子行与第一子行处于同一行中；
第二子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同。
本发明实施例中，进一步的，第二激活指令还用于指示激活内存中的第四子行，第四子行与第二子行处于同一行中；
第四子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同；
第四子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同。
在该方案中，第一锁存器激活第一子行后，第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同时，第二锁存器可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
参阅图7所示，本发明实施例中，激活内存的另一种流程如下：
步骤700：获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
步骤710：根据第一内存访问请求生成第一激活指令，并将第一激活指令发送至内存；
步骤720：从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行位于第一子阵列，第二子行处于第二子阵列；
步骤730：根据第二内存访问请求生成第二激活指令，并将第二激活指令发送至内存；
第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同。
本发明实施例中，进一步的，根据第一内存访问请求生成第一激活指令之前，还包括：
获取第三内存访问请求，第三内存访问请求用于请求访问内存的第三子行，第三子行与第一子行处于同一行，第二子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据第一内存访问请求生成第一激活指令，具体包括：
合并第一内存访问请求和第三内存访问请求，生成第一激活指令。
本发明实施例中，进一步的，根据第二内存访问请求生成第二激活指令之前，还包括：
获取第四内存访问请求，第四内存访问请求用于请求访问内存的第四子行，第四子行与第二子行处于同一行，第四子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同；
根据第二内存访问请求生成第二激活指令，具体包括：
合并第二内存访问请求和第四内存访问请求，生成第二激活指令。
本发明实施例中，可选的，第四子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同。
在该方案中，激活第一子行后，第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同时，可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
参阅图8所示，本发明实施例中，激活内存的另一种流程如下：
步骤800：接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行；
步骤810：根据第一激活指令激活处于内存中的第一子行；
步骤820：接收内存控制器发送的第二激活指令，第二激活指令用于指示激活内存中的第二子行；
步骤830：根据第二激活指令激活处于内存中的第二子行；第一子行位于第一子阵列，第二子行处于第二子阵列；第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同；第一锁存器和第二锁存器均与用于进行数据缓存的全局缓冲器相连。
本发明实施例中，进一步的，第一激活指令还用于指示激活内存中的第三子行，第三子行与第一子行处于同一行中；
第二子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据第一激活指令激活处于内存中的第一子行，具体包括：
由内存中的第一锁存器根据第一激活指令激活处于内存中的第一子行和第三子行。
本发明实施例中，可选的，第二激活指令还用于指示激活内存中的第四子行，第四子行与第二子行处于同一行中；
第四子行包括的任意一存储单元所对应的列号标识与第三子行包括的任意一存储单元所对应的列号标识均不相同；
根据第二激活指令激活处于内存中的第二子行，具体包括：
由内存中的第二锁存器根据第二激活指令激活处于内存中的第二子行和第四子行。
在该方案中，第一锁存器激活第一子行后，第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同时，第二锁存器可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
上述图5A、图5B、图6、图7、图8讲述的是激活第一子行后，与第一子行处于不同子阵列的第二子行包括的任意一存储单元所对应的列号标识与第一子行包括的任意一存储单元所对应的列号标识均不相同时，才可以将第二子行激活，进一步的，为了提高资源利用率，提出了如下方案：
本发明实施例中，为了提高存储单元的资源的利用率，如图9所示，提供一种内存控制器9000，该内存控制器9000包括请求分发模块90、内存调度器91、命令调度器92，其中：
请求分发模块90，用于获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
内存调度器91，用于获取请求分发模块90获取到的第一内存访问请求，并根据第一内存访问请求生成第一激活指令；
命令调度器92，用于将从内存调度器91获取的第一激活指令发送至内存；
请求分发模块90还用于，从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行位于第一子阵列，第二子行处于第二子阵列；
内存调度器91还用于，根据第二内存访问请求生成第二激活指令；
命令调度器92还用于，将从内存调度器91获取的第二激活指令发送至内存；
其中，第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
其中，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元。
本发明实施例中，进一步的，请求分发模块90还用于：
获取第三内存访问请求，第三内存访问请求用于请求访问内存的第三子 行，第三子行与第一子行处于同一行，第二子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元；
内存调度器91具体用于：
合并第一内存访问请求和第三内存访问请求，生成第一激活指令。
本发明实施例中，进一步的，请求分发模块90还用于：
获取第四内存访问请求，第四内存访问请求用于请求访问内存的第四子行，第四子行与第二子行处于同一行，第四子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
内存调度器91具体用于：
合并第二内存访问请求和第四内存访问请求，生成第二激活指令。
本发明实施例中，可选的，第四子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
在该方案中，第一锁存器激活第一子行后，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元时，第二锁存器也可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
本发明实施例中，为了提高存储单元的资源的利用率，如图10所示，内存模块10000，该内存模块10000包括第一锁存器100、第一子行选择解码器101、第二锁存器102、第二子行选择解码器103、其中：
第一锁存器100，用于接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行；
第一子行选择解码器101，用于根据第一激活指令激活处于内存中的第一子行；
第二锁存器102，用于接收内存控制器发送的第二激活指令，第二激活指令用于指示激活内存中的第二子行；
第二子行选择解码器103，用于根据第二激活指令激活处于内存中的第二子行；
第一子行位于第一子阵列，第二子行处于第二子阵列；
第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
第一锁存器100和第二锁存器102均未与用于进行数据缓存的全局缓冲器相连。
本发明实施例中，进一步的，第一激活指令还用于指示激活内存中的第三子行，第三子行与第一子行处于同一行中；
第二子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
本发明实施例中，进一步的，第二激活指令还用于指示激活内存中的第四子行，第四子行与第二子行处于同一行中；
第四子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
第四子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
在该方案中，第一锁存器激活第一子行后，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元时，第二锁存器也可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
本发明实施例中，为了提高存储单元的资源的利用率，如图11所示，提供另一种激活内存的方法：
步骤1100：获取第一内存访问请求，第一内存访问请求用于请求访问内存的第一子行；
步骤1110：获取第一内存访问请求，并根据第一内存访问请求生成第一激活指令；
步骤1120：将第一激活指令发送至内存；
步骤1130：从内存待调度队列中查找第二内存访问请求，内存待调度队列包括多个内存访问请求，第二内存访问请求用于请求访问内存的第二子行，第一子行位于第一子阵列，第二子行处于第二子阵列；
步骤1140：根据第二内存访问请求生成第二激活指令；
步骤1150：将获取的第二激活指令发送至内存；
其中，第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一 行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
其中，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元。
本发明实施例中，进一步的，根据第一内存访问请求生成第一激活指令之前，还包括：获取第三内存访问请求，第三内存访问请求用于请求访问内存的第三子行，第三子行与第一子行处于同一行，第二子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元；
根据第一内存访问请求生成第一激活指令，可以采用如下方式：合并第一内存访问请求和第三内存访问请求，生成第一激活指令。
本发明实施例中，进一步的，根据第二内存访问请求生成第二激活指令之前，还包括：
获取第四内存访问请求，第四内存访问请求用于请求访问内存的第四子行，第四子行与第二子行处于同一行，第四子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
根据第二内存访问请求生成第二激活指令时，可以为：合并第二内存访问请求和第四内存访问请求，生成第二激活指令。
本发明实施例中，可选的，第四子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
在该方案中，第一锁存器激活第一子行后，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元时，第二锁存器也可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
本发明实施例中，为了提高存储单元的资源的利用率，如图12所示，提供另一种激活内存的方法：
步骤1200：接收内存控制器发送的第一激活指令，第一激活指令用于指示激活内存中的第一子行；
步骤1210：根据第一激活指令激活处于内存中的第一子行；
步骤1220：接收内存控制器发送的第二激活指令，第二激活指令用于指示激活内存中的第二子行；
步骤1230：根据第二激活指令激活处于内存中的第二子行；
第一子行位于第一子阵列，第二子行处于第二子阵列；
第一子阵列和第二子阵列均包括至少一行，至少一行中的任意一行包括至少一个子行，至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
第一锁存器和第二锁存器均未与用于进行数据缓存的全局缓冲器相连。
本发明实施例中，进一步的，第一激活指令还用于指示激活内存中的第三子行，第三子行与第一子行处于同一行中；
第二子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
本发明实施例中，进一步的，第二激活指令还用于指示激活内存中的第四子行，第四子行与第二子行处于同一行中；
第四子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元；
第四子行包括列号标识与第三子行包括的存储单元对应的列号标识相同的存储单元。
在该方案中，第一锁存器激活第一子行后，第二子行包括列号标识与第一子行包括的存储单元对应的列号标识相同的存储单元时，第二锁存器也可以将与第一子行处于不同子阵列的第二子行激活，因此，提高了资源的利用率。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器 中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中的功能的步骤。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (22)

  1. 一种激活内存的方法，其特征在于，包括：
    获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
    从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行与所述第二子行处于所述内存的同一行；
    合并所述第一内存访问请求和所述第二内存访问请求，生成第一激活指令，所述第一激活指令用于指示激活所述内存中的所述第一子行和所述第二子行；
    将所述第一激活指令发送至所述内存。
  2. 如权利要求1所述的方法，其特征在于，从内存待调度队列中查找第二内存访问请求之后，还包括：
    生成子行选择向量，并将所述子行选择向量发送至所述内存；
    所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行。
  3. 一种激活内存的方法，其特征在于，包括：
    接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，所述第一子行与所述第二子行均处于所述内存中的同一行中；
    根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行。
  4. 如权利要求3所述的方法，其特征在于，根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行之前，还包括：
    接收所述内存控制器发送的子行选择向量，所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行；
    根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行，具体包括：
    根据所述第一激活指令中、所述子行选择向量激活处于所述内存的所述第一子行和所述第二子行。
  5. 一种内存控制器，其特征在于，包括：
    请求分发模块，用于获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
    内存调度器，用于从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行与所述第二子行处于所述内存的同一行；
    所述内存调度器还用于，合并所述第一内存访问请求和所述第二内存访问请求，生成第一激活指令，所述第一激活指令用于指示激活所述内存中的所述第一子行和所述第二子行；
    命令调度器，用于所述第一激活指令发送至所述内存。
  6. 如权利要求5所述的内存控制器，其特征在于，所述内存调度器还用于：
    生成子行选择向量，并将所述子行选择向量发送至所述内存；
    所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行。
  7. 一种内存模块，其特征在于，包括：
    锁存器，用于接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行和内存中的第二子行，所述第一子行与所述第二子行均处于所述内存中的同一行中；
    子行选择解码器，用于根据从所述锁存器获取的所述第一激活指令激活处于所述内存中的所述第一子行和所述第二子行。
  8. 如权利要求7所述的内存模块，其特征在于，所述锁存器还用于：
    接收所述内存控制器发送的子行选择向量，所述子行选择向量用于标识待激活的子行是所述第一子行和所述第二子行；
    所述子行选择解码器具体用于：
    根据所述第一激活指令中、所述子行选择向量激活处于所述内存 的所述第一子行和所述第二子行。
  9. 一种内存控制器，其特征在于，包括：
    请求分发模块，用于获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
    内存调度器，用于获取所述请求分发模块获取到的第一内存访问请求，并根据所述第一内存访问请求生成第一激活指令；
    命令调度器，用于将从所述内存调度器获取的所述第一激活指令发送至所述内存；
    所述请求分发模块还用于，从所述内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
    所述内存调度器还用于，根据所述第二内存访问请求生成第二激活指令；
    所述命令调度器还用于，将从所述内存调度器获取的所述第二激活指令发送至所述内存；
    其中，所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
    其中，所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同。
  10. 如权利要求9所述的内存控制器，其特征在于，所述请求分发模块还用于：
    获取第三内存访问请求，所述第三内存访问请求用于请求访问内存的第三子行，所述第三子行与所述第一子行处于同一行，所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
    所述内存调度器具体用于：
    合并所述第一内存访问请求和所述第三内存访问请求，生成第一 激活指令。
  11. 如权利要求9或10所述的内存控制器，其特征在于，所述请求分发模块还用于：
    获取第四内存访问请求，所述第四内存访问请求用于请求访问内存的第四子行，所述第四子行与所述第二子行处于同一行，所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
    所述内存调度器具体用于：
    合并所述第二内存访问请求和所述第四内存访问请求，生成第二激活指令。
  12. 如权利要求11所述的内存控制器，其特征在于，所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
  13. 一种内存模块，其特征在于，包括：
    第一锁存器，用于接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行；
    第一子行选择解码器，用于根据所述第一激活指令激活处于所述内存中的所述第一子行；
    第二锁存器，用于接收所述内存控制器发送的第二激活指令，所述第二激活指令用于指示激活所述内存中的第二子行；
    第二子行选择解码器，用于根据所述第二激活指令激活处于所述内存中的所述第二子行；
    所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
    所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
    所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
    所述第一锁存器和所述第二锁存器均与用于进行数据缓存的全 局缓冲器相连。
  14. 如权利要求13所述的内存模块，其特征在于，所述第一激活指令还用于指示激活内存中的第三子行，所述第三子行与所述第一子行处于同一行中；
    所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
  15. 如权利要求13或14所述的内存模块，其特征在于，所述第二激活指令还用于指示激活内存中的第四子行，所述第四子行与所述第二子行处于同一行中；
    所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
    所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
  16. 一种激活内存的方法，其特征在于，包括：
    获取第一内存访问请求，所述第一内存访问请求用于请求访问内存的第一子行；
    根据所述第一内存访问请求生成第一激活指令，并将所述第一激活指令发送至所述内存；
    从内存待调度队列中查找第二内存访问请求，所述内存待调度队列包括多个内存访问请求，所述第二内存访问请求用于请求访问所述内存的第二子行，所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；
    根据所述第二内存访问请求生成第二激活指令，并将所述第二激活指令发送至所述内存；
    所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
    所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同。
  17. 如权利要求16所述的方法，其特征在于，根据所述第一内存访问请求生成第一激活指令之前，还包括：
    获取第三内存访问请求，所述第三内存访问请求用于请求访问内存的第三子行，所述第三子行与所述第一子行处于同一行，所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
    根据所述第一内存访问请求生成第一激活指令，具体包括：
    合并所述第一内存访问请求和所述第三内存访问请求，生成第一激活指令。
  18. 如权利要求16或17所述的方法，其特征在于，根据所述第二内存访问请求生成第二激活指令之前，还包括：
    获取第四内存访问请求，所述第四内存访问请求用于请求访问内存的第四子行，所述第四子行与所述第二子行处于同一行，所述第四子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
    根据所述第二内存访问请求生成第二激活指令，具体包括：
    合并所述第二内存访问请求和所述第四内存访问请求，生成第二激活指令。
  19. 如权利要求18所述的方法，其特征在于，所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同。
  20. 一种激活内存的方法，其特征在于，包括：
    接收内存控制器发送的第一激活指令，所述第一激活指令用于指示激活内存中的第一子行；
    根据所述第一激活指令激活处于所述内存中的所述第一子行；
    接收内存控制器发送的第二激活指令，所述第二激活指令用于指示激活内存中的第二子行；
    根据所述第二激活指令激活处于所述内存中的所述第二子行；
    所述第一子行位于第一子阵列，所述第二子行处于第二子阵列；所述第一子阵列和所述第二子阵列均包括至少一行，所述至少一行中 的任意一行包括至少一个子行，所述至少一个子行中的任意一子行包括至少一个存储单元，任意一存储单元与一个行号标识和一个列号标识相对应；
    所述第二子行包括的任意一存储单元所对应的列号标识与所述第一子行包括的任意一存储单元所对应的列号标识均不相同；
    所述第一锁存器和所述第二锁存器均与用于进行数据缓存的全局缓冲器相连。
  21. 如权利要求20所述的方法，其特征在于，所述第一激活指令还用于指示激活内存中的第三子行，所述第三子行与所述第一子行处于同一行中；
    所述第二子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
    根据所述第一激活指令激活处于所述内存中的所述第一子行，具体包括：
    由所述内存中的第一锁存器根据所述第一激活指令激活处于所述内存中的所述第一子行和所述第三子行。
  22. 如权利要求20或21所述的方法，其特征在于，所述第二激活指令还用于指示激活内存中的第四子行，所述第四子行与所述第二子行处于同一行中；
    所述第四子行包括的任意一存储单元所对应的列号标识与所述第三子行包括的任意一存储单元所对应的列号标识均不相同；
    根据所述第二激活指令激活处于所述内存中的所述第二子行，具体包括：
    由所述内存中的第二锁存器根据所述第二激活指令激活处于所述内存中的所述第二子行和所述第四子行。
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