WO2016078273A1 - 一种直流失配消除方法和装置 - Google Patents

一种直流失配消除方法和装置 Download PDF

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WO2016078273A1
WO2016078273A1 PCT/CN2015/074881 CN2015074881W WO2016078273A1 WO 2016078273 A1 WO2016078273 A1 WO 2016078273A1 CN 2015074881 W CN2015074881 W CN 2015074881W WO 2016078273 A1 WO2016078273 A1 WO 2016078273A1
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dcoc
output stage
digital
receiver
port
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PCT/CN2015/074881
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English (en)
French (fr)
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谢豪律
王勇涛
王倬遥
付慕衡
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深圳市中兴微电子技术有限公司
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Priority to AU2015349443A priority Critical patent/AU2015349443B2/en
Priority to US15/528,104 priority patent/US10164673B2/en
Priority to EP15861845.4A priority patent/EP3223433B1/en
Publication of WO2016078273A1 publication Critical patent/WO2016078273A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits

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  • the present invention relates to receiver technology, and in particular, to a DC mismatch cancellation method and apparatus.
  • the gain of the receiver is very high, usually reaching 60dB to 80dB.
  • High-gain circuits often have large DC mismatches due to circuit mismatch, as is the case with receivers.
  • the DC mismatch of the receiver will cause the receiver's circuit to enter an abnormal working state, affecting the performance of the circuit, even functions such as the receiver's EVM, gain, etc.
  • DC mismatch cancellation (DCOC) is to solve this problem. produced.
  • embodiments of the present invention mainly aim to provide a DC mismatch cancellation method and apparatus.
  • An embodiment of the present invention provides a DC mismatch cancellation method, where the method includes:
  • the receiver After the receiver is powered on, obtaining a digital signal of a mismatch voltage of the circuit output port of the receiver, and obtaining a digital control signal for controlling the DC mismatch to cancel the DCOC output stage by the digital signal, and the DCOC output stage outputs a current according to the digital control signal. Go to the corresponding circuit of the receiver.
  • An embodiment of the present invention provides a DC mismatch cancellation device, where the device includes: a DCOC ADC, a digital signal processor, and a DCOC output stage;
  • a DCOC ADC configured to obtain a digital signal of a mismatch voltage of a circuit output port of the receiver after the receiver is powered on, and transmit the digital signal to the digital signal processor
  • a digital signal processor configured to obtain, by the digital signal, a digital control signal that controls a DCOC output stage, and transmits the digital control signal to a DCOC output stage;
  • a DCOC output stage configured to output current to a corresponding circuit of the receiver based on the digital control signal.
  • the embodiment of the invention provides a DC mismatch cancellation method and device. After the receiver is powered on, a digital signal of a mismatch voltage of a circuit output port of the receiver is obtained, and a digital control signal for controlling a DCOC output stage is obtained from the digital signal. The DCOC output stage outputs a current to the corresponding circuit of the receiver according to the digital control signal, so that the DC mismatch voltage of the receiver can be eliminated.
  • the static calibration mode of the present invention has a simpler, more stable and faster convergence. And there is no need to consider the stability of the circuit.
  • FIG. 1 is a schematic flowchart of a DC mismatch cancellation method according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of circuit connection of a DC mismatch cancellation method according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of current compensation of a filter by a first DCOC output stage according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a DC mismatch cancellation device according to an embodiment of the present invention.
  • Common DC mismatch cancellation methods include “input mismatch memory”, “output mismatch memory”, “preamplification”, “negative feedback loop”, etc. These methods have their own problems when directly applied to direct conversion receivers.
  • the "input mismatch storage”, “pre-amplification” and “output mismatch storage” methods Requires the support of the clock signal, and requires the circuit to disconnect the input signal when measuring the mismatch voltage, which is not in line with the receiver application; for the "negative feedback loop” mode, the circuit structure of this mode is very simple
  • the compensated output mismatch voltage range is limited, especially for the mismatch of the circuit receiving the calibration signal and the previous mismatch of the circuit.
  • the "negative feedback loop” approach is powerless.
  • Several of the above implementations are dynamically calibrated and the convergence speed is relatively slow. Therefore, in a direct conversion receiver with high gain, the present invention employs a statically calibrated DCOC circuit with high speed and simple current output.
  • a digital signal of a mismatch voltage of a circuit output port in the receiver is obtained, and a digital control signal for controlling a DCOC output stage is obtained from the digital signal, and the DCOC output stage is according to the digital control signal.
  • Output current to the corresponding circuit of the receiver is obtained.
  • the embodiment of the invention implements a DC mismatch cancellation method. As shown in FIG. 1 , the method includes the following steps:
  • Step 101 After the receiver is powered on, obtain a digital signal of a mismatch voltage of a circuit output port in the receiver;
  • the input port of the receiver does not receive the input signal, and the mismatch voltage of the output port of the circuit in the receiver is measured by a DCOC analog-to-digital converter (ADC), and the measured mismatch voltage is converted into a digital signal.
  • ADC analog-to-digital converter
  • Step 102 Obtain a digital control signal for controlling a DCOC output stage from the digital signal
  • the digital signal is inversely operated by the digital signal processor to obtain a digital control signal for controlling the DCOC output stage; for example, for the mismatch voltage of the circuit output port in the receiver, due to DV os (I amp *R 2 /V LSB ) is a constant value.
  • the digital signal processor only needs to reverse the digital signal DV os and the constant value (I amp *R 2 /V LSB ) delivered by the DCOC ADC to obtain a binary digital value.
  • the control port of the DCOC output stage is 5 bits, the digital signal processor adds the binary digital value and 011111 to obtain a digital control signal that controls the DCOC output stage.
  • Step 103 The DCOC output stage outputs a current according to the digital control signal to a corresponding circuit of the receiver;
  • the DCOC output stage performs digital-to-analog conversion on the digital control signal according to its own unit step current to obtain a current, and outputs the current to a corresponding circuit of the receiver.
  • the receiver is composed of three stages, namely, a filter, a variable gain amplifier (PGA), and a main ADC (Main ADC), and the DCOC output stage includes a first DCOC output.
  • Stage and second DCOC output stage the first DCOC output stage is used for current compensation of the filter, and the second DCOC output stage is used for current compensation of the PGA; wherein the DCOC ADC first measures the mismatch voltage of the filter output port, After a DCOC output stage current compensates the filter, the mismatch voltage of the PGA output port is measured, and the second DCOC output stage current compensates the PGA.
  • AV os-filter (n1+x)*(I 1-amp *R 2-filter ), where n1 is an integer.
  • x is a fraction less than 1 greater than -1
  • I 1-amp is the unit step current of the first DCOC output stage
  • R 2-filter is the filter output resistance
  • the measured mismatch voltage is converted into a digital signal DV os -filter , assuming the LSB of the ADC is V LSB , then,
  • the digital signal processor Since the DV os-filter (I 1-amp *R 2-filter /V LSB ) is a constant value, the digital signal processor only needs to transmit the digital signal DV os-filter and constant value (I 1 ) from the DCOC ADC. -amp *R 2-filter /V LSB ) to do a reverse operation to get a binary numeric value When the control port of the first DCOC output stage is 5 bits, the digital signal processor adds the binary digital value and 011111 to obtain a digital control signal that controls the first DCOC output stage.
  • the first DCOC output stage includes: control ports DCOC_CONTRL ⁇ 5:0>, reference signal ports IREF_CNTRL ⁇ 3:0>, and output ports ip, in, where DCOC_CONTRL ⁇ 5:0> receives 5-bit digital control signals, IREF_CNTRL ⁇ 3 :0> Receive the bandwidth control signal BW ⁇ 3:0> of the 3-bit filter, control its own unit step current I 1-amp , and the bandwidth control signal of the filter BW ⁇ 3:0> is controlled by the digital signal processor
  • the output port ip in outputs the current obtained by digital -to- analog conversion of the digital control signal according to the unit step current I 1-amp to the input end of the filter, and performs current compensation on the filter to realize the straightness of the filter. Loss is eliminated.
  • the DCOC ADC measures the mismatch voltage of the PGA output port.
  • AV os-PGA (n1+x)*(I 2-amp *R 2-PGA ), where n1 is an integer, x For a fraction less than 1 greater than -1, I 2-amp is the unit step current of the second DCOC output stage, R 2-PGA is the PGA output resistance, and the measured mismatch voltage is converted into a digital signal DV os-PGA
  • the LSB of the DCOC ADC is V LSB , then,
  • the digital signal processor Since the DV os-PGA (I 2-amp *R 2-PGA /V LSB ) is a constant value, the digital signal processor only needs to transmit the digital signal DV os-PGA and constant value (I 2 ) from the DCOC ADC. -amp *R 2-PGA /V LSB ) to do a reverse operation, you can get a binary numeric value When the control port of the second DCOC output stage is 5 bits, the digital signal processor adds the binary digital value and 011111 to obtain a digital control signal that controls the second DCOC output stage.
  • the second DCOC output stage includes: control ports DCOC_CONTRL ⁇ 5:0>, reference signal ports IREF_CNTRL ⁇ 4:0>, and output ports ip, in, where DCOC_CONTRL ⁇ 5:0> receives 5-bit digital control signals, IREF_CNTRL ⁇ 4 :0> Receive the gain control signal ⁇ 4:0> of the 4-bit PGA, control its own unit step current I 2-amp , the gain control signal ⁇ 4:0> of the PGA is transmitted by the digital signal processor, and the output port Ip, in will output the current obtained by digital -to- analog conversion of the digital control signal according to the unit step current I 2-amp to the input end of the PGA, and perform current compensation on the PGA to realize DC mismatch elimination of the PGA.
  • the filter is simplified as two input resistors R1, two output resistors R2, and an operational amplifier OP1.
  • the first DCOC output stage DCOC_CNTRL ⁇ 5:0> 011111, from ip, in The current output by the port is -0.5*I 1-amp and +0.5*I 1-amp , respectively, and the current flows through the resistor R2 to the output ports Von, Vop.
  • the high-gain op amp OP1 pinches the two nodes at the same voltage; at the same time, the common-mode voltage of the output ports Vop and Von is also pinned at a set common-mode voltage. Vcm. Then, the differential output current will generate a differential voltage I 1-amp *R2 at the output port, which is the compensation voltage.
  • the reference signal port IREF_CNTRL ⁇ 3:0> can adjust the size of I 1-amp .
  • the embodiment of the present invention further provides a DC mismatch cancellation device.
  • the device includes: a DCOC ADC 41, a digital signal processor 42, and a DCOC output stage 43.
  • the DCOC ADC 41 is configured to obtain a digital signal of the mismatch voltage of the circuit output port of the receiver after the receiver is powered up, and transmit the digital signal to the digital signal processor 42;
  • the digital signal processor 42 is configured to obtain a digital control signal for controlling the DCOC output stage from the digital signal, and transmit the digital control signal to the DCOC output stage 43;
  • the DCOC output stage 43 is configured to output current to the corresponding circuitry of the receiver based on the digital control signal.
  • the digital signal processor 42 is specifically configured to perform a reverse operation on the digital signal DV os and a constant value (I amp *R 2 /V LSB ) delivered by the DCOC ADC 41 to obtain a binary digital value.
  • a constant value I amp *R 2 /V LSB
  • the binary digital value is added to 011111 to obtain a digital control signal for controlling the DCOC output stage.
  • the receiver is composed of three stages, namely a filter, a variable gain amplifier (PGA) and a main ADC (Main ADC), and the DCOC output stage 43 includes a first DCOC output stage and a second DCOC output stage, first The DCOC output stage is used for current compensation of the filter, and the second DCOC output stage is used for current compensation of the PGA; wherein, the DCOC ADC 41 is specifically configured to measure the filter first.
  • the mismatch voltage of the output port of the wave device is subjected to current compensation of the filter at the first DCOC output stage, and then the mismatch voltage of the PGA output port is measured, and the second DCOC output stage performs current compensation on the PGA.
  • the digital signal processor 42 is specifically configured to perform a reverse operation on the digital signal DV os-filter and a constant value (I 1-amp *R 2-filter /V LSB ) delivered by the DCOC ADC 41 to obtain a binary number. value
  • the control port of the first DCOC output stage is 5 bits
  • the digital control signal of the first DCOC output stage is obtained by adding the binary digital value and 011111.
  • the first DCOC output stage includes: control ports DCOC_CONTRL ⁇ 5:0>, reference signal ports IREF_CNTRL ⁇ 3:0>, and output ports ip, in, where DCOC_CONTRL ⁇ 5:0> receives 5-bit digital control signals, IREF_CNTRL ⁇ 3:0> receives the bandwidth control signal BW ⁇ 3:0> of the 3-bit filter, controls its own unit step current I 1-amp , and the bandwidth control signal BW ⁇ 3:0> of the filter is composed of digital signal
  • the processor 42 delivers, the output ports ip, in will output the current obtained by digital -to- analog conversion of the digital control signal according to the unit step current I 1-amp to the input end of the filter, and perform current compensation on the filter to implement filtering. The DC mismatch of the device is eliminated.
  • the digital signal processor 42 is further configured to perform a reverse operation on the digital signal DV os-PGA and a constant value (I 2-amp *R 2-PGA /V LSB ) delivered by the DCOC ADC 41 to obtain a binary number. value
  • the control port of the second DCOC output stage is 5 bits
  • the digital control signal of the second DCOC output stage is obtained by adding the binary digital value and 011111.
  • the second DCOC output stage includes: control ports DCOC_CONTRL ⁇ 5:0>, reference signal ports IREF_CNTRL ⁇ 4:0>, and output ports ip, in, where DCOC_CONTRL ⁇ 5:0> receives 5-bit digital control signals, IREF_CNTRL ⁇ 4:0> receives the gain control signal ⁇ 4:0> of the 4-bit PGA, controls its own unit step current I 2-amp , and the gain control signal ⁇ 4:0> of the PGA is transmitted by the digital signal processor 42
  • the output ports ip in will output the current obtained by digital -to- analog conversion of the digital control signal according to the unit step current I 2-amp to the input end of the PGA, and perform current compensation on the PGA to realize DC mismatch elimination of the PGA.
  • a digital control signal for controlling a DCOC output stage is obtained by a digital signal of a mismatch voltage of a circuit output port of a receiver, so that a DCOC output stage outputs a corresponding current to a corresponding circuit of the receiver, Eliminate the DC mismatch voltage of the receiver,
  • the static calibration method of the invention has a simpler and more stable circuit structure, a faster convergence speed, and no need for circuit stability.

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Abstract

本发明公开了一种直流失配消除DCOC方法，接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，由所述数字信号得到控制DCOC输出级的数字控制信号，DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路；本发明同时还公开了一种直流失配消除装置。

Description

一种直流失配消除方法和装置 技术领域
本发明涉及接收机技术，尤其涉及一种直流失配消除方法和装置。
背景技术
在接收机中，由于接收机需要对接受到的微弱信号放大，因此接收机的增益是十分高的，通常可以达到60dB～80dB。高增益的电路通常会出现由于电路不匹配带来较大的直流失配，接收机即是如此。接收机的直流失配会导致接收机的电路进入非正常工作状态，影响到电路的性能，甚至是功能，比如接收机的EVM、增益等，直流失配消除(DCOC)就是为了解决这个问题而产生的。
DCOC的实现方法比较多，常见的有输入失配存储、输出失配存储、预放大、负反馈环路等。上面的每一种消除方法都能够实现失配的消除，但是都是基于动态校准的实现方案，存在校准收敛速度慢的问题，不是很适合接收机的应用场合。
发明内容
为解决现有存在的技术问题，本发明实施例主要期望提供一种直流失配消除方法和装置。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种直流失配消除方法，所述方法包括：
接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，由所述数字信号得到控制直流失配消除DCOC输出级的数字控制信号，DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路。
本发明实施例提供一种直流失配消除装置，所述装置包括：DCOC ADC、数字信号处理器、DCOC输出级；其中，
DCOC ADC，配置为接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，将所述数字信号传输给数字信号处理器；
数字信号处理器，配置为由所述数字信号得到控制DCOC输出级的数字控制信号，将所述数字控制信号传输给DCOC输出级；
DCOC输出级，配置为根据所述数字控制信号输出电流到接收机相应的电路。
本发明实施例提供了一种直流失配消除方法和装置，接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，由所述数字信号得到控制DCOC输出级的数字控制信号，DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路，如此，能够消除掉接收机的直流失配电压，本发明的静态校准方式，电路结构更加简单、稳定、收敛速度更快，并且无需考虑的电路稳定性。
附图说明
图1为本发明实施例提供的一种直流失配消除方法的流程示意图；
图2为本发明实施例提供的一种直流失配消除方法的电路连接示意图；
图3为本发明实施例提供的第一DCOC输出级对滤波器进行电流补偿的示意图；
图4为本发明实施例提供的一种直流失配消除装置的结构示意图。
具体实施方式
常见的直流失配消除方式有“输入失配存储”、“输出失配存储”、“预放大”、“负反馈环路”等，这些方式直接应用在直接变频接收机上都有各自的问题。比如，“输入失配存储”、“预放大”和“输出失配存储”的方式， 需要时钟信号的支持，且要求电路在测量失配电压时，断开输入信号，这是不符合接收机应用场合的；对于“负反馈环路”的方式，这种方式的电路结构十分的简单，在功耗、面积上会有很大的优势，但是它的工作速度较慢，并且补偿的输出失配电压范围有限，尤其对于接收校准信号的电路的失配以及该电路之前的失配，“负反馈环路”方式无能为力。上述的几种实现方案都是动态校准的结构，收敛速度相对较慢，因此，在具有高增益的直接变频接收机中，本发明采用了具有高速、简单的电流输出的静态校准的DCOC电路。
本发明实施例中，接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，由所述数字信号得到控制DCOC输出级的数字控制信号，DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路。
下面通过附图及具体实施例对本发明做进一步的详细说明。
本发明实施例实现一种直流失配消除方法，如图1所示，该方法包括以下几个步骤：
步骤101：接收机上电后，获得接收机中电路输出端口的失配电压的数字信号；
具体的，接收机上电后，接收机输入端口不接收输入信号，通过DCOC模数转换器(ADC)测量接收机中电路输出端口的失配电压，将测量到的失配电压转换为数字信号。
这里，假设DCOC ADC测量到接收机中电路输出端口的失配电压为AVos，AVos＝(n1+x)*(Iamp*R2)，其中n1为整数，x为小于1大于-1的小数，Iamp为DCOC输出级的单位步长电流，R2为接收机中所述电路输出端电阻，将测量得到的失配电压转换成数字信号DVos，假设DCOC ADC的最低有效位(LSB)为VLSB，那么，
Figure PCTCN2015074881-appb-000001
步骤102：由所述数字信号得到控制DCOC输出级的数字控制信号；
具体的，通过数字信号处理器对所述数字信号进行逆向运算得到控制DCOC输出级的数字控制信号；例如：对于接收机中电路输出端口的失配电压，由于DVos中(Iamp*R2/VLSB)是一个恒定值，数字信号处理器只需对由DCOC ADC输送来的数字信号DVos和恒定值(Iamp*R2/VLSB)做逆向运算，即可得到一个二进制数字值
Figure PCTCN2015074881-appb-000002
当DCOC输出级的控制端口为5位时，数字信号处理器用所述二进制数字值和011111相加得到控制所述DCOC输出级的数字控制信号。
步骤103：DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路；
具体的，DCOC输出级按照自身的单位步长电流对所述数字控制信号进行数模转换得到电流，输出电流到接收机相应的电路。
本实施例中，如图2所示，所述接收机由三级组成，即滤波器(Filter)、可变增益放大器(PGA)以及主ADC(Main ADC)，DCOC输出级包括第一DCOC输出级和第二DCOC输出级，第一DCOC输出级用于滤波器的电流补偿，第二DCOC输出级用于PGA的电流补偿；其中，DCOC ADC先测量滤波器输出端口的失配电压，在第一DCOC输出级对滤波器进行电流补偿后，再测量PGA输出端口的失配电压，并由第二DCOC输出级对PGA进行电流补偿。
假设DCOC ADC测量到接收机中滤波器输出端口的失配电压为AVos-filter，AVos-filter＝(n1+x)*(I1-amp*R2-filter)，其中n1为整数，x为小于1大于-1的小数，I1-amp为第一DCOC输出级的单位步长电流，R2-filter为滤波器输出端电阻，将测量得到的失配电压转换成数字信号DVos-filter，假设ADC的LSB为VLSB，那么，
Figure PCTCN2015074881-appb-000003
由于DVos-filter中(I1-amp*R2-filter/VLSB)是一个恒定值，数字信号处理器只需 对由DCOC ADC输送来的数字信号DVos-filter和恒定值(I1-amp*R2-filter/VLSB)做逆向运算，即可得到一个二进制数字值
Figure PCTCN2015074881-appb-000004
当第一DCOC输出级的控制端口为5位时，数字信号处理器用所述二进制数字值和011111相加得到控制第一DCOC输出级的数字控制信号。
第一DCOC输出级包括：控制端口DCOC_CONTRL<5:0>、参考信号端口IREF_CNTRL<3:0>和输出端口ip、in，其中，DCOC_CONTRL<5:0>接收5位数字控制信号，IREF_CNTRL<3:0>接收3位滤波器的带宽控制信号BW<3:0>，控制自身的单位步长电流I1-amp，所述滤波器的带宽控制信号BW<3:0>由数字信号处理器输送，输出端口ip、in将按照单位步长电流I1-amp对所述数字控制信号进行数模转换得到的电流输出到滤波器的输入端，对滤波器进行电流补偿，实现滤波器的直流失配消除。
在第一DCOC输出级对滤波器进行电流补偿后，DCOC ADC测量PGA输出端口的失配电压。
假设DCOC ADC测量到接收机中PGA输出端口的失配电压为AVos-PGA，AVos-PGA＝(n1+x)*(I2-amp*R2-PGA)，其中n1为整数，x为小于1大于-1的小数，I2-amp为第二DCOC输出级的单位步长电流，R2-PGA为PGA输出端电阻，将测量得到的失配电压转换成数字信号DVos-PGA，假设DCOC ADC的LSB为VLSB，那么，
Figure PCTCN2015074881-appb-000005
由于DVos-PGA中(I2-amp*R2-PGA/VLSB)是一个恒定值，数字信号处理器只需对由DCOC ADC输送来的数字信号DVos-PGA和恒定值(I2-amp*R2-PGA/VLSB)做逆向运算，即可得到一个二进制数字值
Figure PCTCN2015074881-appb-000006
当第二DCOC输出级的控制端口为5位时，数字信号处理器用所述二进制数字值和011111相加得到控制第二DCOC输出级的数字控制信号。
第二DCOC输出级包括：控制端口DCOC_CONTRL<5:0>、参考信号端口IREF_CNTRL<4:0>和输出端口ip、in，其中，DCOC_CONTRL<5:0>接收5位数字控制信号，IREF_CNTRL<4:0>接收4位PGA的增益控制信号<4:0>，控制自身的单位步长电流I2-amp，所述PGA的增益控制信号<4:0>由数字信号处理器输送，输出端口ip、in将按照单位步长电流I2-amp对所述数字控制信号进行数模转换得到的电流输出到PGA的输入端，对PGA进行电流补偿，实现PGA的直流失配消除。
以第一DCOC输出级对滤波器进行电流补偿为例，详细说明下补偿的工作原理。如图3所示，所述滤波器简化为两个输入端电阻R1、两个输出端电阻R2、运算放大器OP1，当第一DCOC输出级DCOC_CNTRL<5:0>＝011111时，从ip、in端口输出的电流分别为-0.5*I1-amp、+0.5*I1-amp，该电流通过电阻R2流到输出端口Von、Vop。由于节点net_p、net_n位于运放的输入端口，高增益的运算放大器OP1将两个节点牵制在相同的电压；同时，输出端口Vop、Von的共模电压也被牵制在一个设定的共模电压Vcm上。那么，差分的输出电流就会在输出端口产生差分电压I1-amp*R2，这个电压就是补偿电压。因此，第一DCOC输出级在输出端口产生的差分电压(Vop-Von)，在DCOC_CNTRL<5:0>＝111111时，产生最大值+32*I1-amp*R2，在DCOC_CNTRL<5:0>＝000000时，产生最小值-32*I1-amp*R2，且步长为I1-amp*R2。在第一DCOC输出级中，参考信号端口IREF_CNTRL<3:0>可以调节I1-amp的大小。由于R2的阻值会随着数字信号处理器的数字控制字CHANGE<3:0>的变化而变化，导致步长I1-amp*R2的变化，因此，可以通过IREF_CNTRL<3:0>调节I1-amp，在电阻R2变化的时候，I1-amp反向变化，保证步长I1-amp*R2不变。这里，DCOC_CNTRL<5:0>＝n，且n>31时，对滤波器补偿的电压为：(n-31)*I1-amp*R2；DCOC_CNTRL<5:0>＝n，且n<32时，对滤波器补偿的电压为：(n-32) *I1-amp*R2。
基于上述方法，本发明实施例还提供一种直流失配消除装置，如图4所示，该装置包括：DCOC ADC 41、数字信号处理器42、DCOC输出级43；其中，
DCOC ADC 41，配置为接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，将所述数字信号传输给数字信号处理器42；
数字信号处理器42，配置为由所述数字信号得到控制DCOC输出级的数字控制信号，将所述数字控制信号传输给DCOC输出级43；
DCOC输出级43，配置为根据所述数字控制信号输出电流到接收机相应的电路。
所述DCOC ADC 41，具体配置为测量到接收机中电路输出端口的失配电压为AVos，AVos＝(n1+x)*(Iamp*R2)，其中n1为整数，x为小于1大于-1的小数，Iamp为DCOC输出级43的单位步长电流，R2为接收机中所述电路输出端电阻，将测量得到的失配电压转换成数字信号DVos，
Figure PCTCN2015074881-appb-000007
VLSB为DCOC ADC 41的最低有效位(LSB)。
所述数字信号处理器42，具体配置为对由DCOC ADC 41输送来的数字信号DVos和恒定值(Iamp*R2/VLSB)做逆向运算，得到一个二进制数字值
Figure PCTCN2015074881-appb-000008
当DCOC输出级的控制端口为5位时，用所述二进制数字值和011111相加得到控制所述DCOC输出级的数字控制信号。
所述接收机由三级组成，即滤波器(Filter)、可变增益放大器(PGA)以及主ADC(Main ADC)，DCOC输出级43包括第一DCOC输出级和第二DCOC输出级，第一DCOC输出级用于滤波器的电流补偿，第二DCOC输出级用于PGA的电流补偿；其中，DCOC ADC 41，具体配置为先测量滤 波器输出端口的失配电压，在第一DCOC输出级对滤波器进行电流补偿后，再测量PGA输出端口的失配电压，由所述第二DCOC输出级对PGA进行电流补偿。
所述DCOC ADC 41，具体配置为测量到滤波器输出端口的失配电压为AVos-filter，AVos-filter＝(n1+x)*(I1-amp*R2-filter)，其中n1为整数，x为小于1大于-1的小数，I1-amp为第一DCOC输出级的单位步长电流，R2-filter为滤波器输出端电阻，将测量得到的失配电压转换成数字信号DVos-filter，
Figure PCTCN2015074881-appb-000009
VLSB为DCOC ADC 41的LSB。
所述数字信号处理器42，具体配置为对由DCOC ADC 41输送来的数字信号DVos-filter和恒定值(I1-amp*R2-filter/VLSB)做逆向运算，得到一个二进制数字值
Figure PCTCN2015074881-appb-000010
当第一DCOC输出级的控制端口为5位时，用所述二进制数字值和011111相加得到控制第一DCOC输出级的数字控制信号。
所述第一DCOC输出级包括：控制端口DCOC_CONTRL<5:0>、参考信号端口IREF_CNTRL<3:0>和输出端口ip、in，其中，DCOC_CONTRL<5:0>接收5位数字控制信号，IREF_CNTRL<3:0>接收3位滤波器的带宽控制信号BW<3:0>，控制自身的单位步长电流I1-amp，所述滤波器的带宽控制信号BW<3:0>由数字信号处理器42输送，输出端口ip、in将按照单位步长电流I1-amp对所述数字控制信号进行数模转换得到的电流输出到滤波器的输入端，对滤波器进行电流补偿，实现滤波器的直流失配消除。
所述DCOC ADC 41，具体配置为在第一DCOC输出级对滤波器进行电流补偿后，测量PGA输出端口的失配电压AVos-PGA，AVos-PGA＝(n1+x)*(I2-amp*R2-PGA)，其中n1为整数，x为小于1大于-1的小数， I2-amp为第二DCOC输出级的单位步长电流，R2-PGA为PGA输出端电阻，将测量得到的失配电压转换成数字信号DVos-PGA，
Figure PCTCN2015074881-appb-000011
VLSB为DCOC ADC 41的LSB。
所述数字信号处理器42，还配置为对由DCOC ADC 41输送来的数字信号DVos-PGA和恒定值(I2-amp*R2-PGA/VLSB)做逆向运算，得到一个二进制数字值
Figure PCTCN2015074881-appb-000012
当第二DCOC输出级的控制端口为5位时，用所述二进制数字值和011111相加得到控制第二DCOC输出级的数字控制信号。
所述第二DCOC输出级包括：控制端口DCOC_CONTRL<5:0>、参考信号端口IREF_CNTRL<4:0>和输出端口ip、in，其中，DCOC_CONTRL<5:0>接收5位数字控制信号，IREF_CNTRL<4:0>接收4位PGA的增益控制信号<4:0>，控制自身的单位步长电流I2-amp，所述PGA的增益控制信号<4:0>由数字信号处理器42输送，输出端口ip、in将按照单位步长电流I2-amp对所述数字控制信号进行数模转换得到的电流输出到PGA的输入端，对PGA进行电流补偿，实现PGA的直流失配消除。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
综合本发明的各实施例，通过接收机中电路输出端口的失配电压的数字信号，得到控制DCOC输出级的数字控制信号，从而使DCOC输出级输出对应的电流到接收机相应的电路，能够消除掉接收机的直流失配电压， 本发明的静态校准方式，电路结构更加简单、稳定、收敛速度更快，并且无需考虑的电路稳定性。

Claims (12)

  1. 一种直流失配消除方法，所述方法包括：
    接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，由所述数字信号得到控制直流失配消除DCOC输出级的数字控制信号，DCOC输出级根据所述数字控制信号输出电流到接收机相应的电路。
  2. 根据权利要求1所述的方法，其中，所述获得接收机中电路输出端口的失配电压的数字信号包括：通过DCOC模数转换器ADC测量接收机中电路输出端口的失配电压，DCOC ADC测量到失配电压为AVos，AVos＝(n1+x)*(Iamp*R2)，其中n1为整数，x为小于1大于-1的小数，Iamp为DCOC输出级的单位步长电流，R2为接收机中所述电路输出端电阻，将测量得到的失配电压AVos转换成数字信号DVos，
    Figure PCTCN2015074881-appb-100001
    DCOC VLSB为ADC的最低有效位LSB。
  3. 根据权利要求2所述的方法，其中，所述由所述数字信号得到控制直流失配消除DCOC输出级的数字控制信号包括：数字信号处理器对由DCOC ADC输送来的数字信号DVos和恒定值(Iamp*R2/VLSB)做逆向运算，得到一个二进制数字值
    Figure PCTCN2015074881-appb-100002
    当DCOC输出级的控制端口为5位时，数字信号处理器用所述二进制数字值和011111相加得到控制所述DCOC输出级的数字控制信号。
  4. 根据权利要求1所述的方法，其中，所述接收机包括：滤波器、可变增益放大器PGA以及主ADC(Main ADC)，所述DCOC输出级包括第一DCOC输出级和第二DCOC输出级，第一DCOC输出级用于滤波器的电流补偿，第二DCOC输出级用于PGA的电流补偿。
  5. 根据权利要求4所述的方法，其中，所述获得接收机中电路输出端口的失配电压的数字信号包括：DCOC ADC先测量滤波器输出端口的失配电压，在第一DCOC输出级对滤波器进行电流补偿后，再测量PGA输出端口的失配电压，由所述第二DCOC输出级对PGA进行电流补偿。
  6. 一种直流失配消除装置，所述装置包括：DCOC ADC、数字信号处理器、DCOC输出级；其中，
    DCOC ADC，配置为接收机上电后，获得接收机中电路输出端口的失配电压的数字信号，将所述数字信号传输给数字信号处理器；
    数字信号处理器，配置为由所述数字信号得到控制DCOC输出级的数字控制信号，将所述数字控制信号传输给DCOC输出级；
    DCOC输出级，配置为根据所述数字控制信号输出电流到接收机相应的电路。
  7. 根据权利要求6所述的装置，其中，所述DCOC ADC，配置为测量到接收机中电路输出端口的失配电压为AVos，AVos＝(n1+x)*(Iamp*R2)，其中n1为整数，x为小于1大于-1的小数，Iamp为DCOC输出级的单位步长电流，R2为接收机中所述电路输出端电阻，将测量得到的失配电压转换成数字信号DVos，
    Figure PCTCN2015074881-appb-100003
    VLSB为DCOC ADC的LSB。
  8. 根据权利要求7所述的装置，其中，所述数字信号处理器，配置为对由DCOC ADC输送来的数字信号DVos和恒定值(Iamp*R2/VLSB)做逆向运算，得到一个二进制数字值
    Figure PCTCN2015074881-appb-100004
    当DCOC输出级的控制端口为5位时，用所述二进制数字值和011111相加得到控制所述DCOC输出级的数字控制信号。
  9. 根据权利要求6所述的装置，其中，所述接收机包括滤波器、PGA以及主ADC，所述DCOC输出级包括第一DCOC输出级和第二DCOC输出级，第一DCOC输出级用于滤波器的电流补偿，第二DCOC输出级用于PGA的电流补偿。
  10. 根据权利要求9所述的方法，其中，所述DCOC ADC，配置为先测量滤波器输出端口的失配电压，在第一DCOC输出级对滤波器进行电流补偿后，再测量PGA输出端口的失配电压，由所述第二DCOC输出级对PGA进行电流补偿。
  11. 根据权利要求10所述的方法，其中，所述第一DCOC输出级包括：控制端口、参考信号端口和输出端口，其中，控制端口接收5位数字控制信号，参考信号端口接收3位滤波器的带宽控制信号，控制自身的单位步长电流，所述滤波器的带宽控制信号由数字信号处理器输送，输出端口将按照单位步长电流对数字控制信号进行数模转换得到的电流输出到滤波器的输入端，对滤波器进行电流补偿。
  12. 根据权利要求10所述的方法，其中，所述第二DCOC输出级包括：控制端口、参考信号端口和输出端口，其中，控制端口接收5位数字控制信号，参考信号端口接收4位PGA的增益控制信号，控制自身的单位步长电流，所述PGA的增益控制信号由数字信号处理器输送，输出端口将按照单位步长电流对数字控制信号进行数模转换得到的电流输出到PGA的输入端，对PGA进行电流补偿。
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